1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_connector.h>
58 #include <drm/i915_mei_hdcp_interface.h>
60 #include "i915_fixed.h"
61 #include "i915_params.h"
63 #include "i915_utils.h"
65 #include "gt/intel_lrc.h"
66 #include "gt/intel_engine.h"
67 #include "gt/intel_workarounds.h"
69 #include "intel_bios.h"
70 #include "intel_device_info.h"
71 #include "intel_display.h"
72 #include "intel_dpll_mgr.h"
73 #include "intel_frontbuffer.h"
74 #include "intel_opregion.h"
75 #include "intel_runtime_pm.h"
77 #include "intel_uncore.h"
78 #include "intel_wakeref.h"
79 #include "intel_wopcm.h"
82 #include "i915_gem_context.h"
83 #include "i915_gem_fence_reg.h"
84 #include "i915_gem_object.h"
85 #include "i915_gem_gtt.h"
86 #include "i915_gpu_error.h"
87 #include "i915_request.h"
88 #include "i915_scheduler.h"
89 #include "i915_timeline.h"
92 #include "intel_gvt.h"
94 /* General customization:
97 #define DRIVER_NAME "i915"
98 #define DRIVER_DESC "Intel Graphics"
99 #define DRIVER_DATE "20190417"
100 #define DRIVER_TIMESTAMP 1555492067
102 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
103 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
104 * which may not necessarily be a user visible problem. This will either
105 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
106 * enable distros and users to tailor their preferred amount of i915 abrt
109 #define I915_STATE_WARN(condition, format...) ({ \
110 int __ret_warn_on = !!(condition); \
111 if (unlikely(__ret_warn_on)) \
112 if (!WARN(i915_modparams.verbose_state_checks, format)) \
114 unlikely(__ret_warn_on); \
117 #define I915_STATE_WARN_ON(x) \
118 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
120 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
122 bool __i915_inject_load_failure(const char *func, int line);
123 #define i915_inject_load_failure() \
124 __i915_inject_load_failure(__func__, __LINE__)
126 bool i915_error_injected(void);
130 #define i915_inject_load_failure() false
131 #define i915_error_injected() false
135 #define i915_load_error(i915, fmt, ...) \
136 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
141 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
154 #define for_each_hpd_pin(__pin) \
155 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
157 /* Threshold == 5 for long IRQs, 50 for short */
158 #define HPD_STORM_DEFAULT_THRESHOLD 50
160 struct i915_hotplug {
161 struct work_struct hotplug_work;
164 unsigned long last_jiffies;
169 HPD_MARK_DISABLED = 2
171 } stats[HPD_NUM_PINS];
173 struct delayed_work reenable_work;
177 struct work_struct dig_port_work;
179 struct work_struct poll_init_work;
182 unsigned int hpd_storm_threshold;
183 /* Whether or not to count short HPD IRQs in HPD storms */
184 u8 hpd_short_storm_enabled;
187 * if we get a HPD irq from DP and a HPD irq from non-DP
188 * the non-DP HPD could block the workqueue on a mode config
189 * mutex getting, that userspace may have taken. However
190 * userspace is waiting on the DP workqueue to run which is
191 * blocked behind the non-DP one.
193 struct workqueue_struct *dp_wq;
196 #define I915_GEM_GPU_DOMAINS \
197 (I915_GEM_DOMAIN_RENDER | \
198 I915_GEM_DOMAIN_SAMPLER | \
199 I915_GEM_DOMAIN_COMMAND | \
200 I915_GEM_DOMAIN_INSTRUCTION | \
201 I915_GEM_DOMAIN_VERTEX)
203 struct drm_i915_private;
204 struct i915_mm_struct;
205 struct i915_mmu_object;
207 struct drm_i915_file_private {
208 struct drm_i915_private *dev_priv;
209 struct drm_file *file;
213 struct list_head request_list;
214 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
215 * chosen to prevent the CPU getting more than a frame ahead of the GPU
216 * (when using lax throttling for the frontbuffer). We also use it to
217 * offer free GPU waitboosts for severely congested workloads.
219 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
222 struct idr context_idr;
223 struct mutex context_idr_lock; /* guards context_idr */
226 struct mutex vm_idr_lock; /* guards vm_idr */
228 unsigned int bsd_engine;
231 * Every context ban increments per client ban score. Also
232 * hangs in short succession increments ban score. If ban threshold
233 * is reached, client is considered banned and submitting more work
234 * will fail. This is a stop gap measure to limit the badly behaving
235 * clients access to gpu. Note that unbannable contexts never increment
236 * the client ban score.
238 #define I915_CLIENT_SCORE_HANG_FAST 1
239 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
240 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
241 #define I915_CLIENT_SCORE_BANNED 9
242 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
244 unsigned long hang_timestamp;
247 /* Interface history:
250 * 1.2: Add Power Management
251 * 1.3: Add vblank support
252 * 1.4: Fix cmdbuffer path, add heap destroy
253 * 1.5: Add vblank pipe configuration
254 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
255 * - Support vertical blank on secondary display pipe
257 #define DRIVER_MAJOR 1
258 #define DRIVER_MINOR 6
259 #define DRIVER_PATCHLEVEL 0
261 struct intel_overlay;
262 struct intel_overlay_error_state;
264 struct sdvo_device_mapping {
273 struct intel_connector;
274 struct intel_encoder;
275 struct intel_atomic_state;
276 struct intel_crtc_state;
277 struct intel_initial_plane_config;
281 struct intel_cdclk_state;
283 struct drm_i915_display_funcs {
284 void (*get_cdclk)(struct drm_i915_private *dev_priv,
285 struct intel_cdclk_state *cdclk_state);
286 void (*set_cdclk)(struct drm_i915_private *dev_priv,
287 const struct intel_cdclk_state *cdclk_state,
289 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
290 enum i9xx_plane_id i9xx_plane);
291 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
292 int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
293 void (*initial_watermarks)(struct intel_atomic_state *state,
294 struct intel_crtc_state *cstate);
295 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
296 struct intel_crtc_state *cstate);
297 void (*optimize_watermarks)(struct intel_atomic_state *state,
298 struct intel_crtc_state *cstate);
299 int (*compute_global_watermarks)(struct intel_atomic_state *state);
300 void (*update_wm)(struct intel_crtc *crtc);
301 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
302 /* Returns the active state of the crtc, and if the crtc is active,
303 * fills out the pipe-config with the hw state. */
304 bool (*get_pipe_config)(struct intel_crtc *,
305 struct intel_crtc_state *);
306 void (*get_initial_plane_config)(struct intel_crtc *,
307 struct intel_initial_plane_config *);
308 int (*crtc_compute_clock)(struct intel_crtc *crtc,
309 struct intel_crtc_state *crtc_state);
310 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
311 struct drm_atomic_state *old_state);
312 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
313 struct drm_atomic_state *old_state);
314 void (*update_crtcs)(struct drm_atomic_state *state);
315 void (*audio_codec_enable)(struct intel_encoder *encoder,
316 const struct intel_crtc_state *crtc_state,
317 const struct drm_connector_state *conn_state);
318 void (*audio_codec_disable)(struct intel_encoder *encoder,
319 const struct intel_crtc_state *old_crtc_state,
320 const struct drm_connector_state *old_conn_state);
321 void (*fdi_link_train)(struct intel_crtc *crtc,
322 const struct intel_crtc_state *crtc_state);
323 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
324 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
325 /* clock updates for mode set */
327 /* render clock increase/decrease */
328 /* display clock increase/decrease */
329 /* pll clock increase/decrease */
331 int (*color_check)(struct intel_crtc_state *crtc_state);
333 * Program double buffered color management registers during
334 * vblank evasion. The registers should then latch during the
335 * next vblank start, alongside any other double buffered registers
336 * involved with the same commit.
338 void (*color_commit)(const struct intel_crtc_state *crtc_state);
340 * Load LUTs (and other single buffered color management
341 * registers). Will (hopefully) be called during the vblank
342 * following the latching of any double buffered registers
343 * involved with the same commit.
345 void (*load_luts)(const struct intel_crtc_state *crtc_state);
349 struct work_struct work;
351 u32 required_version;
352 u32 max_fw_size; /* bytes */
354 u32 dmc_fw_size; /* dwords */
357 i915_reg_t mmioaddr[8];
361 intel_wakeref_t wakeref;
364 enum i915_cache_level {
366 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
367 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
368 caches, eg sampler/render caches, and the
369 large Last-Level-Cache. LLC is coherent with
370 the CPU, but L3 is only visible to the GPU. */
371 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
374 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
377 /* This is always the inner lock when overlapping with struct_mutex and
378 * it's the outer lock when overlapping with stolen_lock. */
381 unsigned int possible_framebuffer_bits;
382 unsigned int busy_bits;
383 unsigned int visible_pipes_mask;
384 struct intel_crtc *crtc;
386 struct drm_mm_node compressed_fb;
387 struct drm_mm_node *compressed_llb;
395 bool underrun_detected;
396 struct work_struct underrun_work;
399 * Due to the atomic rules we can't access some structures without the
400 * appropriate locking, so we cache information here in order to avoid
403 struct intel_fbc_state_cache {
404 struct i915_vma *vma;
408 unsigned int mode_flags;
409 u32 hsw_bdw_pixel_rate;
413 unsigned int rotation;
418 * Display surface base address adjustement for
419 * pageflips. Note that on gen4+ this only adjusts up
420 * to a tile, offsets within a tile are handled in
421 * the hw itself (with the TILEOFF register).
428 u16 pixel_blend_mode;
432 const struct drm_format_info *format;
438 * This structure contains everything that's relevant to program the
439 * hardware registers. When we want to figure out if we need to disable
440 * and re-enable FBC for a new configuration we just check if there's
441 * something different in the struct. The genx_fbc_activate functions
442 * are supposed to read from it in order to program the registers.
444 struct intel_fbc_reg_params {
445 struct i915_vma *vma;
450 enum i9xx_plane_id i9xx_plane;
451 unsigned int fence_y_offset;
455 const struct drm_format_info *format;
460 unsigned int gen9_wa_cfb_stride;
463 const char *no_fbc_reason;
467 * HIGH_RR is the highest eDP panel refresh rate read from EDID
468 * LOW_RR is the lowest eDP panel refresh rate found from EDID
469 * parsing for same resolution.
471 enum drrs_refresh_rate_type {
474 DRRS_MAX_RR, /* RR count */
477 enum drrs_support_type {
478 DRRS_NOT_SUPPORTED = 0,
479 STATIC_DRRS_SUPPORT = 1,
480 SEAMLESS_DRRS_SUPPORT = 2
486 struct delayed_work work;
488 unsigned busy_frontbuffer_bits;
489 enum drrs_refresh_rate_type refresh_rate_type;
490 enum drrs_support_type type;
496 #define I915_PSR_DEBUG_MODE_MASK 0x0f
497 #define I915_PSR_DEBUG_DEFAULT 0x00
498 #define I915_PSR_DEBUG_DISABLE 0x01
499 #define I915_PSR_DEBUG_ENABLE 0x02
500 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
501 #define I915_PSR_DEBUG_IRQ 0x10
509 struct work_struct work;
510 unsigned busy_frontbuffer_bits;
511 bool sink_psr2_support;
513 bool colorimetry_support;
515 u8 sink_sync_latency;
516 ktime_t last_entry_attempt;
518 bool sink_not_reliable;
520 u16 su_x_granularity;
524 * Sorted by south display engine compatibility.
525 * If the new PCH comes with a south display engine that is not
526 * inherited from the latest item, please do not add it to the
527 * end. Instead, add it right after its "parent" PCH.
530 PCH_NOP = -1, /* PCH without south display */
531 PCH_NONE = 0, /* No PCH present */
532 PCH_IBX, /* Ibexpeak PCH */
533 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
534 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
535 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
536 PCH_CNP, /* Cannon/Comet Lake PCH */
537 PCH_ICP, /* Ice Lake PCH */
540 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
541 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
542 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
543 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
544 #define QUIRK_INCREASE_T12_DELAY (1<<6)
545 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
548 struct intel_fbc_work;
551 struct i2c_adapter adapter;
552 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
556 struct i2c_algo_bit_data bit_algo;
557 struct drm_i915_private *dev_priv;
560 struct i915_suspend_saved_registers {
563 u32 saveCACHE_MODE_0;
564 u32 saveMI_ARB_STATE;
568 u64 saveFENCE[I915_MAX_NUM_FENCES];
569 u32 savePCH_PORT_HOTPLUG;
573 struct vlv_s0ix_state {
580 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
581 u32 media_max_req_count;
582 u32 gfx_max_req_count;
614 /* Display 1 CZ domain */
619 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
621 /* GT SA CZ domain */
628 /* Display 2 CZ domain */
635 struct intel_rps_ei {
642 struct mutex lock; /* protects enabling and the worker */
645 * work, interrupts_enabled and pm_iir are protected by
648 struct work_struct work;
649 bool interrupts_enabled;
652 /* PM interrupt bits that should never be masked */
655 /* Frequencies are stored in potentially platform dependent multiples.
656 * In other words, *_freq needs to be multiplied by X to be interesting.
657 * Soft limits are those which are used for the dynamic reclocking done
658 * by the driver (raise frequencies under heavy loads, and lower for
659 * lighter loads). Hard limits are those imposed by the hardware.
661 * A distinction is made for overclocking, which is never enabled by
662 * default, and is considered to be above the hard limit if it's
665 u8 cur_freq; /* Current frequency (cached, may not == HW) */
666 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
667 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
668 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
669 u8 min_freq; /* AKA RPn. Minimum frequency */
670 u8 boost_freq; /* Frequency to request when wait boosting */
671 u8 idle_freq; /* Frequency to request when we are idle */
672 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
673 u8 rp1_freq; /* "less than" RP0 power/freqency */
674 u8 rp0_freq; /* Non-overclocked max frequency. */
675 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
682 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
683 unsigned int interactive;
685 u8 up_threshold; /* Current %busy required to uplock */
686 u8 down_threshold; /* Current %busy required to downclock */
690 atomic_t num_waiters;
693 /* manual wa residency calculations */
694 struct intel_rps_ei ei;
699 u64 prev_hw_residency[4];
700 u64 cur_residency[4];
703 struct intel_llc_pstate {
707 struct intel_gen6_power_mgmt {
708 struct intel_rps rps;
709 struct intel_rc6 rc6;
710 struct intel_llc_pstate llc_pstate;
713 /* defined intel_pm.c */
714 extern spinlock_t mchdev_lock;
716 struct intel_ilk_power_mgmt {
724 unsigned long last_time1;
725 unsigned long chipset_power;
728 unsigned long gfx_power;
735 struct drm_i915_private;
736 struct i915_power_well;
738 struct i915_power_well_ops {
740 * Synchronize the well's hw state to match the current sw state, for
741 * example enable/disable it based on the current refcount. Called
742 * during driver init and resume time, possibly after first calling
743 * the enable/disable handlers.
745 void (*sync_hw)(struct drm_i915_private *dev_priv,
746 struct i915_power_well *power_well);
748 * Enable the well and resources that depend on it (for example
749 * interrupts located on the well). Called after the 0->1 refcount
752 void (*enable)(struct drm_i915_private *dev_priv,
753 struct i915_power_well *power_well);
755 * Disable the well and resources that depend on it. Called after
756 * the 1->0 refcount transition.
758 void (*disable)(struct drm_i915_private *dev_priv,
759 struct i915_power_well *power_well);
760 /* Returns the hw enabled state. */
761 bool (*is_enabled)(struct drm_i915_private *dev_priv,
762 struct i915_power_well *power_well);
765 struct i915_power_well_regs {
772 /* Power well structure for haswell */
773 struct i915_power_well_desc {
777 /* unique identifier for this power well */
778 enum i915_power_well_id id;
780 * Arbitraty data associated with this power well. Platform and power
786 * request/status flag index in the PUNIT power well
787 * control/status registers.
795 const struct i915_power_well_regs *regs;
797 * request/status flag index in the power well
798 * constrol/status registers.
801 /* Mask of pipes whose IRQ logic is backed by the pw */
803 /* The pw is backing the VGA functionality */
807 * The pw is for an ICL+ TypeC PHY port in
813 const struct i915_power_well_ops *ops;
816 struct i915_power_well {
817 const struct i915_power_well_desc *desc;
818 /* power well enable/disable usage count */
820 /* cached hw enabled state */
824 struct i915_power_domains {
826 * Power wells needed for initialization at driver init and suspend
827 * time are on. They are kept on until after the first modeset.
830 bool display_core_suspended;
831 int power_well_count;
833 intel_wakeref_t wakeref;
836 int domain_use_count[POWER_DOMAIN_NUM];
837 struct i915_power_well *power_wells;
840 #define MAX_L3_SLICES 2
841 struct intel_l3_parity {
842 u32 *remap_info[MAX_L3_SLICES];
843 struct work_struct error_work;
848 /** Memory allocator for GTT stolen memory */
849 struct drm_mm stolen;
850 /** Protects the usage of the GTT stolen memory allocator. This is
851 * always the inner lock when overlapping with struct_mutex. */
852 struct mutex stolen_lock;
854 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
857 /** List of all objects in gtt_space. Used to restore gtt
858 * mappings on resume */
859 struct list_head bound_list;
861 * List of objects which are not bound to the GTT (thus
862 * are idle and not used by the GPU). These objects may or may
863 * not actually have any pages attached.
865 struct list_head unbound_list;
867 /** List of all objects in gtt_space, currently mmaped by userspace.
868 * All objects within this list must also be on bound_list.
870 struct list_head userfault_list;
873 * List of objects which are pending destruction.
875 struct llist_head free_list;
876 struct work_struct free_work;
877 spinlock_t free_lock;
879 * Count of objects pending destructions. Used to skip needlessly
880 * waiting on an RCU barrier if no objects are waiting to be freed.
885 * Small stash of WC pages
887 struct pagestash wc_stash;
890 * tmpfs instance used for shmem backed objects
892 struct vfsmount *gemfs;
894 /** PPGTT used for aliasing the PPGTT with the GTT */
895 struct i915_hw_ppgtt *aliasing_ppgtt;
897 struct notifier_block oom_notifier;
898 struct notifier_block vmap_notifier;
899 struct shrinker shrinker;
901 /** LRU list of objects with fence regs on them. */
902 struct list_head fence_list;
905 * Workqueue to fault in userptr pages, flushed by the execbuf
906 * when required but otherwise left to userspace to try again
909 struct workqueue_struct *userptr_wq;
911 u64 unordered_timeline;
913 /* the indicator for dispatch video commands on two BSD rings */
914 atomic_t bsd_engine_dispatch_index;
916 /** Bit 6 swizzling required for X tiling */
918 /** Bit 6 swizzling required for Y tiling */
921 /* accounting, useful for userland debugging */
922 spinlock_t object_stat_lock;
927 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
929 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
930 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
932 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
933 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
935 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
937 struct ddi_vbt_port_info {
941 * This is an index in the HDMI/DVI DDI buffer translation table.
942 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
943 * populate this field.
945 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
953 u8 supports_typec_usb:1;
956 u8 alternate_aux_channel;
957 u8 alternate_ddc_pin;
961 int dp_max_link_rate; /* 0 for not limited by VBT */
964 enum psr_lines_to_wait {
965 PSR_0_LINES_TO_WAIT = 0,
971 struct intel_vbt_data {
972 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
973 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
976 unsigned int int_tv_support:1;
977 unsigned int lvds_dither:1;
978 unsigned int int_crt_support:1;
979 unsigned int lvds_use_ssc:1;
980 unsigned int int_lvds_support:1;
981 unsigned int display_clock_mode:1;
982 unsigned int fdi_rx_polarity_inverted:1;
983 unsigned int panel_type:4;
985 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
986 enum drm_panel_orientation orientation;
988 enum drrs_support_type drrs_type;
998 struct edp_power_seq pps;
1004 bool require_aux_wakeup;
1006 enum psr_lines_to_wait lines_to_wait;
1007 int tp1_wakeup_time_us;
1008 int tp2_tp3_wakeup_time_us;
1009 int psr2_tp2_tp3_wakeup_time_us;
1015 bool active_low_pwm;
1016 u8 min_brightness; /* min_brightness/255 of max */
1017 u8 controller; /* brightness controller number */
1018 enum intel_backlight_type type;
1024 struct mipi_config *config;
1025 struct mipi_pps_data *pps;
1031 const u8 *sequence[MIPI_SEQ_MAX];
1032 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1033 enum drm_panel_orientation orientation;
1039 struct child_device_config *child_dev;
1041 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1042 struct sdvo_device_mapping sdvo_mappings[2];
1045 enum intel_ddb_partitioning {
1047 INTEL_DDB_PART_5_6, /* IVB+ */
1050 struct intel_wm_level {
1058 struct ilk_wm_values {
1064 enum intel_ddb_partitioning partitioning;
1067 struct g4x_pipe_wm {
1068 u16 plane[I915_MAX_PLANES];
1078 struct vlv_wm_ddl_values {
1079 u8 plane[I915_MAX_PLANES];
1082 struct vlv_wm_values {
1083 struct g4x_pipe_wm pipe[3];
1084 struct g4x_sr_wm sr;
1085 struct vlv_wm_ddl_values ddl[3];
1090 struct g4x_wm_values {
1091 struct g4x_pipe_wm pipe[2];
1092 struct g4x_sr_wm sr;
1093 struct g4x_sr_wm hpll;
1099 struct skl_ddb_entry {
1100 u16 start, end; /* in number of blocks, 'end' is exclusive */
1103 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1105 return entry->end - entry->start;
1108 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1109 const struct skl_ddb_entry *e2)
1111 if (e1->start == e2->start && e1->end == e2->end)
1117 struct skl_ddb_allocation {
1118 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1121 struct skl_ddb_values {
1122 unsigned dirty_pipes;
1123 struct skl_ddb_allocation ddb;
1126 struct skl_wm_level {
1134 /* Stores plane specific WM parameters */
1135 struct skl_wm_params {
1136 bool x_tiled, y_tiled;
1141 u32 plane_pixel_rate;
1142 u32 y_min_scanlines;
1143 u32 plane_bytes_per_line;
1144 uint_fixed_16_16_t plane_blocks_per_line;
1145 uint_fixed_16_16_t y_tile_minimum;
1147 u32 dbuf_block_size;
1151 * This struct helps tracking the state needed for runtime PM, which puts the
1152 * device in PCI D3 state. Notice that when this happens, nothing on the
1153 * graphics device works, even register access, so we don't get interrupts nor
1156 * Every piece of our code that needs to actually touch the hardware needs to
1157 * either call intel_runtime_pm_get or call intel_display_power_get with the
1158 * appropriate power domain.
1160 * Our driver uses the autosuspend delay feature, which means we'll only really
1161 * suspend if we stay with zero refcount for a certain amount of time. The
1162 * default value is currently very conservative (see intel_runtime_pm_enable), but
1163 * it can be changed with the standard runtime PM files from sysfs.
1165 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1166 * goes back to false exactly before we reenable the IRQs. We use this variable
1167 * to check if someone is trying to enable/disable IRQs while they're supposed
1168 * to be disabled. This shouldn't happen and we'll print some error messages in
1171 * For more, read the Documentation/power/runtime_pm.txt.
1173 struct i915_runtime_pm {
1174 atomic_t wakeref_count;
1178 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1180 * To aide detection of wakeref leaks and general misuse, we
1181 * track all wakeref holders. With manual markup (i.e. returning
1182 * a cookie to each rpm_get caller which they then supply to their
1183 * paired rpm_put) we can remove corresponding pairs of and keep
1184 * the array trimmed to active wakerefs.
1186 struct intel_runtime_pm_debug {
1189 depot_stack_handle_t last_acquire;
1190 depot_stack_handle_t last_release;
1192 depot_stack_handle_t *owners;
1193 unsigned long count;
1198 enum intel_pipe_crc_source {
1199 INTEL_PIPE_CRC_SOURCE_NONE,
1200 INTEL_PIPE_CRC_SOURCE_PLANE1,
1201 INTEL_PIPE_CRC_SOURCE_PLANE2,
1202 INTEL_PIPE_CRC_SOURCE_PLANE3,
1203 INTEL_PIPE_CRC_SOURCE_PLANE4,
1204 INTEL_PIPE_CRC_SOURCE_PLANE5,
1205 INTEL_PIPE_CRC_SOURCE_PLANE6,
1206 INTEL_PIPE_CRC_SOURCE_PLANE7,
1207 INTEL_PIPE_CRC_SOURCE_PIPE,
1208 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1209 INTEL_PIPE_CRC_SOURCE_TV,
1210 INTEL_PIPE_CRC_SOURCE_DP_B,
1211 INTEL_PIPE_CRC_SOURCE_DP_C,
1212 INTEL_PIPE_CRC_SOURCE_DP_D,
1213 INTEL_PIPE_CRC_SOURCE_AUTO,
1214 INTEL_PIPE_CRC_SOURCE_MAX,
1217 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1218 struct intel_pipe_crc {
1221 enum intel_pipe_crc_source source;
1224 struct i915_frontbuffer_tracking {
1228 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1235 struct i915_virtual_gpu {
1240 /* used in computing the new watermarks state */
1241 struct intel_wm_config {
1242 unsigned int num_pipes_active;
1243 bool sprites_enabled;
1244 bool sprites_scaled;
1247 struct i915_oa_format {
1252 struct i915_oa_reg {
1257 struct i915_oa_config {
1258 char uuid[UUID_STRING_LEN + 1];
1261 const struct i915_oa_reg *mux_regs;
1263 const struct i915_oa_reg *b_counter_regs;
1264 u32 b_counter_regs_len;
1265 const struct i915_oa_reg *flex_regs;
1268 struct attribute_group sysfs_metric;
1269 struct attribute *attrs[2];
1270 struct device_attribute sysfs_metric_id;
1275 struct i915_perf_stream;
1278 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1280 struct i915_perf_stream_ops {
1282 * @enable: Enables the collection of HW samples, either in response to
1283 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1284 * without `I915_PERF_FLAG_DISABLED`.
1286 void (*enable)(struct i915_perf_stream *stream);
1289 * @disable: Disables the collection of HW samples, either in response
1290 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1293 void (*disable)(struct i915_perf_stream *stream);
1296 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1297 * once there is something ready to read() for the stream
1299 void (*poll_wait)(struct i915_perf_stream *stream,
1304 * @wait_unlocked: For handling a blocking read, wait until there is
1305 * something to ready to read() for the stream. E.g. wait on the same
1306 * wait queue that would be passed to poll_wait().
1308 int (*wait_unlocked)(struct i915_perf_stream *stream);
1311 * @read: Copy buffered metrics as records to userspace
1312 * **buf**: the userspace, destination buffer
1313 * **count**: the number of bytes to copy, requested by userspace
1314 * **offset**: zero at the start of the read, updated as the read
1315 * proceeds, it represents how many bytes have been copied so far and
1316 * the buffer offset for copying the next record.
1318 * Copy as many buffered i915 perf samples and records for this stream
1319 * to userspace as will fit in the given buffer.
1321 * Only write complete records; returning -%ENOSPC if there isn't room
1322 * for a complete record.
1324 * Return any error condition that results in a short read such as
1325 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1326 * returning to userspace.
1328 int (*read)(struct i915_perf_stream *stream,
1334 * @destroy: Cleanup any stream specific resources.
1336 * The stream will always be disabled before this is called.
1338 void (*destroy)(struct i915_perf_stream *stream);
1342 * struct i915_perf_stream - state for a single open stream FD
1344 struct i915_perf_stream {
1346 * @dev_priv: i915 drm device
1348 struct drm_i915_private *dev_priv;
1351 * @link: Links the stream into ``&drm_i915_private->streams``
1353 struct list_head link;
1356 * @wakeref: As we keep the device awake while the perf stream is
1357 * active, we track our runtime pm reference for later release.
1359 intel_wakeref_t wakeref;
1362 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1363 * properties given when opening a stream, representing the contents
1364 * of a single sample as read() by userspace.
1369 * @sample_size: Considering the configured contents of a sample
1370 * combined with the required header size, this is the total size
1371 * of a single sample record.
1376 * @ctx: %NULL if measuring system-wide across all contexts or a
1377 * specific context that is being monitored.
1379 struct i915_gem_context *ctx;
1382 * @enabled: Whether the stream is currently enabled, considering
1383 * whether the stream was opened in a disabled state and based
1384 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1389 * @ops: The callbacks providing the implementation of this specific
1390 * type of configured stream.
1392 const struct i915_perf_stream_ops *ops;
1395 * @oa_config: The OA configuration used by the stream.
1397 struct i915_oa_config *oa_config;
1401 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1403 struct i915_oa_ops {
1405 * @is_valid_b_counter_reg: Validates register's address for
1406 * programming boolean counters for a particular platform.
1408 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1412 * @is_valid_mux_reg: Validates register's address for programming mux
1413 * for a particular platform.
1415 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1418 * @is_valid_flex_reg: Validates register's address for programming
1419 * flex EU filtering for a particular platform.
1421 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1424 * @enable_metric_set: Selects and applies any MUX configuration to set
1425 * up the Boolean and Custom (B/C) counters that are part of the
1426 * counter reports being sampled. May apply system constraints such as
1427 * disabling EU clock gating as required.
1429 int (*enable_metric_set)(struct i915_perf_stream *stream);
1432 * @disable_metric_set: Remove system constraints associated with using
1435 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1438 * @oa_enable: Enable periodic sampling
1440 void (*oa_enable)(struct i915_perf_stream *stream);
1443 * @oa_disable: Disable periodic sampling
1445 void (*oa_disable)(struct i915_perf_stream *stream);
1448 * @read: Copy data from the circular OA buffer into a given userspace
1451 int (*read)(struct i915_perf_stream *stream,
1457 * @oa_hw_tail_read: read the OA tail pointer register
1459 * In particular this enables us to share all the fiddly code for
1460 * handling the OA unit tail pointer race that affects multiple
1463 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1466 struct intel_cdclk_state {
1467 unsigned int cdclk, vco, ref, bypass;
1471 struct drm_i915_private {
1472 struct drm_device drm;
1474 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1475 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1476 struct intel_driver_caps caps;
1479 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1480 * end of stolen which we can optionally use to create GEM objects
1481 * backed by stolen memory. Note that stolen_usable_size tells us
1482 * exactly how much of this we are actually allowed to use, given that
1483 * some portion of it is in fact reserved for use by hardware functions.
1485 struct resource dsm;
1487 * Reseved portion of Data Stolen Memory
1489 struct resource dsm_reserved;
1492 * Stolen memory is segmented in hardware with different portions
1493 * offlimits to certain functions.
1495 * The drm_mm is initialised to the total accessible range, as found
1496 * from the PCI config. On Broadwell+, this is further restricted to
1497 * avoid the first page! The upper end of stolen memory is reserved for
1498 * hardware functions and similarly removed from the accessible range.
1500 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1502 struct intel_uncore uncore;
1504 struct i915_virtual_gpu vgpu;
1506 struct intel_gvt *gvt;
1508 struct intel_wopcm wopcm;
1510 struct intel_huc huc;
1511 struct intel_guc guc;
1513 struct intel_csr csr;
1515 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1517 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1518 * controller on different i2c buses. */
1519 struct mutex gmbus_mutex;
1522 * Base address of where the gmbus and gpio blocks are located (either
1523 * on PCH or on SoC for platforms without PCH).
1527 /* MMIO base address for MIPI regs */
1534 wait_queue_head_t gmbus_wait_queue;
1536 struct pci_dev *bridge_dev;
1537 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1538 /* Context used internally to idle the GPU and setup initial state */
1539 struct i915_gem_context *kernel_context;
1540 /* Context only to be used for injecting preemption commands */
1541 struct i915_gem_context *preempt_context;
1542 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1543 [MAX_ENGINE_INSTANCE + 1];
1545 struct resource mch_res;
1547 /* protects the irq masks */
1548 spinlock_t irq_lock;
1550 bool display_irqs_enabled;
1552 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1553 struct pm_qos_request pm_qos;
1555 /* Sideband mailbox protection */
1556 struct mutex sb_lock;
1557 struct pm_qos_request sb_qos;
1559 /** Cached value of IMR to avoid reads in updating the bitfield */
1562 u32 de_irq_mask[I915_MAX_PIPES];
1569 u32 pipestat_irq_mask[I915_MAX_PIPES];
1571 struct i915_hotplug hotplug;
1572 struct intel_fbc fbc;
1573 struct i915_drrs drrs;
1574 struct intel_opregion opregion;
1575 struct intel_vbt_data vbt;
1577 bool preserve_bios_swizzle;
1580 struct intel_overlay *overlay;
1582 /* backlight registers and fields in struct intel_panel */
1583 struct mutex backlight_lock;
1586 bool no_aux_handshake;
1588 /* protects panel power sequencer state */
1589 struct mutex pps_mutex;
1591 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1592 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1594 unsigned int fsb_freq, mem_freq, is_ddr3;
1595 unsigned int skl_preferred_vco_freq;
1596 unsigned int max_cdclk_freq;
1598 unsigned int max_dotclk_freq;
1599 unsigned int rawclk_freq;
1600 unsigned int hpll_freq;
1601 unsigned int fdi_pll_freq;
1602 unsigned int czclk_freq;
1606 * The current logical cdclk state.
1607 * See intel_atomic_state.cdclk.logical
1609 * For reading holding any crtc lock is sufficient,
1610 * for writing must hold all of them.
1612 struct intel_cdclk_state logical;
1614 * The current actual cdclk state.
1615 * See intel_atomic_state.cdclk.actual
1617 struct intel_cdclk_state actual;
1618 /* The current hardware cdclk state */
1619 struct intel_cdclk_state hw;
1621 int force_min_cdclk;
1625 * wq - Driver workqueue for GEM.
1627 * NOTE: Work items scheduled here are not allowed to grab any modeset
1628 * locks, for otherwise the flushing done in the pageflip code will
1629 * result in deadlocks.
1631 struct workqueue_struct *wq;
1633 /* ordered wq for modesets */
1634 struct workqueue_struct *modeset_wq;
1636 /* Display functions */
1637 struct drm_i915_display_funcs display;
1639 /* PCH chipset type */
1640 enum intel_pch pch_type;
1641 unsigned short pch_id;
1643 unsigned long quirks;
1645 struct drm_atomic_state *modeset_restore_state;
1646 struct drm_modeset_acquire_ctx reset_ctx;
1648 struct i915_ggtt ggtt; /* VM representing the global address space */
1650 struct i915_gem_mm mm;
1651 DECLARE_HASHTABLE(mm_structs, 7);
1652 struct mutex mm_lock;
1654 struct intel_ppat ppat;
1656 /* Kernel Modesetting */
1658 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1659 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1661 #ifdef CONFIG_DEBUG_FS
1662 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1665 /* dpll and cdclk state is protected by connection_mutex */
1666 int num_shared_dpll;
1667 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1668 const struct intel_dpll_mgr *dpll_mgr;
1671 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1672 * Must be global rather than per dpll, because on some platforms
1673 * plls share registers.
1675 struct mutex dpll_lock;
1677 unsigned int active_crtcs;
1678 /* minimum acceptable cdclk for each pipe */
1679 int min_cdclk[I915_MAX_PIPES];
1680 /* minimum acceptable voltage level for each pipe */
1681 u8 min_voltage_level[I915_MAX_PIPES];
1683 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1685 struct i915_wa_list gt_wa_list;
1687 struct i915_frontbuffer_tracking fb_tracking;
1689 struct intel_atomic_helper {
1690 struct llist_head free_list;
1691 struct work_struct free_work;
1696 bool mchbar_need_disable;
1698 struct intel_l3_parity l3_parity;
1702 * Cannot be determined by PCIID. You must always read a register.
1706 /* gen6+ GT PM state */
1707 struct intel_gen6_power_mgmt gt_pm;
1709 /* ilk-only ips/rps state. Everything in here is protected by the global
1710 * mchdev_lock in intel_pm.c */
1711 struct intel_ilk_power_mgmt ips;
1713 struct i915_power_domains power_domains;
1715 struct i915_psr psr;
1717 struct i915_gpu_error gpu_error;
1719 struct drm_i915_gem_object *vlv_pctx;
1721 /* list of fbdev register on this device */
1722 struct intel_fbdev *fbdev;
1723 struct work_struct fbdev_suspend_work;
1725 struct drm_property *broadcast_rgb_property;
1726 struct drm_property *force_audio_property;
1728 /* hda/i915 audio component */
1729 struct i915_audio_component *audio_component;
1730 bool audio_component_registered;
1732 * av_mutex - mutex for audio/video sync
1735 struct mutex av_mutex;
1736 int audio_power_refcount;
1740 struct list_head list;
1741 struct llist_head free_list;
1742 struct work_struct free_work;
1744 /* The hw wants to have a stable context identifier for the
1745 * lifetime of the context (for OA, PASID, faults, etc).
1746 * This is limited in execlists to 21 bits.
1749 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1750 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1751 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1752 struct list_head hw_id_list;
1757 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1758 u32 chv_phy_control;
1760 * Shadows for CHV DPLL_MD regs to keep the state
1761 * checker somewhat working in the presence hardware
1762 * crappiness (can't read out DPLL_MD for pipes B & C).
1764 u32 chv_dpll_md[I915_MAX_PIPES];
1768 bool power_domains_suspended;
1769 struct i915_suspend_saved_registers regfile;
1770 struct vlv_s0ix_state vlv_s0ix_state;
1773 I915_SAGV_UNKNOWN = 0,
1776 I915_SAGV_NOT_CONTROLLED
1781 * Raw watermark latency values:
1782 * in 0.1us units for WM0,
1783 * in 0.5us units for WM1+.
1792 * Raw watermark memory latency values
1793 * for SKL for all 8 levels
1798 /* current hardware state */
1800 struct ilk_wm_values hw;
1801 struct skl_ddb_values skl_hw;
1802 struct vlv_wm_values vlv;
1803 struct g4x_wm_values g4x;
1809 * Should be held around atomic WM register writing; also
1810 * protects * intel_crtc->wm.active and
1811 * cstate->wm.need_postvbl_update.
1813 struct mutex wm_mutex;
1816 * Set during HW readout of watermarks/DDB. Some platforms
1817 * need to know when we're still using BIOS-provided values
1818 * (which we don't fully trust).
1820 bool distrust_bios_wm;
1829 bool symmetric_memory;
1830 enum intel_dram_type {
1839 struct i915_runtime_pm runtime_pm;
1844 struct kobject *metrics_kobj;
1845 struct ctl_table_header *sysctl_header;
1848 * Lock associated with adding/modifying/removing OA configs
1849 * in dev_priv->perf.metrics_idr.
1851 struct mutex metrics_lock;
1854 * List of dynamic configurations, you need to hold
1855 * dev_priv->perf.metrics_lock to access it.
1857 struct idr metrics_idr;
1860 * Lock associated with anything below within this structure
1861 * except exclusive_stream.
1864 struct list_head streams;
1868 * The stream currently using the OA unit. If accessed
1869 * outside a syscall associated to its file
1870 * descriptor, you need to hold
1871 * dev_priv->drm.struct_mutex.
1873 struct i915_perf_stream *exclusive_stream;
1875 struct intel_context *pinned_ctx;
1876 u32 specific_ctx_id;
1877 u32 specific_ctx_id_mask;
1879 struct hrtimer poll_check_timer;
1880 wait_queue_head_t poll_wq;
1884 * For rate limiting any notifications of spurious
1885 * invalid OA reports
1887 struct ratelimit_state spurious_report_rs;
1890 int period_exponent;
1892 struct i915_oa_config test_config;
1895 struct i915_vma *vma;
1902 * Locks reads and writes to all head/tail state
1904 * Consider: the head and tail pointer state
1905 * needs to be read consistently from a hrtimer
1906 * callback (atomic context) and read() fop
1907 * (user context) with tail pointer updates
1908 * happening in atomic context and head updates
1909 * in user context and the (unlikely)
1910 * possibility of read() errors needing to
1911 * reset all head/tail state.
1913 * Note: Contention or performance aren't
1914 * currently a significant concern here
1915 * considering the relatively low frequency of
1916 * hrtimer callbacks (5ms period) and that
1917 * reads typically only happen in response to a
1918 * hrtimer event and likely complete before the
1921 * Note: This lock is not held *while* reading
1922 * and copying data to userspace so the value
1923 * of head observed in htrimer callbacks won't
1924 * represent any partial consumption of data.
1926 spinlock_t ptr_lock;
1929 * One 'aging' tail pointer and one 'aged'
1930 * tail pointer ready to used for reading.
1932 * Initial values of 0xffffffff are invalid
1933 * and imply that an update is required
1934 * (and should be ignored by an attempted
1942 * Index for the aged tail ready to read()
1945 unsigned int aged_tail_idx;
1948 * A monotonic timestamp for when the current
1949 * aging tail pointer was read; used to
1950 * determine when it is old enough to trust.
1952 u64 aging_timestamp;
1955 * Although we can always read back the head
1956 * pointer register, we prefer to avoid
1957 * trusting the HW state, just to avoid any
1958 * risk that some hardware condition could
1959 * somehow bump the head pointer unpredictably
1960 * and cause us to forward the wrong OA buffer
1961 * data to userspace.
1966 u32 gen7_latched_oastatus1;
1967 u32 ctx_oactxctrl_offset;
1968 u32 ctx_flexeu0_offset;
1971 * The RPT_ID/reason field for Gen8+ includes a bit
1972 * to determine if the CTX ID in the report is valid
1973 * but the specific bit differs between Gen 8 and 9
1975 u32 gen8_valid_ctx_bit;
1977 struct i915_oa_ops ops;
1978 const struct i915_oa_format *oa_formats;
1982 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1984 struct i915_gt_timelines {
1985 struct mutex mutex; /* protects list, tainted by GPU */
1986 struct list_head active_list;
1988 /* Pack multiple timelines' seqnos into the same page */
1989 spinlock_t hwsp_lock;
1990 struct list_head hwsp_free_list;
1993 struct list_head active_rings;
1994 struct list_head closed_vma;
1996 struct intel_wakeref wakeref;
1999 * Is the GPU currently considered idle, or busy executing
2000 * userspace requests? Whilst idle, we allow runtime power
2001 * management to power down the hardware and display clocks.
2002 * In order to reduce the effect on performance, there
2003 * is a slight delay before we do so.
2005 intel_wakeref_t awake;
2007 struct blocking_notifier_head pm_notifications;
2009 ktime_t last_init_time;
2011 struct i915_vma *scratch;
2015 struct notifier_block pm_notifier;
2018 * We leave the user IRQ off as much as possible,
2019 * but this means that requests will finish and never
2020 * be retired once the system goes idle. Set a timer to
2021 * fire periodically while the ring is running. When it
2022 * fires, go retire requests.
2024 struct delayed_work retire_work;
2027 * When we detect an idle GPU, we want to turn on
2028 * powersaving features. So once we see that there
2029 * are no more requests outstanding and no more
2030 * arrive within a small period of time, we fire
2031 * off the idle_work.
2033 struct work_struct idle_work;
2036 /* For i945gm vblank irq vs. C3 workaround */
2038 struct work_struct work;
2039 struct pm_qos_request pm_qos;
2040 u8 c3_disable_latency;
2044 /* perform PHY state sanity checks? */
2045 bool chv_phy_assert[2];
2049 /* Used to save the pipe-to-encoder mapping for audio */
2050 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2052 /* necessary resource sharing with HDMI LPE audio driver. */
2054 struct platform_device *platdev;
2058 struct i915_pmu pmu;
2060 struct i915_hdcp_comp_master *hdcp_master;
2061 bool hdcp_comp_added;
2063 /* Mutex to protect the above hdcp component related values. */
2064 struct mutex hdcp_comp_mutex;
2067 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2068 * will be rejected. Instead look for a better place.
2072 struct dram_dimm_info {
2073 u8 size, width, ranks;
2076 struct dram_channel_info {
2077 struct dram_dimm_info dimm_l, dimm_s;
2082 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2084 return container_of(dev, struct drm_i915_private, drm);
2087 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2089 return to_i915(dev_get_drvdata(kdev));
2092 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2094 return container_of(wopcm, struct drm_i915_private, wopcm);
2097 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2099 return container_of(guc, struct drm_i915_private, guc);
2102 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2104 return container_of(huc, struct drm_i915_private, huc);
2107 static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore)
2109 return container_of(uncore, struct drm_i915_private, uncore);
2112 /* Simple iterator over all initialised engines */
2113 #define for_each_engine(engine__, dev_priv__, id__) \
2115 (id__) < I915_NUM_ENGINES; \
2117 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2119 /* Iterator over subset of engines selected by mask */
2120 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2121 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
2123 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2126 enum hdmi_force_audio {
2127 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2128 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2129 HDMI_AUDIO_AUTO, /* trust EDID */
2130 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2133 #define I915_GTT_OFFSET_NONE ((u32)-1)
2136 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2137 * considered to be the frontbuffer for the given plane interface-wise. This
2138 * doesn't mean that the hw necessarily already scans it out, but that any
2139 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2141 * We have one bit per pipe and per scanout plane type.
2143 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2144 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2145 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2146 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2147 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2149 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2150 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2151 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2152 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2153 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2156 * Optimised SGL iterator for GEM objects
2158 static __always_inline struct sgt_iter {
2159 struct scatterlist *sgp;
2166 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2167 struct sgt_iter s = { .sgp = sgl };
2170 s.max = s.curr = s.sgp->offset;
2171 s.max += s.sgp->length;
2173 s.dma = sg_dma_address(s.sgp);
2175 s.pfn = page_to_pfn(sg_page(s.sgp));
2181 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2184 if (unlikely(sg_is_chain(sg)))
2185 sg = sg_chain_ptr(sg);
2190 * __sg_next - return the next scatterlist entry in a list
2191 * @sg: The current sg entry
2194 * If the entry is the last, return NULL; otherwise, step to the next
2195 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2196 * otherwise just return the pointer to the current element.
2198 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2200 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2204 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2205 * @__dmap: DMA address (output)
2206 * @__iter: 'struct sgt_iter' (iterator state, internal)
2207 * @__sgt: sg_table to iterate over (input)
2209 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2210 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2211 ((__dmap) = (__iter).dma + (__iter).curr); \
2212 (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ? \
2213 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2216 * for_each_sgt_page - iterate over the pages of the given sg_table
2217 * @__pp: page pointer (output)
2218 * @__iter: 'struct sgt_iter' (iterator state, internal)
2219 * @__sgt: sg_table to iterate over (input)
2221 #define for_each_sgt_page(__pp, __iter, __sgt) \
2222 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2223 ((__pp) = (__iter).pfn == 0 ? NULL : \
2224 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2225 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2226 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2228 bool i915_sg_trim(struct sg_table *orig_st);
2230 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2232 unsigned int page_sizes;
2236 GEM_BUG_ON(sg->offset);
2237 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2238 page_sizes |= sg->length;
2245 static inline unsigned int i915_sg_segment_size(void)
2247 unsigned int size = swiotlb_max_segment();
2250 return SCATTERLIST_MAX_SEGMENT;
2252 size = rounddown(size, PAGE_SIZE);
2253 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2254 if (size < PAGE_SIZE)
2260 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
2261 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
2262 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2264 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
2265 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
2267 #define REVID_FOREVER 0xff
2268 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2270 #define INTEL_GEN_MASK(s, e) ( \
2271 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2272 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2273 GENMASK((e) - 1, (s) - 1))
2275 /* Returns true if Gen is in inclusive range [Start, End] */
2276 #define IS_GEN_RANGE(dev_priv, s, e) \
2277 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
2279 #define IS_GEN(dev_priv, n) \
2280 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2281 INTEL_INFO(dev_priv)->gen == (n))
2284 * Return true if revision is in range [since,until] inclusive.
2286 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2288 #define IS_REVID(p, since, until) \
2289 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2291 static __always_inline unsigned int
2292 __platform_mask_index(const struct intel_runtime_info *info,
2293 enum intel_platform p)
2295 const unsigned int pbits =
2296 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2298 /* Expand the platform_mask array if this fails. */
2299 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
2300 pbits * ARRAY_SIZE(info->platform_mask));
2305 static __always_inline unsigned int
2306 __platform_mask_bit(const struct intel_runtime_info *info,
2307 enum intel_platform p)
2309 const unsigned int pbits =
2310 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
2312 return p % pbits + INTEL_SUBPLATFORM_BITS;
2316 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
2318 const unsigned int pi = __platform_mask_index(info, p);
2320 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
2323 static __always_inline bool
2324 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
2326 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2327 const unsigned int pi = __platform_mask_index(info, p);
2328 const unsigned int pb = __platform_mask_bit(info, p);
2330 BUILD_BUG_ON(!__builtin_constant_p(p));
2332 return info->platform_mask[pi] & BIT(pb);
2335 static __always_inline bool
2336 IS_SUBPLATFORM(const struct drm_i915_private *i915,
2337 enum intel_platform p, unsigned int s)
2339 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
2340 const unsigned int pi = __platform_mask_index(info, p);
2341 const unsigned int pb = __platform_mask_bit(info, p);
2342 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
2343 const u32 mask = info->platform_mask[pi];
2345 BUILD_BUG_ON(!__builtin_constant_p(p));
2346 BUILD_BUG_ON(!__builtin_constant_p(s));
2347 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
2349 /* Shift and test on the MSB position so sign flag can be used. */
2350 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
2353 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
2355 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2356 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2357 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2358 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2359 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2360 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2361 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2362 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2363 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2364 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2365 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2366 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2367 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2368 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2369 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2370 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
2371 #define IS_IRONLAKE_M(dev_priv) \
2372 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
2373 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2374 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2375 INTEL_INFO(dev_priv)->gt == 1)
2376 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2377 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2378 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2379 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2380 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2381 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2382 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2383 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2384 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2385 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2386 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2387 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
2388 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2389 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2390 #define IS_BDW_ULT(dev_priv) \
2391 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
2392 #define IS_BDW_ULX(dev_priv) \
2393 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
2394 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2395 INTEL_INFO(dev_priv)->gt == 3)
2396 #define IS_HSW_ULT(dev_priv) \
2397 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
2398 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2399 INTEL_INFO(dev_priv)->gt == 3)
2400 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
2401 INTEL_INFO(dev_priv)->gt == 1)
2402 /* ULX machines are also considered ULT. */
2403 #define IS_HSW_ULX(dev_priv) \
2404 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
2405 #define IS_SKL_ULT(dev_priv) \
2406 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
2407 #define IS_SKL_ULX(dev_priv) \
2408 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
2409 #define IS_KBL_ULT(dev_priv) \
2410 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
2411 #define IS_KBL_ULX(dev_priv) \
2412 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
2413 #define IS_AML_ULX(dev_priv) \
2414 (IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
2415 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
2416 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2417 INTEL_INFO(dev_priv)->gt == 2)
2418 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2419 INTEL_INFO(dev_priv)->gt == 3)
2420 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2421 INTEL_INFO(dev_priv)->gt == 4)
2422 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2423 INTEL_INFO(dev_priv)->gt == 2)
2424 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2425 INTEL_INFO(dev_priv)->gt == 3)
2426 #define IS_CFL_ULT(dev_priv) \
2427 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2428 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2429 INTEL_INFO(dev_priv)->gt == 2)
2430 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2431 INTEL_INFO(dev_priv)->gt == 3)
2432 #define IS_CNL_WITH_PORT_F(dev_priv) \
2433 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
2434 #define IS_ICL_WITH_PORT_F(dev_priv) \
2435 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2437 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2439 #define SKL_REVID_A0 0x0
2440 #define SKL_REVID_B0 0x1
2441 #define SKL_REVID_C0 0x2
2442 #define SKL_REVID_D0 0x3
2443 #define SKL_REVID_E0 0x4
2444 #define SKL_REVID_F0 0x5
2445 #define SKL_REVID_G0 0x6
2446 #define SKL_REVID_H0 0x7
2448 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2450 #define BXT_REVID_A0 0x0
2451 #define BXT_REVID_A1 0x1
2452 #define BXT_REVID_B0 0x3
2453 #define BXT_REVID_B_LAST 0x8
2454 #define BXT_REVID_C0 0x9
2456 #define IS_BXT_REVID(dev_priv, since, until) \
2457 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2459 #define KBL_REVID_A0 0x0
2460 #define KBL_REVID_B0 0x1
2461 #define KBL_REVID_C0 0x2
2462 #define KBL_REVID_D0 0x3
2463 #define KBL_REVID_E0 0x4
2465 #define IS_KBL_REVID(dev_priv, since, until) \
2466 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2468 #define GLK_REVID_A0 0x0
2469 #define GLK_REVID_A1 0x1
2471 #define IS_GLK_REVID(dev_priv, since, until) \
2472 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2474 #define CNL_REVID_A0 0x0
2475 #define CNL_REVID_B0 0x1
2476 #define CNL_REVID_C0 0x2
2478 #define IS_CNL_REVID(p, since, until) \
2479 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2481 #define ICL_REVID_A0 0x0
2482 #define ICL_REVID_A2 0x1
2483 #define ICL_REVID_B0 0x3
2484 #define ICL_REVID_B2 0x4
2485 #define ICL_REVID_C0 0x5
2487 #define IS_ICL_REVID(p, since, until) \
2488 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2490 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2491 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2492 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2494 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2496 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
2497 unsigned int first__ = (first); \
2498 unsigned int count__ = (count); \
2499 (INTEL_INFO(dev_priv)->engine_mask & \
2500 GENMASK(first__ + count__ - 1, first__)) >> first__; \
2502 #define VDBOX_MASK(dev_priv) \
2503 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
2504 #define VEBOX_MASK(dev_priv) \
2505 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
2507 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
2508 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
2509 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
2510 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2511 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2513 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
2515 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2516 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2517 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2518 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2519 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2520 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2522 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2524 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2525 #define HAS_PPGTT(dev_priv) \
2526 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2527 #define HAS_FULL_PPGTT(dev_priv) \
2528 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2530 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2531 GEM_BUG_ON((sizes) == 0); \
2532 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2535 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
2536 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2537 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2539 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2540 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2542 /* WaRsDisableCoarsePowerGating:skl,cnl */
2543 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2544 (IS_CANNONLAKE(dev_priv) || \
2545 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2547 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2548 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2549 IS_GEMINILAKE(dev_priv) || \
2550 IS_KABYLAKE(dev_priv))
2552 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2553 * rows, which changed the alignment requirements and fence programming.
2555 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2556 !(IS_I915G(dev_priv) || \
2557 IS_I915GM(dev_priv)))
2558 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
2559 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
2561 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2562 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
2563 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2565 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2567 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
2569 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2570 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2571 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
2572 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2574 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
2575 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
2576 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2578 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
2580 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
2582 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2583 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2585 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
2588 * For now, anything with a GuC requires uCode loading, and then supports
2589 * command submission once loaded. But these are logically independent
2590 * properties, so we have separate macros to test them.
2592 #define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
2593 #define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
2594 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2595 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2597 /* For now, anything with a GuC has also HuC */
2598 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2599 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2601 /* Having a GuC is not the same as using a GuC */
2602 #define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
2603 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
2604 #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
2606 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2608 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2609 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2610 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2611 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2612 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2613 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2614 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2615 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2616 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2617 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2618 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2619 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2620 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2621 #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
2622 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2623 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2624 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2625 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2627 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2628 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2629 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2630 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2631 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2632 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2633 #define HAS_PCH_LPT_LP(dev_priv) \
2634 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2635 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2636 #define HAS_PCH_LPT_H(dev_priv) \
2637 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2638 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2639 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2640 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2641 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2642 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2644 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2646 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2648 /* DPF == dynamic parity feature */
2649 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2650 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2651 2 : HAS_L3_DPF(dev_priv))
2653 #define GT_FREQUENCY_MULTIPLIER 50
2654 #define GEN9_FREQ_SCALER 3
2656 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2658 #include "i915_trace.h"
2660 static inline bool intel_vtd_active(void)
2662 #ifdef CONFIG_INTEL_IOMMU
2663 if (intel_iommu_gfx_mapped)
2669 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2671 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2675 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2677 return IS_BROXTON(dev_priv) && intel_vtd_active();
2682 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2683 const char *fmt, ...);
2685 #define i915_report_error(dev_priv, fmt, ...) \
2686 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2688 #ifdef CONFIG_COMPAT
2689 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2692 #define i915_compat_ioctl NULL
2694 extern const struct dev_pm_ops i915_pm_ops;
2696 extern int i915_driver_load(struct pci_dev *pdev,
2697 const struct pci_device_id *ent);
2698 extern void i915_driver_unload(struct drm_device *dev);
2700 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2701 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2702 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2703 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2704 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2705 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2706 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2708 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2710 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2712 unsigned long delay;
2714 if (unlikely(!i915_modparams.enable_hangcheck))
2717 /* Don't continually defer the hangcheck so that it is always run at
2718 * least once after work has been scheduled on any ring. Otherwise,
2719 * we will ignore a hung ring if a second ring is kept busy.
2722 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2723 queue_delayed_work(system_long_wq,
2724 &dev_priv->gpu_error.hangcheck_work, delay);
2727 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2729 return dev_priv->gvt;
2732 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2734 return dev_priv->vgpu.active;
2738 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2739 struct drm_file *file_priv);
2740 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2741 struct drm_file *file_priv);
2742 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2743 struct drm_file *file_priv);
2744 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2745 struct drm_file *file_priv);
2746 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2747 struct drm_file *file_priv);
2748 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2749 struct drm_file *file_priv);
2750 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2751 struct drm_file *file_priv);
2752 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2753 struct drm_file *file_priv);
2754 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2755 struct drm_file *file_priv);
2756 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2757 struct drm_file *file_priv);
2758 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2759 struct drm_file *file);
2760 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2761 struct drm_file *file);
2762 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2763 struct drm_file *file_priv);
2764 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2765 struct drm_file *file_priv);
2766 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2767 struct drm_file *file_priv);
2768 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2769 struct drm_file *file_priv);
2770 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2771 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2772 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2773 struct drm_file *file);
2774 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2775 struct drm_file *file_priv);
2776 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2777 struct drm_file *file_priv);
2778 void i915_gem_sanitize(struct drm_i915_private *i915);
2779 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2780 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2781 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2782 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2783 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2785 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2786 const struct drm_i915_gem_object_ops *ops);
2787 struct drm_i915_gem_object *
2788 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2789 struct drm_i915_gem_object *
2790 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2791 const void *data, size_t size);
2792 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2793 void i915_gem_free_object(struct drm_gem_object *obj);
2795 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2797 if (!atomic_read(&i915->mm.free_count))
2800 /* A single pass should suffice to release all the freed objects (along
2801 * most call paths) , but be a little more paranoid in that freeing
2802 * the objects does take a little amount of time, during which the rcu
2803 * callbacks could have added new objects into the freed list, and
2804 * armed the work again.
2808 } while (flush_work(&i915->mm.free_work));
2811 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2814 * Similar to objects above (see i915_gem_drain_freed-objects), in
2815 * general we have workers that are armed by RCU and then rearm
2816 * themselves in their callbacks. To be paranoid, we need to
2817 * drain the workqueue a second time after waiting for the RCU
2818 * grace period so that we catch work queued via RCU from the first
2819 * pass. As neither drain_workqueue() nor flush_workqueue() report
2820 * a result, we make an assumption that we only don't require more
2821 * than 3 passes to catch all _recursive_ RCU delayed work.
2827 i915_gem_drain_freed_objects(i915);
2829 drain_workqueue(i915->wq);
2832 struct i915_vma * __must_check
2833 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2834 const struct i915_ggtt_view *view,
2839 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2840 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2842 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2844 static inline int __sg_page_count(const struct scatterlist *sg)
2846 return sg->length >> PAGE_SHIFT;
2849 struct scatterlist *
2850 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2851 unsigned int n, unsigned int *offset);
2854 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2858 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2862 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2865 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2866 struct sg_table *pages,
2867 unsigned int sg_page_sizes);
2868 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2870 static inline int __must_check
2871 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2873 might_lock(&obj->mm.lock);
2875 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2878 return __i915_gem_object_get_pages(obj);
2882 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2884 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2888 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2890 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2892 atomic_inc(&obj->mm.pages_pin_count);
2896 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
2898 return atomic_read(&obj->mm.pages_pin_count);
2902 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2904 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2905 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
2907 atomic_dec(&obj->mm.pages_pin_count);
2911 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2913 __i915_gem_object_unpin_pages(obj);
2916 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock/struct_mutex */
2918 I915_MM_SHRINKER /* called "recursively" from direct-reclaim-esque */
2921 int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2922 enum i915_mm_subclass subclass);
2923 void __i915_gem_object_truncate(struct drm_i915_gem_object *obj);
2925 enum i915_map_type {
2928 #define I915_MAP_OVERRIDE BIT(31)
2929 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
2930 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
2933 static inline enum i915_map_type
2934 i915_coherent_map_type(struct drm_i915_private *i915)
2936 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2940 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
2941 * @obj: the object to map into kernel address space
2942 * @type: the type of mapping, used to select pgprot_t
2944 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
2945 * pages and then returns a contiguous mapping of the backing storage into
2946 * the kernel address space. Based on the @type of mapping, the PTE will be
2947 * set to either WriteBack or WriteCombine (via pgprot_t).
2949 * The caller is responsible for calling i915_gem_object_unpin_map() when the
2950 * mapping is no longer required.
2952 * Returns the pointer through which to access the mapped object, or an
2953 * ERR_PTR() on error.
2955 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2956 enum i915_map_type type);
2958 void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
2959 unsigned long offset,
2960 unsigned long size);
2961 static inline void i915_gem_object_flush_map(struct drm_i915_gem_object *obj)
2963 __i915_gem_object_flush_map(obj, 0, obj->base.size);
2967 * i915_gem_object_unpin_map - releases an earlier mapping
2968 * @obj: the object to unmap
2970 * After pinning the object and mapping its pages, once you are finished
2971 * with your access, call i915_gem_object_unpin_map() to release the pin
2972 * upon the mapping. Once the pin count reaches zero, that mapping may be
2975 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
2977 i915_gem_object_unpin_pages(obj);
2980 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2981 unsigned int *needs_clflush);
2982 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
2983 unsigned int *needs_clflush);
2984 #define CLFLUSH_BEFORE BIT(0)
2985 #define CLFLUSH_AFTER BIT(1)
2986 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
2989 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
2991 i915_gem_object_unpin_pages(obj);
2994 static inline int __must_check
2995 i915_mutex_lock_interruptible(struct drm_device *dev)
2997 return mutex_lock_interruptible(&dev->struct_mutex);
3000 int i915_gem_dumb_create(struct drm_file *file_priv,
3001 struct drm_device *dev,
3002 struct drm_mode_create_dumb *args);
3003 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3004 u32 handle, u64 *offset);
3005 int i915_gem_mmap_gtt_version(void);
3007 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3008 struct drm_i915_gem_object *new,
3009 unsigned frontbuffer_bits);
3011 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3013 static inline bool __i915_wedged(struct i915_gpu_error *error)
3015 return unlikely(test_bit(I915_WEDGED, &error->flags));
3018 static inline bool i915_reset_failed(struct drm_i915_private *i915)
3020 return __i915_wedged(&i915->gpu_error);
3023 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3025 return READ_ONCE(error->reset_count);
3028 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3029 struct intel_engine_cs *engine)
3031 return READ_ONCE(error->reset_engine_count[engine->id]);
3034 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3035 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3037 void i915_gem_init_mmio(struct drm_i915_private *i915);
3038 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3039 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3040 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3041 void i915_gem_fini(struct drm_i915_private *dev_priv);
3042 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3043 unsigned int flags, long timeout);
3044 void i915_gem_suspend(struct drm_i915_private *dev_priv);
3045 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3046 void i915_gem_resume(struct drm_i915_private *dev_priv);
3047 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3048 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3051 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3053 const struct i915_sched_attr *attr);
3054 #define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
3057 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3059 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3061 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3062 struct i915_vma * __must_check
3063 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3065 const struct i915_ggtt_view *view,
3066 unsigned int flags);
3067 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3068 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3070 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3071 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3073 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3074 enum i915_cache_level cache_level);
3076 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3077 struct dma_buf *dma_buf);
3079 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3080 struct drm_gem_object *gem_obj, int flags);
3082 static inline struct i915_hw_ppgtt *
3083 i915_vm_to_ppgtt(struct i915_address_space *vm)
3085 return container_of(vm, struct i915_hw_ppgtt, vm);
3088 /* i915_gem_fence_reg.c */
3089 struct drm_i915_fence_reg *
3090 i915_reserve_fence(struct drm_i915_private *dev_priv);
3091 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3093 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3095 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3096 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3097 struct sg_table *pages);
3098 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3099 struct sg_table *pages);
3101 static inline struct i915_gem_context *
3102 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3104 return idr_find(&file_priv->context_idr, id);
3107 static inline struct i915_gem_context *
3108 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3110 struct i915_gem_context *ctx;
3113 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3114 if (ctx && !kref_get_unless_zero(&ctx->ref))
3121 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3122 struct drm_file *file);
3123 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3124 struct drm_file *file);
3125 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3126 struct drm_file *file);
3127 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3128 struct intel_context *ce,
3131 /* i915_gem_evict.c */
3132 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3133 u64 min_size, u64 alignment,
3134 unsigned cache_level,
3137 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3138 struct drm_mm_node *node,
3139 unsigned int flags);
3140 int i915_gem_evict_vm(struct i915_address_space *vm);
3142 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3144 /* belongs in i915_gem_gtt.h */
3145 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3148 if (INTEL_GEN(dev_priv) < 6)
3149 intel_gtt_chipset_flush();
3152 /* i915_gem_stolen.c */
3153 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3154 struct drm_mm_node *node, u64 size,
3155 unsigned alignment);
3156 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3157 struct drm_mm_node *node, u64 size,
3158 unsigned alignment, u64 start,
3160 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3161 struct drm_mm_node *node);
3162 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3163 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
3164 struct drm_i915_gem_object *
3165 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3166 resource_size_t size);
3167 struct drm_i915_gem_object *
3168 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3169 resource_size_t stolen_offset,
3170 resource_size_t gtt_offset,
3171 resource_size_t size);
3173 /* i915_gem_internal.c */
3174 struct drm_i915_gem_object *
3175 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3178 /* i915_gem_shrinker.c */
3179 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3180 unsigned long target,
3181 unsigned long *nr_scanned,
3183 #define I915_SHRINK_PURGEABLE BIT(0)
3184 #define I915_SHRINK_UNBOUND BIT(1)
3185 #define I915_SHRINK_BOUND BIT(2)
3186 #define I915_SHRINK_ACTIVE BIT(3)
3187 #define I915_SHRINK_VMAPS BIT(4)
3188 #define I915_SHRINK_WRITEBACK BIT(5)
3189 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3190 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3191 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3192 void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
3193 struct mutex *mutex);
3195 /* i915_gem_tiling.c */
3196 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3198 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3200 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3201 i915_gem_object_is_tiled(obj);
3204 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3205 unsigned int tiling, unsigned int stride);
3206 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3207 unsigned int tiling, unsigned int stride);
3209 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3211 /* i915_cmd_parser.c */
3212 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3213 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3214 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3215 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3216 struct drm_i915_gem_object *batch_obj,
3217 struct drm_i915_gem_object *shadow_batch_obj,
3218 u32 batch_start_offset,
3223 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3224 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3225 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3226 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3228 /* i915_suspend.c */
3229 extern int i915_save_state(struct drm_i915_private *dev_priv);
3230 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3233 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3234 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3236 /* intel_device_info.c */
3237 static inline struct intel_device_info *
3238 mkwrite_device_info(struct drm_i915_private *dev_priv)
3240 return (struct intel_device_info *)INTEL_INFO(dev_priv);
3244 extern void intel_modeset_init_hw(struct drm_device *dev);
3245 extern int intel_modeset_init(struct drm_device *dev);
3246 extern void intel_modeset_cleanup(struct drm_device *dev);
3247 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3249 extern void intel_display_resume(struct drm_device *dev);
3250 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3251 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3252 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3253 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3254 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3255 extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
3257 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3260 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3261 struct drm_file *file);
3263 extern struct intel_display_error_state *
3264 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3265 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3266 struct intel_display_error_state *error);
3268 #define __I915_REG_OP(op__, dev_priv__, ...) \
3269 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
3271 #define I915_READ8(reg__) __I915_REG_OP(read8, dev_priv, (reg__))
3272 #define I915_WRITE8(reg__, val__) __I915_REG_OP(write8, dev_priv, (reg__), (val__))
3274 #define I915_READ16(reg__) __I915_REG_OP(read16, dev_priv, (reg__))
3275 #define I915_WRITE16(reg__, val__) __I915_REG_OP(write16, dev_priv, (reg__), (val__))
3276 #define I915_READ16_NOTRACE(reg__) __I915_REG_OP(read16_notrace, dev_priv, (reg__))
3277 #define I915_WRITE16_NOTRACE(reg__, val__) __I915_REG_OP(write16_notrace, dev_priv, (reg__), (val__))
3279 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
3280 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
3281 #define I915_READ_NOTRACE(reg__) __I915_REG_OP(read_notrace, dev_priv, (reg__))
3282 #define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))
3284 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3285 * will be implemented using 2 32-bit writes in an arbitrary order with
3286 * an arbitrary delay between them. This can cause the hardware to
3287 * act upon the intermediate value, possibly leading to corruption and
3288 * machine death. For this reason we do not support I915_WRITE64, or
3289 * dev_priv->uncore.funcs.mmio_writeq.
3291 * When reading a 64-bit value as two 32-bit values, the delay may cause
3292 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3293 * occasionally a 64-bit register does not actualy support a full readq
3294 * and must be read using two 32-bit reads.
3296 * You have been warned.
3298 #define I915_READ64(reg__) __I915_REG_OP(read64, dev_priv, (reg__))
3299 #define I915_READ64_2x32(lower_reg__, upper_reg__) \
3300 __I915_REG_OP(read64_2x32, dev_priv, (lower_reg__), (upper_reg__))
3302 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
3303 #define POSTING_READ16(reg__) __I915_REG_OP(posting_read16, dev_priv, (reg__))
3305 /* These are untraced mmio-accessors that are only valid to be used inside
3306 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3309 * Think twice, and think again, before using these.
3311 * As an example, these accessors can possibly be used between:
3313 * spin_lock_irq(&dev_priv->uncore.lock);
3314 * intel_uncore_forcewake_get__locked();
3318 * intel_uncore_forcewake_put__locked();
3319 * spin_unlock_irq(&dev_priv->uncore.lock);
3322 * Note: some registers may not need forcewake held, so
3323 * intel_uncore_forcewake_{get,put} can be omitted, see
3324 * intel_uncore_forcewake_for_reg().
3326 * Certain architectures will die if the same cacheline is concurrently accessed
3327 * by different clients (e.g. on Ivybridge). Access to registers should
3328 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3329 * a more localised lock guarding all access to that bank of registers.
3331 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
3332 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
3333 #define I915_WRITE64_FW(reg__, val__) __I915_REG_OP(write64_fw, dev_priv, (reg__), (val__))
3334 #define POSTING_READ_FW(reg__) __I915_REG_OP(posting_read_fw, dev_priv, (reg__))
3336 /* "Broadcast RGB" property */
3337 #define INTEL_BROADCAST_RGB_AUTO 0
3338 #define INTEL_BROADCAST_RGB_FULL 1
3339 #define INTEL_BROADCAST_RGB_LIMITED 2
3341 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3342 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3344 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3345 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3346 * perform the operation. To check beforehand, pass in the parameters to
3347 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3348 * you only need to pass in the minor offsets, page-aligned pointers are
3351 * For just checking for SSE4.1, in the foreknowledge that the future use
3352 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3354 #define i915_can_memcpy_from_wc(dst, src, len) \
3355 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3357 #define i915_has_memcpy_from_wc() \
3358 i915_memcpy_from_wc(NULL, NULL, 0)
3361 int remap_io_mapping(struct vm_area_struct *vma,
3362 unsigned long addr, unsigned long pfn, unsigned long size,
3363 struct io_mapping *iomap);
3365 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3367 if (INTEL_GEN(i915) >= 10)
3368 return CNL_HWS_CSB_WRITE_INDEX;
3370 return I915_HWS_CSB_WRITE_INDEX;
3373 static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
3375 return i915_ggtt_offset(i915->gt.scratch);
3378 static inline void add_taint_for_CI(unsigned int taint)
3381 * The system is "ok", just about surviving for the user, but
3382 * CI results are now unreliable as the HW is very suspect.
3383 * CI checks the taint state after every test and will reboot
3384 * the machine if the kernel is tainted.
3386 add_taint(taint, LOCKDEP_STILL_OK);