1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
63 #define pipe_name(p) ((p) + 'A')
71 #define transcoder_name(t) ((t) + 'A')
78 #define plane_name(p) ((p) + 'A')
80 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
90 #define port_name(p) ((p) + 'A')
92 #define I915_NUM_PHYS_VLV 1
104 enum intel_display_power_domain {
108 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
109 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
110 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
111 POWER_DOMAIN_TRANSCODER_A,
112 POWER_DOMAIN_TRANSCODER_B,
113 POWER_DOMAIN_TRANSCODER_C,
114 POWER_DOMAIN_TRANSCODER_EDP,
122 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
124 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
125 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
126 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
127 #define POWER_DOMAIN_TRANSCODER(tran) \
128 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
129 (tran) + POWER_DOMAIN_TRANSCODER_A)
131 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
132 BIT(POWER_DOMAIN_PIPE_A) | \
133 BIT(POWER_DOMAIN_TRANSCODER_EDP))
134 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
135 BIT(POWER_DOMAIN_PIPE_A) | \
136 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
137 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
141 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
142 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
152 #define I915_GEM_GPU_DOMAINS \
153 (I915_GEM_DOMAIN_RENDER | \
154 I915_GEM_DOMAIN_SAMPLER | \
155 I915_GEM_DOMAIN_COMMAND | \
156 I915_GEM_DOMAIN_INSTRUCTION | \
157 I915_GEM_DOMAIN_VERTEX)
159 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
161 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
162 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
163 if ((intel_encoder)->base.crtc == (__crtc))
165 struct drm_i915_private;
168 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
169 /* real shared dpll ids must be >= 0 */
173 #define I915_NUM_PLLS 2
175 struct intel_dpll_hw_state {
182 struct intel_shared_dpll {
183 int refcount; /* count of number of CRTCs sharing this PLL */
184 int active; /* count of number of active CRTCs (i.e. DPMS on) */
185 bool on; /* is the PLL actually active? Disabled during modeset */
187 /* should match the index in the dev_priv->shared_dplls array */
188 enum intel_dpll_id id;
189 struct intel_dpll_hw_state hw_state;
190 void (*mode_set)(struct drm_i915_private *dev_priv,
191 struct intel_shared_dpll *pll);
192 void (*enable)(struct drm_i915_private *dev_priv,
193 struct intel_shared_dpll *pll);
194 void (*disable)(struct drm_i915_private *dev_priv,
195 struct intel_shared_dpll *pll);
196 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
197 struct intel_shared_dpll *pll,
198 struct intel_dpll_hw_state *hw_state);
201 /* Used by dp and fdi links */
202 struct intel_link_m_n {
210 void intel_link_compute_m_n(int bpp, int nlanes,
211 int pixel_clock, int link_clock,
212 struct intel_link_m_n *m_n);
214 struct intel_ddi_plls {
220 /* Interface history:
223 * 1.2: Add Power Management
224 * 1.3: Add vblank support
225 * 1.4: Fix cmdbuffer path, add heap destroy
226 * 1.5: Add vblank pipe configuration
227 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
228 * - Support vertical blank on secondary display pipe
230 #define DRIVER_MAJOR 1
231 #define DRIVER_MINOR 6
232 #define DRIVER_PATCHLEVEL 0
234 #define WATCH_LISTS 0
237 #define I915_GEM_PHYS_CURSOR_0 1
238 #define I915_GEM_PHYS_CURSOR_1 2
239 #define I915_GEM_PHYS_OVERLAY_REGS 3
240 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
242 struct drm_i915_gem_phys_object {
244 struct page **page_list;
245 drm_dma_handle_t *handle;
246 struct drm_i915_gem_object *cur_obj;
249 struct opregion_header;
250 struct opregion_acpi;
251 struct opregion_swsci;
252 struct opregion_asle;
254 struct intel_opregion {
255 struct opregion_header __iomem *header;
256 struct opregion_acpi __iomem *acpi;
257 struct opregion_swsci __iomem *swsci;
258 u32 swsci_gbda_sub_functions;
259 u32 swsci_sbcb_sub_functions;
260 struct opregion_asle __iomem *asle;
262 u32 __iomem *lid_state;
263 struct work_struct asle_work;
265 #define OPREGION_SIZE (8*1024)
267 struct intel_overlay;
268 struct intel_overlay_error_state;
270 struct drm_i915_master_private {
271 drm_local_map_t *sarea;
272 struct _drm_i915_sarea *sarea_priv;
274 #define I915_FENCE_REG_NONE -1
275 #define I915_MAX_NUM_FENCES 32
276 /* 32 fences + sign bit for FENCE_REG_NONE */
277 #define I915_MAX_NUM_FENCE_BITS 6
279 struct drm_i915_fence_reg {
280 struct list_head lru_list;
281 struct drm_i915_gem_object *obj;
285 struct sdvo_device_mapping {
294 struct intel_display_error_state;
296 struct drm_i915_error_state {
304 bool waiting[I915_NUM_RINGS];
305 u32 pipestat[I915_MAX_PIPES];
306 u32 tail[I915_NUM_RINGS];
307 u32 head[I915_NUM_RINGS];
308 u32 ctl[I915_NUM_RINGS];
309 u32 ipeir[I915_NUM_RINGS];
310 u32 ipehr[I915_NUM_RINGS];
311 u32 instdone[I915_NUM_RINGS];
312 u32 acthd[I915_NUM_RINGS];
313 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
314 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
315 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
316 /* our own tracking of ring head and tail */
317 u32 cpu_ring_head[I915_NUM_RINGS];
318 u32 cpu_ring_tail[I915_NUM_RINGS];
319 u32 error; /* gen6+ */
320 u32 err_int; /* gen7 */
321 u32 bbstate[I915_NUM_RINGS];
322 u32 instpm[I915_NUM_RINGS];
323 u32 instps[I915_NUM_RINGS];
324 u32 extra_instdone[I915_NUM_INSTDONE_REG];
325 u32 seqno[I915_NUM_RINGS];
327 u32 fault_reg[I915_NUM_RINGS];
329 u32 faddr[I915_NUM_RINGS];
330 u64 fence[I915_MAX_NUM_FENCES];
332 struct drm_i915_error_ring {
333 struct drm_i915_error_object {
337 } *ringbuffer, *batchbuffer, *ctx;
338 struct drm_i915_error_request {
344 } ring[I915_NUM_RINGS];
345 struct drm_i915_error_buffer {
352 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
359 } **active_bo, **pinned_bo;
360 u32 *active_bo_count, *pinned_bo_count;
361 struct intel_overlay_error_state *overlay;
362 struct intel_display_error_state *display;
363 int hangcheck_score[I915_NUM_RINGS];
364 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
367 struct intel_connector;
368 struct intel_crtc_config;
373 struct drm_i915_display_funcs {
374 bool (*fbc_enabled)(struct drm_device *dev);
375 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
376 void (*disable_fbc)(struct drm_device *dev);
377 int (*get_display_clock_speed)(struct drm_device *dev);
378 int (*get_fifo_size)(struct drm_device *dev, int plane);
380 * find_dpll() - Find the best values for the PLL
381 * @limit: limits for the PLL
382 * @crtc: current CRTC
383 * @target: target frequency in kHz
384 * @refclk: reference clock frequency in kHz
385 * @match_clock: if provided, @best_clock P divider must
386 * match the P divider from @match_clock
387 * used for LVDS downclocking
388 * @best_clock: best PLL values found
390 * Returns true on success, false on failure.
392 bool (*find_dpll)(const struct intel_limit *limit,
393 struct drm_crtc *crtc,
394 int target, int refclk,
395 struct dpll *match_clock,
396 struct dpll *best_clock);
397 void (*update_wm)(struct drm_crtc *crtc);
398 void (*update_sprite_wm)(struct drm_plane *plane,
399 struct drm_crtc *crtc,
400 uint32_t sprite_width, int pixel_size,
401 bool enable, bool scaled);
402 void (*modeset_global_resources)(struct drm_device *dev);
403 /* Returns the active state of the crtc, and if the crtc is active,
404 * fills out the pipe-config with the hw state. */
405 bool (*get_pipe_config)(struct intel_crtc *,
406 struct intel_crtc_config *);
407 int (*crtc_mode_set)(struct drm_crtc *crtc,
409 struct drm_framebuffer *old_fb);
410 void (*crtc_enable)(struct drm_crtc *crtc);
411 void (*crtc_disable)(struct drm_crtc *crtc);
412 void (*off)(struct drm_crtc *crtc);
413 void (*write_eld)(struct drm_connector *connector,
414 struct drm_crtc *crtc,
415 struct drm_display_mode *mode);
416 void (*fdi_link_train)(struct drm_crtc *crtc);
417 void (*init_clock_gating)(struct drm_device *dev);
418 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
419 struct drm_framebuffer *fb,
420 struct drm_i915_gem_object *obj,
422 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
424 void (*hpd_irq_setup)(struct drm_device *dev);
425 /* clock updates for mode set */
427 /* render clock increase/decrease */
428 /* display clock increase/decrease */
429 /* pll clock increase/decrease */
431 int (*setup_backlight)(struct intel_connector *connector);
432 uint32_t (*get_backlight)(struct intel_connector *connector);
433 void (*set_backlight)(struct intel_connector *connector,
435 void (*disable_backlight)(struct intel_connector *connector);
436 void (*enable_backlight)(struct intel_connector *connector);
439 struct intel_uncore_funcs {
440 void (*force_wake_get)(struct drm_i915_private *dev_priv,
442 void (*force_wake_put)(struct drm_i915_private *dev_priv,
445 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
446 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
447 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
448 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
450 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
451 uint8_t val, bool trace);
452 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
453 uint16_t val, bool trace);
454 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
455 uint32_t val, bool trace);
456 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
457 uint64_t val, bool trace);
460 struct intel_uncore {
461 spinlock_t lock; /** lock is also taken in irq contexts. */
463 struct intel_uncore_funcs funcs;
466 unsigned forcewake_count;
468 unsigned fw_rendercount;
469 unsigned fw_mediacount;
471 struct delayed_work force_wake_work;
474 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
475 func(is_mobile) sep \
478 func(is_i945gm) sep \
480 func(need_gfx_hws) sep \
482 func(is_pineview) sep \
483 func(is_broadwater) sep \
484 func(is_crestline) sep \
485 func(is_ivybridge) sep \
486 func(is_valleyview) sep \
487 func(is_haswell) sep \
488 func(is_preliminary) sep \
490 func(has_pipe_cxsr) sep \
491 func(has_hotplug) sep \
492 func(cursor_needs_physical) sep \
493 func(has_overlay) sep \
494 func(overlay_needs_physical) sep \
495 func(supports_tv) sep \
500 #define DEFINE_FLAG(name) u8 name:1
501 #define SEP_SEMICOLON ;
503 struct intel_device_info {
504 u32 display_mmio_offset;
507 u8 ring_mask; /* Rings supported by the HW */
508 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
514 enum i915_cache_level {
516 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
517 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
518 caches, eg sampler/render caches, and the
519 large Last-Level-Cache. LLC is coherent with
520 the CPU, but L3 is only visible to the GPU. */
521 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
524 typedef uint32_t gen6_gtt_pte_t;
527 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
528 * VMA's presence cannot be guaranteed before binding, or after unbinding the
529 * object into/from the address space.
531 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
532 * will always be <= an objects lifetime. So object refcounting should cover us.
535 struct drm_mm_node node;
536 struct drm_i915_gem_object *obj;
537 struct i915_address_space *vm;
539 /** This object's place on the active/inactive lists */
540 struct list_head mm_list;
542 struct list_head vma_link; /* Link in the object's VMA list */
544 /** This vma's place in the batchbuffer or on the eviction list */
545 struct list_head exec_list;
548 * Used for performing relocations during execbuffer insertion.
550 struct hlist_node exec_node;
551 unsigned long exec_handle;
552 struct drm_i915_gem_exec_object2 *exec_entry;
555 * How many users have pinned this object in GTT space. The following
556 * users can each hold at most one reference: pwrite/pread, pin_ioctl
557 * (via user_pin_count), execbuffer (objects are not allowed multiple
558 * times for the same batchbuffer), and the framebuffer code. When
559 * switching/pageflipping, the framebuffer code has at most two buffers
562 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
563 * bits with absolutely no headroom. So use 4 bits. */
564 unsigned int pin_count:4;
565 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
567 /** Unmap an object from an address space. This usually consists of
568 * setting the valid PTE entries to a reserved scratch page. */
569 void (*unbind_vma)(struct i915_vma *vma);
570 /* Map an object into an address space with the given cache flags. */
571 #define GLOBAL_BIND (1<<0)
572 void (*bind_vma)(struct i915_vma *vma,
573 enum i915_cache_level cache_level,
577 struct i915_address_space {
579 struct drm_device *dev;
580 struct list_head global_link;
581 unsigned long start; /* Start offset always 0 for dri2 */
582 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
590 * List of objects currently involved in rendering.
592 * Includes buffers having the contents of their GPU caches
593 * flushed, not necessarily primitives. last_rendering_seqno
594 * represents when the rendering involved will be completed.
596 * A reference is held on the buffer while on this list.
598 struct list_head active_list;
601 * LRU list of objects which are not in the ringbuffer and
602 * are ready to unbind, but are still in the GTT.
604 * last_rendering_seqno is 0 while an object is in this list.
606 * A reference is not held on the buffer while on this list,
607 * as merely being GTT-bound shouldn't prevent its being
608 * freed, and we'll pull it off the list in the free path.
610 struct list_head inactive_list;
612 /* FIXME: Need a more generic return type */
613 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
614 enum i915_cache_level level,
615 bool valid); /* Create a valid PTE */
616 void (*clear_range)(struct i915_address_space *vm,
617 unsigned int first_entry,
618 unsigned int num_entries,
620 void (*insert_entries)(struct i915_address_space *vm,
622 unsigned int first_entry,
623 enum i915_cache_level cache_level);
624 void (*cleanup)(struct i915_address_space *vm);
627 /* The Graphics Translation Table is the way in which GEN hardware translates a
628 * Graphics Virtual Address into a Physical Address. In addition to the normal
629 * collateral associated with any va->pa translations GEN hardware also has a
630 * portion of the GTT which can be mapped by the CPU and remain both coherent
631 * and correct (in cases like swizzling). That region is referred to as GMADR in
635 struct i915_address_space base;
636 size_t stolen_size; /* Total size of stolen memory */
638 unsigned long mappable_end; /* End offset that we can CPU map */
639 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
640 phys_addr_t mappable_base; /* PA of our GMADR */
642 /** "Graphics Stolen Memory" holds the global PTEs */
650 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
651 size_t *stolen, phys_addr_t *mappable_base,
652 unsigned long *mappable_end);
654 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
656 struct i915_hw_ppgtt {
657 struct i915_address_space base;
659 struct drm_mm_node node;
660 unsigned num_pd_entries;
662 struct page **pt_pages;
663 struct page *gen8_pt_pages;
665 struct page *pd_pages;
670 dma_addr_t pd_dma_addr[4];
673 dma_addr_t *pt_dma_addr;
674 dma_addr_t *gen8_pt_dma_addr[4];
677 int (*enable)(struct i915_hw_ppgtt *ppgtt);
678 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
679 struct intel_ring_buffer *ring,
683 struct i915_ctx_hang_stats {
684 /* This context had batch pending when hang was declared */
685 unsigned batch_pending;
687 /* This context had batch active when hang was declared */
688 unsigned batch_active;
690 /* Time when this context was last blamed for a GPU reset */
691 unsigned long guilty_ts;
693 /* This context is banned to submit more work */
697 /* This must match up with the value previously used for execbuf2.rsvd1. */
698 #define DEFAULT_CONTEXT_ID 0
699 struct i915_hw_context {
704 struct drm_i915_file_private *file_priv;
705 struct intel_ring_buffer *last_ring;
706 struct drm_i915_gem_object *obj;
707 struct i915_ctx_hang_stats hang_stats;
708 struct i915_address_space *vm;
710 struct list_head link;
719 struct drm_mm_node *compressed_fb;
720 struct drm_mm_node *compressed_llb;
722 struct intel_fbc_work {
723 struct delayed_work work;
724 struct drm_crtc *crtc;
725 struct drm_framebuffer *fb;
730 FBC_OK, /* FBC is enabled */
731 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
732 FBC_NO_OUTPUT, /* no outputs enabled to compress */
733 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
734 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
735 FBC_MODE_TOO_LARGE, /* mode too large for compression */
736 FBC_BAD_PLANE, /* fbc not supported on plane */
737 FBC_NOT_TILED, /* buffer not tiled */
738 FBC_MULTIPLE_PIPES, /* more than one pipe active */
740 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
750 PCH_NONE = 0, /* No PCH present */
751 PCH_IBX, /* Ibexpeak PCH */
752 PCH_CPT, /* Cougarpoint PCH */
753 PCH_LPT, /* Lynxpoint PCH */
757 enum intel_sbi_destination {
762 #define QUIRK_PIPEA_FORCE (1<<0)
763 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
764 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
767 struct intel_fbc_work;
770 struct i2c_adapter adapter;
774 struct i2c_algo_bit_data bit_algo;
775 struct drm_i915_private *dev_priv;
778 struct i915_suspend_saved_registers {
799 u32 saveTRANS_HTOTAL_A;
800 u32 saveTRANS_HBLANK_A;
801 u32 saveTRANS_HSYNC_A;
802 u32 saveTRANS_VTOTAL_A;
803 u32 saveTRANS_VBLANK_A;
804 u32 saveTRANS_VSYNC_A;
812 u32 savePFIT_PGM_RATIOS;
813 u32 saveBLC_HIST_CTL;
815 u32 saveBLC_PWM_CTL2;
816 u32 saveBLC_HIST_CTL_B;
817 u32 saveBLC_CPU_PWM_CTL;
818 u32 saveBLC_CPU_PWM_CTL2;
831 u32 saveTRANS_HTOTAL_B;
832 u32 saveTRANS_HBLANK_B;
833 u32 saveTRANS_HSYNC_B;
834 u32 saveTRANS_VTOTAL_B;
835 u32 saveTRANS_VBLANK_B;
836 u32 saveTRANS_VSYNC_B;
850 u32 savePP_ON_DELAYS;
851 u32 savePP_OFF_DELAYS;
859 u32 savePFIT_CONTROL;
860 u32 save_palette_a[256];
861 u32 save_palette_b[256];
862 u32 saveDPFC_CB_BASE;
863 u32 saveFBC_CFB_BASE;
866 u32 saveFBC_CONTROL2;
876 u32 saveCACHE_MODE_0;
877 u32 saveMI_ARB_STATE;
888 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
899 u32 savePIPEA_GMCH_DATA_M;
900 u32 savePIPEB_GMCH_DATA_M;
901 u32 savePIPEA_GMCH_DATA_N;
902 u32 savePIPEB_GMCH_DATA_N;
903 u32 savePIPEA_DP_LINK_M;
904 u32 savePIPEB_DP_LINK_M;
905 u32 savePIPEA_DP_LINK_N;
906 u32 savePIPEB_DP_LINK_N;
917 u32 savePCH_DREF_CONTROL;
918 u32 saveDISP_ARB_CTL;
919 u32 savePIPEA_DATA_M1;
920 u32 savePIPEA_DATA_N1;
921 u32 savePIPEA_LINK_M1;
922 u32 savePIPEA_LINK_N1;
923 u32 savePIPEB_DATA_M1;
924 u32 savePIPEB_DATA_N1;
925 u32 savePIPEB_LINK_M1;
926 u32 savePIPEB_LINK_N1;
927 u32 saveMCHBAR_RENDER_STANDBY;
928 u32 savePCH_PORT_HOTPLUG;
931 struct intel_gen6_power_mgmt {
932 /* work and pm_iir are protected by dev_priv->irq_lock */
933 struct work_struct work;
936 /* The below variables an all the rps hw state are protected by
937 * dev->struct mutext. */
947 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
950 struct delayed_work delayed_resume_work;
953 * Protects RPS/RC6 register access and PCU communication.
954 * Must be taken after struct_mutex if nested.
956 struct mutex hw_lock;
959 /* defined intel_pm.c */
960 extern spinlock_t mchdev_lock;
962 struct intel_ilk_power_mgmt {
970 unsigned long last_time1;
971 unsigned long chipset_power;
973 struct timespec last_time2;
974 unsigned long gfx_power;
980 struct drm_i915_gem_object *pwrctx;
981 struct drm_i915_gem_object *renderctx;
984 /* Power well structure for haswell */
985 struct i915_power_well {
988 /* power well enable/disable usage count */
990 unsigned long domains;
992 void (*set)(struct drm_device *dev, struct i915_power_well *power_well,
994 bool (*is_enabled)(struct drm_device *dev,
995 struct i915_power_well *power_well);
998 struct i915_power_domains {
1000 * Power wells needed for initialization at driver init and suspend
1001 * time are on. They are kept on until after the first modeset.
1004 int power_well_count;
1007 int domain_use_count[POWER_DOMAIN_NUM];
1008 struct i915_power_well *power_wells;
1011 struct i915_dri1_state {
1012 unsigned allow_batchbuffer : 1;
1013 u32 __iomem *gfx_hws_cpu_addr;
1024 struct i915_ums_state {
1026 * Flag if the X Server, and thus DRM, is not currently in
1027 * control of the device.
1029 * This is set between LeaveVT and EnterVT. It needs to be
1030 * replaced with a semaphore. It also needs to be
1031 * transitioned away from for kernel modesetting.
1036 #define MAX_L3_SLICES 2
1037 struct intel_l3_parity {
1038 u32 *remap_info[MAX_L3_SLICES];
1039 struct work_struct error_work;
1043 struct i915_gem_mm {
1044 /** Memory allocator for GTT stolen memory */
1045 struct drm_mm stolen;
1046 /** List of all objects in gtt_space. Used to restore gtt
1047 * mappings on resume */
1048 struct list_head bound_list;
1050 * List of objects which are not bound to the GTT (thus
1051 * are idle and not used by the GPU) but still have
1052 * (presumably uncached) pages still attached.
1054 struct list_head unbound_list;
1056 /** Usable portion of the GTT for GEM */
1057 unsigned long stolen_base; /* limited to low memory (32-bit) */
1059 /** PPGTT used for aliasing the PPGTT with the GTT */
1060 struct i915_hw_ppgtt *aliasing_ppgtt;
1062 struct shrinker inactive_shrinker;
1063 bool shrinker_no_lock_stealing;
1065 /** LRU list of objects with fence regs on them. */
1066 struct list_head fence_list;
1069 * We leave the user IRQ off as much as possible,
1070 * but this means that requests will finish and never
1071 * be retired once the system goes idle. Set a timer to
1072 * fire periodically while the ring is running. When it
1073 * fires, go retire requests.
1075 struct delayed_work retire_work;
1078 * When we detect an idle GPU, we want to turn on
1079 * powersaving features. So once we see that there
1080 * are no more requests outstanding and no more
1081 * arrive within a small period of time, we fire
1082 * off the idle_work.
1084 struct delayed_work idle_work;
1087 * Are we in a non-interruptible section of code like
1092 /** Bit 6 swizzling required for X tiling */
1093 uint32_t bit_6_swizzle_x;
1094 /** Bit 6 swizzling required for Y tiling */
1095 uint32_t bit_6_swizzle_y;
1097 /* storage for physical objects */
1098 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1100 /* accounting, useful for userland debugging */
1101 spinlock_t object_stat_lock;
1102 size_t object_memory;
1106 struct drm_i915_error_state_buf {
1115 struct i915_error_state_file_priv {
1116 struct drm_device *dev;
1117 struct drm_i915_error_state *error;
1120 struct i915_gpu_error {
1121 /* For hangcheck timer */
1122 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1123 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1124 /* Hang gpu twice in this window and your context gets banned */
1125 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1127 struct timer_list hangcheck_timer;
1129 /* For reset and error_state handling. */
1131 /* Protected by the above dev->gpu_error.lock. */
1132 struct drm_i915_error_state *first_error;
1133 struct work_struct work;
1136 unsigned long missed_irq_rings;
1139 * State variable controlling the reset flow and count
1141 * This is a counter which gets incremented when reset is triggered,
1142 * and again when reset has been handled. So odd values (lowest bit set)
1143 * means that reset is in progress and even values that
1144 * (reset_counter >> 1):th reset was successfully completed.
1146 * If reset is not completed succesfully, the I915_WEDGE bit is
1147 * set meaning that hardware is terminally sour and there is no
1148 * recovery. All waiters on the reset_queue will be woken when
1151 * This counter is used by the wait_seqno code to notice that reset
1152 * event happened and it needs to restart the entire ioctl (since most
1153 * likely the seqno it waited for won't ever signal anytime soon).
1155 * This is important for lock-free wait paths, where no contended lock
1156 * naturally enforces the correct ordering between the bail-out of the
1157 * waiter and the gpu reset work code.
1159 atomic_t reset_counter;
1161 #define I915_RESET_IN_PROGRESS_FLAG 1
1162 #define I915_WEDGED (1 << 31)
1165 * Waitqueue to signal when the reset has completed. Used by clients
1166 * that wait for dev_priv->mm.wedged to settle.
1168 wait_queue_head_t reset_queue;
1170 /* For gpu hang simulation. */
1171 unsigned int stop_rings;
1173 /* For missed irq/seqno simulation. */
1174 unsigned int test_irq_rings;
1177 enum modeset_restore {
1178 MODESET_ON_LID_OPEN,
1183 struct ddi_vbt_port_info {
1184 uint8_t hdmi_level_shift;
1186 uint8_t supports_dvi:1;
1187 uint8_t supports_hdmi:1;
1188 uint8_t supports_dp:1;
1191 struct intel_vbt_data {
1192 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1193 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1196 unsigned int int_tv_support:1;
1197 unsigned int lvds_dither:1;
1198 unsigned int lvds_vbt:1;
1199 unsigned int int_crt_support:1;
1200 unsigned int lvds_use_ssc:1;
1201 unsigned int display_clock_mode:1;
1202 unsigned int fdi_rx_polarity_inverted:1;
1204 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1209 int edp_preemphasis;
1211 bool edp_initialized;
1214 struct edp_power_seq edp_pps;
1224 union child_device_config *child_dev;
1226 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1229 enum intel_ddb_partitioning {
1231 INTEL_DDB_PART_5_6, /* IVB+ */
1234 struct intel_wm_level {
1242 struct hsw_wm_values {
1243 uint32_t wm_pipe[3];
1245 uint32_t wm_lp_spr[3];
1246 uint32_t wm_linetime[3];
1248 enum intel_ddb_partitioning partitioning;
1252 * This struct tracks the state needed for the Package C8+ feature.
1254 * Package states C8 and deeper are really deep PC states that can only be
1255 * reached when all the devices on the system allow it, so even if the graphics
1256 * device allows PC8+, it doesn't mean the system will actually get to these
1259 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1260 * is disabled and the GPU is idle. When these conditions are met, we manually
1261 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1264 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1265 * the state of some registers, so when we come back from PC8+ we need to
1266 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1267 * need to take care of the registers kept by RC6.
1269 * The interrupt disabling is part of the requirements. We can only leave the
1270 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1271 * can lock the machine.
1273 * Ideally every piece of our code that needs PC8+ disabled would call
1274 * hsw_disable_package_c8, which would increment disable_count and prevent the
1275 * system from reaching PC8+. But we don't have a symmetric way to do this for
1276 * everything, so we have the requirements_met and gpu_idle variables. When we
1277 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1278 * increase it in the opposite case. The requirements_met variable is true when
1279 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1280 * variable is true when the GPU is idle.
1282 * In addition to everything, we only actually enable PC8+ if disable_count
1283 * stays at zero for at least some seconds. This is implemented with the
1284 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1285 * consecutive times when all screens are disabled and some background app
1286 * queries the state of our connectors, or we have some application constantly
1287 * waking up to use the GPU. Only after the enable_work function actually
1288 * enables PC8+ the "enable" variable will become true, which means that it can
1289 * be false even if disable_count is 0.
1291 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1292 * goes back to false exactly before we reenable the IRQs. We use this variable
1293 * to check if someone is trying to enable/disable IRQs while they're supposed
1294 * to be disabled. This shouldn't happen and we'll print some error messages in
1295 * case it happens, but if it actually happens we'll also update the variables
1296 * inside struct regsave so when we restore the IRQs they will contain the
1297 * latest expected values.
1299 * For more, read "Display Sequences for Package C8" on our documentation.
1301 struct i915_package_c8 {
1302 bool requirements_met;
1305 /* Only true after the delayed work task actually enables it. */
1309 struct delayed_work enable_work;
1316 uint32_t gen6_pmimr;
1320 enum intel_pipe_crc_source {
1321 INTEL_PIPE_CRC_SOURCE_NONE,
1322 INTEL_PIPE_CRC_SOURCE_PLANE1,
1323 INTEL_PIPE_CRC_SOURCE_PLANE2,
1324 INTEL_PIPE_CRC_SOURCE_PF,
1325 INTEL_PIPE_CRC_SOURCE_PIPE,
1326 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1327 INTEL_PIPE_CRC_SOURCE_TV,
1328 INTEL_PIPE_CRC_SOURCE_DP_B,
1329 INTEL_PIPE_CRC_SOURCE_DP_C,
1330 INTEL_PIPE_CRC_SOURCE_DP_D,
1331 INTEL_PIPE_CRC_SOURCE_AUTO,
1332 INTEL_PIPE_CRC_SOURCE_MAX,
1335 struct intel_pipe_crc_entry {
1340 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1341 struct intel_pipe_crc {
1343 bool opened; /* exclusive access to the result file */
1344 struct intel_pipe_crc_entry *entries;
1345 enum intel_pipe_crc_source source;
1347 wait_queue_head_t wq;
1350 typedef struct drm_i915_private {
1351 struct drm_device *dev;
1352 struct kmem_cache *slab;
1354 const struct intel_device_info *info;
1356 int relative_constants_mode;
1360 struct intel_uncore uncore;
1362 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1365 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1366 * controller on different i2c buses. */
1367 struct mutex gmbus_mutex;
1370 * Base address of the gmbus and gpio block.
1372 uint32_t gpio_mmio_base;
1374 wait_queue_head_t gmbus_wait_queue;
1376 struct pci_dev *bridge_dev;
1377 struct intel_ring_buffer ring[I915_NUM_RINGS];
1378 uint32_t last_seqno, next_seqno;
1380 drm_dma_handle_t *status_page_dmah;
1381 struct resource mch_res;
1383 atomic_t irq_received;
1385 /* protects the irq masks */
1386 spinlock_t irq_lock;
1388 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1389 struct pm_qos_request pm_qos;
1391 /* DPIO indirect register protection */
1392 struct mutex dpio_lock;
1394 /** Cached value of IMR to avoid reads in updating the bitfield */
1397 u32 de_irq_mask[I915_MAX_PIPES];
1402 struct work_struct hotplug_work;
1403 bool enable_hotplug_processing;
1405 unsigned long hpd_last_jiffies;
1410 HPD_MARK_DISABLED = 2
1412 } hpd_stats[HPD_NUM_PINS];
1414 struct timer_list hotplug_reenable_timer;
1418 struct i915_fbc fbc;
1419 struct intel_opregion opregion;
1420 struct intel_vbt_data vbt;
1423 struct intel_overlay *overlay;
1424 unsigned int sprite_scaling_enabled;
1426 /* backlight registers and fields in struct intel_panel */
1427 spinlock_t backlight_lock;
1430 bool no_aux_handshake;
1432 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1433 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1434 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1436 unsigned int fsb_freq, mem_freq, is_ddr3;
1439 * wq - Driver workqueue for GEM.
1441 * NOTE: Work items scheduled here are not allowed to grab any modeset
1442 * locks, for otherwise the flushing done in the pageflip code will
1443 * result in deadlocks.
1445 struct workqueue_struct *wq;
1447 /* Display functions */
1448 struct drm_i915_display_funcs display;
1450 /* PCH chipset type */
1451 enum intel_pch pch_type;
1452 unsigned short pch_id;
1454 unsigned long quirks;
1456 enum modeset_restore modeset_restore;
1457 struct mutex modeset_restore_lock;
1459 struct list_head vm_list; /* Global list of all address spaces */
1460 struct i915_gtt gtt; /* VMA representing the global address space */
1462 struct i915_gem_mm mm;
1464 /* Kernel Modesetting */
1466 struct sdvo_device_mapping sdvo_mappings[2];
1468 struct drm_crtc *plane_to_crtc_mapping[3];
1469 struct drm_crtc *pipe_to_crtc_mapping[3];
1470 wait_queue_head_t pending_flip_queue;
1472 #ifdef CONFIG_DEBUG_FS
1473 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1476 int num_shared_dpll;
1477 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1478 struct intel_ddi_plls ddi_plls;
1479 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1481 /* Reclocking support */
1482 bool render_reclock_avail;
1483 bool lvds_downclock_avail;
1484 /* indicates the reduced downclock for LVDS*/
1488 bool mchbar_need_disable;
1490 struct intel_l3_parity l3_parity;
1492 /* Cannot be determined by PCIID. You must always read a register. */
1495 /* gen6+ rps state */
1496 struct intel_gen6_power_mgmt rps;
1498 /* ilk-only ips/rps state. Everything in here is protected by the global
1499 * mchdev_lock in intel_pm.c */
1500 struct intel_ilk_power_mgmt ips;
1502 struct i915_power_domains power_domains;
1504 struct i915_psr psr;
1506 struct i915_gpu_error gpu_error;
1508 struct drm_i915_gem_object *vlv_pctx;
1510 #ifdef CONFIG_DRM_I915_FBDEV
1511 /* list of fbdev register on this device */
1512 struct intel_fbdev *fbdev;
1516 * The console may be contended at resume, but we don't
1517 * want it to block on it.
1519 struct work_struct console_resume_work;
1521 struct drm_property *broadcast_rgb_property;
1522 struct drm_property *force_audio_property;
1524 uint32_t hw_context_size;
1525 struct list_head context_list;
1529 struct i915_suspend_saved_registers regfile;
1533 * Raw watermark latency values:
1534 * in 0.1us units for WM0,
1535 * in 0.5us units for WM1+.
1538 uint16_t pri_latency[5];
1540 uint16_t spr_latency[5];
1542 uint16_t cur_latency[5];
1544 /* current hardware state */
1545 struct hsw_wm_values hw;
1548 struct i915_package_c8 pc8;
1550 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1552 struct i915_dri1_state dri1;
1553 /* Old ums support infrastructure, same warning applies. */
1554 struct i915_ums_state ums;
1555 } drm_i915_private_t;
1557 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1559 return dev->dev_private;
1562 /* Iterate over initialised rings */
1563 #define for_each_ring(ring__, dev_priv__, i__) \
1564 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1565 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1567 enum hdmi_force_audio {
1568 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1569 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1570 HDMI_AUDIO_AUTO, /* trust EDID */
1571 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1574 #define I915_GTT_OFFSET_NONE ((u32)-1)
1576 struct drm_i915_gem_object_ops {
1577 /* Interface between the GEM object and its backing storage.
1578 * get_pages() is called once prior to the use of the associated set
1579 * of pages before to binding them into the GTT, and put_pages() is
1580 * called after we no longer need them. As we expect there to be
1581 * associated cost with migrating pages between the backing storage
1582 * and making them available for the GPU (e.g. clflush), we may hold
1583 * onto the pages after they are no longer referenced by the GPU
1584 * in case they may be used again shortly (for example migrating the
1585 * pages to a different memory domain within the GTT). put_pages()
1586 * will therefore most likely be called when the object itself is
1587 * being released or under memory pressure (where we attempt to
1588 * reap pages for the shrinker).
1590 int (*get_pages)(struct drm_i915_gem_object *);
1591 void (*put_pages)(struct drm_i915_gem_object *);
1594 struct drm_i915_gem_object {
1595 struct drm_gem_object base;
1597 const struct drm_i915_gem_object_ops *ops;
1599 /** List of VMAs backed by this object */
1600 struct list_head vma_list;
1602 /** Stolen memory for this object, instead of being backed by shmem. */
1603 struct drm_mm_node *stolen;
1604 struct list_head global_list;
1606 struct list_head ring_list;
1607 /** Used in execbuf to temporarily hold a ref */
1608 struct list_head obj_exec_link;
1611 * This is set if the object is on the active lists (has pending
1612 * rendering and so a non-zero seqno), and is not set if it i s on
1613 * inactive (ready to be unbound) list.
1615 unsigned int active:1;
1618 * This is set if the object has been written to since last bound
1621 unsigned int dirty:1;
1624 * Fence register bits (if any) for this object. Will be set
1625 * as needed when mapped into the GTT.
1626 * Protected by dev->struct_mutex.
1628 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1631 * Advice: are the backing pages purgeable?
1633 unsigned int madv:2;
1636 * Current tiling mode for the object.
1638 unsigned int tiling_mode:2;
1640 * Whether the tiling parameters for the currently associated fence
1641 * register have changed. Note that for the purposes of tracking
1642 * tiling changes we also treat the unfenced register, the register
1643 * slot that the object occupies whilst it executes a fenced
1644 * command (such as BLT on gen2/3), as a "fence".
1646 unsigned int fence_dirty:1;
1649 * Is the object at the current location in the gtt mappable and
1650 * fenceable? Used to avoid costly recalculations.
1652 unsigned int map_and_fenceable:1;
1655 * Whether the current gtt mapping needs to be mappable (and isn't just
1656 * mappable by accident). Track pin and fault separate for a more
1657 * accurate mappable working set.
1659 unsigned int fault_mappable:1;
1660 unsigned int pin_mappable:1;
1661 unsigned int pin_display:1;
1664 * Is the GPU currently using a fence to access this buffer,
1666 unsigned int pending_fenced_gpu_access:1;
1667 unsigned int fenced_gpu_access:1;
1669 unsigned int cache_level:3;
1671 unsigned int has_aliasing_ppgtt_mapping:1;
1672 unsigned int has_global_gtt_mapping:1;
1673 unsigned int has_dma_mapping:1;
1675 struct sg_table *pages;
1676 int pages_pin_count;
1678 /* prime dma-buf support */
1679 void *dma_buf_vmapping;
1682 struct intel_ring_buffer *ring;
1684 /** Breadcrumb of last rendering to the buffer. */
1685 uint32_t last_read_seqno;
1686 uint32_t last_write_seqno;
1687 /** Breadcrumb of last fenced GPU access to the buffer. */
1688 uint32_t last_fenced_seqno;
1690 /** Current tiling stride for the object, if it's tiled. */
1693 /** References from framebuffers, locks out tiling changes. */
1694 unsigned long framebuffer_references;
1696 /** Record of address bit 17 of each page at last unbind. */
1697 unsigned long *bit_17;
1699 /** User space pin count and filp owning the pin */
1700 unsigned long user_pin_count;
1701 struct drm_file *pin_filp;
1703 /** for phy allocated objects */
1704 struct drm_i915_gem_phys_object *phys_obj;
1706 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1708 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1711 * Request queue structure.
1713 * The request queue allows us to note sequence numbers that have been emitted
1714 * and may be associated with active buffers to be retired.
1716 * By keeping this list, we can avoid having to do questionable
1717 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1718 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1720 struct drm_i915_gem_request {
1721 /** On Which ring this request was generated */
1722 struct intel_ring_buffer *ring;
1724 /** GEM sequence number associated with this request. */
1727 /** Position in the ringbuffer of the start of the request */
1730 /** Position in the ringbuffer of the end of the request */
1733 /** Context related to this request */
1734 struct i915_hw_context *ctx;
1736 /** Batch buffer related to this request if any */
1737 struct drm_i915_gem_object *batch_obj;
1739 /** Time at which this request was emitted, in jiffies. */
1740 unsigned long emitted_jiffies;
1742 /** global list entry for this request */
1743 struct list_head list;
1745 struct drm_i915_file_private *file_priv;
1746 /** file_priv list entry for this request */
1747 struct list_head client_list;
1750 struct drm_i915_file_private {
1751 struct drm_i915_private *dev_priv;
1755 struct list_head request_list;
1756 struct delayed_work idle_work;
1758 struct idr context_idr;
1760 struct i915_hw_context *private_default_ctx;
1761 atomic_t rps_wait_boost;
1764 #define INTEL_INFO(dev) (to_i915(dev)->info)
1766 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1767 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1768 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1769 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1770 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1771 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1772 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1773 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1774 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1775 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1776 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1777 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1778 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1779 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1780 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1781 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1782 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1783 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1784 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1785 (dev)->pdev->device == 0x0152 || \
1786 (dev)->pdev->device == 0x015a)
1787 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1788 (dev)->pdev->device == 0x0106 || \
1789 (dev)->pdev->device == 0x010A)
1790 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1791 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1792 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1793 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1794 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1795 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1796 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1797 (((dev)->pdev->device & 0xf) == 0x2 || \
1798 ((dev)->pdev->device & 0xf) == 0x6 || \
1799 ((dev)->pdev->device & 0xf) == 0xe))
1800 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1801 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1802 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1803 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1804 ((dev)->pdev->device & 0x00F0) == 0x0020)
1805 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1808 * The genX designation typically refers to the render engine, so render
1809 * capability related checks should use IS_GEN, while display and other checks
1810 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1813 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1814 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1815 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1816 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1817 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1818 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1819 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1821 #define RENDER_RING (1<<RCS)
1822 #define BSD_RING (1<<VCS)
1823 #define BLT_RING (1<<BCS)
1824 #define VEBOX_RING (1<<VECS)
1825 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1826 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1827 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1828 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1829 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1830 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1832 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1833 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
1834 #define USES_ALIASING_PPGTT(dev) intel_enable_ppgtt(dev, false)
1836 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1837 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1839 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1840 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1842 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1843 * rows, which changed the alignment requirements and fence programming.
1845 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1847 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1848 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1849 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1850 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1851 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1853 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1854 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1855 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1857 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1859 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1860 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1861 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1862 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
1864 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1865 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1866 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1867 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1868 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1869 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1871 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1872 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1873 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1874 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1875 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1876 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1878 /* DPF == dynamic parity feature */
1879 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1880 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1882 #define GT_FREQUENCY_MULTIPLIER 50
1884 #include "i915_trace.h"
1886 extern const struct drm_ioctl_desc i915_ioctls[];
1887 extern int i915_max_ioctl;
1888 extern unsigned int i915_fbpercrtc __always_unused;
1889 extern int i915_panel_ignore_lid __read_mostly;
1890 extern unsigned int i915_powersave __read_mostly;
1891 extern int i915_semaphores __read_mostly;
1892 extern unsigned int i915_lvds_downclock __read_mostly;
1893 extern int i915_lvds_channel_mode __read_mostly;
1894 extern int i915_panel_use_ssc __read_mostly;
1895 extern int i915_vbt_sdvo_panel_type __read_mostly;
1896 extern int i915_enable_rc6 __read_mostly;
1897 extern int i915_enable_fbc __read_mostly;
1898 extern bool i915_enable_hangcheck __read_mostly;
1899 extern int i915_enable_ppgtt __read_mostly;
1900 extern int i915_enable_psr __read_mostly;
1901 extern unsigned int i915_preliminary_hw_support __read_mostly;
1902 extern int i915_disable_power_well __read_mostly;
1903 extern int i915_enable_ips __read_mostly;
1904 extern bool i915_fastboot __read_mostly;
1905 extern int i915_enable_pc8 __read_mostly;
1906 extern int i915_pc8_timeout __read_mostly;
1907 extern bool i915_prefault_disable __read_mostly;
1909 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1910 extern int i915_resume(struct drm_device *dev);
1911 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1912 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1915 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1916 extern void i915_kernel_lost_context(struct drm_device * dev);
1917 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1918 extern int i915_driver_unload(struct drm_device *);
1919 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1920 extern void i915_driver_lastclose(struct drm_device * dev);
1921 extern void i915_driver_preclose(struct drm_device *dev,
1922 struct drm_file *file_priv);
1923 extern void i915_driver_postclose(struct drm_device *dev,
1924 struct drm_file *file_priv);
1925 extern int i915_driver_device_is_agp(struct drm_device * dev);
1926 #ifdef CONFIG_COMPAT
1927 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1930 extern int i915_emit_box(struct drm_device *dev,
1931 struct drm_clip_rect *box,
1933 extern int intel_gpu_reset(struct drm_device *dev);
1934 extern int i915_reset(struct drm_device *dev);
1935 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1936 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1937 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1938 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1940 extern void intel_console_resume(struct work_struct *work);
1943 void i915_queue_hangcheck(struct drm_device *dev);
1944 void i915_handle_error(struct drm_device *dev, bool wedged);
1946 extern void intel_irq_init(struct drm_device *dev);
1947 extern void intel_hpd_init(struct drm_device *dev);
1949 extern void intel_uncore_sanitize(struct drm_device *dev);
1950 extern void intel_uncore_early_sanitize(struct drm_device *dev);
1951 extern void intel_uncore_init(struct drm_device *dev);
1952 extern void intel_uncore_check_errors(struct drm_device *dev);
1953 extern void intel_uncore_fini(struct drm_device *dev);
1956 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1959 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1962 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1963 struct drm_file *file_priv);
1964 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1965 struct drm_file *file_priv);
1966 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1967 struct drm_file *file_priv);
1968 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1969 struct drm_file *file_priv);
1970 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1971 struct drm_file *file_priv);
1972 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1973 struct drm_file *file_priv);
1974 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1975 struct drm_file *file_priv);
1976 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1977 struct drm_file *file_priv);
1978 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1979 struct drm_file *file_priv);
1980 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1981 struct drm_file *file_priv);
1982 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1983 struct drm_file *file_priv);
1984 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1985 struct drm_file *file_priv);
1986 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1987 struct drm_file *file_priv);
1988 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1989 struct drm_file *file);
1990 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1991 struct drm_file *file);
1992 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1993 struct drm_file *file_priv);
1994 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1995 struct drm_file *file_priv);
1996 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1997 struct drm_file *file_priv);
1998 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1999 struct drm_file *file_priv);
2000 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2001 struct drm_file *file_priv);
2002 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2003 struct drm_file *file_priv);
2004 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2005 struct drm_file *file_priv);
2006 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2007 struct drm_file *file_priv);
2008 void i915_gem_load(struct drm_device *dev);
2009 void *i915_gem_object_alloc(struct drm_device *dev);
2010 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2011 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2012 const struct drm_i915_gem_object_ops *ops);
2013 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2015 void i915_gem_free_object(struct drm_gem_object *obj);
2016 void i915_gem_vma_destroy(struct i915_vma *vma);
2018 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2019 struct i915_address_space *vm,
2021 bool map_and_fenceable,
2023 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2024 int __must_check i915_vma_unbind(struct i915_vma *vma);
2025 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
2026 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2027 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2028 void i915_gem_lastclose(struct drm_device *dev);
2030 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2031 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2033 struct sg_page_iter sg_iter;
2035 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2036 return sg_page_iter_page(&sg_iter);
2040 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2042 BUG_ON(obj->pages == NULL);
2043 obj->pages_pin_count++;
2045 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2047 BUG_ON(obj->pages_pin_count == 0);
2048 obj->pages_pin_count--;
2051 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2052 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2053 struct intel_ring_buffer *to);
2054 void i915_vma_move_to_active(struct i915_vma *vma,
2055 struct intel_ring_buffer *ring);
2056 int i915_gem_dumb_create(struct drm_file *file_priv,
2057 struct drm_device *dev,
2058 struct drm_mode_create_dumb *args);
2059 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2060 uint32_t handle, uint64_t *offset);
2062 * Returns true if seq1 is later than seq2.
2065 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2067 return (int32_t)(seq1 - seq2) >= 0;
2070 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2071 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2072 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2073 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2076 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2078 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2079 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2080 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2087 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2089 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2090 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2091 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2092 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2096 bool i915_gem_retire_requests(struct drm_device *dev);
2097 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2098 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2099 bool interruptible);
2100 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2102 return unlikely(atomic_read(&error->reset_counter)
2103 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2106 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2108 return atomic_read(&error->reset_counter) & I915_WEDGED;
2111 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2113 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2116 void i915_gem_reset(struct drm_device *dev);
2117 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2118 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2119 int __must_check i915_gem_init(struct drm_device *dev);
2120 int __must_check i915_gem_init_hw(struct drm_device *dev);
2121 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2122 void i915_gem_init_swizzling(struct drm_device *dev);
2123 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2124 int __must_check i915_gpu_idle(struct drm_device *dev);
2125 int __must_check i915_gem_suspend(struct drm_device *dev);
2126 int __i915_add_request(struct intel_ring_buffer *ring,
2127 struct drm_file *file,
2128 struct drm_i915_gem_object *batch_obj,
2130 #define i915_add_request(ring, seqno) \
2131 __i915_add_request(ring, NULL, NULL, seqno)
2132 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2134 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2136 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2139 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2141 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2143 struct intel_ring_buffer *pipelined);
2144 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2145 int i915_gem_attach_phys_object(struct drm_device *dev,
2146 struct drm_i915_gem_object *obj,
2149 void i915_gem_detach_phys_object(struct drm_device *dev,
2150 struct drm_i915_gem_object *obj);
2151 void i915_gem_free_all_phys_object(struct drm_device *dev);
2152 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2153 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2156 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2158 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2159 int tiling_mode, bool fenced);
2161 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2162 enum i915_cache_level cache_level);
2164 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2165 struct dma_buf *dma_buf);
2167 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2168 struct drm_gem_object *gem_obj, int flags);
2170 void i915_gem_restore_fences(struct drm_device *dev);
2172 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2173 struct i915_address_space *vm);
2174 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2175 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2176 struct i915_address_space *vm);
2177 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2178 struct i915_address_space *vm);
2179 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2180 struct i915_address_space *vm);
2182 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2183 struct i915_address_space *vm);
2185 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2186 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2187 struct i915_vma *vma;
2188 list_for_each_entry(vma, &obj->vma_list, vma_link)
2189 if (vma->pin_count > 0)
2194 /* Some GGTT VM helpers */
2195 #define obj_to_ggtt(obj) \
2196 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2197 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2199 struct i915_address_space *ggtt =
2200 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2204 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2206 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2209 static inline unsigned long
2210 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2212 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2215 static inline unsigned long
2216 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2218 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2221 static inline int __must_check
2222 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2224 bool map_and_fenceable,
2227 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
2228 map_and_fenceable, nonblocking);
2231 /* i915_gem_context.c */
2232 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2233 int __must_check i915_gem_context_init(struct drm_device *dev);
2234 void i915_gem_context_fini(struct drm_device *dev);
2235 void i915_gem_context_reset(struct drm_device *dev);
2236 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2237 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2238 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2239 int i915_switch_context(struct intel_ring_buffer *ring,
2240 struct drm_file *file, struct i915_hw_context *to);
2241 struct i915_hw_context *
2242 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2243 void i915_gem_context_free(struct kref *ctx_ref);
2244 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2246 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2247 kref_get(&ctx->ref);
2250 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2252 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2253 kref_put(&ctx->ref, i915_gem_context_free);
2256 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2257 struct drm_file *file);
2258 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2259 struct drm_file *file);
2261 /* i915_gem_evict.c */
2262 int __must_check i915_gem_evict_something(struct drm_device *dev,
2263 struct i915_address_space *vm,
2266 unsigned cache_level,
2269 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2270 int i915_gem_evict_everything(struct drm_device *dev);
2272 /* i915_gem_gtt.c */
2273 void i915_check_and_clear_faults(struct drm_device *dev);
2274 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2275 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2276 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2277 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2278 void i915_gem_init_global_gtt(struct drm_device *dev);
2279 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2280 unsigned long mappable_end, unsigned long end);
2281 int i915_gem_gtt_init(struct drm_device *dev);
2282 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2284 if (INTEL_INFO(dev)->gen < 6)
2285 intel_gtt_chipset_flush();
2287 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
2288 static inline bool intel_enable_ppgtt(struct drm_device *dev, bool full)
2290 if (i915_enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
2295 #ifdef CONFIG_INTEL_IOMMU
2296 /* Disable ppgtt on SNB if VT-d is on. */
2297 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
2298 DRM_INFO("Disabling PPGTT because VT-d is on\n");
2303 return HAS_ALIASING_PPGTT(dev);
2306 static inline void ppgtt_release(struct kref *kref)
2308 struct i915_hw_ppgtt *ppgtt = container_of(kref, struct i915_hw_ppgtt, ref);
2309 struct drm_device *dev = ppgtt->base.dev;
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311 struct i915_address_space *vm = &ppgtt->base;
2313 if (ppgtt == dev_priv->mm.aliasing_ppgtt ||
2314 (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) {
2315 ppgtt->base.cleanup(&ppgtt->base);
2320 * Make sure vmas are unbound before we take down the drm_mm
2322 * FIXME: Proper refcounting should take care of this, this shouldn't be
2325 if (!list_empty(&vm->active_list)) {
2326 struct i915_vma *vma;
2328 list_for_each_entry(vma, &vm->active_list, mm_list)
2329 if (WARN_ON(list_empty(&vma->vma_link) ||
2330 list_is_singular(&vma->vma_link)))
2333 i915_gem_evict_vm(&ppgtt->base, true);
2335 i915_gem_retire_requests(dev);
2336 i915_gem_evict_vm(&ppgtt->base, false);
2339 ppgtt->base.cleanup(&ppgtt->base);
2342 /* i915_gem_stolen.c */
2343 int i915_gem_init_stolen(struct drm_device *dev);
2344 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2345 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2346 void i915_gem_cleanup_stolen(struct drm_device *dev);
2347 struct drm_i915_gem_object *
2348 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2349 struct drm_i915_gem_object *
2350 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2354 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2356 /* i915_gem_tiling.c */
2357 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2359 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2361 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2362 obj->tiling_mode != I915_TILING_NONE;
2365 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2366 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2367 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2369 /* i915_gem_debug.c */
2371 int i915_verify_lists(struct drm_device *dev);
2373 #define i915_verify_lists(dev) 0
2376 /* i915_debugfs.c */
2377 int i915_debugfs_init(struct drm_minor *minor);
2378 void i915_debugfs_cleanup(struct drm_minor *minor);
2379 #ifdef CONFIG_DEBUG_FS
2380 void intel_display_crc_init(struct drm_device *dev);
2382 static inline void intel_display_crc_init(struct drm_device *dev) {}
2385 /* i915_gpu_error.c */
2387 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2388 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2389 const struct i915_error_state_file_priv *error);
2390 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2391 size_t count, loff_t pos);
2392 static inline void i915_error_state_buf_release(
2393 struct drm_i915_error_state_buf *eb)
2397 void i915_capture_error_state(struct drm_device *dev);
2398 void i915_error_state_get(struct drm_device *dev,
2399 struct i915_error_state_file_priv *error_priv);
2400 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2401 void i915_destroy_error_state(struct drm_device *dev);
2403 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2404 const char *i915_cache_level_str(int type);
2406 /* i915_suspend.c */
2407 extern int i915_save_state(struct drm_device *dev);
2408 extern int i915_restore_state(struct drm_device *dev);
2411 void i915_save_display_reg(struct drm_device *dev);
2412 void i915_restore_display_reg(struct drm_device *dev);
2415 void i915_setup_sysfs(struct drm_device *dev_priv);
2416 void i915_teardown_sysfs(struct drm_device *dev_priv);
2419 extern int intel_setup_gmbus(struct drm_device *dev);
2420 extern void intel_teardown_gmbus(struct drm_device *dev);
2421 static inline bool intel_gmbus_is_port_valid(unsigned port)
2423 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2426 extern struct i2c_adapter *intel_gmbus_get_adapter(
2427 struct drm_i915_private *dev_priv, unsigned port);
2428 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2429 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2430 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2432 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2434 extern void intel_i2c_reset(struct drm_device *dev);
2436 /* intel_opregion.c */
2437 struct intel_encoder;
2438 extern int intel_opregion_setup(struct drm_device *dev);
2440 extern void intel_opregion_init(struct drm_device *dev);
2441 extern void intel_opregion_fini(struct drm_device *dev);
2442 extern void intel_opregion_asle_intr(struct drm_device *dev);
2443 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2445 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2448 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2449 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2450 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2452 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2457 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2465 extern void intel_register_dsm_handler(void);
2466 extern void intel_unregister_dsm_handler(void);
2468 static inline void intel_register_dsm_handler(void) { return; }
2469 static inline void intel_unregister_dsm_handler(void) { return; }
2470 #endif /* CONFIG_ACPI */
2473 extern void intel_modeset_init_hw(struct drm_device *dev);
2474 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2475 extern void intel_modeset_init(struct drm_device *dev);
2476 extern void intel_modeset_gem_init(struct drm_device *dev);
2477 extern void intel_modeset_cleanup(struct drm_device *dev);
2478 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2479 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2480 bool force_restore);
2481 extern void i915_redisable_vga(struct drm_device *dev);
2482 extern bool intel_fbc_enabled(struct drm_device *dev);
2483 extern void intel_disable_fbc(struct drm_device *dev);
2484 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2485 extern void intel_init_pch_refclk(struct drm_device *dev);
2486 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2487 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2488 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2489 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2490 extern void intel_detect_pch(struct drm_device *dev);
2491 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2492 extern int intel_enable_rc6(const struct drm_device *dev);
2494 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2495 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2496 struct drm_file *file);
2497 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2498 struct drm_file *file);
2501 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2502 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2503 struct intel_overlay_error_state *error);
2505 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2506 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2507 struct drm_device *dev,
2508 struct intel_display_error_state *error);
2510 /* On SNB platform, before reading ring registers forcewake bit
2511 * must be set to prevent GT core from power down and stale values being
2514 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2515 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2517 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2518 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2520 /* intel_sideband.c */
2521 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2522 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2523 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2524 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2525 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2526 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2527 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2528 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2529 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2530 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2531 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2532 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2533 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2534 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2535 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2536 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2537 enum intel_sbi_destination destination);
2538 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2539 enum intel_sbi_destination destination);
2541 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2542 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2544 void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2545 void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2547 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2548 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2549 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2550 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2551 ((reg) >= 0x2E000 && (reg) < 0x30000))
2553 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2554 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2555 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2556 ((reg) >= 0x30000 && (reg) < 0x40000))
2558 #define FORCEWAKE_RENDER (1 << 0)
2559 #define FORCEWAKE_MEDIA (1 << 1)
2560 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2563 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2564 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2566 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2567 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2568 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2569 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2571 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2572 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2573 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2574 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2576 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2577 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2579 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2580 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2582 /* "Broadcast RGB" property */
2583 #define INTEL_BROADCAST_RGB_AUTO 0
2584 #define INTEL_BROADCAST_RGB_FULL 1
2585 #define INTEL_BROADCAST_RGB_LIMITED 2
2587 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2589 if (HAS_PCH_SPLIT(dev))
2590 return CPU_VGACNTRL;
2591 else if (IS_VALLEYVIEW(dev))
2592 return VLV_VGACNTRL;
2597 static inline void __user *to_user_ptr(u64 address)
2599 return (void __user *)(uintptr_t)address;
2602 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2604 unsigned long j = msecs_to_jiffies(m);
2606 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2609 static inline unsigned long
2610 timespec_to_jiffies_timeout(const struct timespec *value)
2612 unsigned long j = timespec_to_jiffies(value);
2614 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);