1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain {
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
98 POWER_DOMAIN_TRANSCODER_A,
99 POWER_DOMAIN_TRANSCODER_B,
100 POWER_DOMAIN_TRANSCODER_C,
101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
112 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct drm_i915_private;
138 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
143 #define I915_NUM_PLLS 2
145 struct intel_dpll_hw_state {
152 struct intel_shared_dpll {
153 int refcount; /* count of number of CRTCs sharing this PLL */
154 int active; /* count of number of active CRTCs (i.e. DPMS on) */
155 bool on; /* is the PLL actually active? Disabled during modeset */
157 /* should match the index in the dev_priv->shared_dplls array */
158 enum intel_dpll_id id;
159 struct intel_dpll_hw_state hw_state;
160 void (*mode_set)(struct drm_i915_private *dev_priv,
161 struct intel_shared_dpll *pll);
162 void (*enable)(struct drm_i915_private *dev_priv,
163 struct intel_shared_dpll *pll);
164 void (*disable)(struct drm_i915_private *dev_priv,
165 struct intel_shared_dpll *pll);
166 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
167 struct intel_shared_dpll *pll,
168 struct intel_dpll_hw_state *hw_state);
171 /* Used by dp and fdi links */
172 struct intel_link_m_n {
180 void intel_link_compute_m_n(int bpp, int nlanes,
181 int pixel_clock, int link_clock,
182 struct intel_link_m_n *m_n);
184 struct intel_ddi_plls {
190 /* Interface history:
193 * 1.2: Add Power Management
194 * 1.3: Add vblank support
195 * 1.4: Fix cmdbuffer path, add heap destroy
196 * 1.5: Add vblank pipe configuration
197 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
198 * - Support vertical blank on secondary display pipe
200 #define DRIVER_MAJOR 1
201 #define DRIVER_MINOR 6
202 #define DRIVER_PATCHLEVEL 0
204 #define WATCH_COHERENCY 0
205 #define WATCH_LISTS 0
208 #define I915_GEM_PHYS_CURSOR_0 1
209 #define I915_GEM_PHYS_CURSOR_1 2
210 #define I915_GEM_PHYS_OVERLAY_REGS 3
211 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
213 struct drm_i915_gem_phys_object {
215 struct page **page_list;
216 drm_dma_handle_t *handle;
217 struct drm_i915_gem_object *cur_obj;
220 struct opregion_header;
221 struct opregion_acpi;
222 struct opregion_swsci;
223 struct opregion_asle;
225 struct intel_opregion {
226 struct opregion_header __iomem *header;
227 struct opregion_acpi __iomem *acpi;
228 struct opregion_swsci __iomem *swsci;
229 struct opregion_asle __iomem *asle;
231 u32 __iomem *lid_state;
233 #define OPREGION_SIZE (8*1024)
235 struct intel_overlay;
236 struct intel_overlay_error_state;
238 struct drm_i915_master_private {
239 drm_local_map_t *sarea;
240 struct _drm_i915_sarea *sarea_priv;
242 #define I915_FENCE_REG_NONE -1
243 #define I915_MAX_NUM_FENCES 32
244 /* 32 fences + sign bit for FENCE_REG_NONE */
245 #define I915_MAX_NUM_FENCE_BITS 6
247 struct drm_i915_fence_reg {
248 struct list_head lru_list;
249 struct drm_i915_gem_object *obj;
253 struct sdvo_device_mapping {
262 struct intel_display_error_state;
264 struct drm_i915_error_state {
272 bool waiting[I915_NUM_RINGS];
273 u32 pipestat[I915_MAX_PIPES];
274 u32 tail[I915_NUM_RINGS];
275 u32 head[I915_NUM_RINGS];
276 u32 ctl[I915_NUM_RINGS];
277 u32 ipeir[I915_NUM_RINGS];
278 u32 ipehr[I915_NUM_RINGS];
279 u32 instdone[I915_NUM_RINGS];
280 u32 acthd[I915_NUM_RINGS];
281 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
282 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
283 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
284 /* our own tracking of ring head and tail */
285 u32 cpu_ring_head[I915_NUM_RINGS];
286 u32 cpu_ring_tail[I915_NUM_RINGS];
287 u32 error; /* gen6+ */
288 u32 err_int; /* gen7 */
289 u32 instpm[I915_NUM_RINGS];
290 u32 instps[I915_NUM_RINGS];
291 u32 extra_instdone[I915_NUM_INSTDONE_REG];
292 u32 seqno[I915_NUM_RINGS];
294 u32 fault_reg[I915_NUM_RINGS];
296 u32 faddr[I915_NUM_RINGS];
297 u64 fence[I915_MAX_NUM_FENCES];
299 struct drm_i915_error_ring {
300 struct drm_i915_error_object {
304 } *ringbuffer, *batchbuffer, *ctx;
305 struct drm_i915_error_request {
311 } ring[I915_NUM_RINGS];
312 struct drm_i915_error_buffer {
319 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
326 } *active_bo, *pinned_bo;
327 u32 active_bo_count, pinned_bo_count;
328 struct intel_overlay_error_state *overlay;
329 struct intel_display_error_state *display;
332 struct intel_crtc_config;
337 struct drm_i915_display_funcs {
338 bool (*fbc_enabled)(struct drm_device *dev);
339 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
340 void (*disable_fbc)(struct drm_device *dev);
341 int (*get_display_clock_speed)(struct drm_device *dev);
342 int (*get_fifo_size)(struct drm_device *dev, int plane);
344 * find_dpll() - Find the best values for the PLL
345 * @limit: limits for the PLL
346 * @crtc: current CRTC
347 * @target: target frequency in kHz
348 * @refclk: reference clock frequency in kHz
349 * @match_clock: if provided, @best_clock P divider must
350 * match the P divider from @match_clock
351 * used for LVDS downclocking
352 * @best_clock: best PLL values found
354 * Returns true on success, false on failure.
356 bool (*find_dpll)(const struct intel_limit *limit,
357 struct drm_crtc *crtc,
358 int target, int refclk,
359 struct dpll *match_clock,
360 struct dpll *best_clock);
361 void (*update_wm)(struct drm_device *dev);
362 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
363 uint32_t sprite_width, int pixel_size,
365 void (*modeset_global_resources)(struct drm_device *dev);
366 /* Returns the active state of the crtc, and if the crtc is active,
367 * fills out the pipe-config with the hw state. */
368 bool (*get_pipe_config)(struct intel_crtc *,
369 struct intel_crtc_config *);
370 void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
371 int (*crtc_mode_set)(struct drm_crtc *crtc,
373 struct drm_framebuffer *old_fb);
374 void (*crtc_enable)(struct drm_crtc *crtc);
375 void (*crtc_disable)(struct drm_crtc *crtc);
376 void (*off)(struct drm_crtc *crtc);
377 void (*write_eld)(struct drm_connector *connector,
378 struct drm_crtc *crtc);
379 void (*fdi_link_train)(struct drm_crtc *crtc);
380 void (*init_clock_gating)(struct drm_device *dev);
381 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
382 struct drm_framebuffer *fb,
383 struct drm_i915_gem_object *obj);
384 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
386 void (*hpd_irq_setup)(struct drm_device *dev);
387 /* clock updates for mode set */
389 /* render clock increase/decrease */
390 /* display clock increase/decrease */
391 /* pll clock increase/decrease */
394 struct drm_i915_gt_funcs {
395 void (*force_wake_get)(struct drm_i915_private *dev_priv);
396 void (*force_wake_put)(struct drm_i915_private *dev_priv);
399 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
400 func(is_mobile) sep \
403 func(is_i945gm) sep \
405 func(need_gfx_hws) sep \
407 func(is_pineview) sep \
408 func(is_broadwater) sep \
409 func(is_crestline) sep \
410 func(is_ivybridge) sep \
411 func(is_valleyview) sep \
412 func(is_haswell) sep \
413 func(has_force_wake) sep \
415 func(has_pipe_cxsr) sep \
416 func(has_hotplug) sep \
417 func(cursor_needs_physical) sep \
418 func(has_overlay) sep \
419 func(overlay_needs_physical) sep \
420 func(supports_tv) sep \
421 func(has_bsd_ring) sep \
422 func(has_blt_ring) sep \
423 func(has_vebox_ring) sep \
428 #define DEFINE_FLAG(name) u8 name:1
429 #define SEP_SEMICOLON ;
431 struct intel_device_info {
432 u32 display_mmio_offset;
435 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
441 enum i915_cache_level {
444 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
447 typedef uint32_t gen6_gtt_pte_t;
449 struct i915_address_space {
451 struct drm_device *dev;
452 unsigned long start; /* Start offset always 0 for dri2 */
453 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
460 /* FIXME: Need a more generic return type */
461 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
462 enum i915_cache_level level);
463 void (*clear_range)(struct i915_address_space *vm,
464 unsigned int first_entry,
465 unsigned int num_entries);
466 void (*insert_entries)(struct i915_address_space *vm,
468 unsigned int first_entry,
469 enum i915_cache_level cache_level);
470 void (*cleanup)(struct i915_address_space *vm);
473 /* The Graphics Translation Table is the way in which GEN hardware translates a
474 * Graphics Virtual Address into a Physical Address. In addition to the normal
475 * collateral associated with any va->pa translations GEN hardware also has a
476 * portion of the GTT which can be mapped by the CPU and remain both coherent
477 * and correct (in cases like swizzling). That region is referred to as GMADR in
481 struct i915_address_space base;
482 size_t stolen_size; /* Total size of stolen memory */
484 unsigned long mappable_end; /* End offset that we can CPU map */
485 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
486 phys_addr_t mappable_base; /* PA of our GMADR */
488 /** "Graphics Stolen Memory" holds the global PTEs */
496 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
497 size_t *stolen, phys_addr_t *mappable_base,
498 unsigned long *mappable_end);
500 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
502 struct i915_hw_ppgtt {
503 struct i915_address_space base;
504 unsigned num_pd_entries;
505 struct page **pt_pages;
507 dma_addr_t *pt_dma_addr;
509 int (*enable)(struct drm_device *dev);
512 struct i915_ctx_hang_stats {
513 /* This context had batch pending when hang was declared */
514 unsigned batch_pending;
516 /* This context had batch active when hang was declared */
517 unsigned batch_active;
520 /* This must match up with the value previously used for execbuf2.rsvd1. */
521 #define DEFAULT_CONTEXT_ID 0
522 struct i915_hw_context {
526 struct drm_i915_file_private *file_priv;
527 struct intel_ring_buffer *ring;
528 struct drm_i915_gem_object *obj;
529 struct i915_ctx_hang_stats hang_stats;
538 struct drm_mm_node *compressed_fb;
539 struct drm_mm_node *compressed_llb;
541 struct intel_fbc_work {
542 struct delayed_work work;
543 struct drm_crtc *crtc;
544 struct drm_framebuffer *fb;
549 FBC_NO_OUTPUT, /* no outputs enabled to compress */
550 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
551 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
552 FBC_MODE_TOO_LARGE, /* mode too large for compression */
553 FBC_BAD_PLANE, /* fbc not supported on plane */
554 FBC_NOT_TILED, /* buffer not tiled */
555 FBC_MULTIPLE_PIPES, /* more than one pipe active */
557 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
563 PCH_NONE = 0, /* No PCH present */
564 PCH_IBX, /* Ibexpeak PCH */
565 PCH_CPT, /* Cougarpoint PCH */
566 PCH_LPT, /* Lynxpoint PCH */
570 enum intel_sbi_destination {
575 #define QUIRK_PIPEA_FORCE (1<<0)
576 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
577 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
580 struct intel_fbc_work;
583 struct i2c_adapter adapter;
587 struct i2c_algo_bit_data bit_algo;
588 struct drm_i915_private *dev_priv;
591 struct i915_suspend_saved_registers {
612 u32 saveTRANS_HTOTAL_A;
613 u32 saveTRANS_HBLANK_A;
614 u32 saveTRANS_HSYNC_A;
615 u32 saveTRANS_VTOTAL_A;
616 u32 saveTRANS_VBLANK_A;
617 u32 saveTRANS_VSYNC_A;
625 u32 savePFIT_PGM_RATIOS;
626 u32 saveBLC_HIST_CTL;
628 u32 saveBLC_PWM_CTL2;
629 u32 saveBLC_CPU_PWM_CTL;
630 u32 saveBLC_CPU_PWM_CTL2;
643 u32 saveTRANS_HTOTAL_B;
644 u32 saveTRANS_HBLANK_B;
645 u32 saveTRANS_HSYNC_B;
646 u32 saveTRANS_VTOTAL_B;
647 u32 saveTRANS_VBLANK_B;
648 u32 saveTRANS_VSYNC_B;
662 u32 savePP_ON_DELAYS;
663 u32 savePP_OFF_DELAYS;
671 u32 savePFIT_CONTROL;
672 u32 save_palette_a[256];
673 u32 save_palette_b[256];
674 u32 saveDPFC_CB_BASE;
675 u32 saveFBC_CFB_BASE;
678 u32 saveFBC_CONTROL2;
688 u32 saveCACHE_MODE_0;
689 u32 saveMI_ARB_STATE;
700 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
711 u32 savePIPEA_GMCH_DATA_M;
712 u32 savePIPEB_GMCH_DATA_M;
713 u32 savePIPEA_GMCH_DATA_N;
714 u32 savePIPEB_GMCH_DATA_N;
715 u32 savePIPEA_DP_LINK_M;
716 u32 savePIPEB_DP_LINK_M;
717 u32 savePIPEA_DP_LINK_N;
718 u32 savePIPEB_DP_LINK_N;
729 u32 savePCH_DREF_CONTROL;
730 u32 saveDISP_ARB_CTL;
731 u32 savePIPEA_DATA_M1;
732 u32 savePIPEA_DATA_N1;
733 u32 savePIPEA_LINK_M1;
734 u32 savePIPEA_LINK_N1;
735 u32 savePIPEB_DATA_M1;
736 u32 savePIPEB_DATA_N1;
737 u32 savePIPEB_LINK_M1;
738 u32 savePIPEB_LINK_N1;
739 u32 saveMCHBAR_RENDER_STANDBY;
740 u32 savePCH_PORT_HOTPLUG;
743 struct intel_gen6_power_mgmt {
744 /* work and pm_iir are protected by dev_priv->irq_lock */
745 struct work_struct work;
748 /* On vlv we need to manually drop to Vmin with a delayed work. */
749 struct delayed_work vlv_work;
751 /* The below variables an all the rps hw state are protected by
752 * dev->struct mutext. */
759 struct delayed_work delayed_resume_work;
762 * Protects RPS/RC6 register access and PCU communication.
763 * Must be taken after struct_mutex if nested.
765 struct mutex hw_lock;
768 /* defined intel_pm.c */
769 extern spinlock_t mchdev_lock;
771 struct intel_ilk_power_mgmt {
779 unsigned long last_time1;
780 unsigned long chipset_power;
782 struct timespec last_time2;
783 unsigned long gfx_power;
789 struct drm_i915_gem_object *pwrctx;
790 struct drm_i915_gem_object *renderctx;
793 /* Power well structure for haswell */
794 struct i915_power_well {
795 struct drm_device *device;
797 /* power well enable/disable usage count */
802 struct i915_dri1_state {
803 unsigned allow_batchbuffer : 1;
804 u32 __iomem *gfx_hws_cpu_addr;
815 struct i915_ums_state {
817 * Flag if the X Server, and thus DRM, is not currently in
818 * control of the device.
820 * This is set between LeaveVT and EnterVT. It needs to be
821 * replaced with a semaphore. It also needs to be
822 * transitioned away from for kernel modesetting.
827 struct intel_l3_parity {
829 struct work_struct error_work;
833 /** Memory allocator for GTT stolen memory */
834 struct drm_mm stolen;
835 /** List of all objects in gtt_space. Used to restore gtt
836 * mappings on resume */
837 struct list_head bound_list;
839 * List of objects which are not bound to the GTT (thus
840 * are idle and not used by the GPU) but still have
841 * (presumably uncached) pages still attached.
843 struct list_head unbound_list;
845 /** Usable portion of the GTT for GEM */
846 unsigned long stolen_base; /* limited to low memory (32-bit) */
848 /** PPGTT used for aliasing the PPGTT with the GTT */
849 struct i915_hw_ppgtt *aliasing_ppgtt;
851 struct shrinker inactive_shrinker;
852 bool shrinker_no_lock_stealing;
855 * List of objects currently involved in rendering.
857 * Includes buffers having the contents of their GPU caches
858 * flushed, not necessarily primitives. last_rendering_seqno
859 * represents when the rendering involved will be completed.
861 * A reference is held on the buffer while on this list.
863 struct list_head active_list;
866 * LRU list of objects which are not in the ringbuffer and
867 * are ready to unbind, but are still in the GTT.
869 * last_rendering_seqno is 0 while an object is in this list.
871 * A reference is not held on the buffer while on this list,
872 * as merely being GTT-bound shouldn't prevent its being
873 * freed, and we'll pull it off the list in the free path.
875 struct list_head inactive_list;
877 /** LRU list of objects with fence regs on them. */
878 struct list_head fence_list;
881 * We leave the user IRQ off as much as possible,
882 * but this means that requests will finish and never
883 * be retired once the system goes idle. Set a timer to
884 * fire periodically while the ring is running. When it
885 * fires, go retire requests.
887 struct delayed_work retire_work;
890 * Are we in a non-interruptible section of code like
895 /** Bit 6 swizzling required for X tiling */
896 uint32_t bit_6_swizzle_x;
897 /** Bit 6 swizzling required for Y tiling */
898 uint32_t bit_6_swizzle_y;
900 /* storage for physical objects */
901 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
903 /* accounting, useful for userland debugging */
904 size_t object_memory;
908 struct drm_i915_error_state_buf {
917 struct i915_error_state_file_priv {
918 struct drm_device *dev;
919 struct drm_i915_error_state *error;
922 struct i915_gpu_error {
923 /* For hangcheck timer */
924 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
925 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
926 struct timer_list hangcheck_timer;
928 /* For reset and error_state handling. */
930 /* Protected by the above dev->gpu_error.lock. */
931 struct drm_i915_error_state *first_error;
932 struct work_struct work;
934 unsigned long last_reset;
937 * State variable and reset counter controlling the reset flow
939 * Upper bits are for the reset counter. This counter is used by the
940 * wait_seqno code to race-free noticed that a reset event happened and
941 * that it needs to restart the entire ioctl (since most likely the
942 * seqno it waited for won't ever signal anytime soon).
944 * This is important for lock-free wait paths, where no contended lock
945 * naturally enforces the correct ordering between the bail-out of the
946 * waiter and the gpu reset work code.
948 * Lowest bit controls the reset state machine: Set means a reset is in
949 * progress. This state will (presuming we don't have any bugs) decay
950 * into either unset (successful reset) or the special WEDGED value (hw
951 * terminally sour). All waiters on the reset_queue will be woken when
954 atomic_t reset_counter;
957 * Special values/flags for reset_counter
959 * Note that the code relies on
960 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
963 #define I915_RESET_IN_PROGRESS_FLAG 1
964 #define I915_WEDGED 0xffffffff
967 * Waitqueue to signal when the reset has completed. Used by clients
968 * that wait for dev_priv->mm.wedged to settle.
970 wait_queue_head_t reset_queue;
972 /* For gpu hang simulation. */
973 unsigned int stop_rings;
976 enum modeset_restore {
982 struct intel_vbt_data {
983 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
984 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
987 unsigned int int_tv_support:1;
988 unsigned int lvds_dither:1;
989 unsigned int lvds_vbt:1;
990 unsigned int int_crt_support:1;
991 unsigned int lvds_use_ssc:1;
992 unsigned int display_clock_mode:1;
993 unsigned int fdi_rx_polarity_inverted:1;
995 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1000 int edp_preemphasis;
1002 bool edp_initialized;
1005 struct edp_power_seq edp_pps;
1010 struct child_device_config *child_dev;
1013 typedef struct drm_i915_private {
1014 struct drm_device *dev;
1015 struct kmem_cache *slab;
1017 const struct intel_device_info *info;
1019 int relative_constants_mode;
1023 struct drm_i915_gt_funcs gt;
1024 /** gt_fifo_count and the subsequent register write are synchronized
1025 * with dev->struct_mutex. */
1026 unsigned gt_fifo_count;
1027 /** forcewake_count is protected by gt_lock */
1028 unsigned forcewake_count;
1029 /** gt_lock is also taken in irq contexts. */
1032 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1035 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1036 * controller on different i2c buses. */
1037 struct mutex gmbus_mutex;
1040 * Base address of the gmbus and gpio block.
1042 uint32_t gpio_mmio_base;
1044 wait_queue_head_t gmbus_wait_queue;
1046 struct pci_dev *bridge_dev;
1047 struct intel_ring_buffer ring[I915_NUM_RINGS];
1048 uint32_t last_seqno, next_seqno;
1050 drm_dma_handle_t *status_page_dmah;
1051 struct resource mch_res;
1053 atomic_t irq_received;
1055 /* protects the irq masks */
1056 spinlock_t irq_lock;
1058 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1059 struct pm_qos_request pm_qos;
1061 /* DPIO indirect register protection */
1062 struct mutex dpio_lock;
1064 /** Cached value of IMR to avoid reads in updating the bitfield */
1068 struct work_struct hotplug_work;
1069 bool enable_hotplug_processing;
1071 unsigned long hpd_last_jiffies;
1076 HPD_MARK_DISABLED = 2
1078 } hpd_stats[HPD_NUM_PINS];
1080 struct timer_list hotplug_reenable_timer;
1084 struct i915_fbc fbc;
1085 struct intel_opregion opregion;
1086 struct intel_vbt_data vbt;
1089 struct intel_overlay *overlay;
1090 unsigned int sprite_scaling_enabled;
1096 spinlock_t lock; /* bl registers and the above bl fields */
1097 struct backlight_device *device;
1101 bool no_aux_handshake;
1103 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1104 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1105 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1107 unsigned int fsb_freq, mem_freq, is_ddr3;
1109 struct workqueue_struct *wq;
1111 /* Display functions */
1112 struct drm_i915_display_funcs display;
1114 /* PCH chipset type */
1115 enum intel_pch pch_type;
1116 unsigned short pch_id;
1118 unsigned long quirks;
1120 enum modeset_restore modeset_restore;
1121 struct mutex modeset_restore_lock;
1123 struct i915_gtt gtt; /* VMA representing the global address space */
1125 struct i915_gem_mm mm;
1127 /* Kernel Modesetting */
1129 struct sdvo_device_mapping sdvo_mappings[2];
1131 struct drm_crtc *plane_to_crtc_mapping[3];
1132 struct drm_crtc *pipe_to_crtc_mapping[3];
1133 wait_queue_head_t pending_flip_queue;
1135 int num_shared_dpll;
1136 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1137 struct intel_ddi_plls ddi_plls;
1139 /* Reclocking support */
1140 bool render_reclock_avail;
1141 bool lvds_downclock_avail;
1142 /* indicates the reduced downclock for LVDS*/
1146 bool mchbar_need_disable;
1148 struct intel_l3_parity l3_parity;
1150 /* Cannot be determined by PCIID. You must always read a register. */
1153 /* gen6+ rps state */
1154 struct intel_gen6_power_mgmt rps;
1156 /* ilk-only ips/rps state. Everything in here is protected by the global
1157 * mchdev_lock in intel_pm.c */
1158 struct intel_ilk_power_mgmt ips;
1160 /* Haswell power well */
1161 struct i915_power_well power_well;
1163 struct i915_gpu_error gpu_error;
1165 struct drm_i915_gem_object *vlv_pctx;
1167 /* list of fbdev register on this device */
1168 struct intel_fbdev *fbdev;
1171 * The console may be contended at resume, but we don't
1172 * want it to block on it.
1174 struct work_struct console_resume_work;
1176 struct drm_property *broadcast_rgb_property;
1177 struct drm_property *force_audio_property;
1179 bool hw_contexts_disabled;
1180 uint32_t hw_context_size;
1184 struct i915_suspend_saved_registers regfile;
1186 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1188 struct i915_dri1_state dri1;
1189 /* Old ums support infrastructure, same warning applies. */
1190 struct i915_ums_state ums;
1191 } drm_i915_private_t;
1193 /* Iterate over initialised rings */
1194 #define for_each_ring(ring__, dev_priv__, i__) \
1195 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1196 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1198 enum hdmi_force_audio {
1199 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1200 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1201 HDMI_AUDIO_AUTO, /* trust EDID */
1202 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1205 #define I915_GTT_OFFSET_NONE ((u32)-1)
1207 struct drm_i915_gem_object_ops {
1208 /* Interface between the GEM object and its backing storage.
1209 * get_pages() is called once prior to the use of the associated set
1210 * of pages before to binding them into the GTT, and put_pages() is
1211 * called after we no longer need them. As we expect there to be
1212 * associated cost with migrating pages between the backing storage
1213 * and making them available for the GPU (e.g. clflush), we may hold
1214 * onto the pages after they are no longer referenced by the GPU
1215 * in case they may be used again shortly (for example migrating the
1216 * pages to a different memory domain within the GTT). put_pages()
1217 * will therefore most likely be called when the object itself is
1218 * being released or under memory pressure (where we attempt to
1219 * reap pages for the shrinker).
1221 int (*get_pages)(struct drm_i915_gem_object *);
1222 void (*put_pages)(struct drm_i915_gem_object *);
1225 struct drm_i915_gem_object {
1226 struct drm_gem_object base;
1228 const struct drm_i915_gem_object_ops *ops;
1230 /** Current space allocated to this object in the GTT, if any. */
1231 struct drm_mm_node gtt_space;
1232 /** Stolen memory for this object, instead of being backed by shmem. */
1233 struct drm_mm_node *stolen;
1234 struct list_head global_list;
1236 /** This object's place on the active/inactive lists */
1237 struct list_head ring_list;
1238 struct list_head mm_list;
1239 /** This object's place in the batchbuffer or on the eviction list */
1240 struct list_head exec_list;
1243 * This is set if the object is on the active lists (has pending
1244 * rendering and so a non-zero seqno), and is not set if it i s on
1245 * inactive (ready to be unbound) list.
1247 unsigned int active:1;
1250 * This is set if the object has been written to since last bound
1253 unsigned int dirty:1;
1256 * Fence register bits (if any) for this object. Will be set
1257 * as needed when mapped into the GTT.
1258 * Protected by dev->struct_mutex.
1260 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1263 * Advice: are the backing pages purgeable?
1265 unsigned int madv:2;
1268 * Current tiling mode for the object.
1270 unsigned int tiling_mode:2;
1272 * Whether the tiling parameters for the currently associated fence
1273 * register have changed. Note that for the purposes of tracking
1274 * tiling changes we also treat the unfenced register, the register
1275 * slot that the object occupies whilst it executes a fenced
1276 * command (such as BLT on gen2/3), as a "fence".
1278 unsigned int fence_dirty:1;
1280 /** How many users have pinned this object in GTT space. The following
1281 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1282 * (via user_pin_count), execbuffer (objects are not allowed multiple
1283 * times for the same batchbuffer), and the framebuffer code. When
1284 * switching/pageflipping, the framebuffer code has at most two buffers
1287 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1288 * bits with absolutely no headroom. So use 4 bits. */
1289 unsigned int pin_count:4;
1290 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1293 * Is the object at the current location in the gtt mappable and
1294 * fenceable? Used to avoid costly recalculations.
1296 unsigned int map_and_fenceable:1;
1299 * Whether the current gtt mapping needs to be mappable (and isn't just
1300 * mappable by accident). Track pin and fault separate for a more
1301 * accurate mappable working set.
1303 unsigned int fault_mappable:1;
1304 unsigned int pin_mappable:1;
1307 * Is the GPU currently using a fence to access this buffer,
1309 unsigned int pending_fenced_gpu_access:1;
1310 unsigned int fenced_gpu_access:1;
1312 unsigned int cache_level:2;
1314 unsigned int has_aliasing_ppgtt_mapping:1;
1315 unsigned int has_global_gtt_mapping:1;
1316 unsigned int has_dma_mapping:1;
1318 struct sg_table *pages;
1319 int pages_pin_count;
1321 /* prime dma-buf support */
1322 void *dma_buf_vmapping;
1326 * Used for performing relocations during execbuffer insertion.
1328 struct hlist_node exec_node;
1329 unsigned long exec_handle;
1330 struct drm_i915_gem_exec_object2 *exec_entry;
1332 struct intel_ring_buffer *ring;
1334 /** Breadcrumb of last rendering to the buffer. */
1335 uint32_t last_read_seqno;
1336 uint32_t last_write_seqno;
1337 /** Breadcrumb of last fenced GPU access to the buffer. */
1338 uint32_t last_fenced_seqno;
1340 /** Current tiling stride for the object, if it's tiled. */
1343 /** Record of address bit 17 of each page at last unbind. */
1344 unsigned long *bit_17;
1346 /** User space pin count and filp owning the pin */
1347 uint32_t user_pin_count;
1348 struct drm_file *pin_filp;
1350 /** for phy allocated objects */
1351 struct drm_i915_gem_phys_object *phys_obj;
1353 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1355 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1357 /* Offset of the first PTE pointing to this object */
1358 static inline unsigned long
1359 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
1361 return o->gtt_space.start;
1364 /* Whether or not this object is currently mapped by the translation tables */
1366 i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *o)
1368 return drm_mm_node_allocated(&o->gtt_space);
1371 /* The size used in the translation tables may be larger than the actual size of
1372 * the object on GEN2/GEN3 because of the way tiling is handled. See
1373 * i915_gem_get_gtt_size() for more details.
1375 static inline unsigned long
1376 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o)
1378 return o->gtt_space.size;
1382 i915_gem_obj_ggtt_set_color(struct drm_i915_gem_object *o,
1383 enum i915_cache_level color)
1385 o->gtt_space.color = color;
1389 * Request queue structure.
1391 * The request queue allows us to note sequence numbers that have been emitted
1392 * and may be associated with active buffers to be retired.
1394 * By keeping this list, we can avoid having to do questionable
1395 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1396 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1398 struct drm_i915_gem_request {
1399 /** On Which ring this request was generated */
1400 struct intel_ring_buffer *ring;
1402 /** GEM sequence number associated with this request. */
1405 /** Position in the ringbuffer of the start of the request */
1408 /** Position in the ringbuffer of the end of the request */
1411 /** Context related to this request */
1412 struct i915_hw_context *ctx;
1414 /** Batch buffer related to this request if any */
1415 struct drm_i915_gem_object *batch_obj;
1417 /** Time at which this request was emitted, in jiffies. */
1418 unsigned long emitted_jiffies;
1420 /** global list entry for this request */
1421 struct list_head list;
1423 struct drm_i915_file_private *file_priv;
1424 /** file_priv list entry for this request */
1425 struct list_head client_list;
1428 struct drm_i915_file_private {
1431 struct list_head request_list;
1433 struct idr context_idr;
1435 struct i915_ctx_hang_stats hang_stats;
1438 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1440 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1441 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1442 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1443 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1444 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1445 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1446 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1447 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1448 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1449 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1450 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1451 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1452 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1453 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1454 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1455 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1456 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1457 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1458 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1459 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1460 (dev)->pci_device == 0x0152 || \
1461 (dev)->pci_device == 0x015a)
1462 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1463 (dev)->pci_device == 0x0106 || \
1464 (dev)->pci_device == 0x010A)
1465 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1466 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1467 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1468 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1469 ((dev)->pci_device & 0xFF00) == 0x0A00)
1472 * The genX designation typically refers to the render engine, so render
1473 * capability related checks should use IS_GEN, while display and other checks
1474 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1477 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1478 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1479 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1480 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1481 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1482 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1484 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1485 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1486 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1487 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1488 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1490 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1491 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1493 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1494 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1496 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1497 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1499 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1500 * rows, which changed the alignment requirements and fence programming.
1502 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1504 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1505 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1506 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1507 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1508 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1509 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1510 /* dsparb controlled by hw only */
1511 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1513 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1514 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1515 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1517 #define HAS_IPS(dev) (IS_ULT(dev))
1519 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1521 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1522 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1523 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1525 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1526 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1527 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1528 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1529 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1530 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1532 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1533 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1534 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1535 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1536 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1537 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1539 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1541 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1543 #define GT_FREQUENCY_MULTIPLIER 50
1545 #include "i915_trace.h"
1548 * RC6 is a special power stage which allows the GPU to enter an very
1549 * low-voltage mode when idle, using down to 0V while at this stage. This
1550 * stage is entered automatically when the GPU is idle when RC6 support is
1551 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1553 * There are different RC6 modes available in Intel GPU, which differentiate
1554 * among each other with the latency required to enter and leave RC6 and
1555 * voltage consumed by the GPU in different states.
1557 * The combination of the following flags define which states GPU is allowed
1558 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1559 * RC6pp is deepest RC6. Their support by hardware varies according to the
1560 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1561 * which brings the most power savings; deeper states save more power, but
1562 * require higher latency to switch to and wake up.
1564 #define INTEL_RC6_ENABLE (1<<0)
1565 #define INTEL_RC6p_ENABLE (1<<1)
1566 #define INTEL_RC6pp_ENABLE (1<<2)
1568 extern struct drm_ioctl_desc i915_ioctls[];
1569 extern int i915_max_ioctl;
1570 extern unsigned int i915_fbpercrtc __always_unused;
1571 extern int i915_panel_ignore_lid __read_mostly;
1572 extern unsigned int i915_powersave __read_mostly;
1573 extern int i915_semaphores __read_mostly;
1574 extern unsigned int i915_lvds_downclock __read_mostly;
1575 extern int i915_lvds_channel_mode __read_mostly;
1576 extern int i915_panel_use_ssc __read_mostly;
1577 extern int i915_vbt_sdvo_panel_type __read_mostly;
1578 extern int i915_enable_rc6 __read_mostly;
1579 extern int i915_enable_fbc __read_mostly;
1580 extern bool i915_enable_hangcheck __read_mostly;
1581 extern int i915_enable_ppgtt __read_mostly;
1582 extern unsigned int i915_preliminary_hw_support __read_mostly;
1583 extern int i915_disable_power_well __read_mostly;
1584 extern int i915_enable_ips __read_mostly;
1585 extern bool i915_fastboot __read_mostly;
1587 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1588 extern int i915_resume(struct drm_device *dev);
1589 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1590 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1593 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1594 extern void i915_kernel_lost_context(struct drm_device * dev);
1595 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1596 extern int i915_driver_unload(struct drm_device *);
1597 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1598 extern void i915_driver_lastclose(struct drm_device * dev);
1599 extern void i915_driver_preclose(struct drm_device *dev,
1600 struct drm_file *file_priv);
1601 extern void i915_driver_postclose(struct drm_device *dev,
1602 struct drm_file *file_priv);
1603 extern int i915_driver_device_is_agp(struct drm_device * dev);
1604 #ifdef CONFIG_COMPAT
1605 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1608 extern int i915_emit_box(struct drm_device *dev,
1609 struct drm_clip_rect *box,
1611 extern int intel_gpu_reset(struct drm_device *dev);
1612 extern int i915_reset(struct drm_device *dev);
1613 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1614 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1615 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1616 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1618 extern void intel_console_resume(struct work_struct *work);
1621 void i915_queue_hangcheck(struct drm_device *dev);
1622 void i915_hangcheck_elapsed(unsigned long data);
1623 void i915_handle_error(struct drm_device *dev, bool wedged);
1625 extern void intel_irq_init(struct drm_device *dev);
1626 extern void intel_hpd_init(struct drm_device *dev);
1627 extern void intel_gt_init(struct drm_device *dev);
1628 extern void intel_gt_reset(struct drm_device *dev);
1631 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1634 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1637 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1638 struct drm_file *file_priv);
1639 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1640 struct drm_file *file_priv);
1641 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1642 struct drm_file *file_priv);
1643 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1644 struct drm_file *file_priv);
1645 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1646 struct drm_file *file_priv);
1647 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1648 struct drm_file *file_priv);
1649 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1650 struct drm_file *file_priv);
1651 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1652 struct drm_file *file_priv);
1653 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1654 struct drm_file *file_priv);
1655 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1656 struct drm_file *file_priv);
1657 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1658 struct drm_file *file_priv);
1659 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1660 struct drm_file *file_priv);
1661 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1662 struct drm_file *file_priv);
1663 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1664 struct drm_file *file);
1665 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1666 struct drm_file *file);
1667 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1668 struct drm_file *file_priv);
1669 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1670 struct drm_file *file_priv);
1671 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1672 struct drm_file *file_priv);
1673 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1674 struct drm_file *file_priv);
1675 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1676 struct drm_file *file_priv);
1677 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1678 struct drm_file *file_priv);
1679 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1680 struct drm_file *file_priv);
1681 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1682 struct drm_file *file_priv);
1683 void i915_gem_load(struct drm_device *dev);
1684 void *i915_gem_object_alloc(struct drm_device *dev);
1685 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1686 int i915_gem_init_object(struct drm_gem_object *obj);
1687 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1688 const struct drm_i915_gem_object_ops *ops);
1689 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1691 void i915_gem_free_object(struct drm_gem_object *obj);
1693 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1695 bool map_and_fenceable,
1697 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1698 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1699 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1700 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1701 void i915_gem_lastclose(struct drm_device *dev);
1703 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1704 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1706 struct sg_page_iter sg_iter;
1708 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1709 return sg_page_iter_page(&sg_iter);
1713 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1715 BUG_ON(obj->pages == NULL);
1716 obj->pages_pin_count++;
1718 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1720 BUG_ON(obj->pages_pin_count == 0);
1721 obj->pages_pin_count--;
1724 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1725 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1726 struct intel_ring_buffer *to);
1727 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1728 struct intel_ring_buffer *ring);
1730 int i915_gem_dumb_create(struct drm_file *file_priv,
1731 struct drm_device *dev,
1732 struct drm_mode_create_dumb *args);
1733 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1734 uint32_t handle, uint64_t *offset);
1735 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1738 * Returns true if seq1 is later than seq2.
1741 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1743 return (int32_t)(seq1 - seq2) >= 0;
1746 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1747 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1748 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1749 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1752 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1754 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1755 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1756 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1763 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1765 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1766 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1767 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
1768 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1772 void i915_gem_retire_requests(struct drm_device *dev);
1773 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1774 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1775 bool interruptible);
1776 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1778 return unlikely(atomic_read(&error->reset_counter)
1779 & I915_RESET_IN_PROGRESS_FLAG);
1782 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1784 return atomic_read(&error->reset_counter) == I915_WEDGED;
1787 void i915_gem_reset(struct drm_device *dev);
1788 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1789 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1790 uint32_t read_domains,
1791 uint32_t write_domain);
1792 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1793 int __must_check i915_gem_init(struct drm_device *dev);
1794 int __must_check i915_gem_init_hw(struct drm_device *dev);
1795 void i915_gem_l3_remap(struct drm_device *dev);
1796 void i915_gem_init_swizzling(struct drm_device *dev);
1797 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1798 int __must_check i915_gpu_idle(struct drm_device *dev);
1799 int __must_check i915_gem_idle(struct drm_device *dev);
1800 int __i915_add_request(struct intel_ring_buffer *ring,
1801 struct drm_file *file,
1802 struct drm_i915_gem_object *batch_obj,
1804 #define i915_add_request(ring, seqno) \
1805 __i915_add_request(ring, NULL, NULL, seqno)
1806 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1808 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1810 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1813 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1815 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1817 struct intel_ring_buffer *pipelined);
1818 int i915_gem_attach_phys_object(struct drm_device *dev,
1819 struct drm_i915_gem_object *obj,
1822 void i915_gem_detach_phys_object(struct drm_device *dev,
1823 struct drm_i915_gem_object *obj);
1824 void i915_gem_free_all_phys_object(struct drm_device *dev);
1825 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1828 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1830 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1831 int tiling_mode, bool fenced);
1833 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1834 enum i915_cache_level cache_level);
1836 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1837 struct dma_buf *dma_buf);
1839 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1840 struct drm_gem_object *gem_obj, int flags);
1842 /* i915_gem_context.c */
1843 void i915_gem_context_init(struct drm_device *dev);
1844 void i915_gem_context_fini(struct drm_device *dev);
1845 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1846 int i915_switch_context(struct intel_ring_buffer *ring,
1847 struct drm_file *file, int to_id);
1848 void i915_gem_context_free(struct kref *ctx_ref);
1849 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
1851 kref_get(&ctx->ref);
1854 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
1856 kref_put(&ctx->ref, i915_gem_context_free);
1859 struct i915_ctx_hang_stats * __must_check
1860 i915_gem_context_get_hang_stats(struct drm_device *dev,
1861 struct drm_file *file,
1863 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1864 struct drm_file *file);
1865 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1866 struct drm_file *file);
1868 /* i915_gem_gtt.c */
1869 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1870 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1871 struct drm_i915_gem_object *obj,
1872 enum i915_cache_level cache_level);
1873 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1874 struct drm_i915_gem_object *obj);
1876 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1877 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1878 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1879 enum i915_cache_level cache_level);
1880 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1881 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1882 void i915_gem_init_global_gtt(struct drm_device *dev);
1883 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1884 unsigned long mappable_end, unsigned long end);
1885 int i915_gem_gtt_init(struct drm_device *dev);
1886 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1888 if (INTEL_INFO(dev)->gen < 6)
1889 intel_gtt_chipset_flush();
1893 /* i915_gem_evict.c */
1894 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1896 unsigned cache_level,
1899 int i915_gem_evict_everything(struct drm_device *dev);
1901 /* i915_gem_stolen.c */
1902 int i915_gem_init_stolen(struct drm_device *dev);
1903 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1904 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1905 void i915_gem_cleanup_stolen(struct drm_device *dev);
1906 struct drm_i915_gem_object *
1907 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1908 struct drm_i915_gem_object *
1909 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1913 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1915 /* i915_gem_tiling.c */
1916 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1918 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1920 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1921 obj->tiling_mode != I915_TILING_NONE;
1924 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1925 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1926 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1928 /* i915_gem_debug.c */
1929 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1930 const char *where, uint32_t mark);
1932 int i915_verify_lists(struct drm_device *dev);
1934 #define i915_verify_lists(dev) 0
1936 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1938 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1939 const char *where, uint32_t mark);
1941 /* i915_debugfs.c */
1942 int i915_debugfs_init(struct drm_minor *minor);
1943 void i915_debugfs_cleanup(struct drm_minor *minor);
1945 /* i915_gpu_error.c */
1947 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
1948 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
1949 const struct i915_error_state_file_priv *error);
1950 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
1951 size_t count, loff_t pos);
1952 static inline void i915_error_state_buf_release(
1953 struct drm_i915_error_state_buf *eb)
1957 void i915_capture_error_state(struct drm_device *dev);
1958 void i915_error_state_get(struct drm_device *dev,
1959 struct i915_error_state_file_priv *error_priv);
1960 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
1961 void i915_destroy_error_state(struct drm_device *dev);
1963 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
1964 const char *i915_cache_level_str(int type);
1966 /* i915_suspend.c */
1967 extern int i915_save_state(struct drm_device *dev);
1968 extern int i915_restore_state(struct drm_device *dev);
1971 void i915_save_display_reg(struct drm_device *dev);
1972 void i915_restore_display_reg(struct drm_device *dev);
1975 void i915_setup_sysfs(struct drm_device *dev_priv);
1976 void i915_teardown_sysfs(struct drm_device *dev_priv);
1979 extern int intel_setup_gmbus(struct drm_device *dev);
1980 extern void intel_teardown_gmbus(struct drm_device *dev);
1981 static inline bool intel_gmbus_is_port_valid(unsigned port)
1983 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1986 extern struct i2c_adapter *intel_gmbus_get_adapter(
1987 struct drm_i915_private *dev_priv, unsigned port);
1988 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1989 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1990 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1992 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1994 extern void intel_i2c_reset(struct drm_device *dev);
1996 /* intel_opregion.c */
1997 extern int intel_opregion_setup(struct drm_device *dev);
1999 extern void intel_opregion_init(struct drm_device *dev);
2000 extern void intel_opregion_fini(struct drm_device *dev);
2001 extern void intel_opregion_asle_intr(struct drm_device *dev);
2003 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2004 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2005 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2010 extern void intel_register_dsm_handler(void);
2011 extern void intel_unregister_dsm_handler(void);
2013 static inline void intel_register_dsm_handler(void) { return; }
2014 static inline void intel_unregister_dsm_handler(void) { return; }
2015 #endif /* CONFIG_ACPI */
2018 extern void intel_modeset_init_hw(struct drm_device *dev);
2019 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2020 extern void intel_modeset_init(struct drm_device *dev);
2021 extern void intel_modeset_gem_init(struct drm_device *dev);
2022 extern void intel_modeset_cleanup(struct drm_device *dev);
2023 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2024 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2025 bool force_restore);
2026 extern void i915_redisable_vga(struct drm_device *dev);
2027 extern bool intel_fbc_enabled(struct drm_device *dev);
2028 extern void intel_disable_fbc(struct drm_device *dev);
2029 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2030 extern void intel_init_pch_refclk(struct drm_device *dev);
2031 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2032 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2033 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2034 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2035 extern void intel_detect_pch(struct drm_device *dev);
2036 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2037 extern int intel_enable_rc6(const struct drm_device *dev);
2039 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2040 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2041 struct drm_file *file);
2044 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2045 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2046 struct intel_overlay_error_state *error);
2048 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2049 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2050 struct drm_device *dev,
2051 struct intel_display_error_state *error);
2053 /* On SNB platform, before reading ring registers forcewake bit
2054 * must be set to prevent GT core from power down and stale values being
2057 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
2058 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
2059 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
2061 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2062 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2064 /* intel_sideband.c */
2065 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2066 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2067 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2068 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
2069 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
2070 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2071 enum intel_sbi_destination destination);
2072 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2073 enum intel_sbi_destination destination);
2075 int vlv_gpu_freq(int ddr_freq, int val);
2076 int vlv_freq_opcode(int ddr_freq, int val);
2078 #define __i915_read(x, y) \
2079 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
2087 #define __i915_write(x, y) \
2088 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
2096 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
2097 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
2099 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
2100 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
2101 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
2102 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
2104 #define I915_READ(reg) i915_read32(dev_priv, (reg))
2105 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
2106 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
2107 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
2109 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
2110 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
2112 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2113 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2115 /* "Broadcast RGB" property */
2116 #define INTEL_BROADCAST_RGB_AUTO 0
2117 #define INTEL_BROADCAST_RGB_FULL 1
2118 #define INTEL_BROADCAST_RGB_LIMITED 2
2120 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2122 if (HAS_PCH_SPLIT(dev))
2123 return CPU_VGACNTRL;
2124 else if (IS_VALLEYVIEW(dev))
2125 return VLV_VGACNTRL;
2130 static inline void __user *to_user_ptr(u64 address)
2132 return (void __user *)(uintptr_t)address;
2135 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2137 unsigned long j = msecs_to_jiffies(m);
2139 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2142 static inline unsigned long
2143 timespec_to_jiffies_timeout(const struct timespec *value)
2145 unsigned long j = timespec_to_jiffies(value);
2147 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);