1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
53 #include "i915_params.h"
56 #include "intel_bios.h"
57 #include "intel_dpll_mgr.h"
58 #include "intel_guc.h"
59 #include "intel_lrc.h"
60 #include "intel_ringbuffer.h"
63 #include "i915_gem_fence_reg.h"
64 #include "i915_gem_object.h"
65 #include "i915_gem_gtt.h"
66 #include "i915_gem_render_state.h"
67 #include "i915_gem_request.h"
68 #include "i915_gem_timeline.h"
72 #include "intel_gvt.h"
74 /* General customization:
77 #define DRIVER_NAME "i915"
78 #define DRIVER_DESC "Intel Graphics"
79 #define DRIVER_DATE "20161108"
80 #define DRIVER_TIMESTAMP 1478587895
83 /* Many gcc seem to no see through this and fall over :( */
85 #define WARN_ON(x) ({ \
86 bool __i915_warn_cond = (x); \
87 if (__builtin_constant_p(__i915_warn_cond)) \
88 BUILD_BUG_ON(__i915_warn_cond); \
89 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
91 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
95 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
97 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
98 (long) (x), __func__);
100 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
101 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
102 * which may not necessarily be a user visible problem. This will either
103 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
104 * enable distros and users to tailor their preferred amount of i915 abrt
107 #define I915_STATE_WARN(condition, format...) ({ \
108 int __ret_warn_on = !!(condition); \
109 if (unlikely(__ret_warn_on)) \
110 if (!WARN(i915.verbose_state_checks, format)) \
112 unlikely(__ret_warn_on); \
115 #define I915_STATE_WARN_ON(x) \
116 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
118 bool __i915_inject_load_failure(const char *func, int line);
119 #define i915_inject_load_failure() \
120 __i915_inject_load_failure(__func__, __LINE__)
122 static inline const char *yesno(bool v)
124 return v ? "yes" : "no";
127 static inline const char *onoff(bool v)
129 return v ? "on" : "off";
138 I915_MAX_PIPES = _PIPE_EDP
140 #define pipe_name(p) ((p) + 'A')
152 static inline const char *transcoder_name(enum transcoder transcoder)
154 switch (transcoder) {
163 case TRANSCODER_DSI_A:
165 case TRANSCODER_DSI_C:
172 static inline bool transcoder_is_dsi(enum transcoder transcoder)
174 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
178 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
179 * number of planes per CRTC. Not all platforms really have this many planes,
180 * which means some arrays of size I915_MAX_PLANES may have unused entries
181 * between the topmost sprite plane and the cursor plane.
190 #define plane_name(p) ((p) + 'A')
192 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
203 #define port_name(p) ((p) + 'A')
205 #define I915_NUM_PHYS_VLV 2
217 enum intel_display_power_domain {
221 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
222 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
223 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
224 POWER_DOMAIN_TRANSCODER_A,
225 POWER_DOMAIN_TRANSCODER_B,
226 POWER_DOMAIN_TRANSCODER_C,
227 POWER_DOMAIN_TRANSCODER_EDP,
228 POWER_DOMAIN_TRANSCODER_DSI_A,
229 POWER_DOMAIN_TRANSCODER_DSI_C,
230 POWER_DOMAIN_PORT_DDI_A_LANES,
231 POWER_DOMAIN_PORT_DDI_B_LANES,
232 POWER_DOMAIN_PORT_DDI_C_LANES,
233 POWER_DOMAIN_PORT_DDI_D_LANES,
234 POWER_DOMAIN_PORT_DDI_E_LANES,
235 POWER_DOMAIN_PORT_DSI,
236 POWER_DOMAIN_PORT_CRT,
237 POWER_DOMAIN_PORT_OTHER,
246 POWER_DOMAIN_MODESET,
252 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
253 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
254 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
255 #define POWER_DOMAIN_TRANSCODER(tran) \
256 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
257 (tran) + POWER_DOMAIN_TRANSCODER_A)
261 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
273 #define for_each_hpd_pin(__pin) \
274 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
276 struct i915_hotplug {
277 struct work_struct hotplug_work;
280 unsigned long last_jiffies;
285 HPD_MARK_DISABLED = 2
287 } stats[HPD_NUM_PINS];
289 struct delayed_work reenable_work;
291 struct intel_digital_port *irq_port[I915_MAX_PORTS];
294 struct work_struct dig_port_work;
296 struct work_struct poll_init_work;
300 * if we get a HPD irq from DP and a HPD irq from non-DP
301 * the non-DP HPD could block the workqueue on a mode config
302 * mutex getting, that userspace may have taken. However
303 * userspace is waiting on the DP workqueue to run which is
304 * blocked behind the non-DP one.
306 struct workqueue_struct *dp_wq;
309 #define I915_GEM_GPU_DOMAINS \
310 (I915_GEM_DOMAIN_RENDER | \
311 I915_GEM_DOMAIN_SAMPLER | \
312 I915_GEM_DOMAIN_COMMAND | \
313 I915_GEM_DOMAIN_INSTRUCTION | \
314 I915_GEM_DOMAIN_VERTEX)
316 #define for_each_pipe(__dev_priv, __p) \
317 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
318 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
319 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
320 for_each_if ((__mask) & (1 << (__p)))
321 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
323 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
325 #define for_each_sprite(__dev_priv, __p, __s) \
327 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
330 #define for_each_port_masked(__port, __ports_mask) \
331 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
332 for_each_if ((__ports_mask) & (1 << (__port)))
334 #define for_each_crtc(dev, crtc) \
335 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
337 #define for_each_intel_plane(dev, intel_plane) \
338 list_for_each_entry(intel_plane, \
339 &(dev)->mode_config.plane_list, \
342 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
343 list_for_each_entry(intel_plane, \
344 &(dev)->mode_config.plane_list, \
346 for_each_if ((plane_mask) & \
347 (1 << drm_plane_index(&intel_plane->base)))
349 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
350 list_for_each_entry(intel_plane, \
351 &(dev)->mode_config.plane_list, \
353 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
355 #define for_each_intel_crtc(dev, intel_crtc) \
356 list_for_each_entry(intel_crtc, \
357 &(dev)->mode_config.crtc_list, \
360 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
361 list_for_each_entry(intel_crtc, \
362 &(dev)->mode_config.crtc_list, \
364 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
366 #define for_each_intel_encoder(dev, intel_encoder) \
367 list_for_each_entry(intel_encoder, \
368 &(dev)->mode_config.encoder_list, \
371 #define for_each_intel_connector(dev, intel_connector) \
372 list_for_each_entry(intel_connector, \
373 &(dev)->mode_config.connector_list, \
376 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
377 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
378 for_each_if ((intel_encoder)->base.crtc == (__crtc))
380 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
381 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
382 for_each_if ((intel_connector)->base.encoder == (__encoder))
384 #define for_each_power_domain(domain, mask) \
385 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
386 for_each_if ((1 << (domain)) & (mask))
388 struct drm_i915_private;
389 struct i915_mm_struct;
390 struct i915_mmu_object;
392 struct drm_i915_file_private {
393 struct drm_i915_private *dev_priv;
394 struct drm_file *file;
398 struct list_head request_list;
399 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
400 * chosen to prevent the CPU getting more than a frame ahead of the GPU
401 * (when using lax throttling for the frontbuffer). We also use it to
402 * offer free GPU waitboosts for severely congested workloads.
404 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
406 struct idr context_idr;
408 struct intel_rps_client {
409 struct list_head link;
413 unsigned int bsd_engine;
416 /* Used by dp and fdi links */
417 struct intel_link_m_n {
425 void intel_link_compute_m_n(int bpp, int nlanes,
426 int pixel_clock, int link_clock,
427 struct intel_link_m_n *m_n);
429 /* Interface history:
432 * 1.2: Add Power Management
433 * 1.3: Add vblank support
434 * 1.4: Fix cmdbuffer path, add heap destroy
435 * 1.5: Add vblank pipe configuration
436 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
437 * - Support vertical blank on secondary display pipe
439 #define DRIVER_MAJOR 1
440 #define DRIVER_MINOR 6
441 #define DRIVER_PATCHLEVEL 0
443 struct opregion_header;
444 struct opregion_acpi;
445 struct opregion_swsci;
446 struct opregion_asle;
448 struct intel_opregion {
449 struct opregion_header *header;
450 struct opregion_acpi *acpi;
451 struct opregion_swsci *swsci;
452 u32 swsci_gbda_sub_functions;
453 u32 swsci_sbcb_sub_functions;
454 struct opregion_asle *asle;
459 struct work_struct asle_work;
461 #define OPREGION_SIZE (8*1024)
463 struct intel_overlay;
464 struct intel_overlay_error_state;
466 struct sdvo_device_mapping {
475 struct intel_connector;
476 struct intel_encoder;
477 struct intel_atomic_state;
478 struct intel_crtc_state;
479 struct intel_initial_plane_config;
484 struct drm_i915_display_funcs {
485 int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
486 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
487 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
488 int (*compute_intermediate_wm)(struct drm_device *dev,
489 struct intel_crtc *intel_crtc,
490 struct intel_crtc_state *newstate);
491 void (*initial_watermarks)(struct intel_atomic_state *state,
492 struct intel_crtc_state *cstate);
493 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
494 struct intel_crtc_state *cstate);
495 void (*optimize_watermarks)(struct intel_atomic_state *state,
496 struct intel_crtc_state *cstate);
497 int (*compute_global_watermarks)(struct drm_atomic_state *state);
498 void (*update_wm)(struct intel_crtc *crtc);
499 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
500 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
501 /* Returns the active state of the crtc, and if the crtc is active,
502 * fills out the pipe-config with the hw state. */
503 bool (*get_pipe_config)(struct intel_crtc *,
504 struct intel_crtc_state *);
505 void (*get_initial_plane_config)(struct intel_crtc *,
506 struct intel_initial_plane_config *);
507 int (*crtc_compute_clock)(struct intel_crtc *crtc,
508 struct intel_crtc_state *crtc_state);
509 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
510 struct drm_atomic_state *old_state);
511 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
512 struct drm_atomic_state *old_state);
513 void (*update_crtcs)(struct drm_atomic_state *state,
514 unsigned int *crtc_vblank_mask);
515 void (*audio_codec_enable)(struct drm_connector *connector,
516 struct intel_encoder *encoder,
517 const struct drm_display_mode *adjusted_mode);
518 void (*audio_codec_disable)(struct intel_encoder *encoder);
519 void (*fdi_link_train)(struct drm_crtc *crtc);
520 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
521 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
522 struct drm_framebuffer *fb,
523 struct drm_i915_gem_object *obj,
524 struct drm_i915_gem_request *req,
526 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
527 /* clock updates for mode set */
529 /* render clock increase/decrease */
530 /* display clock increase/decrease */
531 /* pll clock increase/decrease */
533 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
534 void (*load_luts)(struct drm_crtc_state *crtc_state);
537 enum forcewake_domain_id {
538 FW_DOMAIN_ID_RENDER = 0,
539 FW_DOMAIN_ID_BLITTER,
545 enum forcewake_domains {
546 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
547 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
548 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
549 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
554 #define FW_REG_READ (1)
555 #define FW_REG_WRITE (2)
557 enum decoupled_power_domain {
558 GEN9_DECOUPLED_PD_BLITTER = 0,
559 GEN9_DECOUPLED_PD_RENDER,
560 GEN9_DECOUPLED_PD_MEDIA,
561 GEN9_DECOUPLED_PD_ALL
565 GEN9_DECOUPLED_OP_WRITE = 0,
566 GEN9_DECOUPLED_OP_READ
569 enum forcewake_domains
570 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
571 i915_reg_t reg, unsigned int op);
573 struct intel_uncore_funcs {
574 void (*force_wake_get)(struct drm_i915_private *dev_priv,
575 enum forcewake_domains domains);
576 void (*force_wake_put)(struct drm_i915_private *dev_priv,
577 enum forcewake_domains domains);
579 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
580 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
581 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
582 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
584 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
585 uint8_t val, bool trace);
586 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
587 uint16_t val, bool trace);
588 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
589 uint32_t val, bool trace);
592 struct intel_forcewake_range {
596 enum forcewake_domains domains;
599 struct intel_uncore {
600 spinlock_t lock; /** lock is also taken in irq contexts. */
602 const struct intel_forcewake_range *fw_domains_table;
603 unsigned int fw_domains_table_entries;
605 struct intel_uncore_funcs funcs;
609 enum forcewake_domains fw_domains;
610 enum forcewake_domains fw_domains_active;
612 struct intel_uncore_forcewake_domain {
613 struct drm_i915_private *i915;
614 enum forcewake_domain_id id;
615 enum forcewake_domains mask;
617 struct hrtimer timer;
624 } fw_domain[FW_DOMAIN_ID_COUNT];
626 int unclaimed_mmio_check;
629 /* Iterate over initialised fw domains */
630 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
631 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
632 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
634 for_each_if ((mask__) & (domain__)->mask)
636 #define for_each_fw_domain(domain__, dev_priv__) \
637 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
639 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
640 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
641 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
644 struct work_struct work;
646 uint32_t *dmc_payload;
647 uint32_t dmc_fw_size;
650 i915_reg_t mmioaddr[8];
651 uint32_t mmiodata[8];
653 uint32_t allowed_dc_mask;
656 #define DEV_INFO_FOR_EACH_FLAG(func) \
657 /* Keep is_* in chronological order */ \
665 func(is_broadwater); \
666 func(is_crestline); \
667 func(is_ivybridge); \
668 func(is_valleyview); \
669 func(is_cherryview); \
671 func(is_broadwell); \
675 func(is_alpha_support); \
676 /* Keep has_* in alphabetical order */ \
677 func(has_64bit_reloc); \
682 func(has_fpga_dbg); \
683 func(has_gmbus_irq); \
684 func(has_gmch_display); \
687 func(has_hw_contexts); \
690 func(has_logical_ring_contexts); \
692 func(has_pipe_cxsr); \
693 func(has_pooled_eu); \
697 func(has_resource_streamer); \
698 func(has_runtime_pm); \
700 func(cursor_needs_physical); \
701 func(hws_needs_physical); \
702 func(overlay_needs_physical); \
704 func(has_decoupled_mmio)
706 struct sseu_dev_info {
712 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
715 u8 has_subslice_pg:1;
719 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
721 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
724 struct intel_device_info {
725 u32 display_mmio_offset;
728 u8 num_sprites[I915_MAX_PIPES];
731 u8 ring_mask; /* Rings supported by the HW */
733 #define DEFINE_FLAG(name) u8 name:1
734 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
736 u16 ddb_size; /* in blocks */
737 /* Register offsets for the various display pipes and transcoders */
738 int pipe_offsets[I915_MAX_TRANSCODERS];
739 int trans_offsets[I915_MAX_TRANSCODERS];
740 int palette_offsets[I915_MAX_PIPES];
741 int cursor_offsets[I915_MAX_PIPES];
743 /* Slice/subslice/EU info */
744 struct sseu_dev_info sseu;
747 u16 degamma_lut_size;
752 struct intel_display_error_state;
754 struct drm_i915_error_state {
757 struct timeval boottime;
758 struct timeval uptime;
760 struct drm_i915_private *i915;
767 struct intel_device_info device_info;
769 /* Generic register state */
777 u32 error; /* gen6+ */
778 u32 err_int; /* gen7 */
779 u32 fault_data0; /* gen8, gen9 */
780 u32 fault_data1; /* gen8, gen9 */
787 u64 fence[I915_MAX_NUM_FENCES];
788 struct intel_overlay_error_state *overlay;
789 struct intel_display_error_state *display;
790 struct drm_i915_error_object *semaphore;
791 struct drm_i915_error_object *guc_log;
793 struct drm_i915_error_engine {
795 /* Software tracked state */
799 enum intel_engine_hangcheck_action hangcheck_action;
800 struct i915_address_space *vm;
803 /* position of active request inside the ring */
804 u32 rq_head, rq_post, rq_tail;
806 /* our own tracking of ring head and tail */
829 u32 rc_psmi; /* sleep state */
830 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
831 struct intel_instdone instdone;
833 struct drm_i915_error_object {
839 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
841 struct drm_i915_error_object *wa_ctx;
843 struct drm_i915_error_request {
850 } *requests, execlist[2];
852 struct drm_i915_error_waiter {
853 char comm[TASK_COMM_LEN];
867 char comm[TASK_COMM_LEN];
868 } engine[I915_NUM_ENGINES];
870 struct drm_i915_error_buffer {
873 u32 rseqno[I915_NUM_ENGINES], wseqno;
877 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
884 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
885 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
886 struct i915_address_space *active_vm[I915_NUM_ENGINES];
889 enum i915_cache_level {
891 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
892 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
893 caches, eg sampler/render caches, and the
894 large Last-Level-Cache. LLC is coherent with
895 the CPU, but L3 is only visible to the GPU. */
896 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
899 struct i915_ctx_hang_stats {
900 /* This context had batch pending when hang was declared */
901 unsigned batch_pending;
903 /* This context had batch active when hang was declared */
904 unsigned batch_active;
906 /* Time when this context was last blamed for a GPU reset */
907 unsigned long guilty_ts;
909 /* If the contexts causes a second GPU hang within this time,
910 * it is permanently banned from submitting any more work.
912 unsigned long ban_period_seconds;
914 /* This context is banned to submit more work */
918 /* This must match up with the value previously used for execbuf2.rsvd1. */
919 #define DEFAULT_CONTEXT_HANDLE 0
922 * struct i915_gem_context - as the name implies, represents a context.
923 * @ref: reference count.
924 * @user_handle: userspace tracking identity for this context.
925 * @remap_slice: l3 row remapping information.
926 * @flags: context specific flags:
927 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
928 * @file_priv: filp associated with this context (NULL for global default
930 * @hang_stats: information about the role of this context in possible GPU
932 * @ppgtt: virtual memory space used by this context.
933 * @legacy_hw_ctx: render context backing object and whether it is correctly
934 * initialized (legacy ring submission mechanism only).
935 * @link: link in the global list of contexts.
937 * Contexts are memory images used by the hardware to store copies of their
940 struct i915_gem_context {
942 struct drm_i915_private *i915;
943 struct drm_i915_file_private *file_priv;
944 struct i915_hw_ppgtt *ppgtt;
948 struct i915_ctx_hang_stats hang_stats;
951 #define CONTEXT_NO_ZEROMAP BIT(0)
952 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
954 /* Unique identifier for this context, used by the hw for tracking */
957 int priority; /* greater priorities are serviced first */
961 struct intel_context {
962 struct i915_vma *state;
963 struct intel_ring *ring;
964 uint32_t *lrc_reg_state;
968 } engine[I915_NUM_ENGINES];
971 struct atomic_notifier_head status_notifier;
972 bool execlists_force_single_submission;
974 struct list_head link;
989 /* This is always the inner lock when overlapping with struct_mutex and
990 * it's the outer lock when overlapping with stolen_lock. */
993 unsigned int possible_framebuffer_bits;
994 unsigned int busy_bits;
995 unsigned int visible_pipes_mask;
996 struct intel_crtc *crtc;
998 struct drm_mm_node compressed_fb;
999 struct drm_mm_node *compressed_llb;
1006 bool underrun_detected;
1007 struct work_struct underrun_work;
1009 struct intel_fbc_state_cache {
1011 unsigned int mode_flags;
1012 uint32_t hsw_bdw_pixel_rate;
1016 unsigned int rotation;
1023 u64 ilk_ggtt_offset;
1024 uint32_t pixel_format;
1025 unsigned int stride;
1027 unsigned int tiling_mode;
1031 struct intel_fbc_reg_params {
1035 unsigned int fence_y_offset;
1040 uint32_t pixel_format;
1041 unsigned int stride;
1048 struct intel_fbc_work {
1050 u32 scheduled_vblank;
1051 struct work_struct work;
1054 const char *no_fbc_reason;
1058 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1059 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1060 * parsing for same resolution.
1062 enum drrs_refresh_rate_type {
1065 DRRS_MAX_RR, /* RR count */
1068 enum drrs_support_type {
1069 DRRS_NOT_SUPPORTED = 0,
1070 STATIC_DRRS_SUPPORT = 1,
1071 SEAMLESS_DRRS_SUPPORT = 2
1077 struct delayed_work work;
1078 struct intel_dp *dp;
1079 unsigned busy_frontbuffer_bits;
1080 enum drrs_refresh_rate_type refresh_rate_type;
1081 enum drrs_support_type type;
1088 struct intel_dp *enabled;
1090 struct delayed_work work;
1091 unsigned busy_frontbuffer_bits;
1093 bool aux_frame_sync;
1098 PCH_NONE = 0, /* No PCH present */
1099 PCH_IBX, /* Ibexpeak PCH */
1100 PCH_CPT, /* Cougarpoint PCH */
1101 PCH_LPT, /* Lynxpoint PCH */
1102 PCH_SPT, /* Sunrisepoint PCH */
1103 PCH_KBP, /* Kabypoint PCH */
1107 enum intel_sbi_destination {
1112 #define QUIRK_PIPEA_FORCE (1<<0)
1113 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1114 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1115 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1116 #define QUIRK_PIPEB_FORCE (1<<4)
1117 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1120 struct intel_fbc_work;
1122 struct intel_gmbus {
1123 struct i2c_adapter adapter;
1124 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1127 i915_reg_t gpio_reg;
1128 struct i2c_algo_bit_data bit_algo;
1129 struct drm_i915_private *dev_priv;
1132 struct i915_suspend_saved_registers {
1134 u32 saveFBC_CONTROL;
1135 u32 saveCACHE_MODE_0;
1136 u32 saveMI_ARB_STATE;
1140 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1141 u32 savePCH_PORT_HOTPLUG;
1145 struct vlv_s0ix_state {
1152 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1153 u32 media_max_req_count;
1154 u32 gfx_max_req_count;
1180 u32 rp_down_timeout;
1186 /* Display 1 CZ domain */
1191 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1193 /* GT SA CZ domain */
1200 /* Display 2 CZ domain */
1204 u32 clock_gate_dis2;
1207 struct intel_rps_ei {
1213 struct intel_gen6_power_mgmt {
1215 * work, interrupts_enabled and pm_iir are protected by
1216 * dev_priv->irq_lock
1218 struct work_struct work;
1219 bool interrupts_enabled;
1222 /* PM interrupt bits that should never be masked */
1225 /* Frequencies are stored in potentially platform dependent multiples.
1226 * In other words, *_freq needs to be multiplied by X to be interesting.
1227 * Soft limits are those which are used for the dynamic reclocking done
1228 * by the driver (raise frequencies under heavy loads, and lower for
1229 * lighter loads). Hard limits are those imposed by the hardware.
1231 * A distinction is made for overclocking, which is never enabled by
1232 * default, and is considered to be above the hard limit if it's
1235 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1236 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1237 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1238 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1239 u8 min_freq; /* AKA RPn. Minimum frequency */
1240 u8 boost_freq; /* Frequency to request when wait boosting */
1241 u8 idle_freq; /* Frequency to request when we are idle */
1242 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1243 u8 rp1_freq; /* "less than" RP0 power/freqency */
1244 u8 rp0_freq; /* Non-overclocked max frequency. */
1245 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1247 u8 up_threshold; /* Current %busy required to uplock */
1248 u8 down_threshold; /* Current %busy required to downclock */
1251 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1253 spinlock_t client_lock;
1254 struct list_head clients;
1258 struct delayed_work autoenable_work;
1261 /* manual wa residency calculations */
1262 struct intel_rps_ei up_ei, down_ei;
1265 * Protects RPS/RC6 register access and PCU communication.
1266 * Must be taken after struct_mutex if nested. Note that
1267 * this lock may be held for long periods of time when
1268 * talking to hw - so only take it when talking to hw!
1270 struct mutex hw_lock;
1273 /* defined intel_pm.c */
1274 extern spinlock_t mchdev_lock;
1276 struct intel_ilk_power_mgmt {
1284 unsigned long last_time1;
1285 unsigned long chipset_power;
1288 unsigned long gfx_power;
1295 struct drm_i915_private;
1296 struct i915_power_well;
1298 struct i915_power_well_ops {
1300 * Synchronize the well's hw state to match the current sw state, for
1301 * example enable/disable it based on the current refcount. Called
1302 * during driver init and resume time, possibly after first calling
1303 * the enable/disable handlers.
1305 void (*sync_hw)(struct drm_i915_private *dev_priv,
1306 struct i915_power_well *power_well);
1308 * Enable the well and resources that depend on it (for example
1309 * interrupts located on the well). Called after the 0->1 refcount
1312 void (*enable)(struct drm_i915_private *dev_priv,
1313 struct i915_power_well *power_well);
1315 * Disable the well and resources that depend on it. Called after
1316 * the 1->0 refcount transition.
1318 void (*disable)(struct drm_i915_private *dev_priv,
1319 struct i915_power_well *power_well);
1320 /* Returns the hw enabled state. */
1321 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1322 struct i915_power_well *power_well);
1325 /* Power well structure for haswell */
1326 struct i915_power_well {
1329 /* power well enable/disable usage count */
1331 /* cached hw enabled state */
1333 unsigned long domains;
1334 /* unique identifier for this power well */
1337 * Arbitraty data associated with this power well. Platform and power
1341 const struct i915_power_well_ops *ops;
1344 struct i915_power_domains {
1346 * Power wells needed for initialization at driver init and suspend
1347 * time are on. They are kept on until after the first modeset.
1351 int power_well_count;
1354 int domain_use_count[POWER_DOMAIN_NUM];
1355 struct i915_power_well *power_wells;
1358 #define MAX_L3_SLICES 2
1359 struct intel_l3_parity {
1360 u32 *remap_info[MAX_L3_SLICES];
1361 struct work_struct error_work;
1365 struct i915_gem_mm {
1366 /** Memory allocator for GTT stolen memory */
1367 struct drm_mm stolen;
1368 /** Protects the usage of the GTT stolen memory allocator. This is
1369 * always the inner lock when overlapping with struct_mutex. */
1370 struct mutex stolen_lock;
1372 /** List of all objects in gtt_space. Used to restore gtt
1373 * mappings on resume */
1374 struct list_head bound_list;
1376 * List of objects which are not bound to the GTT (thus
1377 * are idle and not used by the GPU). These objects may or may
1378 * not actually have any pages attached.
1380 struct list_head unbound_list;
1382 /** List of all objects in gtt_space, currently mmaped by userspace.
1383 * All objects within this list must also be on bound_list.
1385 struct list_head userfault_list;
1388 * List of objects which are pending destruction.
1390 struct llist_head free_list;
1391 struct work_struct free_work;
1393 /** Usable portion of the GTT for GEM */
1394 unsigned long stolen_base; /* limited to low memory (32-bit) */
1396 /** PPGTT used for aliasing the PPGTT with the GTT */
1397 struct i915_hw_ppgtt *aliasing_ppgtt;
1399 struct notifier_block oom_notifier;
1400 struct notifier_block vmap_notifier;
1401 struct shrinker shrinker;
1403 /** LRU list of objects with fence regs on them. */
1404 struct list_head fence_list;
1407 * Are we in a non-interruptible section of code like
1412 /* the indicator for dispatch video commands on two BSD rings */
1413 atomic_t bsd_engine_dispatch_index;
1415 /** Bit 6 swizzling required for X tiling */
1416 uint32_t bit_6_swizzle_x;
1417 /** Bit 6 swizzling required for Y tiling */
1418 uint32_t bit_6_swizzle_y;
1420 /* accounting, useful for userland debugging */
1421 spinlock_t object_stat_lock;
1426 struct drm_i915_error_state_buf {
1427 struct drm_i915_private *i915;
1436 struct i915_error_state_file_priv {
1437 struct drm_device *dev;
1438 struct drm_i915_error_state *error;
1441 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1442 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1444 struct i915_gpu_error {
1445 /* For hangcheck timer */
1446 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1447 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1448 /* Hang gpu twice in this window and your context gets banned */
1449 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1451 struct delayed_work hangcheck_work;
1453 /* For reset and error_state handling. */
1455 /* Protected by the above dev->gpu_error.lock. */
1456 struct drm_i915_error_state *first_error;
1458 unsigned long missed_irq_rings;
1461 * State variable controlling the reset flow and count
1463 * This is a counter which gets incremented when reset is triggered,
1465 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1466 * meaning that any waiters holding onto the struct_mutex should
1467 * relinquish the lock immediately in order for the reset to start.
1469 * If reset is not completed succesfully, the I915_WEDGE bit is
1470 * set meaning that hardware is terminally sour and there is no
1471 * recovery. All waiters on the reset_queue will be woken when
1474 * This counter is used by the wait_seqno code to notice that reset
1475 * event happened and it needs to restart the entire ioctl (since most
1476 * likely the seqno it waited for won't ever signal anytime soon).
1478 * This is important for lock-free wait paths, where no contended lock
1479 * naturally enforces the correct ordering between the bail-out of the
1480 * waiter and the gpu reset work code.
1482 unsigned long reset_count;
1484 unsigned long flags;
1485 #define I915_RESET_IN_PROGRESS 0
1486 #define I915_WEDGED (BITS_PER_LONG - 1)
1489 * Waitqueue to signal when a hang is detected. Used to for waiters
1490 * to release the struct_mutex for the reset to procede.
1492 wait_queue_head_t wait_queue;
1495 * Waitqueue to signal when the reset has completed. Used by clients
1496 * that wait for dev_priv->mm.wedged to settle.
1498 wait_queue_head_t reset_queue;
1500 /* For missed irq/seqno simulation. */
1501 unsigned long test_irq_rings;
1504 enum modeset_restore {
1505 MODESET_ON_LID_OPEN,
1510 #define DP_AUX_A 0x40
1511 #define DP_AUX_B 0x10
1512 #define DP_AUX_C 0x20
1513 #define DP_AUX_D 0x30
1515 #define DDC_PIN_B 0x05
1516 #define DDC_PIN_C 0x04
1517 #define DDC_PIN_D 0x06
1519 struct ddi_vbt_port_info {
1521 * This is an index in the HDMI/DVI DDI buffer translation table.
1522 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1523 * populate this field.
1525 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1526 uint8_t hdmi_level_shift;
1528 uint8_t supports_dvi:1;
1529 uint8_t supports_hdmi:1;
1530 uint8_t supports_dp:1;
1532 uint8_t alternate_aux_channel;
1533 uint8_t alternate_ddc_pin;
1535 uint8_t dp_boost_level;
1536 uint8_t hdmi_boost_level;
1539 enum psr_lines_to_wait {
1540 PSR_0_LINES_TO_WAIT = 0,
1542 PSR_4_LINES_TO_WAIT,
1546 struct intel_vbt_data {
1547 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1548 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1551 unsigned int int_tv_support:1;
1552 unsigned int lvds_dither:1;
1553 unsigned int lvds_vbt:1;
1554 unsigned int int_crt_support:1;
1555 unsigned int lvds_use_ssc:1;
1556 unsigned int display_clock_mode:1;
1557 unsigned int fdi_rx_polarity_inverted:1;
1558 unsigned int panel_type:4;
1560 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1562 enum drrs_support_type drrs_type;
1573 struct edp_power_seq pps;
1578 bool require_aux_wakeup;
1580 enum psr_lines_to_wait lines_to_wait;
1581 int tp1_wakeup_time;
1582 int tp2_tp3_wakeup_time;
1588 bool active_low_pwm;
1589 u8 min_brightness; /* min_brightness/255 of max */
1590 enum intel_backlight_type type;
1596 struct mipi_config *config;
1597 struct mipi_pps_data *pps;
1601 const u8 *sequence[MIPI_SEQ_MAX];
1607 union child_device_config *child_dev;
1609 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1610 struct sdvo_device_mapping sdvo_mappings[2];
1613 enum intel_ddb_partitioning {
1615 INTEL_DDB_PART_5_6, /* IVB+ */
1618 struct intel_wm_level {
1626 struct ilk_wm_values {
1627 uint32_t wm_pipe[3];
1629 uint32_t wm_lp_spr[3];
1630 uint32_t wm_linetime[3];
1632 enum intel_ddb_partitioning partitioning;
1635 struct vlv_pipe_wm {
1646 struct vlv_wm_values {
1647 struct vlv_pipe_wm pipe[3];
1648 struct vlv_sr_wm sr;
1658 struct skl_ddb_entry {
1659 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1662 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1664 return entry->end - entry->start;
1667 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1668 const struct skl_ddb_entry *e2)
1670 if (e1->start == e2->start && e1->end == e2->end)
1676 struct skl_ddb_allocation {
1677 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1678 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1681 struct skl_wm_values {
1682 unsigned dirty_pipes;
1683 struct skl_ddb_allocation ddb;
1686 struct skl_wm_level {
1688 uint16_t plane_res_b;
1689 uint8_t plane_res_l;
1693 * This struct helps tracking the state needed for runtime PM, which puts the
1694 * device in PCI D3 state. Notice that when this happens, nothing on the
1695 * graphics device works, even register access, so we don't get interrupts nor
1698 * Every piece of our code that needs to actually touch the hardware needs to
1699 * either call intel_runtime_pm_get or call intel_display_power_get with the
1700 * appropriate power domain.
1702 * Our driver uses the autosuspend delay feature, which means we'll only really
1703 * suspend if we stay with zero refcount for a certain amount of time. The
1704 * default value is currently very conservative (see intel_runtime_pm_enable), but
1705 * it can be changed with the standard runtime PM files from sysfs.
1707 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1708 * goes back to false exactly before we reenable the IRQs. We use this variable
1709 * to check if someone is trying to enable/disable IRQs while they're supposed
1710 * to be disabled. This shouldn't happen and we'll print some error messages in
1713 * For more, read the Documentation/power/runtime_pm.txt.
1715 struct i915_runtime_pm {
1716 atomic_t wakeref_count;
1721 enum intel_pipe_crc_source {
1722 INTEL_PIPE_CRC_SOURCE_NONE,
1723 INTEL_PIPE_CRC_SOURCE_PLANE1,
1724 INTEL_PIPE_CRC_SOURCE_PLANE2,
1725 INTEL_PIPE_CRC_SOURCE_PF,
1726 INTEL_PIPE_CRC_SOURCE_PIPE,
1727 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1728 INTEL_PIPE_CRC_SOURCE_TV,
1729 INTEL_PIPE_CRC_SOURCE_DP_B,
1730 INTEL_PIPE_CRC_SOURCE_DP_C,
1731 INTEL_PIPE_CRC_SOURCE_DP_D,
1732 INTEL_PIPE_CRC_SOURCE_AUTO,
1733 INTEL_PIPE_CRC_SOURCE_MAX,
1736 struct intel_pipe_crc_entry {
1741 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1742 struct intel_pipe_crc {
1744 bool opened; /* exclusive access to the result file */
1745 struct intel_pipe_crc_entry *entries;
1746 enum intel_pipe_crc_source source;
1748 wait_queue_head_t wq;
1751 struct i915_frontbuffer_tracking {
1755 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1762 struct i915_wa_reg {
1765 /* bitmask representing WA bits */
1770 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1771 * allowing it for RCS as we don't foresee any requirement of having
1772 * a whitelist for other engines. When it is really required for
1773 * other engines then the limit need to be increased.
1775 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1777 struct i915_workarounds {
1778 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1780 u32 hw_whitelist_count[I915_NUM_ENGINES];
1783 struct i915_virtual_gpu {
1787 /* used in computing the new watermarks state */
1788 struct intel_wm_config {
1789 unsigned int num_pipes_active;
1790 bool sprites_enabled;
1791 bool sprites_scaled;
1794 struct drm_i915_private {
1795 struct drm_device drm;
1797 struct kmem_cache *objects;
1798 struct kmem_cache *vmas;
1799 struct kmem_cache *requests;
1800 struct kmem_cache *dependencies;
1802 const struct intel_device_info info;
1804 int relative_constants_mode;
1808 struct intel_uncore uncore;
1810 struct i915_virtual_gpu vgpu;
1812 struct intel_gvt *gvt;
1814 struct intel_guc guc;
1816 struct intel_csr csr;
1818 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1820 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1821 * controller on different i2c buses. */
1822 struct mutex gmbus_mutex;
1825 * Base address of the gmbus and gpio block.
1827 uint32_t gpio_mmio_base;
1829 /* MMIO base address for MIPI regs */
1830 uint32_t mipi_mmio_base;
1832 uint32_t psr_mmio_base;
1834 uint32_t pps_mmio_base;
1836 wait_queue_head_t gmbus_wait_queue;
1838 struct pci_dev *bridge_dev;
1839 struct i915_gem_context *kernel_context;
1840 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1841 struct i915_vma *semaphore;
1843 struct drm_dma_handle *status_page_dmah;
1844 struct resource mch_res;
1846 /* protects the irq masks */
1847 spinlock_t irq_lock;
1849 /* protects the mmio flip data */
1850 spinlock_t mmio_flip_lock;
1852 bool display_irqs_enabled;
1854 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1855 struct pm_qos_request pm_qos;
1857 /* Sideband mailbox protection */
1858 struct mutex sb_lock;
1860 /** Cached value of IMR to avoid reads in updating the bitfield */
1863 u32 de_irq_mask[I915_MAX_PIPES];
1870 u32 pipestat_irq_mask[I915_MAX_PIPES];
1872 struct i915_hotplug hotplug;
1873 struct intel_fbc fbc;
1874 struct i915_drrs drrs;
1875 struct intel_opregion opregion;
1876 struct intel_vbt_data vbt;
1878 bool preserve_bios_swizzle;
1881 struct intel_overlay *overlay;
1883 /* backlight registers and fields in struct intel_panel */
1884 struct mutex backlight_lock;
1887 bool no_aux_handshake;
1889 /* protects panel power sequencer state */
1890 struct mutex pps_mutex;
1892 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1893 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1895 unsigned int fsb_freq, mem_freq, is_ddr3;
1896 unsigned int skl_preferred_vco_freq;
1897 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1898 unsigned int max_dotclk_freq;
1899 unsigned int rawclk_freq;
1900 unsigned int hpll_freq;
1901 unsigned int czclk_freq;
1904 unsigned int vco, ref;
1908 * wq - Driver workqueue for GEM.
1910 * NOTE: Work items scheduled here are not allowed to grab any modeset
1911 * locks, for otherwise the flushing done in the pageflip code will
1912 * result in deadlocks.
1914 struct workqueue_struct *wq;
1916 /* Display functions */
1917 struct drm_i915_display_funcs display;
1919 /* PCH chipset type */
1920 enum intel_pch pch_type;
1921 unsigned short pch_id;
1923 unsigned long quirks;
1925 enum modeset_restore modeset_restore;
1926 struct mutex modeset_restore_lock;
1927 struct drm_atomic_state *modeset_restore_state;
1928 struct drm_modeset_acquire_ctx reset_ctx;
1930 struct list_head vm_list; /* Global list of all address spaces */
1931 struct i915_ggtt ggtt; /* VM representing the global address space */
1933 struct i915_gem_mm mm;
1934 DECLARE_HASHTABLE(mm_structs, 7);
1935 struct mutex mm_lock;
1937 /* The hw wants to have a stable context identifier for the lifetime
1938 * of the context (for OA, PASID, faults, etc). This is limited
1939 * in execlists to 21 bits.
1941 struct ida context_hw_ida;
1942 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1944 /* Kernel Modesetting */
1946 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1947 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1948 wait_queue_head_t pending_flip_queue;
1950 #ifdef CONFIG_DEBUG_FS
1951 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1954 /* dpll and cdclk state is protected by connection_mutex */
1955 int num_shared_dpll;
1956 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1957 const struct intel_dpll_mgr *dpll_mgr;
1960 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1961 * Must be global rather than per dpll, because on some platforms
1962 * plls share registers.
1964 struct mutex dpll_lock;
1966 unsigned int active_crtcs;
1967 unsigned int min_pixclk[I915_MAX_PIPES];
1969 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1971 struct i915_workarounds workarounds;
1973 struct i915_frontbuffer_tracking fb_tracking;
1977 bool mchbar_need_disable;
1979 struct intel_l3_parity l3_parity;
1981 /* Cannot be determined by PCIID. You must always read a register. */
1984 /* gen6+ rps state */
1985 struct intel_gen6_power_mgmt rps;
1987 /* ilk-only ips/rps state. Everything in here is protected by the global
1988 * mchdev_lock in intel_pm.c */
1989 struct intel_ilk_power_mgmt ips;
1991 struct i915_power_domains power_domains;
1993 struct i915_psr psr;
1995 struct i915_gpu_error gpu_error;
1997 struct drm_i915_gem_object *vlv_pctx;
1999 #ifdef CONFIG_DRM_FBDEV_EMULATION
2000 /* list of fbdev register on this device */
2001 struct intel_fbdev *fbdev;
2002 struct work_struct fbdev_suspend_work;
2005 struct drm_property *broadcast_rgb_property;
2006 struct drm_property *force_audio_property;
2008 /* hda/i915 audio component */
2009 struct i915_audio_component *audio_component;
2010 bool audio_component_registered;
2012 * av_mutex - mutex for audio/video sync
2015 struct mutex av_mutex;
2017 uint32_t hw_context_size;
2018 struct list_head context_list;
2022 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2023 u32 chv_phy_control;
2025 * Shadows for CHV DPLL_MD regs to keep the state
2026 * checker somewhat working in the presence hardware
2027 * crappiness (can't read out DPLL_MD for pipes B & C).
2029 u32 chv_dpll_md[I915_MAX_PIPES];
2033 bool suspended_to_idle;
2034 struct i915_suspend_saved_registers regfile;
2035 struct vlv_s0ix_state vlv_s0ix_state;
2038 I915_SAGV_UNKNOWN = 0,
2041 I915_SAGV_NOT_CONTROLLED
2046 * Raw watermark latency values:
2047 * in 0.1us units for WM0,
2048 * in 0.5us units for WM1+.
2051 uint16_t pri_latency[5];
2053 uint16_t spr_latency[5];
2055 uint16_t cur_latency[5];
2057 * Raw watermark memory latency values
2058 * for SKL for all 8 levels
2061 uint16_t skl_latency[8];
2063 /* current hardware state */
2065 struct ilk_wm_values hw;
2066 struct skl_wm_values skl_hw;
2067 struct vlv_wm_values vlv;
2073 * Should be held around atomic WM register writing; also
2074 * protects * intel_crtc->wm.active and
2075 * cstate->wm.need_postvbl_update.
2077 struct mutex wm_mutex;
2080 * Set during HW readout of watermarks/DDB. Some platforms
2081 * need to know when we're still using BIOS-provided values
2082 * (which we don't fully trust).
2084 bool distrust_bios_wm;
2087 struct i915_runtime_pm pm;
2089 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2091 void (*resume)(struct drm_i915_private *);
2092 void (*cleanup_engine)(struct intel_engine_cs *engine);
2094 struct list_head timelines;
2095 struct i915_gem_timeline global_timeline;
2096 u32 active_requests;
2099 * Is the GPU currently considered idle, or busy executing
2100 * userspace requests? Whilst idle, we allow runtime power
2101 * management to power down the hardware and display clocks.
2102 * In order to reduce the effect on performance, there
2103 * is a slight delay before we do so.
2108 * We leave the user IRQ off as much as possible,
2109 * but this means that requests will finish and never
2110 * be retired once the system goes idle. Set a timer to
2111 * fire periodically while the ring is running. When it
2112 * fires, go retire requests.
2114 struct delayed_work retire_work;
2117 * When we detect an idle GPU, we want to turn on
2118 * powersaving features. So once we see that there
2119 * are no more requests outstanding and no more
2120 * arrive within a small period of time, we fire
2121 * off the idle_work.
2123 struct delayed_work idle_work;
2125 ktime_t last_init_time;
2128 /* perform PHY state sanity checks? */
2129 bool chv_phy_assert[2];
2131 /* Used to save the pipe-to-encoder mapping for audio */
2132 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2135 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2136 * will be rejected. Instead look for a better place.
2140 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2142 return container_of(dev, struct drm_i915_private, drm);
2145 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2147 return to_i915(dev_get_drvdata(kdev));
2150 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2152 return container_of(guc, struct drm_i915_private, guc);
2155 /* Simple iterator over all initialised engines */
2156 #define for_each_engine(engine__, dev_priv__, id__) \
2158 (id__) < I915_NUM_ENGINES; \
2160 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2162 #define __mask_next_bit(mask) ({ \
2163 int __idx = ffs(mask) - 1; \
2164 mask &= ~BIT(__idx); \
2168 /* Iterator over subset of engines selected by mask */
2169 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2170 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2171 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2173 enum hdmi_force_audio {
2174 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2175 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2176 HDMI_AUDIO_AUTO, /* trust EDID */
2177 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2180 #define I915_GTT_OFFSET_NONE ((u32)-1)
2183 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2184 * considered to be the frontbuffer for the given plane interface-wise. This
2185 * doesn't mean that the hw necessarily already scans it out, but that any
2186 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2188 * We have one bit per pipe and per scanout plane type.
2190 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2191 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2192 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2193 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2194 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2195 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2196 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2197 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2198 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2199 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2200 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2201 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2204 * Optimised SGL iterator for GEM objects
2206 static __always_inline struct sgt_iter {
2207 struct scatterlist *sgp;
2214 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2215 struct sgt_iter s = { .sgp = sgl };
2218 s.max = s.curr = s.sgp->offset;
2219 s.max += s.sgp->length;
2221 s.dma = sg_dma_address(s.sgp);
2223 s.pfn = page_to_pfn(sg_page(s.sgp));
2229 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2232 if (unlikely(sg_is_chain(sg)))
2233 sg = sg_chain_ptr(sg);
2238 * __sg_next - return the next scatterlist entry in a list
2239 * @sg: The current sg entry
2242 * If the entry is the last, return NULL; otherwise, step to the next
2243 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2244 * otherwise just return the pointer to the current element.
2246 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2248 #ifdef CONFIG_DEBUG_SG
2249 BUG_ON(sg->sg_magic != SG_MAGIC);
2251 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2255 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2256 * @__dmap: DMA address (output)
2257 * @__iter: 'struct sgt_iter' (iterator state, internal)
2258 * @__sgt: sg_table to iterate over (input)
2260 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2261 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2262 ((__dmap) = (__iter).dma + (__iter).curr); \
2263 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2264 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2267 * for_each_sgt_page - iterate over the pages of the given sg_table
2268 * @__pp: page pointer (output)
2269 * @__iter: 'struct sgt_iter' (iterator state, internal)
2270 * @__sgt: sg_table to iterate over (input)
2272 #define for_each_sgt_page(__pp, __iter, __sgt) \
2273 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2274 ((__pp) = (__iter).pfn == 0 ? NULL : \
2275 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2276 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2277 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2280 * A command that requires special handling by the command parser.
2282 struct drm_i915_cmd_descriptor {
2284 * Flags describing how the command parser processes the command.
2286 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2287 * a length mask if not set
2288 * CMD_DESC_SKIP: The command is allowed but does not follow the
2289 * standard length encoding for the opcode range in
2291 * CMD_DESC_REJECT: The command is never allowed
2292 * CMD_DESC_REGISTER: The command should be checked against the
2293 * register whitelist for the appropriate ring
2294 * CMD_DESC_MASTER: The command is allowed if the submitting process
2298 #define CMD_DESC_FIXED (1<<0)
2299 #define CMD_DESC_SKIP (1<<1)
2300 #define CMD_DESC_REJECT (1<<2)
2301 #define CMD_DESC_REGISTER (1<<3)
2302 #define CMD_DESC_BITMASK (1<<4)
2303 #define CMD_DESC_MASTER (1<<5)
2306 * The command's unique identification bits and the bitmask to get them.
2307 * This isn't strictly the opcode field as defined in the spec and may
2308 * also include type, subtype, and/or subop fields.
2316 * The command's length. The command is either fixed length (i.e. does
2317 * not include a length field) or has a length field mask. The flag
2318 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2319 * a length mask. All command entries in a command table must include
2320 * length information.
2328 * Describes where to find a register address in the command to check
2329 * against the ring's register whitelist. Only valid if flags has the
2330 * CMD_DESC_REGISTER bit set.
2332 * A non-zero step value implies that the command may access multiple
2333 * registers in sequence (e.g. LRI), in that case step gives the
2334 * distance in dwords between individual offset fields.
2342 #define MAX_CMD_DESC_BITMASKS 3
2344 * Describes command checks where a particular dword is masked and
2345 * compared against an expected value. If the command does not match
2346 * the expected value, the parser rejects it. Only valid if flags has
2347 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2350 * If the check specifies a non-zero condition_mask then the parser
2351 * only performs the check when the bits specified by condition_mask
2358 u32 condition_offset;
2360 } bits[MAX_CMD_DESC_BITMASKS];
2364 * A table of commands requiring special handling by the command parser.
2366 * Each engine has an array of tables. Each table consists of an array of
2367 * command descriptors, which must be sorted with command opcodes in
2370 struct drm_i915_cmd_table {
2371 const struct drm_i915_cmd_descriptor *table;
2375 static inline const struct intel_device_info *
2376 intel_info(const struct drm_i915_private *dev_priv)
2378 return &dev_priv->info;
2381 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2383 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2384 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2386 #define REVID_FOREVER 0xff
2387 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2389 #define GEN_FOREVER (0)
2391 * Returns true if Gen is in inclusive range [Start, End].
2393 * Use GEN_FOREVER for unbound start and or end.
2395 #define IS_GEN(dev_priv, s, e) ({ \
2396 unsigned int __s = (s), __e = (e); \
2397 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2398 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2399 if ((__s) != GEN_FOREVER) \
2401 if ((__e) == GEN_FOREVER) \
2402 __e = BITS_PER_LONG - 1; \
2405 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2409 * Return true if revision is in range [since,until] inclusive.
2411 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2413 #define IS_REVID(p, since, until) \
2414 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2416 #define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
2417 #define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
2418 #define IS_I85X(dev_priv) ((dev_priv)->info.is_i85x)
2419 #define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
2420 #define IS_I915G(dev_priv) ((dev_priv)->info.is_i915g)
2421 #define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
2422 #define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
2423 #define IS_I945GM(dev_priv) ((dev_priv)->info.is_i945gm)
2424 #define IS_BROADWATER(dev_priv) ((dev_priv)->info.is_broadwater)
2425 #define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline)
2426 #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
2427 #define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
2428 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2429 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2430 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview)
2431 #define IS_G33(dev_priv) ((dev_priv)->info.is_g33)
2432 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2433 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
2434 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2435 INTEL_DEVID(dev_priv) == 0x0152 || \
2436 INTEL_DEVID(dev_priv) == 0x015a)
2437 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
2438 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
2439 #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
2440 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
2441 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
2442 #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
2443 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
2444 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2445 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2446 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2447 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2448 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2449 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2450 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2451 /* ULX machines are also considered ULT. */
2452 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2453 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2454 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2455 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2456 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2457 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2458 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2459 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2460 /* ULX machines are also considered ULT. */
2461 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2462 INTEL_DEVID(dev_priv) == 0x0A1E)
2463 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2464 INTEL_DEVID(dev_priv) == 0x1913 || \
2465 INTEL_DEVID(dev_priv) == 0x1916 || \
2466 INTEL_DEVID(dev_priv) == 0x1921 || \
2467 INTEL_DEVID(dev_priv) == 0x1926)
2468 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2469 INTEL_DEVID(dev_priv) == 0x1915 || \
2470 INTEL_DEVID(dev_priv) == 0x191E)
2471 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2472 INTEL_DEVID(dev_priv) == 0x5913 || \
2473 INTEL_DEVID(dev_priv) == 0x5916 || \
2474 INTEL_DEVID(dev_priv) == 0x5921 || \
2475 INTEL_DEVID(dev_priv) == 0x5926)
2476 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2477 INTEL_DEVID(dev_priv) == 0x5915 || \
2478 INTEL_DEVID(dev_priv) == 0x591E)
2479 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2480 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2481 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2482 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2484 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2486 #define SKL_REVID_A0 0x0
2487 #define SKL_REVID_B0 0x1
2488 #define SKL_REVID_C0 0x2
2489 #define SKL_REVID_D0 0x3
2490 #define SKL_REVID_E0 0x4
2491 #define SKL_REVID_F0 0x5
2492 #define SKL_REVID_G0 0x6
2493 #define SKL_REVID_H0 0x7
2495 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2497 #define BXT_REVID_A0 0x0
2498 #define BXT_REVID_A1 0x1
2499 #define BXT_REVID_B0 0x3
2500 #define BXT_REVID_C0 0x9
2502 #define IS_BXT_REVID(dev_priv, since, until) \
2503 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2505 #define KBL_REVID_A0 0x0
2506 #define KBL_REVID_B0 0x1
2507 #define KBL_REVID_C0 0x2
2508 #define KBL_REVID_D0 0x3
2509 #define KBL_REVID_E0 0x4
2511 #define IS_KBL_REVID(dev_priv, since, until) \
2512 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2515 * The genX designation typically refers to the render engine, so render
2516 * capability related checks should use IS_GEN, while display and other checks
2517 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2520 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2521 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2522 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2523 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2524 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2525 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2526 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2527 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2529 #define ENGINE_MASK(id) BIT(id)
2530 #define RENDER_RING ENGINE_MASK(RCS)
2531 #define BSD_RING ENGINE_MASK(VCS)
2532 #define BLT_RING ENGINE_MASK(BCS)
2533 #define VEBOX_RING ENGINE_MASK(VECS)
2534 #define BSD2_RING ENGINE_MASK(VCS2)
2535 #define ALL_ENGINES (~0)
2537 #define HAS_ENGINE(dev_priv, id) \
2538 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2540 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2541 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2542 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2543 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2545 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2546 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2547 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2548 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2549 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2551 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2553 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2554 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2555 ((dev_priv)->info.has_logical_ring_contexts)
2556 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2557 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2558 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2560 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2561 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2562 ((dev_priv)->info.overlay_needs_physical)
2564 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2565 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
2567 /* WaRsDisableCoarsePowerGating:skl,bxt */
2568 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2569 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2570 IS_SKL_GT3(dev_priv) || \
2571 IS_SKL_GT4(dev_priv))
2574 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2575 * even when in MSI mode. This results in spurious interrupt warnings if the
2576 * legacy irq no. is shared with another device. The kernel then disables that
2577 * interrupt source and so prevents the other device from working properly.
2579 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2580 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2582 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2583 * rows, which changed the alignment requirements and fence programming.
2585 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2586 !(IS_I915G(dev_priv) || \
2587 IS_I915GM(dev_priv)))
2588 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2589 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2591 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2592 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2593 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2595 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2597 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2599 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2600 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2601 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2602 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2603 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2605 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2607 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2608 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2611 * For now, anything with a GuC requires uCode loading, and then supports
2612 * command submission once loaded. But these are logically independent
2613 * properties, so we have separate macros to test them.
2615 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2616 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2617 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2619 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2621 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2623 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2624 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2625 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2626 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2627 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2628 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2629 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2630 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2631 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2632 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2633 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2634 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2636 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2637 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2638 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2639 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2640 #define HAS_PCH_LPT_LP(dev_priv) \
2641 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2642 #define HAS_PCH_LPT_H(dev_priv) \
2643 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2644 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2645 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2646 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2647 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2649 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2651 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2653 /* DPF == dynamic parity feature */
2654 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2655 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2656 2 : HAS_L3_DPF(dev_priv))
2658 #define GT_FREQUENCY_MULTIPLIER 50
2659 #define GEN9_FREQ_SCALER 3
2661 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2663 #include "i915_trace.h"
2665 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2667 #ifdef CONFIG_INTEL_IOMMU
2668 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2674 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2675 extern int i915_resume_switcheroo(struct drm_device *dev);
2677 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2680 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2684 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2685 const char *fmt, ...);
2687 #define i915_report_error(dev_priv, fmt, ...) \
2688 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2690 #ifdef CONFIG_COMPAT
2691 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2694 #define i915_compat_ioctl NULL
2696 extern const struct dev_pm_ops i915_pm_ops;
2698 extern int i915_driver_load(struct pci_dev *pdev,
2699 const struct pci_device_id *ent);
2700 extern void i915_driver_unload(struct drm_device *dev);
2701 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2702 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2703 extern void i915_reset(struct drm_i915_private *dev_priv);
2704 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2705 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2706 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2707 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2708 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2709 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2710 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2711 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2713 /* intel_hotplug.c */
2714 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2715 u32 pin_mask, u32 long_mask);
2716 void intel_hpd_init(struct drm_i915_private *dev_priv);
2717 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2718 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2719 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2720 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2721 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2724 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2726 unsigned long delay;
2728 if (unlikely(!i915.enable_hangcheck))
2731 /* Don't continually defer the hangcheck so that it is always run at
2732 * least once after work has been scheduled on any ring. Otherwise,
2733 * we will ignore a hung ring if a second ring is kept busy.
2736 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2737 queue_delayed_work(system_long_wq,
2738 &dev_priv->gpu_error.hangcheck_work, delay);
2742 void i915_handle_error(struct drm_i915_private *dev_priv,
2744 const char *fmt, ...);
2746 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2747 int intel_irq_install(struct drm_i915_private *dev_priv);
2748 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2750 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2751 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2752 bool restore_forcewake);
2753 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2754 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2755 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2756 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2757 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2759 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2760 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2761 enum forcewake_domains domains);
2762 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2763 enum forcewake_domains domains);
2764 /* Like above but the caller must manage the uncore.lock itself.
2765 * Must be used with I915_READ_FW and friends.
2767 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2768 enum forcewake_domains domains);
2769 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2770 enum forcewake_domains domains);
2771 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2773 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2775 int intel_wait_for_register(struct drm_i915_private *dev_priv,
2779 const unsigned long timeout_ms);
2780 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2784 const unsigned long timeout_ms);
2786 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2788 return dev_priv->gvt;
2791 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2793 return dev_priv->vgpu.active;
2797 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2801 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2804 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2805 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2806 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2809 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2810 uint32_t interrupt_mask,
2811 uint32_t enabled_irq_mask);
2813 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2815 ilk_update_display_irq(dev_priv, bits, bits);
2818 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2820 ilk_update_display_irq(dev_priv, bits, 0);
2822 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2824 uint32_t interrupt_mask,
2825 uint32_t enabled_irq_mask);
2826 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2827 enum pipe pipe, uint32_t bits)
2829 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2831 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2832 enum pipe pipe, uint32_t bits)
2834 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2836 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2837 uint32_t interrupt_mask,
2838 uint32_t enabled_irq_mask);
2840 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2842 ibx_display_interrupt_update(dev_priv, bits, bits);
2845 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2847 ibx_display_interrupt_update(dev_priv, bits, 0);
2851 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2852 struct drm_file *file_priv);
2853 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2854 struct drm_file *file_priv);
2855 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2856 struct drm_file *file_priv);
2857 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2858 struct drm_file *file_priv);
2859 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2860 struct drm_file *file_priv);
2861 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2862 struct drm_file *file_priv);
2863 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2864 struct drm_file *file_priv);
2865 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2866 struct drm_file *file_priv);
2867 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2868 struct drm_file *file_priv);
2869 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2870 struct drm_file *file_priv);
2871 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2872 struct drm_file *file);
2873 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2874 struct drm_file *file);
2875 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2876 struct drm_file *file_priv);
2877 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2878 struct drm_file *file_priv);
2879 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2880 struct drm_file *file_priv);
2881 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2882 struct drm_file *file_priv);
2883 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2884 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2885 struct drm_file *file);
2886 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2887 struct drm_file *file_priv);
2888 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2889 struct drm_file *file_priv);
2890 int i915_gem_load_init(struct drm_device *dev);
2891 void i915_gem_load_cleanup(struct drm_device *dev);
2892 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2893 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2894 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2896 void *i915_gem_object_alloc(struct drm_device *dev);
2897 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2898 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2899 const struct drm_i915_gem_object_ops *ops);
2900 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
2902 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2903 struct drm_device *dev, const void *data, size_t size);
2904 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2905 void i915_gem_free_object(struct drm_gem_object *obj);
2907 struct i915_vma * __must_check
2908 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2909 const struct i915_ggtt_view *view,
2914 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2915 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2917 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2919 static inline int __sg_page_count(const struct scatterlist *sg)
2921 return sg->length >> PAGE_SHIFT;
2924 struct scatterlist *
2925 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2926 unsigned int n, unsigned int *offset);
2929 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2933 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2937 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2940 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2941 struct sg_table *pages);
2942 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2944 static inline int __must_check
2945 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2947 might_lock(&obj->mm.lock);
2949 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2952 return __i915_gem_object_get_pages(obj);
2956 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2958 GEM_BUG_ON(!obj->mm.pages);
2960 atomic_inc(&obj->mm.pages_pin_count);
2964 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
2966 return atomic_read(&obj->mm.pages_pin_count);
2970 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2972 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
2973 GEM_BUG_ON(!obj->mm.pages);
2975 atomic_dec(&obj->mm.pages_pin_count);
2976 GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
2980 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2982 __i915_gem_object_unpin_pages(obj);
2985 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
2990 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2991 enum i915_mm_subclass subclass);
2992 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
2994 enum i915_map_type {
3000 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3001 * @obj - the object to map into kernel address space
3002 * @type - the type of mapping, used to select pgprot_t
3004 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3005 * pages and then returns a contiguous mapping of the backing storage into
3006 * the kernel address space. Based on the @type of mapping, the PTE will be
3007 * set to either WriteBack or WriteCombine (via pgprot_t).
3009 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3010 * mapping is no longer required.
3012 * Returns the pointer through which to access the mapped object, or an
3013 * ERR_PTR() on error.
3015 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3016 enum i915_map_type type);
3019 * i915_gem_object_unpin_map - releases an earlier mapping
3020 * @obj - the object to unmap
3022 * After pinning the object and mapping its pages, once you are finished
3023 * with your access, call i915_gem_object_unpin_map() to release the pin
3024 * upon the mapping. Once the pin count reaches zero, that mapping may be
3027 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3029 i915_gem_object_unpin_pages(obj);
3032 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3033 unsigned int *needs_clflush);
3034 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3035 unsigned int *needs_clflush);
3036 #define CLFLUSH_BEFORE 0x1
3037 #define CLFLUSH_AFTER 0x2
3038 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3041 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3043 i915_gem_object_unpin_pages(obj);
3046 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3047 void i915_vma_move_to_active(struct i915_vma *vma,
3048 struct drm_i915_gem_request *req,
3049 unsigned int flags);
3050 int i915_gem_dumb_create(struct drm_file *file_priv,
3051 struct drm_device *dev,
3052 struct drm_mode_create_dumb *args);
3053 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3054 uint32_t handle, uint64_t *offset);
3055 int i915_gem_mmap_gtt_version(void);
3057 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3058 struct drm_i915_gem_object *new,
3059 unsigned frontbuffer_bits);
3061 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3063 struct drm_i915_gem_request *
3064 i915_gem_find_active_request(struct intel_engine_cs *engine);
3066 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3068 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3070 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3073 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3075 return unlikely(test_bit(I915_WEDGED, &error->flags));
3078 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3080 return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3083 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3085 return READ_ONCE(error->reset_count);
3088 void i915_gem_reset(struct drm_i915_private *dev_priv);
3089 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3090 void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3091 int __must_check i915_gem_init(struct drm_device *dev);
3092 int __must_check i915_gem_init_hw(struct drm_device *dev);
3093 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3094 void i915_gem_cleanup_engines(struct drm_device *dev);
3095 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3096 unsigned int flags);
3097 int __must_check i915_gem_suspend(struct drm_device *dev);
3098 void i915_gem_resume(struct drm_device *dev);
3099 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3100 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3103 struct intel_rps_client *rps);
3104 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3107 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3110 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3113 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3114 struct i915_vma * __must_check
3115 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3117 const struct i915_ggtt_view *view);
3118 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3119 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3121 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3122 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3124 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3126 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3127 int tiling_mode, bool fenced);
3129 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3130 enum i915_cache_level cache_level);
3132 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3133 struct dma_buf *dma_buf);
3135 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3136 struct drm_gem_object *gem_obj, int flags);
3139 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3140 struct i915_address_space *vm,
3141 const struct i915_ggtt_view *view);
3144 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3145 struct i915_address_space *vm,
3146 const struct i915_ggtt_view *view);
3148 static inline struct i915_hw_ppgtt *
3149 i915_vm_to_ppgtt(struct i915_address_space *vm)
3151 return container_of(vm, struct i915_hw_ppgtt, base);
3154 static inline struct i915_vma *
3155 i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
3156 const struct i915_ggtt_view *view)
3158 return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3161 static inline unsigned long
3162 i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
3163 const struct i915_ggtt_view *view)
3165 return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3168 /* i915_gem_fence_reg.c */
3169 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3170 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3172 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3174 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3175 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3176 struct sg_table *pages);
3177 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3178 struct sg_table *pages);
3180 /* i915_gem_context.c */
3181 int __must_check i915_gem_context_init(struct drm_device *dev);
3182 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3183 void i915_gem_context_fini(struct drm_device *dev);
3184 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3185 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3186 int i915_switch_context(struct drm_i915_gem_request *req);
3187 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3189 i915_gem_context_pin_legacy(struct i915_gem_context *ctx,
3190 unsigned int flags);
3191 void i915_gem_context_free(struct kref *ctx_ref);
3192 struct drm_i915_gem_object *
3193 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3194 struct i915_gem_context *
3195 i915_gem_context_create_gvt(struct drm_device *dev);
3197 static inline struct i915_gem_context *
3198 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3200 struct i915_gem_context *ctx;
3202 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3204 ctx = idr_find(&file_priv->context_idr, id);
3206 return ERR_PTR(-ENOENT);
3211 static inline struct i915_gem_context *
3212 i915_gem_context_get(struct i915_gem_context *ctx)
3214 kref_get(&ctx->ref);
3218 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3220 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3221 kref_put(&ctx->ref, i915_gem_context_free);
3224 static inline struct intel_timeline *
3225 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3226 struct intel_engine_cs *engine)
3228 struct i915_address_space *vm;
3230 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3231 return &vm->timeline.engine[engine->id];
3234 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3236 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3239 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3240 struct drm_file *file);
3241 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3242 struct drm_file *file);
3243 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3244 struct drm_file *file_priv);
3245 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3246 struct drm_file *file_priv);
3247 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3248 struct drm_file *file);
3250 /* i915_gem_evict.c */
3251 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3252 u64 min_size, u64 alignment,
3253 unsigned cache_level,
3256 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3257 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3259 /* belongs in i915_gem_gtt.h */
3260 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3263 if (INTEL_GEN(dev_priv) < 6)
3264 intel_gtt_chipset_flush();
3267 /* i915_gem_stolen.c */
3268 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3269 struct drm_mm_node *node, u64 size,
3270 unsigned alignment);
3271 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3272 struct drm_mm_node *node, u64 size,
3273 unsigned alignment, u64 start,
3275 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3276 struct drm_mm_node *node);
3277 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3278 void i915_gem_cleanup_stolen(struct drm_device *dev);
3279 struct drm_i915_gem_object *
3280 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3281 struct drm_i915_gem_object *
3282 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3287 /* i915_gem_internal.c */
3288 struct drm_i915_gem_object *
3289 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3292 /* i915_gem_shrinker.c */
3293 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3294 unsigned long target,
3296 #define I915_SHRINK_PURGEABLE 0x1
3297 #define I915_SHRINK_UNBOUND 0x2
3298 #define I915_SHRINK_BOUND 0x4
3299 #define I915_SHRINK_ACTIVE 0x8
3300 #define I915_SHRINK_VMAPS 0x10
3301 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3302 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3303 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3306 /* i915_gem_tiling.c */
3307 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3309 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3311 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3312 i915_gem_object_is_tiled(obj);
3315 /* i915_debugfs.c */
3316 #ifdef CONFIG_DEBUG_FS
3317 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3318 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3319 int i915_debugfs_connector_add(struct drm_connector *connector);
3320 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3322 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3323 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3324 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3326 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3329 /* i915_gpu_error.c */
3330 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3333 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3334 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3335 const struct i915_error_state_file_priv *error);
3336 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3337 struct drm_i915_private *i915,
3338 size_t count, loff_t pos);
3339 static inline void i915_error_state_buf_release(
3340 struct drm_i915_error_state_buf *eb)
3344 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3346 const char *error_msg);
3347 void i915_error_state_get(struct drm_device *dev,
3348 struct i915_error_state_file_priv *error_priv);
3349 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3350 void i915_destroy_error_state(struct drm_device *dev);
3354 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3356 const char *error_msg)
3360 static inline void i915_destroy_error_state(struct drm_device *dev)
3366 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3368 /* i915_cmd_parser.c */
3369 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3370 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3371 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3372 bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
3373 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3374 struct drm_i915_gem_object *batch_obj,
3375 struct drm_i915_gem_object *shadow_batch_obj,
3376 u32 batch_start_offset,
3380 /* i915_suspend.c */
3381 extern int i915_save_state(struct drm_device *dev);
3382 extern int i915_restore_state(struct drm_device *dev);
3385 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3386 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3389 extern int intel_setup_gmbus(struct drm_device *dev);
3390 extern void intel_teardown_gmbus(struct drm_device *dev);
3391 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3394 extern struct i2c_adapter *
3395 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3396 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3397 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3398 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3400 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3402 extern void intel_i2c_reset(struct drm_device *dev);
3405 int intel_bios_init(struct drm_i915_private *dev_priv);
3406 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3407 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3408 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3409 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3410 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3411 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3412 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3413 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3415 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3419 /* intel_opregion.c */
3421 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3422 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3423 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3424 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3425 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3427 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3429 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3431 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3432 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3433 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3434 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3438 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3443 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3447 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3455 extern void intel_register_dsm_handler(void);
3456 extern void intel_unregister_dsm_handler(void);
3458 static inline void intel_register_dsm_handler(void) { return; }
3459 static inline void intel_unregister_dsm_handler(void) { return; }
3460 #endif /* CONFIG_ACPI */
3462 /* intel_device_info.c */
3463 static inline struct intel_device_info *
3464 mkwrite_device_info(struct drm_i915_private *dev_priv)
3466 return (struct intel_device_info *)&dev_priv->info;
3469 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3470 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3473 extern void intel_modeset_init_hw(struct drm_device *dev);
3474 extern int intel_modeset_init(struct drm_device *dev);
3475 extern void intel_modeset_gem_init(struct drm_device *dev);
3476 extern void intel_modeset_cleanup(struct drm_device *dev);
3477 extern int intel_connector_register(struct drm_connector *);
3478 extern void intel_connector_unregister(struct drm_connector *);
3479 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3481 extern void intel_display_resume(struct drm_device *dev);
3482 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3483 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3484 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3485 extern void intel_init_pch_refclk(struct drm_device *dev);
3486 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3487 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3490 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3491 struct drm_file *file);
3494 extern struct intel_overlay_error_state *
3495 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3496 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3497 struct intel_overlay_error_state *error);
3499 extern struct intel_display_error_state *
3500 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3501 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3502 struct drm_i915_private *dev_priv,
3503 struct intel_display_error_state *error);
3505 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3506 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3508 /* intel_sideband.c */
3509 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3510 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3511 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3512 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3513 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3514 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3515 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3516 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3517 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3518 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3519 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3520 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3521 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3522 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3523 enum intel_sbi_destination destination);
3524 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3525 enum intel_sbi_destination destination);
3526 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3527 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3529 /* intel_dpio_phy.c */
3530 void bxt_port_to_phy_channel(enum port port,
3531 enum dpio_phy *phy, enum dpio_channel *ch);
3532 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3533 enum port port, u32 margin, u32 scale,
3534 u32 enable, u32 deemphasis);
3535 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3536 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3537 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3539 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3541 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3542 uint8_t lane_count);
3543 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3544 uint8_t lane_lat_optim_mask);
3545 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3547 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3548 u32 deemph_reg_value, u32 margin_reg_value,
3549 bool uniq_trans_scale);
3550 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3552 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3553 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3554 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3555 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3557 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3558 u32 demph_reg_value, u32 preemph_reg_value,
3559 u32 uniqtranscale_reg_value, u32 tx3_demph);
3560 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3561 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3562 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3564 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3565 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3567 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3568 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3570 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3571 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3572 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3573 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3575 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3576 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3577 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3578 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3580 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3581 * will be implemented using 2 32-bit writes in an arbitrary order with
3582 * an arbitrary delay between them. This can cause the hardware to
3583 * act upon the intermediate value, possibly leading to corruption and
3584 * machine death. For this reason we do not support I915_WRITE64, or
3585 * dev_priv->uncore.funcs.mmio_writeq.
3587 * When reading a 64-bit value as two 32-bit values, the delay may cause
3588 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3589 * occasionally a 64-bit register does not actualy support a full readq
3590 * and must be read using two 32-bit reads.
3592 * You have been warned.
3594 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3596 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3597 u32 upper, lower, old_upper, loop = 0; \
3598 upper = I915_READ(upper_reg); \
3600 old_upper = upper; \
3601 lower = I915_READ(lower_reg); \
3602 upper = I915_READ(upper_reg); \
3603 } while (upper != old_upper && loop++ < 2); \
3604 (u64)upper << 32 | lower; })
3606 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3607 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3609 #define __raw_read(x, s) \
3610 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3613 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3616 #define __raw_write(x, s) \
3617 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3618 i915_reg_t reg, uint##x##_t val) \
3620 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3635 /* These are untraced mmio-accessors that are only valid to be used inside
3636 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3639 * Think twice, and think again, before using these.
3641 * As an example, these accessors can possibly be used between:
3643 * spin_lock_irq(&dev_priv->uncore.lock);
3644 * intel_uncore_forcewake_get__locked();
3648 * intel_uncore_forcewake_put__locked();
3649 * spin_unlock_irq(&dev_priv->uncore.lock);
3652 * Note: some registers may not need forcewake held, so
3653 * intel_uncore_forcewake_{get,put} can be omitted, see
3654 * intel_uncore_forcewake_for_reg().
3656 * Certain architectures will die if the same cacheline is concurrently accessed
3657 * by different clients (e.g. on Ivybridge). Access to registers should
3658 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3659 * a more localised lock guarding all access to that bank of registers.
3661 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3662 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3663 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3664 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3666 /* "Broadcast RGB" property */
3667 #define INTEL_BROADCAST_RGB_AUTO 0
3668 #define INTEL_BROADCAST_RGB_FULL 1
3669 #define INTEL_BROADCAST_RGB_LIMITED 2
3671 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3673 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3674 return VLV_VGACNTRL;
3675 else if (INTEL_GEN(dev_priv) >= 5)
3676 return CPU_VGACNTRL;
3681 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3683 unsigned long j = msecs_to_jiffies(m);
3685 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3688 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3690 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3693 static inline unsigned long
3694 timespec_to_jiffies_timeout(const struct timespec *value)
3696 unsigned long j = timespec_to_jiffies(value);
3698 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3702 * If you need to wait X milliseconds between events A and B, but event B
3703 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3704 * when event A happened, then just before event B you call this function and
3705 * pass the timestamp as the first argument, and X as the second argument.
3708 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3710 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3713 * Don't re-read the value of "jiffies" every time since it may change
3714 * behind our back and break the math.
3716 tmp_jiffies = jiffies;
3717 target_jiffies = timestamp_jiffies +
3718 msecs_to_jiffies_timeout(to_wait_ms);
3720 if (time_after(target_jiffies, tmp_jiffies)) {
3721 remaining_jiffies = target_jiffies - tmp_jiffies;
3722 while (remaining_jiffies)
3724 schedule_timeout_uninterruptible(remaining_jiffies);
3729 __i915_request_irq_complete(struct drm_i915_gem_request *req)
3731 struct intel_engine_cs *engine = req->engine;
3733 /* Before we do the heavier coherent read of the seqno,
3734 * check the value (hopefully) in the CPU cacheline.
3736 if (__i915_gem_request_completed(req))
3739 /* Ensure our read of the seqno is coherent so that we
3740 * do not "miss an interrupt" (i.e. if this is the last
3741 * request and the seqno write from the GPU is not visible
3742 * by the time the interrupt fires, we will see that the
3743 * request is incomplete and go back to sleep awaiting
3744 * another interrupt that will never come.)
3746 * Strictly, we only need to do this once after an interrupt,
3747 * but it is easier and safer to do it every time the waiter
3750 if (engine->irq_seqno_barrier &&
3751 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3752 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3753 struct task_struct *tsk;
3755 /* The ordering of irq_posted versus applying the barrier
3756 * is crucial. The clearing of the current irq_posted must
3757 * be visible before we perform the barrier operation,
3758 * such that if a subsequent interrupt arrives, irq_posted
3759 * is reasserted and our task rewoken (which causes us to
3760 * do another __i915_request_irq_complete() immediately
3761 * and reapply the barrier). Conversely, if the clear
3762 * occurs after the barrier, then an interrupt that arrived
3763 * whilst we waited on the barrier would not trigger a
3764 * barrier on the next pass, and the read may not see the
3767 engine->irq_seqno_barrier(engine);
3769 /* If we consume the irq, but we are no longer the bottom-half,
3770 * the real bottom-half may not have serialised their own
3771 * seqno check with the irq-barrier (i.e. may have inspected
3772 * the seqno before we believe it coherent since they see
3773 * irq_posted == false but we are still running).
3776 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3777 if (tsk && tsk != current)
3778 /* Note that if the bottom-half is changed as we
3779 * are sending the wake-up, the new bottom-half will
3780 * be woken by whomever made the change. We only have
3781 * to worry about when we steal the irq-posted for
3784 wake_up_process(tsk);
3787 if (__i915_gem_request_completed(req))
3794 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3795 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3798 int remap_io_mapping(struct vm_area_struct *vma,
3799 unsigned long addr, unsigned long pfn, unsigned long size,
3800 struct io_mapping *iomap);
3802 #define ptr_mask_bits(ptr) ({ \
3803 unsigned long __v = (unsigned long)(ptr); \
3804 (typeof(ptr))(__v & PAGE_MASK); \
3807 #define ptr_unpack_bits(ptr, bits) ({ \
3808 unsigned long __v = (unsigned long)(ptr); \
3809 (bits) = __v & ~PAGE_MASK; \
3810 (typeof(ptr))(__v & PAGE_MASK); \
3813 #define ptr_pack_bits(ptr, bits) \
3814 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3816 #define fetch_and_zero(ptr) ({ \
3817 typeof(*ptr) __T = *(ptr); \
3818 *(ptr) = (typeof(*ptr))0; \