1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
35 #include <linux/pm_qos.h>
37 #include <drm/ttm/ttm_device.h>
39 #include "display/intel_display_limits.h"
40 #include "display/intel_display_core.h"
42 #include "gem/i915_gem_context_types.h"
43 #include "gem/i915_gem_shrinker.h"
44 #include "gem/i915_gem_stolen.h"
46 #include "gt/intel_engine.h"
47 #include "gt/intel_gt_types.h"
48 #include "gt/intel_region_lmem.h"
49 #include "gt/intel_workarounds.h"
50 #include "gt/uc/intel_uc.h"
52 #include "soc/intel_pch.h"
54 #include "i915_drm_client.h"
56 #include "i915_gpu_error.h"
57 #include "i915_params.h"
58 #include "i915_perf_types.h"
59 #include "i915_scheduler.h"
60 #include "i915_utils.h"
61 #include "intel_device_info.h"
62 #include "intel_memory_region.h"
63 #include "intel_runtime_pm.h"
64 #include "intel_step.h"
65 #include "intel_uncore.h"
67 struct drm_i915_clock_gating_funcs;
68 struct vlv_s0ix_state;
71 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
73 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */
76 * The start and end of DSM which we can optionally use to create GEM
77 * objects backed by stolen memory.
79 * Note that usable_size tells us exactly how much of this we are
80 * actually allowed to use, given that some portion of it is in fact
81 * reserved for use by hardware functions.
83 struct resource stolen;
86 * Reserved portion of DSM.
88 struct resource reserved;
91 * Total size minus reserved ranges.
93 * DSM is segmented in hardware with different portions offlimits to
96 * The drm_mm is initialised to the total accessible range, as found
97 * from the PCI config. On Broadwell+, this is further restricted to
98 * avoid the first page! The upper end of DSM is reserved for hardware
99 * functions and similarly removed from the accessible range.
101 resource_size_t usable_size;
104 struct i915_suspend_saved_registers {
112 #define MAX_L3_SLICES 2
113 struct intel_l3_parity {
114 u32 *remap_info[MAX_L3_SLICES];
115 struct work_struct error_work;
121 * Shortcut for the stolen region. This points to either
122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
126 struct intel_memory_region *stolen_region;
127 /** Memory allocator for GTT stolen memory */
128 struct drm_mm stolen;
129 /** Protects the usage of the GTT stolen memory allocator. This is
130 * always the inner lock when overlapping with struct_mutex. */
131 struct mutex stolen_lock;
133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
137 * List of objects which are purgeable.
139 struct list_head purge_list;
142 * List of objects which have allocated pages and are shrinkable.
144 struct list_head shrink_list;
147 * List of objects which are pending destruction.
149 struct llist_head free_list;
150 struct work_struct free_work;
152 * Count of objects pending destructions. Used to skip needlessly
153 * waiting on an RCU barrier if no objects are waiting to be freed.
158 * tmpfs instance used for shmem backed objects
160 struct vfsmount *gemfs;
162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
164 struct notifier_block oom_notifier;
165 struct notifier_block vmap_notifier;
166 struct shrinker shrinker;
168 #ifdef CONFIG_MMU_NOTIFIER
170 * notifier_lock for mmu notifiers, memory may not be allocated
171 * while holding this lock.
173 rwlock_t notifier_lock;
176 /* shrinker accounting, also useful for userland debugging */
181 struct i915_virtual_gpu {
182 struct mutex lock; /* serialises sending of g2v_notify command pkts */
186 u8 *initial_cfg_space;
187 struct list_head entry;
190 struct i915_selftest_stash {
192 struct ida mock_region_instances;
195 struct drm_i915_private {
196 struct drm_device drm;
198 struct intel_display display;
200 /* FIXME: Device release actions should all be moved to drmm_ */
203 /* i915 device parameters */
204 struct i915_params params;
206 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
207 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
208 struct intel_driver_caps caps;
212 struct intel_uncore uncore;
213 struct intel_uncore_mmio_debug mmio_debug;
215 struct i915_virtual_gpu vgpu;
217 struct intel_gvt *gvt;
220 struct pci_dev *pdev;
221 struct resource mch_res;
222 bool mchbar_need_disable;
225 struct rb_root uabi_engines;
226 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
228 /* protects the irq masks */
231 bool display_irqs_enabled;
233 /* Sideband mailbox protection */
234 struct mutex sb_lock;
235 struct pm_qos_request sb_qos;
237 /** Cached value of IMR to avoid reads in updating the bitfield */
240 u32 de_irq_mask[I915_MAX_PIPES];
242 u32 pipestat_irq_mask[I915_MAX_PIPES];
244 bool preserve_bios_swizzle;
246 unsigned int fsb_freq, mem_freq, is_ddr3;
247 unsigned int skl_preferred_vco_freq;
249 unsigned int max_dotclk_freq;
250 unsigned int hpll_freq;
251 unsigned int czclk_freq;
254 * wq - Driver workqueue for GEM.
256 * NOTE: Work items scheduled here are not allowed to grab any modeset
257 * locks, for otherwise the flushing done in the pageflip code will
258 * result in deadlocks.
260 struct workqueue_struct *wq;
262 /* pm private clock gating functions */
263 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
265 /* PCH chipset type */
266 enum intel_pch pch_type;
267 unsigned short pch_id;
269 unsigned long gem_quirks;
271 struct i915_gem_mm mm;
273 struct intel_l3_parity l3_parity;
277 * Cannot be determined by PCIID. You must always read a register.
281 struct i915_gpu_error gpu_error;
284 struct i915_suspend_saved_registers regfile;
285 struct vlv_s0ix_state *vlv_s0ix_state;
288 bool wm_lv_0_adjust_needed;
290 bool symmetric_memory;
291 enum intel_dram_type {
301 u8 num_psf_gv_points;
304 struct intel_runtime_pm runtime_pm;
306 struct i915_perf perf;
308 struct i915_hwmon *hwmon;
310 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
314 * i915->gt[0] == &i915->gt0
316 #define I915_MAX_GT 4
317 struct intel_gt *gt[I915_MAX_GT];
319 struct kobject *sysfs_gt;
321 /* Quick lookup of media GT (current platforms only have one) */
322 struct intel_gt *media_gt;
325 struct i915_gem_contexts {
326 spinlock_t lock; /* locks list */
327 struct list_head list;
331 * We replace the local file with a global mappings as the
332 * backing storage for the mmap is on the device and not
333 * on the struct file, and we do not want to prolong the
334 * lifetime of the local fd. To minimise the number of
335 * anonymous inodes we create, we use a global singleton to
336 * share the global mapping.
338 struct file *mmap_singleton;
341 struct intel_pxp *pxp;
343 /* For i915gm/i945gm vblank irq workaround */
350 struct i915_drm_clients clients;
352 /* The TTM device structure. */
353 struct ttm_device bdev;
355 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
358 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
359 * will be rejected. Instead look for a better place.
363 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
365 return container_of(dev, struct drm_i915_private, drm);
368 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
370 return dev_get_drvdata(kdev);
373 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
375 return pci_get_drvdata(pdev);
378 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
383 /* Simple iterator over all initialised engines */
384 #define for_each_engine(engine__, dev_priv__, id__) \
386 (id__) < I915_NUM_ENGINES; \
388 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
390 /* Iterator over subset of engines selected by mask */
391 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
392 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
394 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
397 #define rb_to_uabi_engine(rb) \
398 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
400 #define for_each_uabi_engine(engine__, i915__) \
401 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
403 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
405 #define for_each_uabi_class_engine(engine__, class__, i915__) \
406 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
407 (engine__) && (engine__)->uabi_class == (class__); \
408 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
410 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
411 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
412 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
414 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
416 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
418 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
419 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
420 RUNTIME_INFO(i915)->graphics.ip.rel)
421 #define IS_GRAPHICS_VER(i915, from, until) \
422 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
424 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
425 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
426 RUNTIME_INFO(i915)->media.ip.rel)
427 #define IS_MEDIA_VER(i915, from, until) \
428 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
430 #define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver)
431 #define IS_DISPLAY_VER(i915, from, until) \
432 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
434 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
436 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
437 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
438 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
439 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
441 #define IS_DISPLAY_STEP(__i915, since, until) \
442 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
443 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
445 #define IS_GRAPHICS_STEP(__i915, since, until) \
446 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
447 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
449 #define IS_MEDIA_STEP(__i915, since, until) \
450 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
451 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
453 #define IS_BASEDIE_STEP(__i915, since, until) \
454 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
455 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
457 static __always_inline unsigned int
458 __platform_mask_index(const struct intel_runtime_info *info,
459 enum intel_platform p)
461 const unsigned int pbits =
462 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
464 /* Expand the platform_mask array if this fails. */
465 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
466 pbits * ARRAY_SIZE(info->platform_mask));
471 static __always_inline unsigned int
472 __platform_mask_bit(const struct intel_runtime_info *info,
473 enum intel_platform p)
475 const unsigned int pbits =
476 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
478 return p % pbits + INTEL_SUBPLATFORM_BITS;
482 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
484 const unsigned int pi = __platform_mask_index(info, p);
486 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
489 static __always_inline bool
490 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
492 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
493 const unsigned int pi = __platform_mask_index(info, p);
494 const unsigned int pb = __platform_mask_bit(info, p);
496 BUILD_BUG_ON(!__builtin_constant_p(p));
498 return info->platform_mask[pi] & BIT(pb);
501 static __always_inline bool
502 IS_SUBPLATFORM(const struct drm_i915_private *i915,
503 enum intel_platform p, unsigned int s)
505 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
506 const unsigned int pi = __platform_mask_index(info, p);
507 const unsigned int pb = __platform_mask_bit(info, p);
508 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
509 const u32 mask = info->platform_mask[pi];
511 BUILD_BUG_ON(!__builtin_constant_p(p));
512 BUILD_BUG_ON(!__builtin_constant_p(s));
513 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
515 /* Shift and test on the MSB position so sign flag can be used. */
516 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
519 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
520 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
522 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
523 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
524 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
525 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
526 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
527 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
528 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
529 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
530 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
531 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
532 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
533 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
534 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
535 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
536 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
537 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
538 #define IS_IRONLAKE_M(dev_priv) \
539 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
540 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
541 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
542 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
543 INTEL_INFO(dev_priv)->gt == 1)
544 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
545 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
546 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
547 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
548 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
549 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
550 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
551 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
552 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
553 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
554 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
555 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
556 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
557 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
558 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
559 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
560 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
561 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
562 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
563 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
564 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
565 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
567 #define IS_METEORLAKE_M(dev_priv) \
568 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
569 #define IS_METEORLAKE_P(dev_priv) \
570 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
571 #define IS_DG2_G10(dev_priv) \
572 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
573 #define IS_DG2_G11(dev_priv) \
574 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
575 #define IS_DG2_G12(dev_priv) \
576 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
577 #define IS_ADLS_RPLS(dev_priv) \
578 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
579 #define IS_ADLP_N(dev_priv) \
580 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
581 #define IS_ADLP_RPLP(dev_priv) \
582 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
583 #define IS_ADLP_RPLU(dev_priv) \
584 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
585 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
586 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
587 #define IS_BDW_ULT(dev_priv) \
588 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
589 #define IS_BDW_ULX(dev_priv) \
590 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
591 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
592 INTEL_INFO(dev_priv)->gt == 3)
593 #define IS_HSW_ULT(dev_priv) \
594 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
595 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
596 INTEL_INFO(dev_priv)->gt == 3)
597 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
598 INTEL_INFO(dev_priv)->gt == 1)
599 /* ULX machines are also considered ULT. */
600 #define IS_HSW_ULX(dev_priv) \
601 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
602 #define IS_SKL_ULT(dev_priv) \
603 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
604 #define IS_SKL_ULX(dev_priv) \
605 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
606 #define IS_KBL_ULT(dev_priv) \
607 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
608 #define IS_KBL_ULX(dev_priv) \
609 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
610 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
611 INTEL_INFO(dev_priv)->gt == 2)
612 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
613 INTEL_INFO(dev_priv)->gt == 3)
614 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
615 INTEL_INFO(dev_priv)->gt == 4)
616 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
617 INTEL_INFO(dev_priv)->gt == 2)
618 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
619 INTEL_INFO(dev_priv)->gt == 3)
620 #define IS_CFL_ULT(dev_priv) \
621 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
622 #define IS_CFL_ULX(dev_priv) \
623 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
624 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
625 INTEL_INFO(dev_priv)->gt == 2)
626 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
627 INTEL_INFO(dev_priv)->gt == 3)
629 #define IS_CML_ULT(dev_priv) \
630 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
631 #define IS_CML_ULX(dev_priv) \
632 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
633 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
634 INTEL_INFO(dev_priv)->gt == 2)
636 #define IS_ICL_WITH_PORT_F(dev_priv) \
637 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
639 #define IS_TGL_UY(dev_priv) \
640 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
642 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
644 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
645 (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
646 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
647 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
649 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
650 (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
651 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
652 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
654 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
655 (IS_TIGERLAKE(__i915) && \
656 IS_DISPLAY_STEP(__i915, since, until))
658 #define IS_RKL_DISPLAY_STEP(p, since, until) \
659 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
661 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
662 (IS_ALDERLAKE_S(__i915) && \
663 IS_DISPLAY_STEP(__i915, since, until))
665 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
666 (IS_ALDERLAKE_S(__i915) && \
667 IS_GRAPHICS_STEP(__i915, since, until))
669 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
670 (IS_ALDERLAKE_P(__i915) && \
671 IS_DISPLAY_STEP(__i915, since, until))
673 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
674 (IS_ALDERLAKE_P(__i915) && \
675 IS_GRAPHICS_STEP(__i915, since, until))
677 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
678 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
680 #define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
681 (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
682 IS_GRAPHICS_STEP(__i915, since, until))
684 #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
685 (IS_METEORLAKE(__i915) && \
686 IS_DISPLAY_STEP(__i915, since, until))
688 #define IS_MTL_MEDIA_STEP(__i915, since, until) \
689 (IS_METEORLAKE(__i915) && \
690 IS_MEDIA_STEP(__i915, since, until))
693 * DG2 hardware steppings are a bit unusual. The hardware design was forked to
694 * create three variants (G10, G11, and G12) which each have distinct
695 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT
696 * stepping back to "A0" for their first iterations, even though they're more
697 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
698 * functionality and workarounds. However the display stepping does not reset
699 * in the same manner --- a specific stepping like "B0" has a consistent
700 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
702 * TLDR: All GT workarounds and stepping-specific logic must be applied in
703 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
704 * and stepping-specific logic will be applied with a general DG2-wide stepping
707 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
708 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
709 IS_GRAPHICS_STEP(__i915, since, until))
711 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
713 IS_DISPLAY_STEP(__i915, since, until))
715 #define IS_PVC_BD_STEP(__i915, since, until) \
716 (IS_PONTEVECCHIO(__i915) && \
717 IS_BASEDIE_STEP(__i915, since, until))
719 #define IS_PVC_CT_STEP(__i915, since, until) \
720 (IS_PONTEVECCHIO(__i915) && \
721 IS_GRAPHICS_STEP(__i915, since, until))
723 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
724 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
725 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
727 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
728 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
730 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
731 unsigned int first__ = (first); \
732 unsigned int count__ = (count); \
733 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
736 #define ENGINE_INSTANCES_MASK(gt, first, count) \
737 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
739 #define RCS_MASK(gt) \
740 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
741 #define BCS_MASK(gt) \
742 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
743 #define VDBOX_MASK(gt) \
744 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
745 #define VEBOX_MASK(gt) \
746 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
747 #define CCS_MASK(gt) \
748 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
750 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
753 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
754 * All later gens can run the final buffer from the ppgtt
756 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
758 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
759 #define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
760 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
761 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
762 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
763 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
765 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
767 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
768 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
769 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
770 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
772 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
774 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
775 #define HAS_PPGTT(dev_priv) \
776 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
777 #define HAS_FULL_PPGTT(dev_priv) \
778 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
780 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
781 GEM_BUG_ON((sizes) == 0); \
782 ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
785 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
786 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
787 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
789 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
790 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
792 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
793 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
795 /* WaRsDisableCoarsePowerGating:skl,cnl */
796 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
797 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
799 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
800 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
801 IS_GEMINILAKE(dev_priv) || \
802 IS_KABYLAKE(dev_priv))
804 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
805 * rows, which changed the alignment requirements and fence programming.
807 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
808 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
809 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
810 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
812 #define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
813 #define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
814 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
816 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
818 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
819 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
821 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
823 #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
824 #define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
825 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
826 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
827 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
828 #define HAS_PSR_HW_TRACKING(dev_priv) \
829 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
830 #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
831 #define HAS_TRANSCODER(dev_priv, trans) ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
833 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
834 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
835 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
837 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
839 #define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc)
840 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
841 #define HAS_DSC(__i915) (RUNTIME_INFO(__i915)->has_dsc)
842 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
844 #define HAS_HECI_PXP(dev_priv) \
845 (INTEL_INFO(dev_priv)->has_heci_pxp)
847 #define HAS_HECI_GSCFI(dev_priv) \
848 (INTEL_INFO(dev_priv)->has_heci_gscfi)
850 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
852 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
854 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
855 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
857 #define HAS_OA_BPC_REPORTING(dev_priv) \
858 (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
859 #define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
860 (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
863 * Set this flag, when platform requires 64K GTT page sizes or larger for
864 * device local memory access.
866 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
868 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
869 #define HAS_SAGV(dev_priv) (DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv))
871 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
872 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
874 #define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
877 * Platform has the dedicated compression control state for each lmem surfaces
878 * stored in lmem to support the 3D and media compression formats.
880 #define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
882 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
884 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
886 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
888 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
890 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
892 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
894 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
896 /* DPF == dynamic parity feature */
897 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
898 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
899 2 : HAS_L3_DPF(dev_priv))
901 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
903 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
905 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
907 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
909 /* Only valid when HAS_DISPLAY() is true */
910 #define INTEL_DISPLAY_ENABLED(dev_priv) \
911 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \
912 !(dev_priv)->params.disable_display && \
913 !intel_opregion_headless_sku(dev_priv))
915 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
916 (INTEL_INFO(dev_priv)->has_guc_deprivilege)
918 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
919 IS_ALDERLAKE_S(dev_priv))
921 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
923 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
925 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
927 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
928 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
930 /* intel_device_info.c */
931 static inline struct intel_device_info *
932 mkwrite_device_info(struct drm_i915_private *dev_priv)
934 return (struct intel_device_info *)INTEL_INFO(dev_priv);