1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <asm/hypervisor.h>
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <linux/backlight.h>
42 #include <linux/hash.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/mm_types.h>
46 #include <linux/perf_event.h>
47 #include <linux/pm_qos.h>
48 #include <linux/dma-resv.h>
49 #include <linux/shmem_fs.h>
50 #include <linux/stackdepot.h>
51 #include <linux/xarray.h>
53 #include <drm/intel-gtt.h>
54 #include <drm/drm_gem.h>
55 #include <drm/drm_auth.h>
56 #include <drm/drm_cache.h>
57 #include <drm/drm_util.h>
58 #include <drm/drm_dsc.h>
59 #include <drm/drm_atomic.h>
60 #include <drm/drm_connector.h>
61 #include <drm/i915_mei_hdcp_interface.h>
62 #include <drm/ttm/ttm_device.h>
64 #include "i915_params.h"
66 #include "i915_utils.h"
68 #include "display/intel_bios.h"
69 #include "display/intel_display.h"
70 #include "display/intel_display_power.h"
71 #include "display/intel_dmc.h"
72 #include "display/intel_dpll_mgr.h"
73 #include "display/intel_dsb.h"
74 #include "display/intel_frontbuffer.h"
75 #include "display/intel_global_state.h"
76 #include "display/intel_gmbus.h"
77 #include "display/intel_opregion.h"
79 #include "gem/i915_gem_context_types.h"
80 #include "gem/i915_gem_shrinker.h"
81 #include "gem/i915_gem_stolen.h"
82 #include "gem/i915_gem_lmem.h"
84 #include "gt/intel_engine.h"
85 #include "gt/intel_gt_types.h"
86 #include "gt/intel_region_lmem.h"
87 #include "gt/intel_workarounds.h"
88 #include "gt/uc/intel_uc.h"
90 #include "intel_device_info.h"
91 #include "intel_memory_region.h"
92 #include "intel_pch.h"
93 #include "intel_runtime_pm.h"
94 #include "intel_step.h"
95 #include "intel_uncore.h"
96 #include "intel_wakeref.h"
97 #include "intel_wopcm.h"
100 #include "i915_gem_gtt.h"
101 #include "i915_gpu_error.h"
102 #include "i915_perf_types.h"
103 #include "i915_request.h"
104 #include "i915_scheduler.h"
105 #include "gt/intel_timeline.h"
106 #include "i915_vma.h"
107 #include "i915_irq.h"
110 /* General customization:
113 #define DRIVER_NAME "i915"
114 #define DRIVER_DESC "Intel Graphics"
115 #define DRIVER_DATE "20201103"
116 #define DRIVER_TIMESTAMP 1604406085
118 struct drm_i915_gem_object;
122 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
141 #define for_each_hpd_pin(__pin) \
142 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
144 /* Threshold == 5 for long IRQs, 50 for short */
145 #define HPD_STORM_DEFAULT_THRESHOLD 50
147 struct i915_hotplug {
148 struct delayed_work hotplug_work;
150 const u32 *hpd, *pch_hpd;
153 unsigned long last_jiffies;
158 HPD_MARK_DISABLED = 2
160 } stats[HPD_NUM_PINS];
163 struct delayed_work reenable_work;
167 struct work_struct dig_port_work;
169 struct work_struct poll_init_work;
172 unsigned int hpd_storm_threshold;
173 /* Whether or not to count short HPD IRQs in HPD storms */
174 u8 hpd_short_storm_enabled;
177 * if we get a HPD irq from DP and a HPD irq from non-DP
178 * the non-DP HPD could block the workqueue on a mode config
179 * mutex getting, that userspace may have taken. However
180 * userspace is waiting on the DP workqueue to run which is
181 * blocked behind the non-DP one.
183 struct workqueue_struct *dp_wq;
186 #define I915_GEM_GPU_DOMAINS \
187 (I915_GEM_DOMAIN_RENDER | \
188 I915_GEM_DOMAIN_SAMPLER | \
189 I915_GEM_DOMAIN_COMMAND | \
190 I915_GEM_DOMAIN_INSTRUCTION | \
191 I915_GEM_DOMAIN_VERTEX)
193 struct drm_i915_private;
194 struct i915_mm_struct;
195 struct i915_mmu_object;
197 struct drm_i915_file_private {
198 struct drm_i915_private *dev_priv;
201 struct drm_file *file;
205 struct xarray context_xa;
208 unsigned int bsd_engine;
211 * Every context ban increments per client ban score. Also
212 * hangs in short succession increments ban score. If ban threshold
213 * is reached, client is considered banned and submitting more work
214 * will fail. This is a stop gap measure to limit the badly behaving
215 * clients access to gpu. Note that unbannable contexts never increment
216 * the client ban score.
218 #define I915_CLIENT_SCORE_HANG_FAST 1
219 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
220 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
221 #define I915_CLIENT_SCORE_BANNED 9
222 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
224 unsigned long hang_timestamp;
227 /* Interface history:
230 * 1.2: Add Power Management
231 * 1.3: Add vblank support
232 * 1.4: Fix cmdbuffer path, add heap destroy
233 * 1.5: Add vblank pipe configuration
234 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
235 * - Support vertical blank on secondary display pipe
237 #define DRIVER_MAJOR 1
238 #define DRIVER_MINOR 6
239 #define DRIVER_PATCHLEVEL 0
241 struct intel_overlay;
242 struct intel_overlay_error_state;
244 struct sdvo_device_mapping {
253 struct intel_connector;
254 struct intel_encoder;
255 struct intel_atomic_state;
256 struct intel_cdclk_config;
257 struct intel_cdclk_state;
258 struct intel_cdclk_vals;
259 struct intel_initial_plane_config;
264 struct drm_i915_display_funcs {
265 void (*get_cdclk)(struct drm_i915_private *dev_priv,
266 struct intel_cdclk_config *cdclk_config);
267 void (*set_cdclk)(struct drm_i915_private *dev_priv,
268 const struct intel_cdclk_config *cdclk_config,
270 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
271 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
272 enum i9xx_plane_id i9xx_plane);
273 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
274 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
275 void (*initial_watermarks)(struct intel_atomic_state *state,
276 struct intel_crtc *crtc);
277 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
278 struct intel_crtc *crtc);
279 void (*optimize_watermarks)(struct intel_atomic_state *state,
280 struct intel_crtc *crtc);
281 int (*compute_global_watermarks)(struct intel_atomic_state *state);
282 void (*update_wm)(struct intel_crtc *crtc);
283 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
284 u8 (*calc_voltage_level)(int cdclk);
285 /* Returns the active state of the crtc, and if the crtc is active,
286 * fills out the pipe-config with the hw state. */
287 bool (*get_pipe_config)(struct intel_crtc *,
288 struct intel_crtc_state *);
289 void (*get_initial_plane_config)(struct intel_crtc *,
290 struct intel_initial_plane_config *);
291 int (*crtc_compute_clock)(struct intel_crtc *crtc,
292 struct intel_crtc_state *crtc_state);
293 void (*crtc_enable)(struct intel_atomic_state *state,
294 struct intel_crtc *crtc);
295 void (*crtc_disable)(struct intel_atomic_state *state,
296 struct intel_crtc *crtc);
297 void (*commit_modeset_enables)(struct intel_atomic_state *state);
298 void (*commit_modeset_disables)(struct intel_atomic_state *state);
299 void (*audio_codec_enable)(struct intel_encoder *encoder,
300 const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state);
302 void (*audio_codec_disable)(struct intel_encoder *encoder,
303 const struct intel_crtc_state *old_crtc_state,
304 const struct drm_connector_state *old_conn_state);
305 void (*fdi_link_train)(struct intel_crtc *crtc,
306 const struct intel_crtc_state *crtc_state);
307 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
308 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
309 /* clock updates for mode set */
311 /* render clock increase/decrease */
312 /* display clock increase/decrease */
313 /* pll clock increase/decrease */
315 int (*color_check)(struct intel_crtc_state *crtc_state);
317 * Program double buffered color management registers during
318 * vblank evasion. The registers should then latch during the
319 * next vblank start, alongside any other double buffered registers
320 * involved with the same commit.
322 void (*color_commit)(const struct intel_crtc_state *crtc_state);
324 * Load LUTs (and other single buffered color management
325 * registers). Will (hopefully) be called during the vblank
326 * following the latching of any double buffered registers
327 * involved with the same commit.
329 void (*load_luts)(const struct intel_crtc_state *crtc_state);
330 void (*read_luts)(struct intel_crtc_state *crtc_state);
333 enum i915_cache_level {
335 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
336 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
337 caches, eg sampler/render caches, and the
338 large Last-Level-Cache. LLC is coherent with
339 the CPU, but L3 is only visible to the GPU. */
340 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
343 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
346 /* This is always the inner lock when overlapping with struct_mutex and
347 * it's the outer lock when overlapping with stolen_lock. */
350 unsigned int possible_framebuffer_bits;
351 unsigned int busy_bits;
352 struct intel_crtc *crtc;
354 struct drm_mm_node compressed_fb;
355 struct drm_mm_node *compressed_llb;
363 bool underrun_detected;
364 struct work_struct underrun_work;
367 * Due to the atomic rules we can't access some structures without the
368 * appropriate locking, so we cache information here in order to avoid
371 struct intel_fbc_state_cache {
373 unsigned int mode_flags;
374 u32 hsw_bdw_pixel_rate;
378 unsigned int rotation;
383 * Display surface base address adjustement for
384 * pageflips. Note that on gen4+ this only adjusts up
385 * to a tile, offsets within a tile are handled in
386 * the hw itself (with the TILEOFF register).
391 u16 pixel_blend_mode;
395 const struct drm_format_info *format;
400 unsigned int fence_y_offset;
401 u16 gen9_wa_cfb_stride;
408 * This structure contains everything that's relevant to program the
409 * hardware registers. When we want to figure out if we need to disable
410 * and re-enable FBC for a new configuration we just check if there's
411 * something different in the struct. The genx_fbc_activate functions
412 * are supposed to read from it in order to program the registers.
414 struct intel_fbc_reg_params {
417 enum i9xx_plane_id i9xx_plane;
421 const struct drm_format_info *format;
427 unsigned int fence_y_offset;
428 u16 gen9_wa_cfb_stride;
434 const char *no_fbc_reason;
438 * HIGH_RR is the highest eDP panel refresh rate read from EDID
439 * LOW_RR is the lowest eDP panel refresh rate found from EDID
440 * parsing for same resolution.
442 enum drrs_refresh_rate_type {
445 DRRS_MAX_RR, /* RR count */
448 enum drrs_support_type {
449 DRRS_NOT_SUPPORTED = 0,
450 STATIC_DRRS_SUPPORT = 1,
451 SEAMLESS_DRRS_SUPPORT = 2
457 struct delayed_work work;
459 unsigned busy_frontbuffer_bits;
460 enum drrs_refresh_rate_type refresh_rate_type;
461 enum drrs_support_type type;
464 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
465 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
466 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
467 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
468 #define QUIRK_INCREASE_T12_DELAY (1<<6)
469 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
472 struct intel_fbc_work;
475 struct i2c_adapter adapter;
476 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
480 struct i2c_algo_bit_data bit_algo;
481 struct drm_i915_private *dev_priv;
484 struct i915_suspend_saved_registers {
492 struct vlv_s0ix_state;
494 #define MAX_L3_SLICES 2
495 struct intel_l3_parity {
496 u32 *remap_info[MAX_L3_SLICES];
497 struct work_struct error_work;
503 * Shortcut for the stolen region. This points to either
504 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
505 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
508 struct intel_memory_region *stolen_region;
509 /** Memory allocator for GTT stolen memory */
510 struct drm_mm stolen;
511 /** Protects the usage of the GTT stolen memory allocator. This is
512 * always the inner lock when overlapping with struct_mutex. */
513 struct mutex stolen_lock;
515 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
519 * List of objects which are purgeable.
521 struct list_head purge_list;
524 * List of objects which have allocated pages and are shrinkable.
526 struct list_head shrink_list;
529 * List of objects which are pending destruction.
531 struct llist_head free_list;
532 struct work_struct free_work;
534 * Count of objects pending destructions. Used to skip needlessly
535 * waiting on an RCU barrier if no objects are waiting to be freed.
540 * tmpfs instance used for shmem backed objects
542 struct vfsmount *gemfs;
544 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
546 struct notifier_block oom_notifier;
547 struct notifier_block vmap_notifier;
548 struct shrinker shrinker;
550 #ifdef CONFIG_MMU_NOTIFIER
552 * notifier_lock for mmu notifiers, memory may not be allocated
553 * while holding this lock.
555 spinlock_t notifier_lock;
558 /* shrinker accounting, also useful for userland debugging */
563 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
565 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
568 static inline unsigned long
569 i915_fence_timeout(const struct drm_i915_private *i915)
571 return i915_fence_context_timeout(i915, U64_MAX);
574 /* Amount of SAGV/QGV points, BSpec precisely defines this */
575 #define I915_NUM_QGV_POINTS 8
577 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
579 struct ddi_vbt_port_info {
580 /* Non-NULL if port present. */
581 struct intel_bios_encoder_data *devdata;
585 /* This is an index in the HDMI/DVI DDI buffer translation table. */
587 u8 hdmi_level_shift_set:1;
589 u8 alternate_aux_channel;
590 u8 alternate_ddc_pin;
592 int dp_max_link_rate; /* 0 for not limited by VBT */
595 enum psr_lines_to_wait {
596 PSR_0_LINES_TO_WAIT = 0,
602 struct intel_vbt_data {
606 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
607 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
610 unsigned int int_tv_support:1;
611 unsigned int lvds_dither:1;
612 unsigned int int_crt_support:1;
613 unsigned int lvds_use_ssc:1;
614 unsigned int int_lvds_support:1;
615 unsigned int display_clock_mode:1;
616 unsigned int fdi_rx_polarity_inverted:1;
617 unsigned int panel_type:4;
619 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
620 enum drm_panel_orientation orientation;
622 enum drrs_support_type drrs_type;
632 struct edp_power_seq pps;
639 bool require_aux_wakeup;
641 enum psr_lines_to_wait lines_to_wait;
642 int tp1_wakeup_time_us;
643 int tp2_tp3_wakeup_time_us;
644 int psr2_tp2_tp3_wakeup_time_us;
651 u8 min_brightness; /* min_brightness/255 of max */
652 u8 controller; /* brightness controller number */
653 enum intel_backlight_type type;
659 struct mipi_config *config;
660 struct mipi_pps_data *pps;
666 const u8 *sequence[MIPI_SEQ_MAX];
667 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
668 enum drm_panel_orientation orientation;
673 struct list_head display_devices;
675 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
676 struct sdvo_device_mapping sdvo_mappings[2];
679 enum intel_ddb_partitioning {
681 INTEL_DDB_PART_5_6, /* IVB+ */
684 struct ilk_wm_values {
689 enum intel_ddb_partitioning partitioning;
693 u16 plane[I915_MAX_PLANES];
703 struct vlv_wm_ddl_values {
704 u8 plane[I915_MAX_PLANES];
707 struct vlv_wm_values {
708 struct g4x_pipe_wm pipe[3];
710 struct vlv_wm_ddl_values ddl[3];
715 struct g4x_wm_values {
716 struct g4x_pipe_wm pipe[2];
718 struct g4x_sr_wm hpll;
724 struct skl_ddb_entry {
725 u16 start, end; /* in number of blocks, 'end' is exclusive */
728 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
730 return entry->end - entry->start;
733 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
734 const struct skl_ddb_entry *e2)
736 if (e1->start == e2->start && e1->end == e2->end)
742 struct i915_frontbuffer_tracking {
746 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
753 struct i915_virtual_gpu {
754 struct mutex lock; /* serialises sending of g2v_notify command pkts */
759 struct intel_cdclk_config {
760 unsigned int cdclk, vco, ref, bypass;
764 struct i915_selftest_stash {
766 struct ida mock_region_instances;
769 struct drm_i915_private {
770 struct drm_device drm;
772 /* FIXME: Device release actions should all be moved to drmm_ */
775 /* i915 device parameters */
776 struct i915_params params;
778 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
779 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
780 struct intel_driver_caps caps;
783 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
784 * end of stolen which we can optionally use to create GEM objects
785 * backed by stolen memory. Note that stolen_usable_size tells us
786 * exactly how much of this we are actually allowed to use, given that
787 * some portion of it is in fact reserved for use by hardware functions.
791 * Reseved portion of Data Stolen Memory
793 struct resource dsm_reserved;
796 * Stolen memory is segmented in hardware with different portions
797 * offlimits to certain functions.
799 * The drm_mm is initialised to the total accessible range, as found
800 * from the PCI config. On Broadwell+, this is further restricted to
801 * avoid the first page! The upper end of stolen memory is reserved for
802 * hardware functions and similarly removed from the accessible range.
804 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
806 struct intel_uncore uncore;
807 struct intel_uncore_mmio_debug mmio_debug;
809 struct i915_virtual_gpu vgpu;
811 struct intel_gvt *gvt;
813 struct intel_wopcm wopcm;
815 struct intel_dmc dmc;
817 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
819 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
820 * controller on different i2c buses. */
821 struct mutex gmbus_mutex;
824 * Base address of where the gmbus and gpio blocks are located (either
825 * on PCH or on SoC for platforms without PCH).
829 u32 hsw_psr_mmio_adjust;
831 /* MMIO base address for MIPI regs */
836 wait_queue_head_t gmbus_wait_queue;
838 struct pci_dev *bridge_dev;
840 struct rb_root uabi_engines;
842 struct resource mch_res;
844 /* protects the irq masks */
847 bool display_irqs_enabled;
849 /* Sideband mailbox protection */
850 struct mutex sb_lock;
851 struct pm_qos_request sb_qos;
853 /** Cached value of IMR to avoid reads in updating the bitfield */
856 u32 de_irq_mask[I915_MAX_PIPES];
858 u32 pipestat_irq_mask[I915_MAX_PIPES];
860 struct i915_hotplug hotplug;
861 struct intel_fbc fbc;
862 struct i915_drrs drrs;
863 struct intel_opregion opregion;
864 struct intel_vbt_data vbt;
866 bool preserve_bios_swizzle;
869 struct intel_overlay *overlay;
871 /* backlight registers and fields in struct intel_panel */
872 struct mutex backlight_lock;
874 /* protects panel power sequencer state */
875 struct mutex pps_mutex;
877 unsigned int fsb_freq, mem_freq, is_ddr3;
878 unsigned int skl_preferred_vco_freq;
879 unsigned int max_cdclk_freq;
881 unsigned int max_dotclk_freq;
882 unsigned int hpll_freq;
883 unsigned int fdi_pll_freq;
884 unsigned int czclk_freq;
887 /* The current hardware cdclk configuration */
888 struct intel_cdclk_config hw;
890 /* cdclk, divider, and ratio table from bspec */
891 const struct intel_cdclk_vals *table;
893 struct intel_global_obj obj;
897 /* The current hardware dbuf configuration */
900 struct intel_global_obj obj;
904 * wq - Driver workqueue for GEM.
906 * NOTE: Work items scheduled here are not allowed to grab any modeset
907 * locks, for otherwise the flushing done in the pageflip code will
908 * result in deadlocks.
910 struct workqueue_struct *wq;
912 /* ordered wq for modesets */
913 struct workqueue_struct *modeset_wq;
914 /* unbound hipri wq for page flips/plane updates */
915 struct workqueue_struct *flip_wq;
917 /* Display functions */
918 struct drm_i915_display_funcs display;
920 /* PCH chipset type */
921 enum intel_pch pch_type;
922 unsigned short pch_id;
924 unsigned long quirks;
926 struct drm_atomic_state *modeset_restore_state;
927 struct drm_modeset_acquire_ctx reset_ctx;
929 struct i915_ggtt ggtt; /* VM representing the global address space */
931 struct i915_gem_mm mm;
933 /* Kernel Modesetting */
935 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
936 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
939 * dpll and cdclk state is protected by connection_mutex
940 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
941 * Must be global rather than per dpll, because on some platforms plls
948 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
949 const struct intel_dpll_mgr *mgr;
957 struct list_head global_obj_list;
960 * For reading active_pipes holding any crtc lock is
961 * sufficient, for writing must hold all of them.
965 struct i915_wa_list gt_wa_list;
967 struct i915_frontbuffer_tracking fb_tracking;
969 struct intel_atomic_helper {
970 struct llist_head free_list;
971 struct work_struct free_work;
974 bool mchbar_need_disable;
976 struct intel_l3_parity l3_parity;
979 * HTI (aka HDPORT) state read during initial hw readout. Most
980 * platforms don't have HTI, so this will just stay 0. Those that do
981 * will use this later to figure out which PLLs and PHYs are unavailable
988 * Cannot be determined by PCIID. You must always read a register.
992 struct i915_power_domains power_domains;
994 struct i915_gpu_error gpu_error;
996 struct drm_i915_gem_object *vlv_pctx;
998 /* list of fbdev register on this device */
999 struct intel_fbdev *fbdev;
1000 struct work_struct fbdev_suspend_work;
1002 struct drm_property *broadcast_rgb_property;
1003 struct drm_property *force_audio_property;
1005 /* hda/i915 audio component */
1006 struct i915_audio_component *audio_component;
1007 bool audio_component_registered;
1009 * av_mutex - mutex for audio/video sync
1012 struct mutex av_mutex;
1013 int audio_power_refcount;
1014 u32 audio_freq_cntrl;
1018 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1019 u32 chv_phy_control;
1021 * Shadows for CHV DPLL_MD regs to keep the state
1022 * checker somewhat working in the presence hardware
1023 * crappiness (can't read out DPLL_MD for pipes B & C).
1025 u32 chv_dpll_md[I915_MAX_PIPES];
1029 bool power_domains_suspended;
1030 struct i915_suspend_saved_registers regfile;
1031 struct vlv_s0ix_state *vlv_s0ix_state;
1034 I915_SAGV_UNKNOWN = 0,
1037 I915_SAGV_NOT_CONTROLLED
1040 u32 sagv_block_time_us;
1044 * Raw watermark latency values:
1045 * in 0.1us units for WM0,
1046 * in 0.5us units for WM1+.
1055 * Raw watermark memory latency values
1056 * for SKL for all 8 levels
1061 /* current hardware state */
1063 struct ilk_wm_values hw;
1064 struct vlv_wm_values vlv;
1065 struct g4x_wm_values g4x;
1071 * Should be held around atomic WM register writing; also
1072 * protects * intel_crtc->wm.active and
1073 * crtc_state->wm.need_postvbl_update.
1075 struct mutex wm_mutex;
1079 bool wm_lv_0_adjust_needed;
1081 bool symmetric_memory;
1082 enum intel_dram_type {
1094 struct intel_bw_info {
1095 /* for each QGV point */
1096 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1101 struct intel_global_obj bw_obj;
1103 struct intel_runtime_pm runtime_pm;
1105 struct i915_perf perf;
1107 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1111 struct i915_gem_contexts {
1112 spinlock_t lock; /* locks list */
1113 struct list_head list;
1117 * We replace the local file with a global mappings as the
1118 * backing storage for the mmap is on the device and not
1119 * on the struct file, and we do not want to prolong the
1120 * lifetime of the local fd. To minimise the number of
1121 * anonymous inodes we create, we use a global singleton to
1122 * share the global mapping.
1124 struct file *mmap_singleton;
1127 u8 framestart_delay;
1129 /* Window2 specifies time required to program DSB (Window2) in number of scan lines */
1134 /* For i915gm/i945gm vblank irq workaround */
1137 /* perform PHY state sanity checks? */
1138 bool chv_phy_assert[2];
1142 /* Used to save the pipe-to-encoder mapping for audio */
1143 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1145 /* necessary resource sharing with HDMI LPE audio driver. */
1147 struct platform_device *platdev;
1151 struct i915_pmu pmu;
1153 struct i915_hdcp_comp_master *hdcp_master;
1154 bool hdcp_comp_added;
1156 /* Mutex to protect the above hdcp component related values. */
1157 struct mutex hdcp_comp_mutex;
1159 /* The TTM device structure. */
1160 struct ttm_device bdev;
1162 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1165 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1166 * will be rejected. Instead look for a better place.
1170 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1172 return container_of(dev, struct drm_i915_private, drm);
1175 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1177 return dev_get_drvdata(kdev);
1180 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1182 return pci_get_drvdata(pdev);
1185 /* Simple iterator over all initialised engines */
1186 #define for_each_engine(engine__, dev_priv__, id__) \
1188 (id__) < I915_NUM_ENGINES; \
1190 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1192 /* Iterator over subset of engines selected by mask */
1193 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1194 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1196 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1199 #define rb_to_uabi_engine(rb) \
1200 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1202 #define for_each_uabi_engine(engine__, i915__) \
1203 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1205 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1207 #define for_each_uabi_class_engine(engine__, class__, i915__) \
1208 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
1209 (engine__) && (engine__)->uabi_class == (class__); \
1210 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1212 #define I915_GTT_OFFSET_NONE ((u32)-1)
1215 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1216 * considered to be the frontbuffer for the given plane interface-wise. This
1217 * doesn't mean that the hw necessarily already scans it out, but that any
1218 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1220 * We have one bit per pipe and per scanout plane type.
1222 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1223 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1224 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1225 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1226 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1228 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1229 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1230 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1231 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1232 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1234 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1235 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1236 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1238 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1241 * Deprecated: this will be replaced by individual IP checks:
1242 * GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER()
1244 #define INTEL_GEN(dev_priv) GRAPHICS_VER(dev_priv)
1246 * Deprecated: use IS_GRAPHICS_VER(), IS_MEDIA_VER() and IS_DISPLAY_VER() as
1249 #define IS_GEN_RANGE(dev_priv, s, e) IS_GRAPHICS_VER(dev_priv, (s), (e))
1251 * Deprecated: use GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER() as appropriate.
1253 #define IS_GEN(dev_priv, n) (GRAPHICS_VER(dev_priv) == (n))
1255 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
1257 #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
1258 #define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics_ver, \
1259 INTEL_INFO(i915)->graphics_rel)
1260 #define IS_GRAPHICS_VER(i915, from, until) \
1261 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
1263 #define MEDIA_VER(i915) (INTEL_INFO(i915)->media_ver)
1264 #define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media_ver, \
1265 INTEL_INFO(i915)->media_rel)
1266 #define IS_MEDIA_VER(i915, from, until) \
1267 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
1269 #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
1270 #define IS_DISPLAY_VER(i915, from, until) \
1271 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
1273 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
1275 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1277 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
1278 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
1280 #define IS_DISPLAY_STEP(__i915, since, until) \
1281 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
1282 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
1284 #define IS_GT_STEP(__i915, since, until) \
1285 (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
1286 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
1288 static __always_inline unsigned int
1289 __platform_mask_index(const struct intel_runtime_info *info,
1290 enum intel_platform p)
1292 const unsigned int pbits =
1293 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1295 /* Expand the platform_mask array if this fails. */
1296 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1297 pbits * ARRAY_SIZE(info->platform_mask));
1302 static __always_inline unsigned int
1303 __platform_mask_bit(const struct intel_runtime_info *info,
1304 enum intel_platform p)
1306 const unsigned int pbits =
1307 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1309 return p % pbits + INTEL_SUBPLATFORM_BITS;
1313 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1315 const unsigned int pi = __platform_mask_index(info, p);
1317 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
1320 static __always_inline bool
1321 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1323 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1324 const unsigned int pi = __platform_mask_index(info, p);
1325 const unsigned int pb = __platform_mask_bit(info, p);
1327 BUILD_BUG_ON(!__builtin_constant_p(p));
1329 return info->platform_mask[pi] & BIT(pb);
1332 static __always_inline bool
1333 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1334 enum intel_platform p, unsigned int s)
1336 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1337 const unsigned int pi = __platform_mask_index(info, p);
1338 const unsigned int pb = __platform_mask_bit(info, p);
1339 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1340 const u32 mask = info->platform_mask[pi];
1342 BUILD_BUG_ON(!__builtin_constant_p(p));
1343 BUILD_BUG_ON(!__builtin_constant_p(s));
1344 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1346 /* Shift and test on the MSB position so sign flag can be used. */
1347 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1350 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1351 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1353 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1354 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1355 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1356 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1357 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1358 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1359 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1360 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1361 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1362 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1363 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1364 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1365 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1366 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1367 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1368 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1369 #define IS_IRONLAKE_M(dev_priv) \
1370 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1371 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
1372 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1373 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1374 INTEL_INFO(dev_priv)->gt == 1)
1375 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1376 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1377 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1378 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1379 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1380 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1381 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1382 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1383 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1384 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
1385 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1386 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1387 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
1388 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1389 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1390 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1391 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
1392 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
1393 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
1394 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
1395 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1396 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1397 #define IS_BDW_ULT(dev_priv) \
1398 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1399 #define IS_BDW_ULX(dev_priv) \
1400 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1401 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1402 INTEL_INFO(dev_priv)->gt == 3)
1403 #define IS_HSW_ULT(dev_priv) \
1404 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1405 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1406 INTEL_INFO(dev_priv)->gt == 3)
1407 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1408 INTEL_INFO(dev_priv)->gt == 1)
1409 /* ULX machines are also considered ULT. */
1410 #define IS_HSW_ULX(dev_priv) \
1411 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1412 #define IS_SKL_ULT(dev_priv) \
1413 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1414 #define IS_SKL_ULX(dev_priv) \
1415 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1416 #define IS_KBL_ULT(dev_priv) \
1417 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1418 #define IS_KBL_ULX(dev_priv) \
1419 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1420 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1421 INTEL_INFO(dev_priv)->gt == 2)
1422 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1423 INTEL_INFO(dev_priv)->gt == 3)
1424 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1425 INTEL_INFO(dev_priv)->gt == 4)
1426 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1427 INTEL_INFO(dev_priv)->gt == 2)
1428 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1429 INTEL_INFO(dev_priv)->gt == 3)
1430 #define IS_CFL_ULT(dev_priv) \
1431 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1432 #define IS_CFL_ULX(dev_priv) \
1433 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1434 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1435 INTEL_INFO(dev_priv)->gt == 2)
1436 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1437 INTEL_INFO(dev_priv)->gt == 3)
1439 #define IS_CML_ULT(dev_priv) \
1440 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1441 #define IS_CML_ULX(dev_priv) \
1442 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1443 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
1444 INTEL_INFO(dev_priv)->gt == 2)
1446 #define IS_CNL_WITH_PORT_F(dev_priv) \
1447 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1448 #define IS_ICL_WITH_PORT_F(dev_priv) \
1449 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1451 #define IS_TGL_U(dev_priv) \
1452 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1454 #define IS_TGL_Y(dev_priv) \
1455 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1457 #define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since, until))
1459 #define IS_KBL_GT_STEP(dev_priv, since, until) \
1460 (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
1461 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
1462 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
1464 #define IS_JSL_EHL_GT_STEP(p, since, until) \
1465 (IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))
1466 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
1467 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
1469 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
1470 (IS_TIGERLAKE(__i915) && \
1471 IS_DISPLAY_STEP(__i915, since, until))
1473 #define IS_TGL_UY_GT_STEP(__i915, since, until) \
1474 ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1475 IS_GT_STEP(__i915, since, until))
1477 #define IS_TGL_GT_STEP(__i915, since, until) \
1478 (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
1479 IS_GT_STEP(__i915, since, until))
1481 #define IS_RKL_DISPLAY_STEP(p, since, until) \
1482 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
1484 #define IS_DG1_GT_STEP(p, since, until) \
1485 (IS_DG1(p) && IS_GT_STEP(p, since, until))
1486 #define IS_DG1_DISPLAY_STEP(p, since, until) \
1487 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
1489 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
1490 (IS_ALDERLAKE_S(__i915) && \
1491 IS_DISPLAY_STEP(__i915, since, until))
1493 #define IS_ADLS_GT_STEP(__i915, since, until) \
1494 (IS_ALDERLAKE_S(__i915) && \
1495 IS_GT_STEP(__i915, since, until))
1497 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
1498 (IS_ALDERLAKE_P(__i915) && \
1499 IS_DISPLAY_STEP(__i915, since, until))
1501 #define IS_ADLP_GT_STEP(__i915, since, until) \
1502 (IS_ALDERLAKE_P(__i915) && \
1503 IS_GT_STEP(__i915, since, until))
1505 #define IS_XEHPSDV_GT_STEP(p, since, until) \
1506 (IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
1508 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1509 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
1510 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
1512 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1513 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1515 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
1516 unsigned int first__ = (first); \
1517 unsigned int count__ = (count); \
1518 ((gt)->info.engine_mask & \
1519 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1521 #define VDBOX_MASK(gt) \
1522 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
1523 #define VEBOX_MASK(gt) \
1524 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1527 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1528 * All later gens can run the final buffer from the ppgtt
1530 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
1532 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1533 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1534 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1535 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
1536 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
1538 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1540 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1541 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1542 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1543 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1545 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
1547 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1549 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1550 #define HAS_PPGTT(dev_priv) \
1551 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1552 #define HAS_FULL_PPGTT(dev_priv) \
1553 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1555 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1556 GEM_BUG_ON((sizes) == 0); \
1557 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1560 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1561 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1562 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1564 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1565 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1567 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1568 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
1570 /* WaRsDisableCoarsePowerGating:skl,cnl */
1571 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1572 (IS_CANNONLAKE(dev_priv) || \
1573 IS_SKL_GT3(dev_priv) || \
1574 IS_SKL_GT4(dev_priv))
1576 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
1577 #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
1578 IS_GEMINILAKE(dev_priv) || \
1579 IS_KABYLAKE(dev_priv))
1581 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1582 * rows, which changed the alignment requirements and fence programming.
1584 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
1585 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
1586 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1587 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1589 #define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
1590 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1591 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
1593 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1595 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1597 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1598 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
1599 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1600 #define HAS_PSR_HW_TRACKING(dev_priv) \
1601 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1602 #define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
1603 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1605 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1606 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1607 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1609 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1611 #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
1613 #define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12)
1615 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1616 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1618 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1620 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1621 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1623 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1625 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1627 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1630 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1632 #define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
1634 /* DPF == dynamic parity feature */
1635 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1636 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1637 2 : HAS_L3_DPF(dev_priv))
1639 #define GT_FREQUENCY_MULTIPLIER 50
1640 #define GEN9_FREQ_SCALER 3
1642 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1644 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1646 #define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 12)
1648 /* Only valid when HAS_DISPLAY() is true */
1649 #define INTEL_DISPLAY_ENABLED(dev_priv) \
1650 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1652 static inline bool run_as_guest(void)
1654 return !hypervisor_is_type(X86_HYPER_NATIVE);
1657 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
1658 IS_ALDERLAKE_S(dev_priv))
1660 static inline bool intel_vtd_active(void)
1662 #ifdef CONFIG_INTEL_IOMMU
1663 if (intel_iommu_gfx_mapped)
1667 /* Running as a guest, we assume the host is enforcing VT'd */
1668 return run_as_guest();
1671 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1673 return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active();
1677 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
1679 return IS_BROXTON(i915) && intel_vtd_active();
1683 intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915)
1685 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915);
1689 extern const struct dev_pm_ops i915_pm_ops;
1691 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1692 void i915_driver_remove(struct drm_i915_private *i915);
1693 void i915_driver_shutdown(struct drm_i915_private *i915);
1695 int i915_resume_switcheroo(struct drm_i915_private *i915);
1696 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1698 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1699 struct drm_file *file_priv);
1702 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1703 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1704 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1705 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1707 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915,
1708 u16 type, u16 instance);
1710 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1713 * A single pass should suffice to release all the freed objects (along
1714 * most call paths) , but be a little more paranoid in that freeing
1715 * the objects does take a little amount of time, during which the rcu
1716 * callbacks could have added new objects into the freed list, and
1717 * armed the work again.
1719 while (atomic_read(&i915->mm.free_count)) {
1720 flush_work(&i915->mm.free_work);
1725 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1728 * Similar to objects above (see i915_gem_drain_freed-objects), in
1729 * general we have workers that are armed by RCU and then rearm
1730 * themselves in their callbacks. To be paranoid, we need to
1731 * drain the workqueue a second time after waiting for the RCU
1732 * grace period so that we catch work queued via RCU from the first
1733 * pass. As neither drain_workqueue() nor flush_workqueue() report
1734 * a result, we make an assumption that we only don't require more
1735 * than 3 passes to catch all _recursive_ RCU delayed work.
1740 flush_workqueue(i915->wq);
1742 i915_gem_drain_freed_objects(i915);
1744 drain_workqueue(i915->wq);
1747 struct i915_vma * __must_check
1748 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
1749 struct i915_gem_ww_ctx *ww,
1750 const struct i915_ggtt_view *view,
1751 u64 size, u64 alignment, u64 flags);
1753 static inline struct i915_vma * __must_check
1754 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1755 const struct i915_ggtt_view *view,
1756 u64 size, u64 alignment, u64 flags)
1758 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
1761 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1762 unsigned long flags);
1763 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1764 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1765 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1766 #define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3)
1768 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1770 int i915_gem_dumb_create(struct drm_file *file_priv,
1771 struct drm_device *dev,
1772 struct drm_mode_create_dumb *args);
1774 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1776 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1778 return atomic_read(&error->reset_count);
1781 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1782 const struct intel_engine_cs *engine)
1784 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1787 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1788 void i915_gem_driver_register(struct drm_i915_private *i915);
1789 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1790 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1791 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1792 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1793 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1794 void i915_gem_resume(struct drm_i915_private *dev_priv);
1796 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1798 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1799 enum i915_cache_level cache_level);
1801 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1802 struct dma_buf *dma_buf);
1804 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1806 static inline struct i915_gem_context *
1807 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1809 return xa_load(&file_priv->context_xa, id);
1812 static inline struct i915_gem_context *
1813 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1815 struct i915_gem_context *ctx;
1818 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1819 if (ctx && !kref_get_unless_zero(&ctx->ref))
1826 /* i915_gem_evict.c */
1827 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1828 u64 min_size, u64 alignment,
1829 unsigned long color,
1832 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1833 struct drm_mm_node *node,
1834 unsigned int flags);
1835 int i915_gem_evict_vm(struct i915_address_space *vm);
1837 /* i915_gem_internal.c */
1838 struct drm_i915_gem_object *
1839 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1842 /* i915_gem_tiling.c */
1843 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1845 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1847 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1848 i915_gem_object_is_tiled(obj);
1851 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1852 unsigned int tiling, unsigned int stride);
1853 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1854 unsigned int tiling, unsigned int stride);
1856 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1858 /* i915_cmd_parser.c */
1859 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1860 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1861 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1862 unsigned long *intel_engine_cmd_parser_alloc_jump_whitelist(u32 batch_length,
1865 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1866 struct i915_vma *batch,
1867 unsigned long batch_offset,
1868 unsigned long batch_length,
1869 struct i915_vma *shadow,
1870 unsigned long *jump_whitelist,
1872 const void *batch_map);
1873 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1875 /* intel_device_info.c */
1876 static inline struct intel_device_info *
1877 mkwrite_device_info(struct drm_i915_private *dev_priv)
1879 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1882 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1883 struct drm_file *file);
1886 int remap_io_mapping(struct vm_area_struct *vma,
1887 unsigned long addr, unsigned long pfn, unsigned long size,
1888 struct io_mapping *iomap);
1889 int remap_io_sg(struct vm_area_struct *vma,
1890 unsigned long addr, unsigned long size,
1891 struct scatterlist *sgl, resource_size_t iobase);
1893 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1895 if (GRAPHICS_VER(i915) >= 10)
1896 return CNL_HWS_CSB_WRITE_INDEX;
1898 return I915_HWS_CSB_WRITE_INDEX;
1901 static inline enum i915_map_type
1902 i915_coherent_map_type(struct drm_i915_private *i915,
1903 struct drm_i915_gem_object *obj, bool always_coherent)
1905 if (i915_gem_object_is_lmem(obj))
1907 if (HAS_LLC(i915) || always_coherent)