1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/dma-resv.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
49 #include <linux/xarray.h>
51 #include <drm/intel-gtt.h>
52 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
53 #include <drm/drm_gem.h>
54 #include <drm/drm_auth.h>
55 #include <drm/drm_cache.h>
56 #include <drm/drm_util.h>
57 #include <drm/drm_dsc.h>
58 #include <drm/drm_atomic.h>
59 #include <drm/drm_connector.h>
60 #include <drm/i915_mei_hdcp_interface.h>
62 #include "i915_fixed.h"
63 #include "i915_params.h"
65 #include "i915_utils.h"
67 #include "display/intel_bios.h"
68 #include "display/intel_display.h"
69 #include "display/intel_display_power.h"
70 #include "display/intel_dpll_mgr.h"
71 #include "display/intel_dsb.h"
72 #include "display/intel_frontbuffer.h"
73 #include "display/intel_global_state.h"
74 #include "display/intel_gmbus.h"
75 #include "display/intel_opregion.h"
77 #include "gem/i915_gem_context_types.h"
78 #include "gem/i915_gem_shrinker.h"
79 #include "gem/i915_gem_stolen.h"
81 #include "gt/intel_lrc.h"
82 #include "gt/intel_engine.h"
83 #include "gt/intel_gt_types.h"
84 #include "gt/intel_workarounds.h"
85 #include "gt/uc/intel_uc.h"
87 #include "intel_device_info.h"
88 #include "intel_pch.h"
89 #include "intel_runtime_pm.h"
90 #include "intel_memory_region.h"
91 #include "intel_uncore.h"
92 #include "intel_wakeref.h"
93 #include "intel_wopcm.h"
96 #include "i915_gem_fence_reg.h"
97 #include "i915_gem_gtt.h"
98 #include "i915_gpu_error.h"
99 #include "i915_perf_types.h"
100 #include "i915_request.h"
101 #include "i915_scheduler.h"
102 #include "gt/intel_timeline.h"
103 #include "i915_vma.h"
104 #include "i915_irq.h"
106 #include "intel_region_lmem.h"
108 #include "intel_gvt.h"
110 /* General customization:
113 #define DRIVER_NAME "i915"
114 #define DRIVER_DESC "Intel Graphics"
115 #define DRIVER_DATE "20200225"
116 #define DRIVER_TIMESTAMP 1582656081
118 struct drm_i915_gem_object;
122 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
139 #define for_each_hpd_pin(__pin) \
140 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
142 /* Threshold == 5 for long IRQs, 50 for short */
143 #define HPD_STORM_DEFAULT_THRESHOLD 50
145 struct i915_hotplug {
146 struct delayed_work hotplug_work;
149 unsigned long last_jiffies;
154 HPD_MARK_DISABLED = 2
156 } stats[HPD_NUM_PINS];
159 struct delayed_work reenable_work;
163 struct work_struct dig_port_work;
165 struct work_struct poll_init_work;
168 unsigned int hpd_storm_threshold;
169 /* Whether or not to count short HPD IRQs in HPD storms */
170 u8 hpd_short_storm_enabled;
173 * if we get a HPD irq from DP and a HPD irq from non-DP
174 * the non-DP HPD could block the workqueue on a mode config
175 * mutex getting, that userspace may have taken. However
176 * userspace is waiting on the DP workqueue to run which is
177 * blocked behind the non-DP one.
179 struct workqueue_struct *dp_wq;
182 #define I915_GEM_GPU_DOMAINS \
183 (I915_GEM_DOMAIN_RENDER | \
184 I915_GEM_DOMAIN_SAMPLER | \
185 I915_GEM_DOMAIN_COMMAND | \
186 I915_GEM_DOMAIN_INSTRUCTION | \
187 I915_GEM_DOMAIN_VERTEX)
189 struct drm_i915_private;
190 struct i915_mm_struct;
191 struct i915_mmu_object;
193 struct drm_i915_file_private {
194 struct drm_i915_private *dev_priv;
197 struct drm_file *file;
203 struct list_head request_list;
206 struct xarray context_xa;
209 unsigned int bsd_engine;
212 * Every context ban increments per client ban score. Also
213 * hangs in short succession increments ban score. If ban threshold
214 * is reached, client is considered banned and submitting more work
215 * will fail. This is a stop gap measure to limit the badly behaving
216 * clients access to gpu. Note that unbannable contexts never increment
217 * the client ban score.
219 #define I915_CLIENT_SCORE_HANG_FAST 1
220 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
221 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
222 #define I915_CLIENT_SCORE_BANNED 9
223 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
225 unsigned long hang_timestamp;
228 /* Interface history:
231 * 1.2: Add Power Management
232 * 1.3: Add vblank support
233 * 1.4: Fix cmdbuffer path, add heap destroy
234 * 1.5: Add vblank pipe configuration
235 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
236 * - Support vertical blank on secondary display pipe
238 #define DRIVER_MAJOR 1
239 #define DRIVER_MINOR 6
240 #define DRIVER_PATCHLEVEL 0
242 struct intel_overlay;
243 struct intel_overlay_error_state;
245 struct sdvo_device_mapping {
254 struct intel_connector;
255 struct intel_encoder;
256 struct intel_atomic_state;
257 struct intel_cdclk_config;
258 struct intel_cdclk_state;
259 struct intel_cdclk_vals;
260 struct intel_initial_plane_config;
265 struct drm_i915_display_funcs {
266 void (*get_cdclk)(struct drm_i915_private *dev_priv,
267 struct intel_cdclk_config *cdclk_config);
268 void (*set_cdclk)(struct drm_i915_private *dev_priv,
269 const struct intel_cdclk_config *cdclk_config,
271 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
272 enum i9xx_plane_id i9xx_plane);
273 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
274 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
275 void (*initial_watermarks)(struct intel_atomic_state *state,
276 struct intel_crtc *crtc);
277 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
278 struct intel_crtc *crtc);
279 void (*optimize_watermarks)(struct intel_atomic_state *state,
280 struct intel_crtc *crtc);
281 int (*compute_global_watermarks)(struct intel_atomic_state *state);
282 void (*update_wm)(struct intel_crtc *crtc);
283 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
284 u8 (*calc_voltage_level)(int cdclk);
285 /* Returns the active state of the crtc, and if the crtc is active,
286 * fills out the pipe-config with the hw state. */
287 bool (*get_pipe_config)(struct intel_crtc *,
288 struct intel_crtc_state *);
289 void (*get_initial_plane_config)(struct intel_crtc *,
290 struct intel_initial_plane_config *);
291 int (*crtc_compute_clock)(struct intel_crtc *crtc,
292 struct intel_crtc_state *crtc_state);
293 void (*crtc_enable)(struct intel_atomic_state *state,
294 struct intel_crtc *crtc);
295 void (*crtc_disable)(struct intel_atomic_state *state,
296 struct intel_crtc *crtc);
297 void (*commit_modeset_enables)(struct intel_atomic_state *state);
298 void (*commit_modeset_disables)(struct intel_atomic_state *state);
299 void (*audio_codec_enable)(struct intel_encoder *encoder,
300 const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state);
302 void (*audio_codec_disable)(struct intel_encoder *encoder,
303 const struct intel_crtc_state *old_crtc_state,
304 const struct drm_connector_state *old_conn_state);
305 void (*fdi_link_train)(struct intel_crtc *crtc,
306 const struct intel_crtc_state *crtc_state);
307 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
308 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
309 /* clock updates for mode set */
311 /* render clock increase/decrease */
312 /* display clock increase/decrease */
313 /* pll clock increase/decrease */
315 int (*color_check)(struct intel_crtc_state *crtc_state);
317 * Program double buffered color management registers during
318 * vblank evasion. The registers should then latch during the
319 * next vblank start, alongside any other double buffered registers
320 * involved with the same commit.
322 void (*color_commit)(const struct intel_crtc_state *crtc_state);
324 * Load LUTs (and other single buffered color management
325 * registers). Will (hopefully) be called during the vblank
326 * following the latching of any double buffered registers
327 * involved with the same commit.
329 void (*load_luts)(const struct intel_crtc_state *crtc_state);
330 void (*read_luts)(struct intel_crtc_state *crtc_state);
334 struct work_struct work;
336 u32 required_version;
337 u32 max_fw_size; /* bytes */
339 u32 dmc_fw_size; /* dwords */
342 i915_reg_t mmioaddr[20];
347 intel_wakeref_t wakeref;
350 enum i915_cache_level {
352 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
353 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
354 caches, eg sampler/render caches, and the
355 large Last-Level-Cache. LLC is coherent with
356 the CPU, but L3 is only visible to the GPU. */
357 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
360 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
363 /* This is always the inner lock when overlapping with struct_mutex and
364 * it's the outer lock when overlapping with stolen_lock. */
367 unsigned int possible_framebuffer_bits;
368 unsigned int busy_bits;
369 struct intel_crtc *crtc;
371 struct drm_mm_node compressed_fb;
372 struct drm_mm_node *compressed_llb;
380 bool underrun_detected;
381 struct work_struct underrun_work;
384 * Due to the atomic rules we can't access some structures without the
385 * appropriate locking, so we cache information here in order to avoid
388 struct intel_fbc_state_cache {
390 unsigned int mode_flags;
391 u32 hsw_bdw_pixel_rate;
395 unsigned int rotation;
400 * Display surface base address adjustement for
401 * pageflips. Note that on gen4+ this only adjusts up
402 * to a tile, offsets within a tile are handled in
403 * the hw itself (with the TILEOFF register).
410 u16 pixel_blend_mode;
414 const struct drm_format_info *format;
417 u16 gen9_wa_cfb_stride;
422 * This structure contains everything that's relevant to program the
423 * hardware registers. When we want to figure out if we need to disable
424 * and re-enable FBC for a new configuration we just check if there's
425 * something different in the struct. The genx_fbc_activate functions
426 * are supposed to read from it in order to program the registers.
428 struct intel_fbc_reg_params {
431 enum i9xx_plane_id i9xx_plane;
432 unsigned int fence_y_offset;
436 const struct drm_format_info *format;
441 u16 gen9_wa_cfb_stride;
446 const char *no_fbc_reason;
450 * HIGH_RR is the highest eDP panel refresh rate read from EDID
451 * LOW_RR is the lowest eDP panel refresh rate found from EDID
452 * parsing for same resolution.
454 enum drrs_refresh_rate_type {
457 DRRS_MAX_RR, /* RR count */
460 enum drrs_support_type {
461 DRRS_NOT_SUPPORTED = 0,
462 STATIC_DRRS_SUPPORT = 1,
463 SEAMLESS_DRRS_SUPPORT = 2
469 struct delayed_work work;
471 unsigned busy_frontbuffer_bits;
472 enum drrs_refresh_rate_type refresh_rate_type;
473 enum drrs_support_type type;
479 #define I915_PSR_DEBUG_MODE_MASK 0x0f
480 #define I915_PSR_DEBUG_DEFAULT 0x00
481 #define I915_PSR_DEBUG_DISABLE 0x01
482 #define I915_PSR_DEBUG_ENABLE 0x02
483 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
484 #define I915_PSR_DEBUG_IRQ 0x10
491 enum transcoder transcoder;
493 struct work_struct work;
494 unsigned busy_frontbuffer_bits;
495 bool sink_psr2_support;
497 bool colorimetry_support;
499 u8 sink_sync_latency;
500 ktime_t last_entry_attempt;
502 bool sink_not_reliable;
504 u16 su_x_granularity;
506 u32 dc3co_exit_delay;
507 struct delayed_work dc3co_work;
508 bool force_mode_changed;
511 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
512 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
513 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
514 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
515 #define QUIRK_INCREASE_T12_DELAY (1<<6)
516 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
519 struct intel_fbc_work;
522 struct i2c_adapter adapter;
523 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
527 struct i2c_algo_bit_data bit_algo;
528 struct drm_i915_private *dev_priv;
531 struct i915_suspend_saved_registers {
534 u32 saveCACHE_MODE_0;
535 u32 saveMI_ARB_STATE;
539 u64 saveFENCE[I915_MAX_NUM_FENCES];
540 u32 savePCH_PORT_HOTPLUG;
544 struct vlv_s0ix_state;
546 #define MAX_L3_SLICES 2
547 struct intel_l3_parity {
548 u32 *remap_info[MAX_L3_SLICES];
549 struct work_struct error_work;
554 /** Memory allocator for GTT stolen memory */
555 struct drm_mm stolen;
556 /** Protects the usage of the GTT stolen memory allocator. This is
557 * always the inner lock when overlapping with struct_mutex. */
558 struct mutex stolen_lock;
560 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
564 * List of objects which are purgeable.
566 struct list_head purge_list;
569 * List of objects which have allocated pages and are shrinkable.
571 struct list_head shrink_list;
574 * List of objects which are pending destruction.
576 struct llist_head free_list;
577 struct work_struct free_work;
579 * Count of objects pending destructions. Used to skip needlessly
580 * waiting on an RCU barrier if no objects are waiting to be freed.
585 * Small stash of WC pages
587 struct pagestash wc_stash;
590 * tmpfs instance used for shmem backed objects
592 struct vfsmount *gemfs;
594 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
596 struct notifier_block oom_notifier;
597 struct notifier_block vmap_notifier;
598 struct shrinker shrinker;
601 * Workqueue to fault in userptr pages, flushed by the execbuf
602 * when required but otherwise left to userspace to try again
605 struct workqueue_struct *userptr_wq;
607 /* shrinker accounting, also useful for userland debugging */
612 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
614 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
615 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
617 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
618 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
620 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
622 /* Amount of SAGV/QGV points, BSpec precisely defines this */
623 #define I915_NUM_QGV_POINTS 8
625 struct ddi_vbt_port_info {
626 /* Non-NULL if port present. */
627 const struct child_device_config *child;
631 /* This is an index in the HDMI/DVI DDI buffer translation table. */
633 u8 hdmi_level_shift_set:1;
639 u8 supports_typec_usb:1;
642 u8 alternate_aux_channel;
643 u8 alternate_ddc_pin;
647 int dp_max_link_rate; /* 0 for not limited by VBT */
650 enum psr_lines_to_wait {
651 PSR_0_LINES_TO_WAIT = 0,
657 struct intel_vbt_data {
658 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
659 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
662 unsigned int int_tv_support:1;
663 unsigned int lvds_dither:1;
664 unsigned int int_crt_support:1;
665 unsigned int lvds_use_ssc:1;
666 unsigned int int_lvds_support:1;
667 unsigned int display_clock_mode:1;
668 unsigned int fdi_rx_polarity_inverted:1;
669 unsigned int panel_type:4;
671 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
672 enum drm_panel_orientation orientation;
674 enum drrs_support_type drrs_type;
684 struct edp_power_seq pps;
690 bool require_aux_wakeup;
692 enum psr_lines_to_wait lines_to_wait;
693 int tp1_wakeup_time_us;
694 int tp2_tp3_wakeup_time_us;
695 int psr2_tp2_tp3_wakeup_time_us;
702 u8 min_brightness; /* min_brightness/255 of max */
703 u8 controller; /* brightness controller number */
704 enum intel_backlight_type type;
710 struct mipi_config *config;
711 struct mipi_pps_data *pps;
717 const u8 *sequence[MIPI_SEQ_MAX];
718 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
719 enum drm_panel_orientation orientation;
724 struct list_head display_devices;
726 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
727 struct sdvo_device_mapping sdvo_mappings[2];
730 enum intel_ddb_partitioning {
732 INTEL_DDB_PART_5_6, /* IVB+ */
735 struct intel_wm_level {
743 struct ilk_wm_values {
748 enum intel_ddb_partitioning partitioning;
752 u16 plane[I915_MAX_PLANES];
762 struct vlv_wm_ddl_values {
763 u8 plane[I915_MAX_PLANES];
766 struct vlv_wm_values {
767 struct g4x_pipe_wm pipe[3];
769 struct vlv_wm_ddl_values ddl[3];
774 struct g4x_wm_values {
775 struct g4x_pipe_wm pipe[2];
777 struct g4x_sr_wm hpll;
783 struct skl_ddb_entry {
784 u16 start, end; /* in number of blocks, 'end' is exclusive */
787 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
789 return entry->end - entry->start;
792 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
793 const struct skl_ddb_entry *e2)
795 if (e1->start == e2->start && e1->end == e2->end)
801 struct skl_wm_level {
809 /* Stores plane specific WM parameters */
810 struct skl_wm_params {
811 bool x_tiled, y_tiled;
816 u32 plane_pixel_rate;
818 u32 plane_bytes_per_line;
819 uint_fixed_16_16_t plane_blocks_per_line;
820 uint_fixed_16_16_t y_tile_minimum;
825 struct i915_frontbuffer_tracking {
829 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
836 struct i915_virtual_gpu {
837 struct mutex lock; /* serialises sending of g2v_notify command pkts */
842 /* used in computing the new watermarks state */
843 struct intel_wm_config {
844 unsigned int num_pipes_active;
845 bool sprites_enabled;
849 struct intel_cdclk_config {
850 unsigned int cdclk, vco, ref, bypass;
854 struct i915_selftest_stash {
858 struct drm_i915_private {
859 struct drm_device drm;
861 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
862 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
863 struct intel_driver_caps caps;
866 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
867 * end of stolen which we can optionally use to create GEM objects
868 * backed by stolen memory. Note that stolen_usable_size tells us
869 * exactly how much of this we are actually allowed to use, given that
870 * some portion of it is in fact reserved for use by hardware functions.
874 * Reseved portion of Data Stolen Memory
876 struct resource dsm_reserved;
879 * Stolen memory is segmented in hardware with different portions
880 * offlimits to certain functions.
882 * The drm_mm is initialised to the total accessible range, as found
883 * from the PCI config. On Broadwell+, this is further restricted to
884 * avoid the first page! The upper end of stolen memory is reserved for
885 * hardware functions and similarly removed from the accessible range.
887 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
889 struct intel_uncore uncore;
890 struct intel_uncore_mmio_debug mmio_debug;
892 struct i915_virtual_gpu vgpu;
894 struct intel_gvt *gvt;
896 struct intel_wopcm wopcm;
898 struct intel_csr csr;
900 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
902 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
903 * controller on different i2c buses. */
904 struct mutex gmbus_mutex;
907 * Base address of where the gmbus and gpio blocks are located (either
908 * on PCH or on SoC for platforms without PCH).
912 u32 hsw_psr_mmio_adjust;
914 /* MMIO base address for MIPI regs */
919 wait_queue_head_t gmbus_wait_queue;
921 struct pci_dev *bridge_dev;
923 struct intel_engine_cs *engine[I915_NUM_ENGINES];
924 struct rb_root uabi_engines;
926 struct resource mch_res;
928 /* protects the irq masks */
931 bool display_irqs_enabled;
933 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
934 struct pm_qos_request pm_qos;
936 /* Sideband mailbox protection */
937 struct mutex sb_lock;
938 struct pm_qos_request sb_qos;
940 /** Cached value of IMR to avoid reads in updating the bitfield */
943 u32 de_irq_mask[I915_MAX_PIPES];
945 u32 pipestat_irq_mask[I915_MAX_PIPES];
947 struct i915_hotplug hotplug;
948 struct intel_fbc fbc;
949 struct i915_drrs drrs;
950 struct intel_opregion opregion;
951 struct intel_vbt_data vbt;
953 bool preserve_bios_swizzle;
956 struct intel_overlay *overlay;
958 /* backlight registers and fields in struct intel_panel */
959 struct mutex backlight_lock;
961 /* protects panel power sequencer state */
962 struct mutex pps_mutex;
964 unsigned int fsb_freq, mem_freq, is_ddr3;
965 unsigned int skl_preferred_vco_freq;
966 unsigned int max_cdclk_freq;
968 unsigned int max_dotclk_freq;
969 unsigned int hpll_freq;
970 unsigned int fdi_pll_freq;
971 unsigned int czclk_freq;
974 /* The current hardware cdclk configuration */
975 struct intel_cdclk_config hw;
977 /* cdclk, divider, and ratio table from bspec */
978 const struct intel_cdclk_vals *table;
980 struct intel_global_obj obj;
984 * wq - Driver workqueue for GEM.
986 * NOTE: Work items scheduled here are not allowed to grab any modeset
987 * locks, for otherwise the flushing done in the pageflip code will
988 * result in deadlocks.
990 struct workqueue_struct *wq;
992 /* ordered wq for modesets */
993 struct workqueue_struct *modeset_wq;
994 /* unbound hipri wq for page flips/plane updates */
995 struct workqueue_struct *flip_wq;
997 /* Display functions */
998 struct drm_i915_display_funcs display;
1000 /* PCH chipset type */
1001 enum intel_pch pch_type;
1002 unsigned short pch_id;
1004 unsigned long quirks;
1006 struct drm_atomic_state *modeset_restore_state;
1007 struct drm_modeset_acquire_ctx reset_ctx;
1009 struct i915_ggtt ggtt; /* VM representing the global address space */
1011 struct i915_gem_mm mm;
1012 DECLARE_HASHTABLE(mm_structs, 7);
1013 struct mutex mm_lock;
1015 /* Kernel Modesetting */
1017 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1018 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1021 * dpll and cdclk state is protected by connection_mutex
1022 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
1023 * Must be global rather than per dpll, because on some platforms plls
1029 int num_shared_dpll;
1030 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1031 const struct intel_dpll_mgr *mgr;
1034 struct list_head global_obj_list;
1037 * For reading active_pipes holding any crtc lock is
1038 * sufficient, for writing must hold all of them.
1042 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1044 struct i915_wa_list gt_wa_list;
1046 struct i915_frontbuffer_tracking fb_tracking;
1048 struct intel_atomic_helper {
1049 struct llist_head free_list;
1050 struct work_struct free_work;
1053 bool mchbar_need_disable;
1055 struct intel_l3_parity l3_parity;
1059 * Cannot be determined by PCIID. You must always read a register.
1063 struct i915_power_domains power_domains;
1065 struct i915_psr psr;
1067 struct i915_gpu_error gpu_error;
1069 struct drm_i915_gem_object *vlv_pctx;
1071 /* list of fbdev register on this device */
1072 struct intel_fbdev *fbdev;
1073 struct work_struct fbdev_suspend_work;
1075 struct drm_property *broadcast_rgb_property;
1076 struct drm_property *force_audio_property;
1078 /* hda/i915 audio component */
1079 struct i915_audio_component *audio_component;
1080 bool audio_component_registered;
1082 * av_mutex - mutex for audio/video sync
1085 struct mutex av_mutex;
1086 int audio_power_refcount;
1087 u32 audio_freq_cntrl;
1091 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1092 u32 chv_phy_control;
1094 * Shadows for CHV DPLL_MD regs to keep the state
1095 * checker somewhat working in the presence hardware
1096 * crappiness (can't read out DPLL_MD for pipes B & C).
1098 u32 chv_dpll_md[I915_MAX_PIPES];
1102 bool power_domains_suspended;
1103 struct i915_suspend_saved_registers regfile;
1104 struct vlv_s0ix_state *vlv_s0ix_state;
1107 I915_SAGV_UNKNOWN = 0,
1110 I915_SAGV_NOT_CONTROLLED
1113 u32 sagv_block_time_us;
1117 * Raw watermark latency values:
1118 * in 0.1us units for WM0,
1119 * in 0.5us units for WM1+.
1128 * Raw watermark memory latency values
1129 * for SKL for all 8 levels
1134 /* current hardware state */
1136 struct ilk_wm_values hw;
1137 struct vlv_wm_values vlv;
1138 struct g4x_wm_values g4x;
1144 * Should be held around atomic WM register writing; also
1145 * protects * intel_crtc->wm.active and
1146 * crtc_state->wm.need_postvbl_update.
1148 struct mutex wm_mutex;
1151 * Set during HW readout of watermarks/DDB. Some platforms
1152 * need to know when we're still using BIOS-provided values
1153 * (which we don't fully trust).
1155 bool distrust_bios_wm;
1158 u8 enabled_dbuf_slices_mask; /* GEN11 has configurable 2 slices */
1166 bool symmetric_memory;
1167 enum intel_dram_type {
1176 struct intel_bw_info {
1177 /* for each QGV point */
1178 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1183 struct intel_global_obj bw_obj;
1185 struct intel_runtime_pm runtime_pm;
1187 struct i915_perf perf;
1189 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1193 struct i915_gem_contexts {
1194 spinlock_t lock; /* locks list */
1195 struct list_head list;
1197 struct llist_head free_list;
1198 struct work_struct free_work;
1202 * We replace the local file with a global mappings as the
1203 * backing storage for the mmap is on the device and not
1204 * on the struct file, and we do not want to prolong the
1205 * lifetime of the local fd. To minimise the number of
1206 * anonymous inodes we create, we use a global singleton to
1207 * share the global mapping.
1209 struct file *mmap_singleton;
1214 /* For i915gm/i945gm vblank irq workaround */
1217 /* perform PHY state sanity checks? */
1218 bool chv_phy_assert[2];
1222 /* Used to save the pipe-to-encoder mapping for audio */
1223 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1225 /* necessary resource sharing with HDMI LPE audio driver. */
1227 struct platform_device *platdev;
1231 struct i915_pmu pmu;
1233 struct i915_hdcp_comp_master *hdcp_master;
1234 bool hdcp_comp_added;
1236 /* Mutex to protect the above hdcp component related values. */
1237 struct mutex hdcp_comp_mutex;
1239 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1242 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1243 * will be rejected. Instead look for a better place.
1247 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1249 return container_of(dev, struct drm_i915_private, drm);
1252 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1254 return dev_get_drvdata(kdev);
1257 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1259 return pci_get_drvdata(pdev);
1262 /* Simple iterator over all initialised engines */
1263 #define for_each_engine(engine__, dev_priv__, id__) \
1265 (id__) < I915_NUM_ENGINES; \
1267 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1269 /* Iterator over subset of engines selected by mask */
1270 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1271 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1273 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1276 #define rb_to_uabi_engine(rb) \
1277 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1279 #define for_each_uabi_engine(engine__, i915__) \
1280 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1282 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1284 #define I915_GTT_OFFSET_NONE ((u32)-1)
1287 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1288 * considered to be the frontbuffer for the given plane interface-wise. This
1289 * doesn't mean that the hw necessarily already scans it out, but that any
1290 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1292 * We have one bit per pipe and per scanout plane type.
1294 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1295 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1296 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1297 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1298 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1300 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1301 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1302 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1303 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1304 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1306 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1307 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1308 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1310 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
1311 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1313 #define REVID_FOREVER 0xff
1314 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
1316 #define INTEL_GEN_MASK(s, e) ( \
1317 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1318 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1319 GENMASK((e) - 1, (s) - 1))
1321 /* Returns true if Gen is in inclusive range [Start, End] */
1322 #define IS_GEN_RANGE(dev_priv, s, e) \
1323 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1325 #define IS_GEN(dev_priv, n) \
1326 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1327 INTEL_INFO(dev_priv)->gen == (n))
1329 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
1332 * Return true if revision is in range [since,until] inclusive.
1334 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1336 #define IS_REVID(p, since, until) \
1337 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1339 static __always_inline unsigned int
1340 __platform_mask_index(const struct intel_runtime_info *info,
1341 enum intel_platform p)
1343 const unsigned int pbits =
1344 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1346 /* Expand the platform_mask array if this fails. */
1347 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1348 pbits * ARRAY_SIZE(info->platform_mask));
1353 static __always_inline unsigned int
1354 __platform_mask_bit(const struct intel_runtime_info *info,
1355 enum intel_platform p)
1357 const unsigned int pbits =
1358 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1360 return p % pbits + INTEL_SUBPLATFORM_BITS;
1364 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1366 const unsigned int pi = __platform_mask_index(info, p);
1368 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1371 static __always_inline bool
1372 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1374 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1375 const unsigned int pi = __platform_mask_index(info, p);
1376 const unsigned int pb = __platform_mask_bit(info, p);
1378 BUILD_BUG_ON(!__builtin_constant_p(p));
1380 return info->platform_mask[pi] & BIT(pb);
1383 static __always_inline bool
1384 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1385 enum intel_platform p, unsigned int s)
1387 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1388 const unsigned int pi = __platform_mask_index(info, p);
1389 const unsigned int pb = __platform_mask_bit(info, p);
1390 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1391 const u32 mask = info->platform_mask[pi];
1393 BUILD_BUG_ON(!__builtin_constant_p(p));
1394 BUILD_BUG_ON(!__builtin_constant_p(s));
1395 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1397 /* Shift and test on the MSB position so sign flag can be used. */
1398 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1401 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1402 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
1404 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1405 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1406 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1407 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1408 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1409 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1410 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1411 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1412 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1413 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1414 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1415 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1416 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1417 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1418 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1419 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1420 #define IS_IRONLAKE_M(dev_priv) \
1421 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1422 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1423 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1424 INTEL_INFO(dev_priv)->gt == 1)
1425 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1426 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1427 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1428 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1429 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1430 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1431 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1432 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1433 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1434 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1435 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1436 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1437 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1438 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1439 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1440 #define IS_BDW_ULT(dev_priv) \
1441 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1442 #define IS_BDW_ULX(dev_priv) \
1443 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1444 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1445 INTEL_INFO(dev_priv)->gt == 3)
1446 #define IS_HSW_ULT(dev_priv) \
1447 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1448 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1449 INTEL_INFO(dev_priv)->gt == 3)
1450 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1451 INTEL_INFO(dev_priv)->gt == 1)
1452 /* ULX machines are also considered ULT. */
1453 #define IS_HSW_ULX(dev_priv) \
1454 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1455 #define IS_SKL_ULT(dev_priv) \
1456 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1457 #define IS_SKL_ULX(dev_priv) \
1458 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1459 #define IS_KBL_ULT(dev_priv) \
1460 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1461 #define IS_KBL_ULX(dev_priv) \
1462 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1463 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1464 INTEL_INFO(dev_priv)->gt == 2)
1465 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1466 INTEL_INFO(dev_priv)->gt == 3)
1467 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1468 INTEL_INFO(dev_priv)->gt == 4)
1469 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1470 INTEL_INFO(dev_priv)->gt == 2)
1471 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1472 INTEL_INFO(dev_priv)->gt == 3)
1473 #define IS_CFL_ULT(dev_priv) \
1474 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1475 #define IS_CFL_ULX(dev_priv) \
1476 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1477 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1478 INTEL_INFO(dev_priv)->gt == 2)
1479 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
1480 INTEL_INFO(dev_priv)->gt == 3)
1481 #define IS_CNL_WITH_PORT_F(dev_priv) \
1482 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1483 #define IS_ICL_WITH_PORT_F(dev_priv) \
1484 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1486 #define SKL_REVID_A0 0x0
1487 #define SKL_REVID_B0 0x1
1488 #define SKL_REVID_C0 0x2
1489 #define SKL_REVID_D0 0x3
1490 #define SKL_REVID_E0 0x4
1491 #define SKL_REVID_F0 0x5
1492 #define SKL_REVID_G0 0x6
1493 #define SKL_REVID_H0 0x7
1495 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1497 #define BXT_REVID_A0 0x0
1498 #define BXT_REVID_A1 0x1
1499 #define BXT_REVID_B0 0x3
1500 #define BXT_REVID_B_LAST 0x8
1501 #define BXT_REVID_C0 0x9
1503 #define IS_BXT_REVID(dev_priv, since, until) \
1504 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1506 #define KBL_REVID_A0 0x0
1507 #define KBL_REVID_B0 0x1
1508 #define KBL_REVID_C0 0x2
1509 #define KBL_REVID_D0 0x3
1510 #define KBL_REVID_E0 0x4
1512 #define IS_KBL_REVID(dev_priv, since, until) \
1513 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1515 #define GLK_REVID_A0 0x0
1516 #define GLK_REVID_A1 0x1
1517 #define GLK_REVID_A2 0x2
1518 #define GLK_REVID_B0 0x3
1520 #define IS_GLK_REVID(dev_priv, since, until) \
1521 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1523 #define CNL_REVID_A0 0x0
1524 #define CNL_REVID_B0 0x1
1525 #define CNL_REVID_C0 0x2
1527 #define IS_CNL_REVID(p, since, until) \
1528 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1530 #define ICL_REVID_A0 0x0
1531 #define ICL_REVID_A2 0x1
1532 #define ICL_REVID_B0 0x3
1533 #define ICL_REVID_B2 0x4
1534 #define ICL_REVID_C0 0x5
1536 #define IS_ICL_REVID(p, since, until) \
1537 (IS_ICELAKE(p) && IS_REVID(p, since, until))
1539 #define TGL_REVID_A0 0x0
1541 #define IS_TGL_REVID(p, since, until) \
1542 (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1544 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1545 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1546 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1548 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1550 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
1551 unsigned int first__ = (first); \
1552 unsigned int count__ = (count); \
1553 (INTEL_INFO(dev_priv)->engine_mask & \
1554 GENMASK(first__ + count__ - 1, first__)) >> first__; \
1556 #define VDBOX_MASK(dev_priv) \
1557 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
1558 #define VEBOX_MASK(dev_priv) \
1559 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
1562 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1563 * All later gens can run the final buffer from the ppgtt
1565 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1567 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
1568 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
1569 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1570 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1571 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
1572 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1574 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
1576 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1577 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1578 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1579 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1580 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1581 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1583 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1585 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1586 #define HAS_PPGTT(dev_priv) \
1587 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1588 #define HAS_FULL_PPGTT(dev_priv) \
1589 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1591 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1592 GEM_BUG_ON((sizes) == 0); \
1593 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1596 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
1597 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1598 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1600 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1601 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
1603 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1604 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1606 /* WaRsDisableCoarsePowerGating:skl,cnl */
1607 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
1608 (IS_CANNONLAKE(dev_priv) || \
1609 IS_SKL_GT3(dev_priv) || \
1610 IS_SKL_GT4(dev_priv))
1612 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1613 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1614 IS_GEMINILAKE(dev_priv) || \
1615 IS_KABYLAKE(dev_priv))
1617 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1618 * rows, which changed the alignment requirements and fence programming.
1620 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1621 !(IS_I915G(dev_priv) || \
1622 IS_I915GM(dev_priv)))
1623 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
1624 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
1626 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
1627 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1628 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1630 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1632 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
1634 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
1635 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1636 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
1637 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
1639 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
1640 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
1641 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
1643 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
1645 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
1647 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1648 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1650 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
1652 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1653 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1655 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
1657 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1659 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
1662 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1664 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1666 /* DPF == dynamic parity feature */
1667 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1668 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1669 2 : HAS_L3_DPF(dev_priv))
1671 #define GT_FREQUENCY_MULTIPLIER 50
1672 #define GEN9_FREQ_SCALER 3
1674 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1676 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1678 /* Only valid when HAS_DISPLAY() is true */
1679 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
1681 static inline bool intel_vtd_active(void)
1683 #ifdef CONFIG_INTEL_IOMMU
1684 if (intel_iommu_gfx_mapped)
1690 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1692 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1696 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1698 return IS_BROXTON(dev_priv) && intel_vtd_active();
1702 extern const struct dev_pm_ops i915_pm_ops;
1704 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1705 void i915_driver_remove(struct drm_i915_private *i915);
1707 int i915_resume_switcheroo(struct drm_i915_private *i915);
1708 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1710 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
1712 return dev_priv->gvt;
1715 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
1717 return dev_priv->vgpu.active;
1720 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1721 struct drm_file *file_priv);
1724 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1725 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1726 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1727 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1728 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1729 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1731 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1733 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1736 * A single pass should suffice to release all the freed objects (along
1737 * most call paths) , but be a little more paranoid in that freeing
1738 * the objects does take a little amount of time, during which the rcu
1739 * callbacks could have added new objects into the freed list, and
1740 * armed the work again.
1742 while (atomic_read(&i915->mm.free_count)) {
1743 flush_work(&i915->mm.free_work);
1748 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1751 * Similar to objects above (see i915_gem_drain_freed-objects), in
1752 * general we have workers that are armed by RCU and then rearm
1753 * themselves in their callbacks. To be paranoid, we need to
1754 * drain the workqueue a second time after waiting for the RCU
1755 * grace period so that we catch work queued via RCU from the first
1756 * pass. As neither drain_workqueue() nor flush_workqueue() report
1757 * a result, we make an assumption that we only don't require more
1758 * than 3 passes to catch all _recursive_ RCU delayed work.
1763 flush_workqueue(i915->wq);
1765 i915_gem_drain_freed_objects(i915);
1767 drain_workqueue(i915->wq);
1770 struct i915_vma * __must_check
1771 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1772 const struct i915_ggtt_view *view,
1777 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1778 unsigned long flags);
1779 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1780 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1782 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1784 static inline int __must_check
1785 i915_mutex_lock_interruptible(struct drm_device *dev)
1787 return mutex_lock_interruptible(&dev->struct_mutex);
1790 int i915_gem_dumb_create(struct drm_file *file_priv,
1791 struct drm_device *dev,
1792 struct drm_mode_create_dumb *args);
1794 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1796 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1798 return atomic_read(&error->reset_count);
1801 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1802 const struct intel_engine_cs *engine)
1804 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1807 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1808 void i915_gem_driver_register(struct drm_i915_private *i915);
1809 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1810 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1811 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1812 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1813 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1814 void i915_gem_resume(struct drm_i915_private *dev_priv);
1816 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1817 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1819 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1820 enum i915_cache_level cache_level);
1822 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1823 struct dma_buf *dma_buf);
1825 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1827 static inline struct i915_gem_context *
1828 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1830 return xa_load(&file_priv->context_xa, id);
1833 static inline struct i915_gem_context *
1834 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1836 struct i915_gem_context *ctx;
1839 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1840 if (ctx && !kref_get_unless_zero(&ctx->ref))
1847 /* i915_gem_evict.c */
1848 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1849 u64 min_size, u64 alignment,
1850 unsigned long color,
1853 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1854 struct drm_mm_node *node,
1855 unsigned int flags);
1856 int i915_gem_evict_vm(struct i915_address_space *vm);
1858 /* i915_gem_internal.c */
1859 struct drm_i915_gem_object *
1860 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1863 /* i915_gem_tiling.c */
1864 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1866 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1868 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1869 i915_gem_object_is_tiled(obj);
1872 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1873 unsigned int tiling, unsigned int stride);
1874 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1875 unsigned int tiling, unsigned int stride);
1877 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1879 /* i915_cmd_parser.c */
1880 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1881 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1882 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1883 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1884 struct i915_vma *batch,
1887 struct i915_vma *shadow,
1889 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1891 /* intel_device_info.c */
1892 static inline struct intel_device_info *
1893 mkwrite_device_info(struct drm_i915_private *dev_priv)
1895 return (struct intel_device_info *)INTEL_INFO(dev_priv);
1898 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1899 struct drm_file *file);
1901 #define __I915_REG_OP(op__, dev_priv__, ...) \
1902 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
1904 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
1905 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
1907 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
1909 /* These are untraced mmio-accessors that are only valid to be used inside
1910 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
1913 * Think twice, and think again, before using these.
1915 * As an example, these accessors can possibly be used between:
1917 * spin_lock_irq(&dev_priv->uncore.lock);
1918 * intel_uncore_forcewake_get__locked();
1922 * intel_uncore_forcewake_put__locked();
1923 * spin_unlock_irq(&dev_priv->uncore.lock);
1926 * Note: some registers may not need forcewake held, so
1927 * intel_uncore_forcewake_{get,put} can be omitted, see
1928 * intel_uncore_forcewake_for_reg().
1930 * Certain architectures will die if the same cacheline is concurrently accessed
1931 * by different clients (e.g. on Ivybridge). Access to registers should
1932 * therefore generally be serialised, by either the dev_priv->uncore.lock or
1933 * a more localised lock guarding all access to that bank of registers.
1935 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
1936 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
1939 int remap_io_mapping(struct vm_area_struct *vma,
1940 unsigned long addr, unsigned long pfn, unsigned long size,
1941 struct io_mapping *iomap);
1942 int remap_io_sg(struct vm_area_struct *vma,
1943 unsigned long addr, unsigned long size,
1944 struct scatterlist *sgl, resource_size_t iobase);
1946 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
1948 if (INTEL_GEN(i915) >= 10)
1949 return CNL_HWS_CSB_WRITE_INDEX;
1951 return I915_HWS_CSB_WRITE_INDEX;
1954 static inline enum i915_map_type
1955 i915_coherent_map_type(struct drm_i915_private *i915)
1957 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;