drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include <linux/pm_qos.h>
  36
  37 #include <drm/ttm/ttm_device.h>
  38
  39 #include "display/intel_display.h"
  40 #include "display/intel_display_core.h"
  41
  42 #include "gem/i915_gem_context_types.h"
  43 #include "gem/i915_gem_shrinker.h"
  44 #include "gem/i915_gem_stolen.h"
  45
  46 #include "gt/intel_engine.h"
  47 #include "gt/intel_gt_types.h"
  48 #include "gt/intel_region_lmem.h"
  49 #include "gt/intel_workarounds.h"
  50 #include "gt/uc/intel_uc.h"
  51
  52 #include "i915_drm_client.h"
  53 #include "i915_gem.h"
  54 #include "i915_gpu_error.h"
  55 #include "i915_params.h"
  56 #include "i915_perf_types.h"
  57 #include "i915_scheduler.h"
  58 #include "i915_utils.h"
  59 #include "intel_device_info.h"
  60 #include "intel_memory_region.h"
  61 #include "intel_pch.h"
  62 #include "intel_runtime_pm.h"
  63 #include "intel_step.h"
  64 #include "intel_uncore.h"
  65 #include "intel_wopcm.h"
  66
  67 struct drm_i915_clock_gating_funcs;
  68 struct drm_i915_gem_object;
  69 struct drm_i915_private;
  70 struct intel_connector;
  71 struct intel_dp;
  72 struct intel_encoder;
  73 struct intel_limit;
  74 struct intel_overlay_error_state;
  75 struct vlv_s0ix_state;
  76
  77 #define I915_GEM_GPU_DOMAINS \
  78         (I915_GEM_DOMAIN_RENDER | \
  79          I915_GEM_DOMAIN_SAMPLER | \
  80          I915_GEM_DOMAIN_COMMAND | \
  81          I915_GEM_DOMAIN_INSTRUCTION | \
  82          I915_GEM_DOMAIN_VERTEX)
  83
  84 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
  85
  86 #define GEM_QUIRK_PIN_SWIZZLED_PAGES    BIT(0)
  87
  88 struct i915_suspend_saved_registers {
  89         u32 saveDSPARB;
  90         u32 saveSWF0[16];
  91         u32 saveSWF1[16];
  92         u32 saveSWF3[3];
  93         u16 saveGCDGMBUS;
  94 };
  95
  96 #define MAX_L3_SLICES 2
  97 struct intel_l3_parity {
  98         u32 *remap_info[MAX_L3_SLICES];
  99         struct work_struct error_work;
 100         int which_slice;
 101 };
 102
 103 struct i915_gem_mm {
 104         /*
 105          * Shortcut for the stolen region. This points to either
 106          * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
 107          * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
 108          * support stolen.
 109          */
 110         struct intel_memory_region *stolen_region;
 111         /** Memory allocator for GTT stolen memory */
 112         struct drm_mm stolen;
 113         /** Protects the usage of the GTT stolen memory allocator. This is
 114          * always the inner lock when overlapping with struct_mutex. */
 115         struct mutex stolen_lock;
 116
 117         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 118         spinlock_t obj_lock;
 119
 120         /**
 121          * List of objects which are purgeable.
 122          */
 123         struct list_head purge_list;
 124
 125         /**
 126          * List of objects which have allocated pages and are shrinkable.
 127          */
 128         struct list_head shrink_list;
 129
 130         /**
 131          * List of objects which are pending destruction.
 132          */
 133         struct llist_head free_list;
 134         struct work_struct free_work;
 135         /**
 136          * Count of objects pending destructions. Used to skip needlessly
 137          * waiting on an RCU barrier if no objects are waiting to be freed.
 138          */
 139         atomic_t free_count;
 140
 141         /**
 142          * tmpfs instance used for shmem backed objects
 143          */
 144         struct vfsmount *gemfs;
 145
 146         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 147
 148         struct notifier_block oom_notifier;
 149         struct notifier_block vmap_notifier;
 150         struct shrinker shrinker;
 151
 152 #ifdef CONFIG_MMU_NOTIFIER
 153         /**
 154          * notifier_lock for mmu notifiers, memory may not be allocated
 155          * while holding this lock.
 156          */
 157         rwlock_t notifier_lock;
 158 #endif
 159
 160         /* shrinker accounting, also useful for userland debugging */
 161         u64 shrink_memory;
 162         u32 shrink_count;
 163 };
 164
 165 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 166
 167 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 168                                          u64 context);
 169
 170 static inline unsigned long
 171 i915_fence_timeout(const struct drm_i915_private *i915)
 172 {
 173         return i915_fence_context_timeout(i915, U64_MAX);
 174 }
 175
 176 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 177
 178 struct i915_virtual_gpu {
 179         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 180         bool active;
 181         u32 caps;
 182         u32 *initial_mmio;
 183         u8 *initial_cfg_space;
 184         struct list_head entry;
 185 };
 186
 187 struct i915_selftest_stash {
 188         atomic_t counter;
 189         struct ida mock_region_instances;
 190 };
 191
 192 struct drm_i915_private {
 193         struct drm_device drm;
 194
 195         struct intel_display display;
 196
 197         /* FIXME: Device release actions should all be moved to drmm_ */
 198         bool do_release;
 199
 200         /* i915 device parameters */
 201         struct i915_params params;
 202
 203         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 204         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 205         struct intel_driver_caps caps;
 206
 207         /**
 208          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 209          * end of stolen which we can optionally use to create GEM objects
 210          * backed by stolen memory. Note that stolen_usable_size tells us
 211          * exactly how much of this we are actually allowed to use, given that
 212          * some portion of it is in fact reserved for use by hardware functions.
 213          */
 214         struct resource dsm;
 215         /**
 216          * Reseved portion of Data Stolen Memory
 217          */
 218         struct resource dsm_reserved;
 219
 220         /*
 221          * Stolen memory is segmented in hardware with different portions
 222          * offlimits to certain functions.
 223          *
 224          * The drm_mm is initialised to the total accessible range, as found
 225          * from the PCI config. On Broadwell+, this is further restricted to
 226          * avoid the first page! The upper end of stolen memory is reserved for
 227          * hardware functions and similarly removed from the accessible range.
 228          */
 229         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 230
 231         struct intel_uncore uncore;
 232         struct intel_uncore_mmio_debug mmio_debug;
 233
 234         struct i915_virtual_gpu vgpu;
 235
 236         struct intel_gvt *gvt;
 237
 238         struct intel_wopcm wopcm;
 239
 240         struct pci_dev *bridge_dev;
 241
 242         struct rb_root uabi_engines;
 243         unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
 244
 245         struct resource mch_res;
 246
 247         /* protects the irq masks */
 248         spinlock_t irq_lock;
 249
 250         bool display_irqs_enabled;
 251
 252         /* Sideband mailbox protection */
 253         struct mutex sb_lock;
 254         struct pm_qos_request sb_qos;
 255
 256         /** Cached value of IMR to avoid reads in updating the bitfield */
 257         union {
 258                 u32 irq_mask;
 259                 u32 de_irq_mask[I915_MAX_PIPES];
 260         };
 261         u32 pipestat_irq_mask[I915_MAX_PIPES];
 262
 263         bool preserve_bios_swizzle;
 264
 265         unsigned int fsb_freq, mem_freq, is_ddr3;
 266         unsigned int skl_preferred_vco_freq;
 267
 268         unsigned int max_dotclk_freq;
 269         unsigned int hpll_freq;
 270         unsigned int czclk_freq;
 271
 272         /**
 273          * wq - Driver workqueue for GEM.
 274          *
 275          * NOTE: Work items scheduled here are not allowed to grab any modeset
 276          * locks, for otherwise the flushing done in the pageflip code will
 277          * result in deadlocks.
 278          */
 279         struct workqueue_struct *wq;
 280
 281         /* pm private clock gating functions */
 282         const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
 283
 284         /* PCH chipset type */
 285         enum intel_pch pch_type;
 286         unsigned short pch_id;
 287
 288         unsigned long gem_quirks;
 289
 290         struct drm_atomic_state *modeset_restore_state;
 291         struct drm_modeset_acquire_ctx reset_ctx;
 292
 293         struct i915_gem_mm mm;
 294
 295         /* Kernel Modesetting */
 296
 297         struct list_head global_obj_list;
 298
 299         bool mchbar_need_disable;
 300
 301         struct intel_l3_parity l3_parity;
 302
 303         /*
 304          * HTI (aka HDPORT) state read during initial hw readout.  Most
 305          * platforms don't have HTI, so this will just stay 0.  Those that do
 306          * will use this later to figure out which PLLs and PHYs are unavailable
 307          * for driver usage.
 308          */
 309         u32 hti_state;
 310
 311         /*
 312          * edram size in MB.
 313          * Cannot be determined by PCIID. You must always read a register.
 314          */
 315         u32 edram_size_mb;
 316
 317         struct i915_gpu_error gpu_error;
 318
 319         /*
 320          * Shadows for CHV DPLL_MD regs to keep the state
 321          * checker somewhat working in the presence hardware
 322          * crappiness (can't read out DPLL_MD for pipes B & C).
 323          */
 324         u32 chv_dpll_md[I915_MAX_PIPES];
 325         u32 bxt_phy_grc;
 326
 327         u32 suspend_count;
 328         struct i915_suspend_saved_registers regfile;
 329         struct vlv_s0ix_state *vlv_s0ix_state;
 330
 331         struct dram_info {
 332                 bool wm_lv_0_adjust_needed;
 333                 u8 num_channels;
 334                 bool symmetric_memory;
 335                 enum intel_dram_type {
 336                         INTEL_DRAM_UNKNOWN,
 337                         INTEL_DRAM_DDR3,
 338                         INTEL_DRAM_DDR4,
 339                         INTEL_DRAM_LPDDR3,
 340                         INTEL_DRAM_LPDDR4,
 341                         INTEL_DRAM_DDR5,
 342                         INTEL_DRAM_LPDDR5,
 343                 } type;
 344                 u8 num_qgv_points;
 345                 u8 num_psf_gv_points;
 346         } dram_info;
 347
 348         struct intel_runtime_pm runtime_pm;
 349
 350         struct i915_perf perf;
 351
 352         struct i915_hwmon *hwmon;
 353
 354         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
 355         struct intel_gt gt0;
 356
 357         /*
 358          * i915->gt[0] == &i915->gt0
 359          */
 360 #define I915_MAX_GT 4
 361         struct intel_gt *gt[I915_MAX_GT];
 362
 363         struct kobject *sysfs_gt;
 364
 365         /* Quick lookup of media GT (current platforms only have one) */
 366         struct intel_gt *media_gt;
 367
 368         struct {
 369                 struct i915_gem_contexts {
 370                         spinlock_t lock; /* locks list */
 371                         struct list_head list;
 372                 } contexts;
 373
 374                 /*
 375                  * We replace the local file with a global mappings as the
 376                  * backing storage for the mmap is on the device and not
 377                  * on the struct file, and we do not want to prolong the
 378                  * lifetime of the local fd. To minimise the number of
 379                  * anonymous inodes we create, we use a global singleton to
 380                  * share the global mapping.
 381                  */
 382                 struct file *mmap_singleton;
 383         } gem;
 384
 385         u8 pch_ssc_use;
 386
 387         /* For i915gm/i945gm vblank irq workaround */
 388         u8 vblank_enabled;
 389
 390         bool irq_enabled;
 391
 392         /*
 393          * DG2: Mask of PHYs that were not calibrated by the firmware
 394          * and should not be used.
 395          */
 396         u8 snps_phy_failed_calibration;
 397
 398         struct i915_pmu pmu;
 399
 400         struct i915_drm_clients clients;
 401
 402         /* The TTM device structure. */
 403         struct ttm_device bdev;
 404
 405         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
 406
 407         /*
 408          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 409          * will be rejected. Instead look for a better place.
 410          */
 411 };
 412
 413 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
 414 {
 415         return container_of(dev, struct drm_i915_private, drm);
 416 }
 417
 418 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 419 {
 420         return dev_get_drvdata(kdev);
 421 }
 422
 423 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 424 {
 425         return pci_get_drvdata(pdev);
 426 }
 427
 428 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 429 {
 430         return &i915->gt0;
 431 }
 432
 433 /* Simple iterator over all initialised engines */
 434 #define for_each_engine(engine__, dev_priv__, id__) \
 435         for ((id__) = 0; \
 436              (id__) < I915_NUM_ENGINES; \
 437              (id__)++) \
 438                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
 439
 440 /* Iterator over subset of engines selected by mask */
 441 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
 442         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
 443              (tmp__) ? \
 444              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
 445              0;)
 446
 447 #define rb_to_uabi_engine(rb) \
 448         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
 449
 450 #define for_each_uabi_engine(engine__, i915__) \
 451         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
 452              (engine__); \
 453              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 454
 455 #define for_each_uabi_class_engine(engine__, class__, i915__) \
 456         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
 457              (engine__) && (engine__)->uabi_class == (class__); \
 458              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 459
 460 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
 461 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
 462 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
 463
 464 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
 465
 466 #define IP_VER(ver, rel)                ((ver) << 8 | (rel))
 467
 468 #define GRAPHICS_VER(i915)              (RUNTIME_INFO(i915)->graphics.ip.ver)
 469 #define GRAPHICS_VER_FULL(i915)         IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
 470                                                RUNTIME_INFO(i915)->graphics.ip.rel)
 471 #define IS_GRAPHICS_VER(i915, from, until) \
 472         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
 473
 474 #define MEDIA_VER(i915)                 (RUNTIME_INFO(i915)->media.ip.ver)
 475 #define MEDIA_VER_FULL(i915)            IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
 476                                                RUNTIME_INFO(i915)->media.ip.rel)
 477 #define IS_MEDIA_VER(i915, from, until) \
 478         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 479
 480 #define DISPLAY_VER(i915)       (RUNTIME_INFO(i915)->display.ip.ver)
 481 #define IS_DISPLAY_VER(i915, from, until) \
 482         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 483
 484 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
 485
 486 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
 487
 488 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 489 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
 490 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
 491 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
 492
 493 #define IS_DISPLAY_STEP(__i915, since, until) \
 494         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
 495          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
 496
 497 #define IS_GRAPHICS_STEP(__i915, since, until) \
 498         (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
 499          INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
 500
 501 #define IS_MEDIA_STEP(__i915, since, until) \
 502         (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
 503          INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
 504
 505 #define IS_BASEDIE_STEP(__i915, since, until) \
 506         (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
 507          INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
 508
 509 static __always_inline unsigned int
 510 __platform_mask_index(const struct intel_runtime_info *info,
 511                       enum intel_platform p)
 512 {
 513         const unsigned int pbits =
 514                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 515
 516         /* Expand the platform_mask array if this fails. */
 517         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 518                      pbits * ARRAY_SIZE(info->platform_mask));
 519
 520         return p / pbits;
 521 }
 522
 523 static __always_inline unsigned int
 524 __platform_mask_bit(const struct intel_runtime_info *info,
 525                     enum intel_platform p)
 526 {
 527         const unsigned int pbits =
 528                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 529
 530         return p % pbits + INTEL_SUBPLATFORM_BITS;
 531 }
 532
 533 static inline u32
 534 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
 535 {
 536         const unsigned int pi = __platform_mask_index(info, p);
 537
 538         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
 539 }
 540
 541 static __always_inline bool
 542 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
 543 {
 544         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 545         const unsigned int pi = __platform_mask_index(info, p);
 546         const unsigned int pb = __platform_mask_bit(info, p);
 547
 548         BUILD_BUG_ON(!__builtin_constant_p(p));
 549
 550         return info->platform_mask[pi] & BIT(pb);
 551 }
 552
 553 static __always_inline bool
 554 IS_SUBPLATFORM(const struct drm_i915_private *i915,
 555                enum intel_platform p, unsigned int s)
 556 {
 557         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 558         const unsigned int pi = __platform_mask_index(info, p);
 559         const unsigned int pb = __platform_mask_bit(info, p);
 560         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
 561         const u32 mask = info->platform_mask[pi];
 562
 563         BUILD_BUG_ON(!__builtin_constant_p(p));
 564         BUILD_BUG_ON(!__builtin_constant_p(s));
 565         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
 566
 567         /* Shift and test on the MSB position so sign flag can be used. */
 568         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
 569 }
 570
 571 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
 572 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
 573
 574 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
 575 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
 576 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
 577 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
 578 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
 579 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
 580 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
 581 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
 582 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
 583 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
 584 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
 585 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
 586 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
 587 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
 588 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
 589 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
 590 #define IS_IRONLAKE_M(dev_priv) \
 591         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
 592 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
 593 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 594 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
 595                                  INTEL_INFO(dev_priv)->gt == 1)
 596 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
 597 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 598 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
 599 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
 600 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
 601 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
 602 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
 603 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 604 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 605 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 606 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 607 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
 608                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
 609 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 610 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 611 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
 612 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 613 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
 614 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
 615 #define IS_DG2(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG2)
 616 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 617 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
 618
 619 #define IS_METEORLAKE_M(dev_priv) \
 620         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
 621 #define IS_METEORLAKE_P(dev_priv) \
 622         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
 623 #define IS_DG2_G10(dev_priv) \
 624         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 625 #define IS_DG2_G11(dev_priv) \
 626         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 627 #define IS_DG2_G12(dev_priv) \
 628         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 629 #define IS_ADLS_RPLS(dev_priv) \
 630         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 631 #define IS_ADLP_N(dev_priv) \
 632         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 633 #define IS_ADLP_RPLP(dev_priv) \
 634         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 635 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 636                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 637 #define IS_BDW_ULT(dev_priv) \
 638         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
 639 #define IS_BDW_ULX(dev_priv) \
 640         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
 641 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
 642                                  INTEL_INFO(dev_priv)->gt == 3)
 643 #define IS_HSW_ULT(dev_priv) \
 644         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
 645 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
 646                                  INTEL_INFO(dev_priv)->gt == 3)
 647 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
 648                                  INTEL_INFO(dev_priv)->gt == 1)
 649 /* ULX machines are also considered ULT. */
 650 #define IS_HSW_ULX(dev_priv) \
 651         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
 652 #define IS_SKL_ULT(dev_priv) \
 653         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 654 #define IS_SKL_ULX(dev_priv) \
 655         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 656 #define IS_KBL_ULT(dev_priv) \
 657         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 658 #define IS_KBL_ULX(dev_priv) \
 659         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 660 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 661                                  INTEL_INFO(dev_priv)->gt == 2)
 662 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 663                                  INTEL_INFO(dev_priv)->gt == 3)
 664 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 665                                  INTEL_INFO(dev_priv)->gt == 4)
 666 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 667                                  INTEL_INFO(dev_priv)->gt == 2)
 668 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 669                                  INTEL_INFO(dev_priv)->gt == 3)
 670 #define IS_CFL_ULT(dev_priv) \
 671         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
 672 #define IS_CFL_ULX(dev_priv) \
 673         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
 674 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 675                                  INTEL_INFO(dev_priv)->gt == 2)
 676 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 677                                  INTEL_INFO(dev_priv)->gt == 3)
 678
 679 #define IS_CML_ULT(dev_priv) \
 680         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
 681 #define IS_CML_ULX(dev_priv) \
 682         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
 683 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
 684                                  INTEL_INFO(dev_priv)->gt == 2)
 685
 686 #define IS_ICL_WITH_PORT_F(dev_priv) \
 687         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 688
 689 #define IS_TGL_UY(dev_priv) \
 690         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 691
 692 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 693
 694 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
 695         (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
 696 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
 697         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 698
 699 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
 700         (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
 701 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
 702         (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 703
 704 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 705         (IS_TIGERLAKE(__i915) && \
 706          IS_DISPLAY_STEP(__i915, since, until))
 707
 708 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
 709         (IS_TGL_UY(__i915) && \
 710          IS_GRAPHICS_STEP(__i915, since, until))
 711
 712 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
 713         (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
 714          IS_GRAPHICS_STEP(__i915, since, until))
 715
 716 #define IS_RKL_DISPLAY_STEP(p, since, until) \
 717         (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 718
 719 #define IS_DG1_GRAPHICS_STEP(p, since, until) \
 720         (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
 721 #define IS_DG1_DISPLAY_STEP(p, since, until) \
 722         (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
 723
 724 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
 725         (IS_ALDERLAKE_S(__i915) && \
 726          IS_DISPLAY_STEP(__i915, since, until))
 727
 728 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
 729         (IS_ALDERLAKE_S(__i915) && \
 730          IS_GRAPHICS_STEP(__i915, since, until))
 731
 732 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
 733         (IS_ALDERLAKE_P(__i915) && \
 734          IS_DISPLAY_STEP(__i915, since, until))
 735
 736 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
 737         (IS_ALDERLAKE_P(__i915) && \
 738          IS_GRAPHICS_STEP(__i915, since, until))
 739
 740 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 741         (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 742
 743 /*
 744  * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
 745  * create three variants (G10, G11, and G12) which each have distinct
 746  * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
 747  * stepping back to "A0" for their first iterations, even though they're more
 748  * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
 749  * functionality and workarounds.  However the display stepping does not reset
 750  * in the same manner --- a specific stepping like "B0" has a consistent
 751  * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
 752  *
 753  * TLDR:  All GT workarounds and stepping-specific logic must be applied in
 754  * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
 755  * and stepping-specific logic will be applied with a general DG2-wide stepping
 756  * number.
 757  */
 758 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
 759         (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
 760          IS_GRAPHICS_STEP(__i915, since, until))
 761
 762 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
 763         (IS_DG2(__i915) && \
 764          IS_DISPLAY_STEP(__i915, since, until))
 765
 766 #define IS_PVC_BD_STEP(__i915, since, until) \
 767         (IS_PONTEVECCHIO(__i915) && \
 768          IS_BASEDIE_STEP(__i915, since, until))
 769
 770 #define IS_PVC_CT_STEP(__i915, since, until) \
 771         (IS_PONTEVECCHIO(__i915) && \
 772          IS_GRAPHICS_STEP(__i915, since, until))
 773
 774 #define IS_LP(dev_priv)         (INTEL_INFO(dev_priv)->is_lp)
 775 #define IS_GEN9_LP(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
 776 #define IS_GEN9_BC(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
 777
 778 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
 779 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
 780
 781 #define ENGINE_INSTANCES_MASK(gt, first, count) ({              \
 782         unsigned int first__ = (first);                                 \
 783         unsigned int count__ = (count);                                 \
 784         ((gt)->info.engine_mask &                                               \
 785          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
 786 })
 787 #define RCS_MASK(gt) \
 788         ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
 789 #define BCS_MASK(gt) \
 790         ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
 791 #define VDBOX_MASK(gt) \
 792         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
 793 #define VEBOX_MASK(gt) \
 794         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
 795 #define CCS_MASK(gt) \
 796         ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
 797
 798 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
 799
 800 /*
 801  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
 802  * All later gens can run the final buffer from the ppgtt
 803  */
 804 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 805
 806 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
 807 #define HAS_4TILE(dev_priv)     (INTEL_INFO(dev_priv)->has_4tile)
 808 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
 809 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
 810 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
 811 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
 812
 813 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
 814
 815 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 816                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
 817 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
 818                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 819
 820 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 821
 822 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
 823 #define HAS_PPGTT(dev_priv) \
 824         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 825 #define HAS_FULL_PPGTT(dev_priv) \
 826         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
 827
 828 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 829         GEM_BUG_ON((sizes) == 0); \
 830         ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
 831 })
 832
 833 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
 834 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
 835                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
 836
 837 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 838 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
 839
 840 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
 841         (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
 842
 843 /* WaRsDisableCoarsePowerGating:skl,cnl */
 844 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
 845         (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 846
 847 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
 848 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
 849                                         IS_GEMINILAKE(dev_priv) || \
 850                                         IS_KABYLAKE(dev_priv))
 851
 852 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 853  * rows, which changed the alignment requirements and fence programming.
 854  */
 855 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
 856                                          !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
 857 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
 858 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
 859
 860 #define HAS_FW_BLC(dev_priv)    (DISPLAY_VER(dev_priv) > 2)
 861 #define HAS_FBC(dev_priv)       (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
 862 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
 863
 864 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 865
 866 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
 867 #define HAS_DP20(dev_priv)      (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
 868
 869 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)       (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 870
 871 #define HAS_CDCLK_CRAWL(dev_priv)        (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 872 #define HAS_CDCLK_SQUASH(dev_priv)       (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
 873 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
 874 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 875 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
 876 #define HAS_PSR_HW_TRACKING(dev_priv) \
 877         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 878 #define HAS_PSR2_SEL_FETCH(dev_priv)     (DISPLAY_VER(dev_priv) >= 12)
 879 #define HAS_TRANSCODER(dev_priv, trans)  ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 880
 881 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
 882 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
 883 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
 884
 885 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
 886
 887 #define HAS_DMC(dev_priv)       (RUNTIME_INFO(dev_priv)->has_dmc)
 888
 889 #define HAS_HECI_PXP(dev_priv) \
 890         (INTEL_INFO(dev_priv)->has_heci_pxp)
 891
 892 #define HAS_HECI_GSCFI(dev_priv) \
 893         (INTEL_INFO(dev_priv)->has_heci_gscfi)
 894
 895 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
 896
 897 #define HAS_MSO(i915)           (DISPLAY_VER(i915) >= 12)
 898
 899 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 900 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 901
 902 #define HAS_OA_BPC_REPORTING(dev_priv) \
 903         (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
 904 #define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
 905         (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
 906
 907 /*
 908  * Set this flag, when platform requires 64K GTT page sizes or larger for
 909  * device local memory access.
 910  */
 911 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 912
 913 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
 914
 915 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
 916 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
 917
 918 #define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)
 919
 920 /*
 921  * Platform has the dedicated compression control state for each lmem surfaces
 922  * stored in lmem to support the 3D and media compression formats.
 923  */
 924 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 925
 926 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
 927
 928 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
 929
 930 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
 931
 932 #define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
 933                             INTEL_INFO(dev_priv)->has_pxp) && \
 934                             VDBOX_MASK(to_gt(dev_priv)))
 935
 936 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
 937
 938 #define HAS_GMD_ID(i915)        (INTEL_INFO(i915)->has_gmd_id)
 939
 940 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 941
 942 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
 943
 944 /* DPF == dynamic parity feature */
 945 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 946 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 947                                  2 : HAS_L3_DPF(dev_priv))
 948
 949 #define GT_FREQUENCY_MULTIPLIER 50
 950 #define GEN9_FREQ_SCALER 3
 951
 952 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
 953
 954 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
 955
 956 #define HAS_VRR(i915)   (DISPLAY_VER(i915) >= 11)
 957
 958 #define HAS_ASYNC_FLIPS(i915)           (DISPLAY_VER(i915) >= 5)
 959
 960 /* Only valid when HAS_DISPLAY() is true */
 961 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 962         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),         \
 963          !(dev_priv)->params.disable_display &&                         \
 964          !intel_opregion_headless_sku(dev_priv))
 965
 966 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
 967         (INTEL_INFO(dev_priv)->has_guc_deprivilege)
 968
 969 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
 970                                               IS_ALDERLAKE_S(dev_priv))
 971
 972 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 973
 974 #define HAS_3D_PIPELINE(i915)   (INTEL_INFO(i915)->has_3d_pipeline)
 975
 976 #define HAS_ONE_EU_PER_FUSE_BIT(i915)   (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
 977
 978 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
 979                                        GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
 980
 981 /* intel_device_info.c */
 982 static inline struct intel_device_info *
 983 mkwrite_device_info(struct drm_i915_private *dev_priv)
 984 {
 985         return (struct intel_device_info *)INTEL_INFO(dev_priv);
 986 }
 987
 988 #endif