drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_vgpu.h"
  53 #include "intel_drv.h"
  54 #include "intel_uc.h"
  55
  56 static struct drm_driver driver;
  57
  58 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  59 static unsigned int i915_load_fail_count;
  60
  61 bool __i915_inject_load_failure(const char *func, int line)
  62 {
  63         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  64                 return false;
  65
  66         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  67                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  68                          i915_modparams.inject_load_failure, func, line);
  69                 return true;
  70         }
  71
  72         return false;
  73 }
  74 #endif
  75
  76 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  77 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  78                     "providing the dmesg log by booting with drm.debug=0xf"
  79
  80 void
  81 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  82               const char *fmt, ...)
  83 {
  84         static bool shown_bug_once;
  85         struct device *kdev = dev_priv->drm.dev;
  86         bool is_error = level[1] <= KERN_ERR[1];
  87         bool is_debug = level[1] == KERN_DEBUG[1];
  88         struct va_format vaf;
  89         va_list args;
  90
  91         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  92                 return;
  93
  94         va_start(args, fmt);
  95
  96         vaf.fmt = fmt;
  97         vaf.va = &args;
  98
  99         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 100                    __builtin_return_address(0), &vaf);
 101
 102         if (is_error && !shown_bug_once) {
 103                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 104                 shown_bug_once = true;
 105         }
 106
 107         va_end(args);
 108 }
 109
 110 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 111 {
 112 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
 113         return i915_modparams.inject_load_failure &&
 114                i915_load_fail_count == i915_modparams.inject_load_failure;
 115 #else
 116         return false;
 117 #endif
 118 }
 119
 120 #define i915_load_error(dev_priv, fmt, ...)                                  \
 121         __i915_printk(dev_priv,                                              \
 122                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 123                       fmt, ##__VA_ARGS__)
 124
 125 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 126 static enum intel_pch
 127 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 128 {
 129         switch (id) {
 130         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 131                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 132                 WARN_ON(!IS_GEN5(dev_priv));
 133                 return PCH_IBX;
 134         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 135                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 136                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 137                 return PCH_CPT;
 138         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 139                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 140                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 141                 /* PantherPoint is CPT compatible */
 142                 return PCH_CPT;
 143         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 144                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 145                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 146                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 147                 return PCH_LPT;
 148         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 149                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 150                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 151                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 152                 return PCH_LPT;
 153         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 154                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 155                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 156                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 157                 /* WildcatPoint is LPT compatible */
 158                 return PCH_LPT;
 159         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 160                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 161                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 162                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 163                 /* WildcatPoint is LPT compatible */
 164                 return PCH_LPT;
 165         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 166                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 167                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 168                 return PCH_SPT;
 169         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 170                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 171                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 172                 return PCH_SPT;
 173         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 174                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 175                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 176                         !IS_COFFEELAKE(dev_priv));
 177                 return PCH_KBP;
 178         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 179                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 180                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 181                 return PCH_CNP;
 182         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 183                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 184                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 185                 return PCH_CNP;
 186         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 187                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 188                 WARN_ON(!IS_ICELAKE(dev_priv));
 189                 return PCH_ICP;
 190         default:
 191                 return PCH_NONE;
 192         }
 193 }
 194
 195 static bool intel_is_virt_pch(unsigned short id,
 196                               unsigned short svendor, unsigned short sdevice)
 197 {
 198         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 199                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 200                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 201                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 202                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 203 }
 204
 205 static unsigned short
 206 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 207 {
 208         unsigned short id = 0;
 209
 210         /*
 211          * In a virtualized passthrough environment we can be in a
 212          * setup where the ISA bridge is not able to be passed through.
 213          * In this case, a south bridge can be emulated and we have to
 214          * make an educated guess as to which PCH is really there.
 215          */
 216
 217         if (IS_GEN5(dev_priv))
 218                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 219         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 220                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 221         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 222                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 223         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 224                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 225         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 226                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 227         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 228                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 229
 230         if (id)
 231                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 232         else
 233                 DRM_DEBUG_KMS("Assuming no PCH\n");
 234
 235         return id;
 236 }
 237
 238 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 239 {
 240         struct pci_dev *pch = NULL;
 241
 242         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 243          * (which really amounts to a PCH but no South Display).
 244          */
 245         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 246                 dev_priv->pch_type = PCH_NOP;
 247                 return;
 248         }
 249
 250         /*
 251          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 252          * make graphics device passthrough work easy for VMM, that only
 253          * need to expose ISA bridge to let driver know the real hardware
 254          * underneath. This is a requirement from virtualization team.
 255          *
 256          * In some virtualized environments (e.g. XEN), there is irrelevant
 257          * ISA bridge in the system. To work reliably, we should scan trhough
 258          * all the ISA bridge devices and check for the first match, instead
 259          * of only checking the first one.
 260          */
 261         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 262                 unsigned short id;
 263                 enum intel_pch pch_type;
 264
 265                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 266                         continue;
 267
 268                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 269
 270                 pch_type = intel_pch_type(dev_priv, id);
 271                 if (pch_type != PCH_NONE) {
 272                         dev_priv->pch_type = pch_type;
 273                         dev_priv->pch_id = id;
 274                         break;
 275                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 276                                          pch->subsystem_device)) {
 277                         id = intel_virt_detect_pch(dev_priv);
 278                         if (id) {
 279                                 pch_type = intel_pch_type(dev_priv, id);
 280                                 if (WARN_ON(pch_type == PCH_NONE))
 281                                         pch_type = PCH_NOP;
 282                         } else {
 283                                 pch_type = PCH_NOP;
 284                         }
 285                         dev_priv->pch_type = pch_type;
 286                         dev_priv->pch_id = id;
 287                         break;
 288                 }
 289         }
 290         if (!pch)
 291                 DRM_DEBUG_KMS("No PCH found.\n");
 292
 293         pci_dev_put(pch);
 294 }
 295
 296 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 297                                struct drm_file *file_priv)
 298 {
 299         struct drm_i915_private *dev_priv = to_i915(dev);
 300         struct pci_dev *pdev = dev_priv->drm.pdev;
 301         drm_i915_getparam_t *param = data;
 302         int value;
 303
 304         switch (param->param) {
 305         case I915_PARAM_IRQ_ACTIVE:
 306         case I915_PARAM_ALLOW_BATCHBUFFER:
 307         case I915_PARAM_LAST_DISPATCH:
 308         case I915_PARAM_HAS_EXEC_CONSTANTS:
 309                 /* Reject all old ums/dri params. */
 310                 return -ENODEV;
 311         case I915_PARAM_CHIPSET_ID:
 312                 value = pdev->device;
 313                 break;
 314         case I915_PARAM_REVISION:
 315                 value = pdev->revision;
 316                 break;
 317         case I915_PARAM_NUM_FENCES_AVAIL:
 318                 value = dev_priv->num_fence_regs;
 319                 break;
 320         case I915_PARAM_HAS_OVERLAY:
 321                 value = dev_priv->overlay ? 1 : 0;
 322                 break;
 323         case I915_PARAM_HAS_BSD:
 324                 value = !!dev_priv->engine[VCS];
 325                 break;
 326         case I915_PARAM_HAS_BLT:
 327                 value = !!dev_priv->engine[BCS];
 328                 break;
 329         case I915_PARAM_HAS_VEBOX:
 330                 value = !!dev_priv->engine[VECS];
 331                 break;
 332         case I915_PARAM_HAS_BSD2:
 333                 value = !!dev_priv->engine[VCS2];
 334                 break;
 335         case I915_PARAM_HAS_LLC:
 336                 value = HAS_LLC(dev_priv);
 337                 break;
 338         case I915_PARAM_HAS_WT:
 339                 value = HAS_WT(dev_priv);
 340                 break;
 341         case I915_PARAM_HAS_ALIASING_PPGTT:
 342                 value = USES_PPGTT(dev_priv);
 343                 break;
 344         case I915_PARAM_HAS_SEMAPHORES:
 345                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 346                 break;
 347         case I915_PARAM_HAS_SECURE_BATCHES:
 348                 value = capable(CAP_SYS_ADMIN);
 349                 break;
 350         case I915_PARAM_CMD_PARSER_VERSION:
 351                 value = i915_cmd_parser_get_version(dev_priv);
 352                 break;
 353         case I915_PARAM_SUBSLICE_TOTAL:
 354                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 355                 if (!value)
 356                         return -ENODEV;
 357                 break;
 358         case I915_PARAM_EU_TOTAL:
 359                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 360                 if (!value)
 361                         return -ENODEV;
 362                 break;
 363         case I915_PARAM_HAS_GPU_RESET:
 364                 value = i915_modparams.enable_hangcheck &&
 365                         intel_has_gpu_reset(dev_priv);
 366                 if (value && intel_has_reset_engine(dev_priv))
 367                         value = 2;
 368                 break;
 369         case I915_PARAM_HAS_RESOURCE_STREAMER:
 370                 value = HAS_RESOURCE_STREAMER(dev_priv);
 371                 break;
 372         case I915_PARAM_HAS_POOLED_EU:
 373                 value = HAS_POOLED_EU(dev_priv);
 374                 break;
 375         case I915_PARAM_MIN_EU_IN_POOL:
 376                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 377                 break;
 378         case I915_PARAM_HUC_STATUS:
 379                 intel_runtime_pm_get(dev_priv);
 380                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 381                 intel_runtime_pm_put(dev_priv);
 382                 break;
 383         case I915_PARAM_MMAP_GTT_VERSION:
 384                 /* Though we've started our numbering from 1, and so class all
 385                  * earlier versions as 0, in effect their value is undefined as
 386                  * the ioctl will report EINVAL for the unknown param!
 387                  */
 388                 value = i915_gem_mmap_gtt_version();
 389                 break;
 390         case I915_PARAM_HAS_SCHEDULER:
 391                 value = dev_priv->caps.scheduler;
 392                 break;
 393
 394         case I915_PARAM_MMAP_VERSION:
 395                 /* Remember to bump this if the version changes! */
 396         case I915_PARAM_HAS_GEM:
 397         case I915_PARAM_HAS_PAGEFLIPPING:
 398         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 399         case I915_PARAM_HAS_RELAXED_FENCING:
 400         case I915_PARAM_HAS_COHERENT_RINGS:
 401         case I915_PARAM_HAS_RELAXED_DELTA:
 402         case I915_PARAM_HAS_GEN7_SOL_RESET:
 403         case I915_PARAM_HAS_WAIT_TIMEOUT:
 404         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 405         case I915_PARAM_HAS_PINNED_BATCHES:
 406         case I915_PARAM_HAS_EXEC_NO_RELOC:
 407         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 408         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 409         case I915_PARAM_HAS_EXEC_SOFTPIN:
 410         case I915_PARAM_HAS_EXEC_ASYNC:
 411         case I915_PARAM_HAS_EXEC_FENCE:
 412         case I915_PARAM_HAS_EXEC_CAPTURE:
 413         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 414         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 415                 /* For the time being all of these are always true;
 416                  * if some supported hardware does not have one of these
 417                  * features this value needs to be provided from
 418                  * INTEL_INFO(), a feature macro, or similar.
 419                  */
 420                 value = 1;
 421                 break;
 422         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 423                 value = intel_engines_has_context_isolation(dev_priv);
 424                 break;
 425         case I915_PARAM_SLICE_MASK:
 426                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 427                 if (!value)
 428                         return -ENODEV;
 429                 break;
 430         case I915_PARAM_SUBSLICE_MASK:
 431                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 432                 if (!value)
 433                         return -ENODEV;
 434                 break;
 435         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 436                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 437                 break;
 438         default:
 439                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 440                 return -EINVAL;
 441         }
 442
 443         if (put_user(value, param->value))
 444                 return -EFAULT;
 445
 446         return 0;
 447 }
 448
 449 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 450 {
 451         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 452         if (!dev_priv->bridge_dev) {
 453                 DRM_ERROR("bridge device not found\n");
 454                 return -1;
 455         }
 456         return 0;
 457 }
 458
 459 /* Allocate space for the MCH regs if needed, return nonzero on error */
 460 static int
 461 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 462 {
 463         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 464         u32 temp_lo, temp_hi = 0;
 465         u64 mchbar_addr;
 466         int ret;
 467
 468         if (INTEL_GEN(dev_priv) >= 4)
 469                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 470         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 471         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 472
 473         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 474 #ifdef CONFIG_PNP
 475         if (mchbar_addr &&
 476             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 477                 return 0;
 478 #endif
 479
 480         /* Get some space for it */
 481         dev_priv->mch_res.name = "i915 MCHBAR";
 482         dev_priv->mch_res.flags = IORESOURCE_MEM;
 483         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 484                                      &dev_priv->mch_res,
 485                                      MCHBAR_SIZE, MCHBAR_SIZE,
 486                                      PCIBIOS_MIN_MEM,
 487                                      0, pcibios_align_resource,
 488                                      dev_priv->bridge_dev);
 489         if (ret) {
 490                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 491                 dev_priv->mch_res.start = 0;
 492                 return ret;
 493         }
 494
 495         if (INTEL_GEN(dev_priv) >= 4)
 496                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 497                                        upper_32_bits(dev_priv->mch_res.start));
 498
 499         pci_write_config_dword(dev_priv->bridge_dev, reg,
 500                                lower_32_bits(dev_priv->mch_res.start));
 501         return 0;
 502 }
 503
 504 /* Setup MCHBAR if possible, return true if we should disable it again */
 505 static void
 506 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 507 {
 508         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 509         u32 temp;
 510         bool enabled;
 511
 512         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 513                 return;
 514
 515         dev_priv->mchbar_need_disable = false;
 516
 517         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 518                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 519                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 520         } else {
 521                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 522                 enabled = temp & 1;
 523         }
 524
 525         /* If it's already enabled, don't have to do anything */
 526         if (enabled)
 527                 return;
 528
 529         if (intel_alloc_mchbar_resource(dev_priv))
 530                 return;
 531
 532         dev_priv->mchbar_need_disable = true;
 533
 534         /* Space is allocated or reserved, so enable it. */
 535         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 536                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 537                                        temp | DEVEN_MCHBAR_EN);
 538         } else {
 539                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 540                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 541         }
 542 }
 543
 544 static void
 545 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 546 {
 547         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 548
 549         if (dev_priv->mchbar_need_disable) {
 550                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 551                         u32 deven_val;
 552
 553                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 554                                               &deven_val);
 555                         deven_val &= ~DEVEN_MCHBAR_EN;
 556                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 557                                                deven_val);
 558                 } else {
 559                         u32 mchbar_val;
 560
 561                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 562                                               &mchbar_val);
 563                         mchbar_val &= ~1;
 564                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 565                                                mchbar_val);
 566                 }
 567         }
 568
 569         if (dev_priv->mch_res.start)
 570                 release_resource(&dev_priv->mch_res);
 571 }
 572
 573 /* true = enable decode, false = disable decoder */
 574 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 575 {
 576         struct drm_i915_private *dev_priv = cookie;
 577
 578         intel_modeset_vga_set_state(dev_priv, state);
 579         if (state)
 580                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 581                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 582         else
 583                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 584 }
 585
 586 static int i915_resume_switcheroo(struct drm_device *dev);
 587 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 588
 589 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 590 {
 591         struct drm_device *dev = pci_get_drvdata(pdev);
 592         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 593
 594         if (state == VGA_SWITCHEROO_ON) {
 595                 pr_info("switched on\n");
 596                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 597                 /* i915 resume handler doesn't set to D0 */
 598                 pci_set_power_state(pdev, PCI_D0);
 599                 i915_resume_switcheroo(dev);
 600                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 601         } else {
 602                 pr_info("switched off\n");
 603                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 604                 i915_suspend_switcheroo(dev, pmm);
 605                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 606         }
 607 }
 608
 609 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 610 {
 611         struct drm_device *dev = pci_get_drvdata(pdev);
 612
 613         /*
 614          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 615          * locking inversion with the driver load path. And the access here is
 616          * completely racy anyway. So don't bother with locking for now.
 617          */
 618         return dev->open_count == 0;
 619 }
 620
 621 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 622         .set_gpu_state = i915_switcheroo_set_state,
 623         .reprobe = NULL,
 624         .can_switch = i915_switcheroo_can_switch,
 625 };
 626
 627 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 628 {
 629         /* Flush any outstanding unpin_work. */
 630         i915_gem_drain_workqueue(dev_priv);
 631
 632         mutex_lock(&dev_priv->drm.struct_mutex);
 633         intel_uc_fini_hw(dev_priv);
 634         intel_uc_fini(dev_priv);
 635         i915_gem_cleanup_engines(dev_priv);
 636         i915_gem_contexts_fini(dev_priv);
 637         mutex_unlock(&dev_priv->drm.struct_mutex);
 638
 639         intel_uc_fini_misc(dev_priv);
 640         i915_gem_cleanup_userptr(dev_priv);
 641
 642         i915_gem_drain_freed_objects(dev_priv);
 643
 644         WARN_ON(!list_empty(&dev_priv->contexts.list));
 645 }
 646
 647 static int i915_load_modeset_init(struct drm_device *dev)
 648 {
 649         struct drm_i915_private *dev_priv = to_i915(dev);
 650         struct pci_dev *pdev = dev_priv->drm.pdev;
 651         int ret;
 652
 653         if (i915_inject_load_failure())
 654                 return -ENODEV;
 655
 656         intel_bios_init(dev_priv);
 657
 658         /* If we have > 1 VGA cards, then we need to arbitrate access
 659          * to the common VGA resources.
 660          *
 661          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 662          * then we do not take part in VGA arbitration and the
 663          * vga_client_register() fails with -ENODEV.
 664          */
 665         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 666         if (ret && ret != -ENODEV)
 667                 goto out;
 668
 669         intel_register_dsm_handler();
 670
 671         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 672         if (ret)
 673                 goto cleanup_vga_client;
 674
 675         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 676         intel_update_rawclk(dev_priv);
 677
 678         intel_power_domains_init_hw(dev_priv, false);
 679
 680         intel_csr_ucode_init(dev_priv);
 681
 682         ret = intel_irq_install(dev_priv);
 683         if (ret)
 684                 goto cleanup_csr;
 685
 686         intel_setup_gmbus(dev_priv);
 687
 688         /* Important: The output setup functions called by modeset_init need
 689          * working irqs for e.g. gmbus and dp aux transfers. */
 690         ret = intel_modeset_init(dev);
 691         if (ret)
 692                 goto cleanup_irq;
 693
 694         intel_uc_init_fw(dev_priv);
 695
 696         ret = i915_gem_init(dev_priv);
 697         if (ret)
 698                 goto cleanup_uc;
 699
 700         intel_setup_overlay(dev_priv);
 701
 702         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 703                 return 0;
 704
 705         ret = intel_fbdev_init(dev);
 706         if (ret)
 707                 goto cleanup_gem;
 708
 709         /* Only enable hotplug handling once the fbdev is fully set up. */
 710         intel_hpd_init(dev_priv);
 711
 712         return 0;
 713
 714 cleanup_gem:
 715         if (i915_gem_suspend(dev_priv))
 716                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 717         i915_gem_fini(dev_priv);
 718 cleanup_uc:
 719         intel_uc_fini_fw(dev_priv);
 720 cleanup_irq:
 721         drm_irq_uninstall(dev);
 722         intel_teardown_gmbus(dev_priv);
 723 cleanup_csr:
 724         intel_csr_ucode_fini(dev_priv);
 725         intel_power_domains_fini(dev_priv);
 726         vga_switcheroo_unregister_client(pdev);
 727 cleanup_vga_client:
 728         vga_client_register(pdev, NULL, NULL, NULL);
 729 out:
 730         return ret;
 731 }
 732
 733 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 734 {
 735         struct apertures_struct *ap;
 736         struct pci_dev *pdev = dev_priv->drm.pdev;
 737         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 738         bool primary;
 739         int ret;
 740
 741         ap = alloc_apertures(1);
 742         if (!ap)
 743                 return -ENOMEM;
 744
 745         ap->ranges[0].base = ggtt->gmadr.start;
 746         ap->ranges[0].size = ggtt->mappable_end;
 747
 748         primary =
 749                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 750
 751         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 752
 753         kfree(ap);
 754
 755         return ret;
 756 }
 757
 758 #if !defined(CONFIG_VGA_CONSOLE)
 759 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 760 {
 761         return 0;
 762 }
 763 #elif !defined(CONFIG_DUMMY_CONSOLE)
 764 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 765 {
 766         return -ENODEV;
 767 }
 768 #else
 769 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 770 {
 771         int ret = 0;
 772
 773         DRM_INFO("Replacing VGA console driver\n");
 774
 775         console_lock();
 776         if (con_is_bound(&vga_con))
 777                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 778         if (ret == 0) {
 779                 ret = do_unregister_con_driver(&vga_con);
 780
 781                 /* Ignore "already unregistered". */
 782                 if (ret == -ENODEV)
 783                         ret = 0;
 784         }
 785         console_unlock();
 786
 787         return ret;
 788 }
 789 #endif
 790
 791 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 792 {
 793         /*
 794          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 795          * CHV x1 PHY (DP/HDMI D)
 796          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 797          */
 798         if (IS_CHERRYVIEW(dev_priv)) {
 799                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 800                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 801         } else if (IS_VALLEYVIEW(dev_priv)) {
 802                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 803         }
 804 }
 805
 806 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 807 {
 808         /*
 809          * The i915 workqueue is primarily used for batched retirement of
 810          * requests (and thus managing bo) once the task has been completed
 811          * by the GPU. i915_retire_requests() is called directly when we
 812          * need high-priority retirement, such as waiting for an explicit
 813          * bo.
 814          *
 815          * It is also used for periodic low-priority events, such as
 816          * idle-timers and recording error state.
 817          *
 818          * All tasks on the workqueue are expected to acquire the dev mutex
 819          * so there is no point in running more than one instance of the
 820          * workqueue at any time.  Use an ordered one.
 821          */
 822         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 823         if (dev_priv->wq == NULL)
 824                 goto out_err;
 825
 826         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 827         if (dev_priv->hotplug.dp_wq == NULL)
 828                 goto out_free_wq;
 829
 830         return 0;
 831
 832 out_free_wq:
 833         destroy_workqueue(dev_priv->wq);
 834 out_err:
 835         DRM_ERROR("Failed to allocate workqueues.\n");
 836
 837         return -ENOMEM;
 838 }
 839
 840 static void i915_engines_cleanup(struct drm_i915_private *i915)
 841 {
 842         struct intel_engine_cs *engine;
 843         enum intel_engine_id id;
 844
 845         for_each_engine(engine, i915, id)
 846                 kfree(engine);
 847 }
 848
 849 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 850 {
 851         destroy_workqueue(dev_priv->hotplug.dp_wq);
 852         destroy_workqueue(dev_priv->wq);
 853 }
 854
 855 /*
 856  * We don't keep the workarounds for pre-production hardware, so we expect our
 857  * driver to fail on these machines in one way or another. A little warning on
 858  * dmesg may help both the user and the bug triagers.
 859  *
 860  * Our policy for removing pre-production workarounds is to keep the
 861  * current gen workarounds as a guide to the bring-up of the next gen
 862  * (workarounds have a habit of persisting!). Anything older than that
 863  * should be removed along with the complications they introduce.
 864  */
 865 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 866 {
 867         bool pre = false;
 868
 869         pre |= IS_HSW_EARLY_SDV(dev_priv);
 870         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 871         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 872
 873         if (pre) {
 874                 DRM_ERROR("This is a pre-production stepping. "
 875                           "It may not be fully functional.\n");
 876                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 877         }
 878 }
 879
 880 /**
 881  * i915_driver_init_early - setup state not requiring device access
 882  * @dev_priv: device private
 883  * @ent: the matching pci_device_id
 884  *
 885  * Initialize everything that is a "SW-only" state, that is state not
 886  * requiring accessing the device or exposing the driver via kernel internal
 887  * or userspace interfaces. Example steps belonging here: lock initialization,
 888  * system memory allocation, setting up device specific attributes and
 889  * function hooks not requiring accessing the device.
 890  */
 891 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 892                                   const struct pci_device_id *ent)
 893 {
 894         const struct intel_device_info *match_info =
 895                 (struct intel_device_info *)ent->driver_data;
 896         struct intel_device_info *device_info;
 897         int ret = 0;
 898
 899         if (i915_inject_load_failure())
 900                 return -ENODEV;
 901
 902         /* Setup the write-once "constant" device info */
 903         device_info = mkwrite_device_info(dev_priv);
 904         memcpy(device_info, match_info, sizeof(*device_info));
 905         device_info->device_id = dev_priv->drm.pdev->device;
 906
 907         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 908                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 909         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 910         spin_lock_init(&dev_priv->irq_lock);
 911         spin_lock_init(&dev_priv->gpu_error.lock);
 912         mutex_init(&dev_priv->backlight_lock);
 913         spin_lock_init(&dev_priv->uncore.lock);
 914
 915         mutex_init(&dev_priv->sb_lock);
 916         mutex_init(&dev_priv->modeset_restore_lock);
 917         mutex_init(&dev_priv->av_mutex);
 918         mutex_init(&dev_priv->wm.wm_mutex);
 919         mutex_init(&dev_priv->pps_mutex);
 920
 921         intel_uc_init_early(dev_priv);
 922         i915_memcpy_init_early(dev_priv);
 923
 924         ret = i915_workqueues_init(dev_priv);
 925         if (ret < 0)
 926                 goto err_engines;
 927
 928         /* This must be called before any calls to HAS_PCH_* */
 929         intel_detect_pch(dev_priv);
 930
 931         intel_pm_setup(dev_priv);
 932         intel_init_dpio(dev_priv);
 933         intel_power_domains_init(dev_priv);
 934         intel_irq_init(dev_priv);
 935         intel_hangcheck_init(dev_priv);
 936         intel_init_display_hooks(dev_priv);
 937         intel_init_clock_gating_hooks(dev_priv);
 938         intel_init_audio_hooks(dev_priv);
 939         ret = i915_gem_load_init(dev_priv);
 940         if (ret < 0)
 941                 goto err_irq;
 942
 943         intel_display_crc_init(dev_priv);
 944
 945         intel_detect_preproduction_hw(dev_priv);
 946
 947         return 0;
 948
 949 err_irq:
 950         intel_irq_fini(dev_priv);
 951         i915_workqueues_cleanup(dev_priv);
 952 err_engines:
 953         i915_engines_cleanup(dev_priv);
 954         return ret;
 955 }
 956
 957 /**
 958  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 959  * @dev_priv: device private
 960  */
 961 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 962 {
 963         i915_gem_load_cleanup(dev_priv);
 964         intel_irq_fini(dev_priv);
 965         i915_workqueues_cleanup(dev_priv);
 966         i915_engines_cleanup(dev_priv);
 967 }
 968
 969 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 970 {
 971         struct pci_dev *pdev = dev_priv->drm.pdev;
 972         int mmio_bar;
 973         int mmio_size;
 974
 975         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 976         /*
 977          * Before gen4, the registers and the GTT are behind different BARs.
 978          * However, from gen4 onwards, the registers and the GTT are shared
 979          * in the same BAR, so we want to restrict this ioremap from
 980          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 981          * the register BAR remains the same size for all the earlier
 982          * generations up to Ironlake.
 983          */
 984         if (INTEL_GEN(dev_priv) < 5)
 985                 mmio_size = 512 * 1024;
 986         else
 987                 mmio_size = 2 * 1024 * 1024;
 988         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 989         if (dev_priv->regs == NULL) {
 990                 DRM_ERROR("failed to map registers\n");
 991
 992                 return -EIO;
 993         }
 994
 995         /* Try to make sure MCHBAR is enabled before poking at it */
 996         intel_setup_mchbar(dev_priv);
 997
 998         return 0;
 999 }
1000
1001 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
1002 {
1003         struct pci_dev *pdev = dev_priv->drm.pdev;
1004
1005         intel_teardown_mchbar(dev_priv);
1006         pci_iounmap(pdev, dev_priv->regs);
1007 }
1008
1009 /**
1010  * i915_driver_init_mmio - setup device MMIO
1011  * @dev_priv: device private
1012  *
1013  * Setup minimal device state necessary for MMIO accesses later in the
1014  * initialization sequence. The setup here should avoid any other device-wide
1015  * side effects or exposing the driver via kernel internal or user space
1016  * interfaces.
1017  */
1018 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1019 {
1020         int ret;
1021
1022         if (i915_inject_load_failure())
1023                 return -ENODEV;
1024
1025         if (i915_get_bridge_dev(dev_priv))
1026                 return -EIO;
1027
1028         ret = i915_mmio_setup(dev_priv);
1029         if (ret < 0)
1030                 goto err_bridge;
1031
1032         intel_uncore_init(dev_priv);
1033
1034         intel_uc_init_mmio(dev_priv);
1035
1036         ret = intel_engines_init_mmio(dev_priv);
1037         if (ret)
1038                 goto err_uncore;
1039
1040         i915_gem_init_mmio(dev_priv);
1041
1042         return 0;
1043
1044 err_uncore:
1045         intel_uncore_fini(dev_priv);
1046 err_bridge:
1047         pci_dev_put(dev_priv->bridge_dev);
1048
1049         return ret;
1050 }
1051
1052 /**
1053  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1054  * @dev_priv: device private
1055  */
1056 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1057 {
1058         intel_uncore_fini(dev_priv);
1059         i915_mmio_cleanup(dev_priv);
1060         pci_dev_put(dev_priv->bridge_dev);
1061 }
1062
1063 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1064 {
1065         /*
1066          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1067          * user's requested state against the hardware/driver capabilities.  We
1068          * do this now so that we can print out any log messages once rather
1069          * than every time we check intel_enable_ppgtt().
1070          */
1071         i915_modparams.enable_ppgtt =
1072                 intel_sanitize_enable_ppgtt(dev_priv,
1073                                             i915_modparams.enable_ppgtt);
1074         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1075
1076         intel_uc_sanitize_options(dev_priv);
1077
1078         intel_gvt_sanitize_options(dev_priv);
1079 }
1080
1081 /**
1082  * i915_driver_init_hw - setup state requiring device access
1083  * @dev_priv: device private
1084  *
1085  * Setup state that requires accessing the device, but doesn't require
1086  * exposing the driver via kernel internal or userspace interfaces.
1087  */
1088 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1089 {
1090         struct pci_dev *pdev = dev_priv->drm.pdev;
1091         int ret;
1092
1093         if (i915_inject_load_failure())
1094                 return -ENODEV;
1095
1096         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1097
1098         intel_sanitize_options(dev_priv);
1099
1100         i915_perf_init(dev_priv);
1101
1102         ret = i915_ggtt_probe_hw(dev_priv);
1103         if (ret)
1104                 return ret;
1105
1106         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1107          * otherwise the vga fbdev driver falls over. */
1108         ret = i915_kick_out_firmware_fb(dev_priv);
1109         if (ret) {
1110                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1111                 goto out_ggtt;
1112         }
1113
1114         ret = i915_kick_out_vgacon(dev_priv);
1115         if (ret) {
1116                 DRM_ERROR("failed to remove conflicting VGA console\n");
1117                 goto out_ggtt;
1118         }
1119
1120         ret = i915_ggtt_init_hw(dev_priv);
1121         if (ret)
1122                 return ret;
1123
1124         ret = i915_ggtt_enable_hw(dev_priv);
1125         if (ret) {
1126                 DRM_ERROR("failed to enable GGTT\n");
1127                 goto out_ggtt;
1128         }
1129
1130         pci_set_master(pdev);
1131
1132         /* overlay on gen2 is broken and can't address above 1G */
1133         if (IS_GEN2(dev_priv)) {
1134                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1135                 if (ret) {
1136                         DRM_ERROR("failed to set DMA mask\n");
1137
1138                         goto out_ggtt;
1139                 }
1140         }
1141
1142         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1143          * using 32bit addressing, overwriting memory if HWS is located
1144          * above 4GB.
1145          *
1146          * The documentation also mentions an issue with undefined
1147          * behaviour if any general state is accessed within a page above 4GB,
1148          * which also needs to be handled carefully.
1149          */
1150         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1151                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1152
1153                 if (ret) {
1154                         DRM_ERROR("failed to set DMA mask\n");
1155
1156                         goto out_ggtt;
1157                 }
1158         }
1159
1160         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1161                            PM_QOS_DEFAULT_VALUE);
1162
1163         intel_uncore_sanitize(dev_priv);
1164
1165         intel_opregion_setup(dev_priv);
1166
1167         i915_gem_load_init_fences(dev_priv);
1168
1169         /* On the 945G/GM, the chipset reports the MSI capability on the
1170          * integrated graphics even though the support isn't actually there
1171          * according to the published specs.  It doesn't appear to function
1172          * correctly in testing on 945G.
1173          * This may be a side effect of MSI having been made available for PEG
1174          * and the registers being closely associated.
1175          *
1176          * According to chipset errata, on the 965GM, MSI interrupts may
1177          * be lost or delayed, and was defeatured. MSI interrupts seem to
1178          * get lost on g4x as well, and interrupt delivery seems to stay
1179          * properly dead afterwards. So we'll just disable them for all
1180          * pre-gen5 chipsets.
1181          */
1182         if (INTEL_GEN(dev_priv) >= 5) {
1183                 if (pci_enable_msi(pdev) < 0)
1184                         DRM_DEBUG_DRIVER("can't enable MSI");
1185         }
1186
1187         ret = intel_gvt_init(dev_priv);
1188         if (ret)
1189                 goto out_ggtt;
1190
1191         return 0;
1192
1193 out_ggtt:
1194         i915_ggtt_cleanup_hw(dev_priv);
1195
1196         return ret;
1197 }
1198
1199 /**
1200  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1201  * @dev_priv: device private
1202  */
1203 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1204 {
1205         struct pci_dev *pdev = dev_priv->drm.pdev;
1206
1207         i915_perf_fini(dev_priv);
1208
1209         if (pdev->msi_enabled)
1210                 pci_disable_msi(pdev);
1211
1212         pm_qos_remove_request(&dev_priv->pm_qos);
1213         i915_ggtt_cleanup_hw(dev_priv);
1214 }
1215
1216 /**
1217  * i915_driver_register - register the driver with the rest of the system
1218  * @dev_priv: device private
1219  *
1220  * Perform any steps necessary to make the driver available via kernel
1221  * internal or userspace interfaces.
1222  */
1223 static void i915_driver_register(struct drm_i915_private *dev_priv)
1224 {
1225         struct drm_device *dev = &dev_priv->drm;
1226
1227         i915_gem_shrinker_register(dev_priv);
1228         i915_pmu_register(dev_priv);
1229
1230         /*
1231          * Notify a valid surface after modesetting,
1232          * when running inside a VM.
1233          */
1234         if (intel_vgpu_active(dev_priv))
1235                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1236
1237         /* Reveal our presence to userspace */
1238         if (drm_dev_register(dev, 0) == 0) {
1239                 i915_debugfs_register(dev_priv);
1240                 i915_guc_log_register(dev_priv);
1241                 i915_setup_sysfs(dev_priv);
1242
1243                 /* Depends on sysfs having been initialized */
1244                 i915_perf_register(dev_priv);
1245         } else
1246                 DRM_ERROR("Failed to register driver for userspace access!\n");
1247
1248         if (INTEL_INFO(dev_priv)->num_pipes) {
1249                 /* Must be done after probing outputs */
1250                 intel_opregion_register(dev_priv);
1251                 acpi_video_register();
1252         }
1253
1254         if (IS_GEN5(dev_priv))
1255                 intel_gpu_ips_init(dev_priv);
1256
1257         intel_audio_init(dev_priv);
1258
1259         /*
1260          * Some ports require correctly set-up hpd registers for detection to
1261          * work properly (leading to ghost connected connector status), e.g. VGA
1262          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1263          * irqs are fully enabled. We do it last so that the async config
1264          * cannot run before the connectors are registered.
1265          */
1266         intel_fbdev_initial_config_async(dev);
1267
1268         /*
1269          * We need to coordinate the hotplugs with the asynchronous fbdev
1270          * configuration, for which we use the fbdev->async_cookie.
1271          */
1272         if (INTEL_INFO(dev_priv)->num_pipes)
1273                 drm_kms_helper_poll_init(dev);
1274 }
1275
1276 /**
1277  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1278  * @dev_priv: device private
1279  */
1280 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1281 {
1282         intel_fbdev_unregister(dev_priv);
1283         intel_audio_deinit(dev_priv);
1284
1285         /*
1286          * After flushing the fbdev (incl. a late async config which will
1287          * have delayed queuing of a hotplug event), then flush the hotplug
1288          * events.
1289          */
1290         drm_kms_helper_poll_fini(&dev_priv->drm);
1291
1292         intel_gpu_ips_teardown();
1293         acpi_video_unregister();
1294         intel_opregion_unregister(dev_priv);
1295
1296         i915_perf_unregister(dev_priv);
1297         i915_pmu_unregister(dev_priv);
1298
1299         i915_teardown_sysfs(dev_priv);
1300         i915_guc_log_unregister(dev_priv);
1301         drm_dev_unregister(&dev_priv->drm);
1302
1303         i915_gem_shrinker_unregister(dev_priv);
1304 }
1305
1306 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1307 {
1308         if (drm_debug & DRM_UT_DRIVER) {
1309                 struct drm_printer p = drm_debug_printer("i915 device info:");
1310
1311                 intel_device_info_dump(&dev_priv->info, &p);
1312                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1313         }
1314
1315         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1316                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1317         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1318                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1319 }
1320
1321 /**
1322  * i915_driver_load - setup chip and create an initial config
1323  * @pdev: PCI device
1324  * @ent: matching PCI ID entry
1325  *
1326  * The driver load routine has to do several things:
1327  *   - drive output discovery via intel_modeset_init()
1328  *   - initialize the memory manager
1329  *   - allocate initial config memory
1330  *   - setup the DRM framebuffer with the allocated memory
1331  */
1332 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1333 {
1334         const struct intel_device_info *match_info =
1335                 (struct intel_device_info *)ent->driver_data;
1336         struct drm_i915_private *dev_priv;
1337         int ret;
1338
1339         /* Enable nuclear pageflip on ILK+ */
1340         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1341                 driver.driver_features &= ~DRIVER_ATOMIC;
1342
1343         ret = -ENOMEM;
1344         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1345         if (dev_priv)
1346                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1347         if (ret) {
1348                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1349                 goto out_free;
1350         }
1351
1352         dev_priv->drm.pdev = pdev;
1353         dev_priv->drm.dev_private = dev_priv;
1354
1355         ret = pci_enable_device(pdev);
1356         if (ret)
1357                 goto out_fini;
1358
1359         pci_set_drvdata(pdev, &dev_priv->drm);
1360         /*
1361          * Disable the system suspend direct complete optimization, which can
1362          * leave the device suspended skipping the driver's suspend handlers
1363          * if the device was already runtime suspended. This is needed due to
1364          * the difference in our runtime and system suspend sequence and
1365          * becaue the HDA driver may require us to enable the audio power
1366          * domain during system suspend.
1367          */
1368         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1369
1370         ret = i915_driver_init_early(dev_priv, ent);
1371         if (ret < 0)
1372                 goto out_pci_disable;
1373
1374         intel_runtime_pm_get(dev_priv);
1375
1376         ret = i915_driver_init_mmio(dev_priv);
1377         if (ret < 0)
1378                 goto out_runtime_pm_put;
1379
1380         ret = i915_driver_init_hw(dev_priv);
1381         if (ret < 0)
1382                 goto out_cleanup_mmio;
1383
1384         /*
1385          * TODO: move the vblank init and parts of modeset init steps into one
1386          * of the i915_driver_init_/i915_driver_register functions according
1387          * to the role/effect of the given init step.
1388          */
1389         if (INTEL_INFO(dev_priv)->num_pipes) {
1390                 ret = drm_vblank_init(&dev_priv->drm,
1391                                       INTEL_INFO(dev_priv)->num_pipes);
1392                 if (ret)
1393                         goto out_cleanup_hw;
1394         }
1395
1396         ret = i915_load_modeset_init(&dev_priv->drm);
1397         if (ret < 0)
1398                 goto out_cleanup_hw;
1399
1400         i915_driver_register(dev_priv);
1401
1402         intel_runtime_pm_enable(dev_priv);
1403
1404         intel_init_ipc(dev_priv);
1405
1406         intel_runtime_pm_put(dev_priv);
1407
1408         i915_welcome_messages(dev_priv);
1409
1410         return 0;
1411
1412 out_cleanup_hw:
1413         i915_driver_cleanup_hw(dev_priv);
1414 out_cleanup_mmio:
1415         i915_driver_cleanup_mmio(dev_priv);
1416 out_runtime_pm_put:
1417         intel_runtime_pm_put(dev_priv);
1418         i915_driver_cleanup_early(dev_priv);
1419 out_pci_disable:
1420         pci_disable_device(pdev);
1421 out_fini:
1422         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1423         drm_dev_fini(&dev_priv->drm);
1424 out_free:
1425         kfree(dev_priv);
1426         return ret;
1427 }
1428
1429 void i915_driver_unload(struct drm_device *dev)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(dev);
1432         struct pci_dev *pdev = dev_priv->drm.pdev;
1433
1434         i915_driver_unregister(dev_priv);
1435
1436         if (i915_gem_suspend(dev_priv))
1437                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1438
1439         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1440
1441         drm_atomic_helper_shutdown(dev);
1442
1443         intel_gvt_cleanup(dev_priv);
1444
1445         intel_modeset_cleanup(dev);
1446
1447         intel_bios_cleanup(dev_priv);
1448
1449         vga_switcheroo_unregister_client(pdev);
1450         vga_client_register(pdev, NULL, NULL, NULL);
1451
1452         intel_csr_ucode_fini(dev_priv);
1453
1454         /* Free error state after interrupts are fully disabled. */
1455         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1456         i915_reset_error_state(dev_priv);
1457
1458         i915_gem_fini(dev_priv);
1459         intel_uc_fini_fw(dev_priv);
1460         intel_fbc_cleanup_cfb(dev_priv);
1461
1462         intel_power_domains_fini(dev_priv);
1463
1464         i915_driver_cleanup_hw(dev_priv);
1465         i915_driver_cleanup_mmio(dev_priv);
1466
1467         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1468 }
1469
1470 static void i915_driver_release(struct drm_device *dev)
1471 {
1472         struct drm_i915_private *dev_priv = to_i915(dev);
1473
1474         i915_driver_cleanup_early(dev_priv);
1475         drm_dev_fini(&dev_priv->drm);
1476
1477         kfree(dev_priv);
1478 }
1479
1480 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1481 {
1482         struct drm_i915_private *i915 = to_i915(dev);
1483         int ret;
1484
1485         ret = i915_gem_open(i915, file);
1486         if (ret)
1487                 return ret;
1488
1489         return 0;
1490 }
1491
1492 /**
1493  * i915_driver_lastclose - clean up after all DRM clients have exited
1494  * @dev: DRM device
1495  *
1496  * Take care of cleaning up after all DRM clients have exited.  In the
1497  * mode setting case, we want to restore the kernel's initial mode (just
1498  * in case the last client left us in a bad state).
1499  *
1500  * Additionally, in the non-mode setting case, we'll tear down the GTT
1501  * and DMA structures, since the kernel won't be using them, and clea
1502  * up any GEM state.
1503  */
1504 static void i915_driver_lastclose(struct drm_device *dev)
1505 {
1506         intel_fbdev_restore_mode(dev);
1507         vga_switcheroo_process_delayed_switch();
1508 }
1509
1510 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1511 {
1512         struct drm_i915_file_private *file_priv = file->driver_priv;
1513
1514         mutex_lock(&dev->struct_mutex);
1515         i915_gem_context_close(file);
1516         i915_gem_release(dev, file);
1517         mutex_unlock(&dev->struct_mutex);
1518
1519         kfree(file_priv);
1520 }
1521
1522 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1523 {
1524         struct drm_device *dev = &dev_priv->drm;
1525         struct intel_encoder *encoder;
1526
1527         drm_modeset_lock_all(dev);
1528         for_each_intel_encoder(dev, encoder)
1529                 if (encoder->suspend)
1530                         encoder->suspend(encoder);
1531         drm_modeset_unlock_all(dev);
1532 }
1533
1534 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1535                               bool rpm_resume);
1536 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1537
1538 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1539 {
1540 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1541         if (acpi_target_system_state() < ACPI_STATE_S3)
1542                 return true;
1543 #endif
1544         return false;
1545 }
1546
1547 static int i915_drm_suspend(struct drm_device *dev)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(dev);
1550         struct pci_dev *pdev = dev_priv->drm.pdev;
1551         pci_power_t opregion_target_state;
1552         int error;
1553
1554         /* ignore lid events during suspend */
1555         mutex_lock(&dev_priv->modeset_restore_lock);
1556         dev_priv->modeset_restore = MODESET_SUSPENDED;
1557         mutex_unlock(&dev_priv->modeset_restore_lock);
1558
1559         disable_rpm_wakeref_asserts(dev_priv);
1560
1561         /* We do a lot of poking in a lot of registers, make sure they work
1562          * properly. */
1563         intel_display_set_init_power(dev_priv, true);
1564
1565         drm_kms_helper_poll_disable(dev);
1566
1567         pci_save_state(pdev);
1568
1569         error = i915_gem_suspend(dev_priv);
1570         if (error) {
1571                 dev_err(&pdev->dev,
1572                         "GEM idle failed, resume might fail\n");
1573                 goto out;
1574         }
1575
1576         intel_display_suspend(dev);
1577
1578         intel_dp_mst_suspend(dev);
1579
1580         intel_runtime_pm_disable_interrupts(dev_priv);
1581         intel_hpd_cancel_work(dev_priv);
1582
1583         intel_suspend_encoders(dev_priv);
1584
1585         intel_suspend_hw(dev_priv);
1586
1587         i915_gem_suspend_gtt_mappings(dev_priv);
1588
1589         i915_save_state(dev_priv);
1590
1591         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1592         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1593
1594         intel_uncore_suspend(dev_priv);
1595         intel_opregion_unregister(dev_priv);
1596
1597         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1598
1599         dev_priv->suspend_count++;
1600
1601         intel_csr_ucode_suspend(dev_priv);
1602
1603 out:
1604         enable_rpm_wakeref_asserts(dev_priv);
1605
1606         return error;
1607 }
1608
1609 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1610 {
1611         struct drm_i915_private *dev_priv = to_i915(dev);
1612         struct pci_dev *pdev = dev_priv->drm.pdev;
1613         bool fw_csr;
1614         int ret;
1615
1616         disable_rpm_wakeref_asserts(dev_priv);
1617
1618         intel_display_set_init_power(dev_priv, false);
1619
1620         fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
1621                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1622         /*
1623          * In case of firmware assisted context save/restore don't manually
1624          * deinit the power domains. This also means the CSR/DMC firmware will
1625          * stay active, it will power down any HW resources as required and
1626          * also enable deeper system power states that would be blocked if the
1627          * firmware was inactive.
1628          */
1629         if (!fw_csr)
1630                 intel_power_domains_suspend(dev_priv);
1631
1632         ret = 0;
1633         if (IS_GEN9_LP(dev_priv))
1634                 bxt_enable_dc9(dev_priv);
1635         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1636                 hsw_enable_pc8(dev_priv);
1637         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1638                 ret = vlv_suspend_complete(dev_priv);
1639
1640         if (ret) {
1641                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1642                 if (!fw_csr)
1643                         intel_power_domains_init_hw(dev_priv, true);
1644
1645                 goto out;
1646         }
1647
1648         pci_disable_device(pdev);
1649         /*
1650          * During hibernation on some platforms the BIOS may try to access
1651          * the device even though it's already in D3 and hang the machine. So
1652          * leave the device in D0 on those platforms and hope the BIOS will
1653          * power down the device properly. The issue was seen on multiple old
1654          * GENs with different BIOS vendors, so having an explicit blacklist
1655          * is inpractical; apply the workaround on everything pre GEN6. The
1656          * platforms where the issue was seen:
1657          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1658          * Fujitsu FSC S7110
1659          * Acer Aspire 1830T
1660          */
1661         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1662                 pci_set_power_state(pdev, PCI_D3hot);
1663
1664         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1665
1666 out:
1667         enable_rpm_wakeref_asserts(dev_priv);
1668
1669         return ret;
1670 }
1671
1672 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1673 {
1674         int error;
1675
1676         if (!dev) {
1677                 DRM_ERROR("dev: %p\n", dev);
1678                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1679                 return -ENODEV;
1680         }
1681
1682         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1683                          state.event != PM_EVENT_FREEZE))
1684                 return -EINVAL;
1685
1686         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1687                 return 0;
1688
1689         error = i915_drm_suspend(dev);
1690         if (error)
1691                 return error;
1692
1693         return i915_drm_suspend_late(dev, false);
1694 }
1695
1696 static int i915_drm_resume(struct drm_device *dev)
1697 {
1698         struct drm_i915_private *dev_priv = to_i915(dev);
1699         int ret;
1700
1701         disable_rpm_wakeref_asserts(dev_priv);
1702         intel_sanitize_gt_powersave(dev_priv);
1703
1704         ret = i915_ggtt_enable_hw(dev_priv);
1705         if (ret)
1706                 DRM_ERROR("failed to re-enable GGTT\n");
1707
1708         intel_csr_ucode_resume(dev_priv);
1709
1710         i915_restore_state(dev_priv);
1711         intel_pps_unlock_regs_wa(dev_priv);
1712         intel_opregion_setup(dev_priv);
1713
1714         intel_init_pch_refclk(dev_priv);
1715
1716         /*
1717          * Interrupts have to be enabled before any batches are run. If not the
1718          * GPU will hang. i915_gem_init_hw() will initiate batches to
1719          * update/restore the context.
1720          *
1721          * drm_mode_config_reset() needs AUX interrupts.
1722          *
1723          * Modeset enabling in intel_modeset_init_hw() also needs working
1724          * interrupts.
1725          */
1726         intel_runtime_pm_enable_interrupts(dev_priv);
1727
1728         drm_mode_config_reset(dev);
1729
1730         i915_gem_resume(dev_priv);
1731
1732         intel_modeset_init_hw(dev);
1733         intel_init_clock_gating(dev_priv);
1734
1735         spin_lock_irq(&dev_priv->irq_lock);
1736         if (dev_priv->display.hpd_irq_setup)
1737                 dev_priv->display.hpd_irq_setup(dev_priv);
1738         spin_unlock_irq(&dev_priv->irq_lock);
1739
1740         intel_dp_mst_resume(dev);
1741
1742         intel_display_resume(dev);
1743
1744         drm_kms_helper_poll_enable(dev);
1745
1746         /*
1747          * ... but also need to make sure that hotplug processing
1748          * doesn't cause havoc. Like in the driver load code we don't
1749          * bother with the tiny race here where we might loose hotplug
1750          * notifications.
1751          * */
1752         intel_hpd_init(dev_priv);
1753
1754         intel_opregion_register(dev_priv);
1755
1756         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1757
1758         mutex_lock(&dev_priv->modeset_restore_lock);
1759         dev_priv->modeset_restore = MODESET_DONE;
1760         mutex_unlock(&dev_priv->modeset_restore_lock);
1761
1762         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1763
1764         enable_rpm_wakeref_asserts(dev_priv);
1765
1766         return 0;
1767 }
1768
1769 static int i915_drm_resume_early(struct drm_device *dev)
1770 {
1771         struct drm_i915_private *dev_priv = to_i915(dev);
1772         struct pci_dev *pdev = dev_priv->drm.pdev;
1773         int ret;
1774
1775         /*
1776          * We have a resume ordering issue with the snd-hda driver also
1777          * requiring our device to be power up. Due to the lack of a
1778          * parent/child relationship we currently solve this with an early
1779          * resume hook.
1780          *
1781          * FIXME: This should be solved with a special hdmi sink device or
1782          * similar so that power domains can be employed.
1783          */
1784
1785         /*
1786          * Note that we need to set the power state explicitly, since we
1787          * powered off the device during freeze and the PCI core won't power
1788          * it back up for us during thaw. Powering off the device during
1789          * freeze is not a hard requirement though, and during the
1790          * suspend/resume phases the PCI core makes sure we get here with the
1791          * device powered on. So in case we change our freeze logic and keep
1792          * the device powered we can also remove the following set power state
1793          * call.
1794          */
1795         ret = pci_set_power_state(pdev, PCI_D0);
1796         if (ret) {
1797                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1798                 goto out;
1799         }
1800
1801         /*
1802          * Note that pci_enable_device() first enables any parent bridge
1803          * device and only then sets the power state for this device. The
1804          * bridge enabling is a nop though, since bridge devices are resumed
1805          * first. The order of enabling power and enabling the device is
1806          * imposed by the PCI core as described above, so here we preserve the
1807          * same order for the freeze/thaw phases.
1808          *
1809          * TODO: eventually we should remove pci_disable_device() /
1810          * pci_enable_enable_device() from suspend/resume. Due to how they
1811          * depend on the device enable refcount we can't anyway depend on them
1812          * disabling/enabling the device.
1813          */
1814         if (pci_enable_device(pdev)) {
1815                 ret = -EIO;
1816                 goto out;
1817         }
1818
1819         pci_set_master(pdev);
1820
1821         disable_rpm_wakeref_asserts(dev_priv);
1822
1823         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1824                 ret = vlv_resume_prepare(dev_priv, false);
1825         if (ret)
1826                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1827                           ret);
1828
1829         intel_uncore_resume_early(dev_priv);
1830
1831         if (IS_GEN9_LP(dev_priv)) {
1832                 if (!dev_priv->suspended_to_idle)
1833                         gen9_sanitize_dc_state(dev_priv);
1834                 bxt_disable_dc9(dev_priv);
1835         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1836                 hsw_disable_pc8(dev_priv);
1837         }
1838
1839         intel_uncore_sanitize(dev_priv);
1840
1841         if (IS_GEN9_LP(dev_priv) ||
1842             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1843                 intel_power_domains_init_hw(dev_priv, true);
1844         else
1845                 intel_display_set_init_power(dev_priv, true);
1846
1847         i915_gem_sanitize(dev_priv);
1848
1849         enable_rpm_wakeref_asserts(dev_priv);
1850
1851 out:
1852         dev_priv->suspended_to_idle = false;
1853
1854         return ret;
1855 }
1856
1857 static int i915_resume_switcheroo(struct drm_device *dev)
1858 {
1859         int ret;
1860
1861         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1862                 return 0;
1863
1864         ret = i915_drm_resume_early(dev);
1865         if (ret)
1866                 return ret;
1867
1868         return i915_drm_resume(dev);
1869 }
1870
1871 /**
1872  * i915_reset - reset chip after a hang
1873  * @i915: #drm_i915_private to reset
1874  * @flags: Instructions
1875  *
1876  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1877  * on failure.
1878  *
1879  * Caller must hold the struct_mutex.
1880  *
1881  * Procedure is fairly simple:
1882  *   - reset the chip using the reset reg
1883  *   - re-init context state
1884  *   - re-init hardware status page
1885  *   - re-init ring buffer
1886  *   - re-init interrupt state
1887  *   - re-init display
1888  */
1889 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1890 {
1891         struct i915_gpu_error *error = &i915->gpu_error;
1892         int ret;
1893         int i;
1894
1895         might_sleep();
1896         lockdep_assert_held(&i915->drm.struct_mutex);
1897         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1898
1899         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1900                 return;
1901
1902         /* Clear any previous failed attempts at recovery. Time to try again. */
1903         if (!i915_gem_unset_wedged(i915))
1904                 goto wakeup;
1905
1906         if (!(flags & I915_RESET_QUIET))
1907                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1908         error->reset_count++;
1909
1910         disable_irq(i915->drm.irq);
1911         ret = i915_gem_reset_prepare(i915);
1912         if (ret) {
1913                 dev_err(i915->drm.dev, "GPU recovery failed\n");
1914                 goto taint;
1915         }
1916
1917         if (!intel_has_gpu_reset(i915)) {
1918                 if (i915_modparams.reset)
1919                         dev_err(i915->drm.dev, "GPU reset not supported\n");
1920                 else
1921                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1922                 goto error;
1923         }
1924
1925         for (i = 0; i < 3; i++) {
1926                 ret = intel_gpu_reset(i915, ALL_ENGINES);
1927                 if (ret == 0)
1928                         break;
1929
1930                 msleep(100);
1931         }
1932         if (ret) {
1933                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1934                 goto taint;
1935         }
1936
1937         /* Ok, now get things going again... */
1938
1939         /*
1940          * Everything depends on having the GTT running, so we need to start
1941          * there.
1942          */
1943         ret = i915_ggtt_enable_hw(i915);
1944         if (ret) {
1945                 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1946                           ret);
1947                 goto error;
1948         }
1949
1950         i915_gem_reset(i915);
1951         intel_overlay_reset(i915);
1952
1953         /*
1954          * Next we need to restore the context, but we don't use those
1955          * yet either...
1956          *
1957          * Ring buffer needs to be re-initialized in the KMS case, or if X
1958          * was running at the time of the reset (i.e. we weren't VT
1959          * switched away).
1960          */
1961         ret = i915_gem_init_hw(i915);
1962         if (ret) {
1963                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1964                           ret);
1965                 goto error;
1966         }
1967
1968         i915_queue_hangcheck(i915);
1969
1970 finish:
1971         i915_gem_reset_finish(i915);
1972         enable_irq(i915->drm.irq);
1973
1974 wakeup:
1975         clear_bit(I915_RESET_HANDOFF, &error->flags);
1976         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1977         return;
1978
1979 taint:
1980         /*
1981          * History tells us that if we cannot reset the GPU now, we
1982          * never will. This then impacts everything that is run
1983          * subsequently. On failing the reset, we mark the driver
1984          * as wedged, preventing further execution on the GPU.
1985          * We also want to go one step further and add a taint to the
1986          * kernel so that any subsequent faults can be traced back to
1987          * this failure. This is important for CI, where if the
1988          * GPU/driver fails we would like to reboot and restart testing
1989          * rather than continue on into oblivion. For everyone else,
1990          * the system should still plod along, but they have been warned!
1991          */
1992         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1993 error:
1994         i915_gem_set_wedged(i915);
1995         i915_retire_requests(i915);
1996         intel_gpu_reset(i915, ALL_ENGINES);
1997         goto finish;
1998 }
1999
2000 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2001                                         struct intel_engine_cs *engine)
2002 {
2003         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2004 }
2005
2006 /**
2007  * i915_reset_engine - reset GPU engine to recover from a hang
2008  * @engine: engine to reset
2009  * @flags: options
2010  *
2011  * Reset a specific GPU engine. Useful if a hang is detected.
2012  * Returns zero on successful reset or otherwise an error code.
2013  *
2014  * Procedure is:
2015  *  - identifies the request that caused the hang and it is dropped
2016  *  - reset engine (which will force the engine to idle)
2017  *  - re-init/configure engine
2018  */
2019 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
2020 {
2021         struct i915_gpu_error *error = &engine->i915->gpu_error;
2022         struct i915_request *active_request;
2023         int ret;
2024
2025         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2026
2027         active_request = i915_gem_reset_prepare_engine(engine);
2028         if (IS_ERR_OR_NULL(active_request)) {
2029                 /* Either the previous reset failed, or we pardon the reset. */
2030                 ret = PTR_ERR(active_request);
2031                 goto out;
2032         }
2033
2034         if (!(flags & I915_RESET_QUIET)) {
2035                 dev_notice(engine->i915->drm.dev,
2036                            "Resetting %s after gpu hang\n", engine->name);
2037         }
2038         error->reset_engine_count[engine->id]++;
2039
2040         if (!engine->i915->guc.execbuf_client)
2041                 ret = intel_gt_reset_engine(engine->i915, engine);
2042         else
2043                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2044         if (ret) {
2045                 /* If we fail here, we expect to fallback to a global reset */
2046                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2047                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2048                                  engine->name, ret);
2049                 goto out;
2050         }
2051
2052         /*
2053          * The request that caused the hang is stuck on elsp, we know the
2054          * active request and can drop it, adjust head to skip the offending
2055          * request to resume executing remaining requests in the queue.
2056          */
2057         i915_gem_reset_engine(engine, active_request);
2058
2059         /*
2060          * The engine and its registers (and workarounds in case of render)
2061          * have been reset to their default values. Follow the init_ring
2062          * process to program RING_MODE, HWSP and re-enable submission.
2063          */
2064         ret = engine->init_hw(engine);
2065         if (ret)
2066                 goto out;
2067
2068 out:
2069         i915_gem_reset_finish_engine(engine);
2070         return ret;
2071 }
2072
2073 static int i915_pm_suspend(struct device *kdev)
2074 {
2075         struct pci_dev *pdev = to_pci_dev(kdev);
2076         struct drm_device *dev = pci_get_drvdata(pdev);
2077
2078         if (!dev) {
2079                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2080                 return -ENODEV;
2081         }
2082
2083         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2084                 return 0;
2085
2086         return i915_drm_suspend(dev);
2087 }
2088
2089 static int i915_pm_suspend_late(struct device *kdev)
2090 {
2091         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2092
2093         /*
2094          * We have a suspend ordering issue with the snd-hda driver also
2095          * requiring our device to be power up. Due to the lack of a
2096          * parent/child relationship we currently solve this with an late
2097          * suspend hook.
2098          *
2099          * FIXME: This should be solved with a special hdmi sink device or
2100          * similar so that power domains can be employed.
2101          */
2102         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2103                 return 0;
2104
2105         return i915_drm_suspend_late(dev, false);
2106 }
2107
2108 static int i915_pm_poweroff_late(struct device *kdev)
2109 {
2110         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2111
2112         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2113                 return 0;
2114
2115         return i915_drm_suspend_late(dev, true);
2116 }
2117
2118 static int i915_pm_resume_early(struct device *kdev)
2119 {
2120         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2121
2122         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2123                 return 0;
2124
2125         return i915_drm_resume_early(dev);
2126 }
2127
2128 static int i915_pm_resume(struct device *kdev)
2129 {
2130         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2131
2132         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2133                 return 0;
2134
2135         return i915_drm_resume(dev);
2136 }
2137
2138 /* freeze: before creating the hibernation_image */
2139 static int i915_pm_freeze(struct device *kdev)
2140 {
2141         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2142         int ret;
2143
2144         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2145                 ret = i915_drm_suspend(dev);
2146                 if (ret)
2147                         return ret;
2148         }
2149
2150         ret = i915_gem_freeze(kdev_to_i915(kdev));
2151         if (ret)
2152                 return ret;
2153
2154         return 0;
2155 }
2156
2157 static int i915_pm_freeze_late(struct device *kdev)
2158 {
2159         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2160         int ret;
2161
2162         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2163                 ret = i915_drm_suspend_late(dev, true);
2164                 if (ret)
2165                         return ret;
2166         }
2167
2168         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2169         if (ret)
2170                 return ret;
2171
2172         return 0;
2173 }
2174
2175 /* thaw: called after creating the hibernation image, but before turning off. */
2176 static int i915_pm_thaw_early(struct device *kdev)
2177 {
2178         return i915_pm_resume_early(kdev);
2179 }
2180
2181 static int i915_pm_thaw(struct device *kdev)
2182 {
2183         return i915_pm_resume(kdev);
2184 }
2185
2186 /* restore: called after loading the hibernation image. */
2187 static int i915_pm_restore_early(struct device *kdev)
2188 {
2189         return i915_pm_resume_early(kdev);
2190 }
2191
2192 static int i915_pm_restore(struct device *kdev)
2193 {
2194         return i915_pm_resume(kdev);
2195 }
2196
2197 /*
2198  * Save all Gunit registers that may be lost after a D3 and a subsequent
2199  * S0i[R123] transition. The list of registers needing a save/restore is
2200  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2201  * registers in the following way:
2202  * - Driver: saved/restored by the driver
2203  * - Punit : saved/restored by the Punit firmware
2204  * - No, w/o marking: no need to save/restore, since the register is R/O or
2205  *                    used internally by the HW in a way that doesn't depend
2206  *                    keeping the content across a suspend/resume.
2207  * - Debug : used for debugging
2208  *
2209  * We save/restore all registers marked with 'Driver', with the following
2210  * exceptions:
2211  * - Registers out of use, including also registers marked with 'Debug'.
2212  *   These have no effect on the driver's operation, so we don't save/restore
2213  *   them to reduce the overhead.
2214  * - Registers that are fully setup by an initialization function called from
2215  *   the resume path. For example many clock gating and RPS/RC6 registers.
2216  * - Registers that provide the right functionality with their reset defaults.
2217  *
2218  * TODO: Except for registers that based on the above 3 criteria can be safely
2219  * ignored, we save/restore all others, practically treating the HW context as
2220  * a black-box for the driver. Further investigation is needed to reduce the
2221  * saved/restored registers even further, by following the same 3 criteria.
2222  */
2223 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2224 {
2225         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2226         int i;
2227
2228         /* GAM 0x4000-0x4770 */
2229         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2230         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2231         s->arb_mode             = I915_READ(ARB_MODE);
2232         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2233         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2234
2235         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2236                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2237
2238         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2239         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2240
2241         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2242         s->ecochk               = I915_READ(GAM_ECOCHK);
2243         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2244         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2245
2246         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2247
2248         /* MBC 0x9024-0x91D0, 0x8500 */
2249         s->g3dctl               = I915_READ(VLV_G3DCTL);
2250         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2251         s->mbctl                = I915_READ(GEN6_MBCTL);
2252
2253         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2254         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2255         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2256         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2257         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2258         s->rstctl               = I915_READ(GEN6_RSTCTL);
2259         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2260
2261         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2262         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2263         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2264         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2265         s->ecobus               = I915_READ(ECOBUS);
2266         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2267         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2268         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2269         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2270         s->rcedata              = I915_READ(VLV_RCEDATA);
2271         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2272
2273         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2274         s->gt_imr               = I915_READ(GTIMR);
2275         s->gt_ier               = I915_READ(GTIER);
2276         s->pm_imr               = I915_READ(GEN6_PMIMR);
2277         s->pm_ier               = I915_READ(GEN6_PMIER);
2278
2279         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2280                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2281
2282         /* GT SA CZ domain, 0x100000-0x138124 */
2283         s->tilectl              = I915_READ(TILECTL);
2284         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2285         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2286         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2287         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2288
2289         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2290         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2291         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2292         s->pcbr                 = I915_READ(VLV_PCBR);
2293         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2294
2295         /*
2296          * Not saving any of:
2297          * DFT,         0x9800-0x9EC0
2298          * SARB,        0xB000-0xB1FC
2299          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2300          * PCI CFG
2301          */
2302 }
2303
2304 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2305 {
2306         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2307         u32 val;
2308         int i;
2309
2310         /* GAM 0x4000-0x4770 */
2311         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2312         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2313         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2314         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2315         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2316
2317         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2318                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2319
2320         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2321         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2322
2323         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2324         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2325         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2326         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2327
2328         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2329
2330         /* MBC 0x9024-0x91D0, 0x8500 */
2331         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2332         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2333         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2334
2335         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2336         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2337         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2338         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2339         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2340         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2341         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2342
2343         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2344         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2345         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2346         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2347         I915_WRITE(ECOBUS,              s->ecobus);
2348         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2349         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2350         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2351         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2352         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2353         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2354
2355         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2356         I915_WRITE(GTIMR,               s->gt_imr);
2357         I915_WRITE(GTIER,               s->gt_ier);
2358         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2359         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2360
2361         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2362                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2363
2364         /* GT SA CZ domain, 0x100000-0x138124 */
2365         I915_WRITE(TILECTL,                     s->tilectl);
2366         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2367         /*
2368          * Preserve the GT allow wake and GFX force clock bit, they are not
2369          * be restored, as they are used to control the s0ix suspend/resume
2370          * sequence by the caller.
2371          */
2372         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2373         val &= VLV_GTLC_ALLOWWAKEREQ;
2374         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2375         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2376
2377         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2378         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2379         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2380         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2381
2382         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2383
2384         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2385         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2386         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2387         I915_WRITE(VLV_PCBR,                    s->pcbr);
2388         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2389 }
2390
2391 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2392                                   u32 mask, u32 val)
2393 {
2394         /* The HW does not like us polling for PW_STATUS frequently, so
2395          * use the sleeping loop rather than risk the busy spin within
2396          * intel_wait_for_register().
2397          *
2398          * Transitioning between RC6 states should be at most 2ms (see
2399          * valleyview_enable_rps) so use a 3ms timeout.
2400          */
2401         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2402                         3);
2403 }
2404
2405 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2406 {
2407         u32 val;
2408         int err;
2409
2410         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2411         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2412         if (force_on)
2413                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2414         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2415
2416         if (!force_on)
2417                 return 0;
2418
2419         err = intel_wait_for_register(dev_priv,
2420                                       VLV_GTLC_SURVIVABILITY_REG,
2421                                       VLV_GFX_CLK_STATUS_BIT,
2422                                       VLV_GFX_CLK_STATUS_BIT,
2423                                       20);
2424         if (err)
2425                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2426                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2427
2428         return err;
2429 }
2430
2431 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2432 {
2433         u32 mask;
2434         u32 val;
2435         int err;
2436
2437         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2438         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2439         if (allow)
2440                 val |= VLV_GTLC_ALLOWWAKEREQ;
2441         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2442         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2443
2444         mask = VLV_GTLC_ALLOWWAKEACK;
2445         val = allow ? mask : 0;
2446
2447         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2448         if (err)
2449                 DRM_ERROR("timeout disabling GT waking\n");
2450
2451         return err;
2452 }
2453
2454 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2455                                   bool wait_for_on)
2456 {
2457         u32 mask;
2458         u32 val;
2459
2460         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2461         val = wait_for_on ? mask : 0;
2462
2463         /*
2464          * RC6 transitioning can be delayed up to 2 msec (see
2465          * valleyview_enable_rps), use 3 msec for safety.
2466          */
2467         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2468                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2469                           onoff(wait_for_on));
2470 }
2471
2472 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2473 {
2474         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2475                 return;
2476
2477         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2478         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2479 }
2480
2481 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2482 {
2483         u32 mask;
2484         int err;
2485
2486         /*
2487          * Bspec defines the following GT well on flags as debug only, so
2488          * don't treat them as hard failures.
2489          */
2490         vlv_wait_for_gt_wells(dev_priv, false);
2491
2492         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2493         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2494
2495         vlv_check_no_gt_access(dev_priv);
2496
2497         err = vlv_force_gfx_clock(dev_priv, true);
2498         if (err)
2499                 goto err1;
2500
2501         err = vlv_allow_gt_wake(dev_priv, false);
2502         if (err)
2503                 goto err2;
2504
2505         if (!IS_CHERRYVIEW(dev_priv))
2506                 vlv_save_gunit_s0ix_state(dev_priv);
2507
2508         err = vlv_force_gfx_clock(dev_priv, false);
2509         if (err)
2510                 goto err2;
2511
2512         return 0;
2513
2514 err2:
2515         /* For safety always re-enable waking and disable gfx clock forcing */
2516         vlv_allow_gt_wake(dev_priv, true);
2517 err1:
2518         vlv_force_gfx_clock(dev_priv, false);
2519
2520         return err;
2521 }
2522
2523 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2524                                 bool rpm_resume)
2525 {
2526         int err;
2527         int ret;
2528
2529         /*
2530          * If any of the steps fail just try to continue, that's the best we
2531          * can do at this point. Return the first error code (which will also
2532          * leave RPM permanently disabled).
2533          */
2534         ret = vlv_force_gfx_clock(dev_priv, true);
2535
2536         if (!IS_CHERRYVIEW(dev_priv))
2537                 vlv_restore_gunit_s0ix_state(dev_priv);
2538
2539         err = vlv_allow_gt_wake(dev_priv, true);
2540         if (!ret)
2541                 ret = err;
2542
2543         err = vlv_force_gfx_clock(dev_priv, false);
2544         if (!ret)
2545                 ret = err;
2546
2547         vlv_check_no_gt_access(dev_priv);
2548
2549         if (rpm_resume)
2550                 intel_init_clock_gating(dev_priv);
2551
2552         return ret;
2553 }
2554
2555 static int intel_runtime_suspend(struct device *kdev)
2556 {
2557         struct pci_dev *pdev = to_pci_dev(kdev);
2558         struct drm_device *dev = pci_get_drvdata(pdev);
2559         struct drm_i915_private *dev_priv = to_i915(dev);
2560         int ret;
2561
2562         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2563                 return -ENODEV;
2564
2565         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2566                 return -ENODEV;
2567
2568         DRM_DEBUG_KMS("Suspending device\n");
2569
2570         disable_rpm_wakeref_asserts(dev_priv);
2571
2572         /*
2573          * We are safe here against re-faults, since the fault handler takes
2574          * an RPM reference.
2575          */
2576         i915_gem_runtime_suspend(dev_priv);
2577
2578         intel_uc_suspend(dev_priv);
2579
2580         intel_runtime_pm_disable_interrupts(dev_priv);
2581
2582         intel_uncore_suspend(dev_priv);
2583
2584         ret = 0;
2585         if (IS_GEN9_LP(dev_priv)) {
2586                 bxt_display_core_uninit(dev_priv);
2587                 bxt_enable_dc9(dev_priv);
2588         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2589                 hsw_enable_pc8(dev_priv);
2590         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2591                 ret = vlv_suspend_complete(dev_priv);
2592         }
2593
2594         if (ret) {
2595                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2596                 intel_uncore_runtime_resume(dev_priv);
2597
2598                 intel_runtime_pm_enable_interrupts(dev_priv);
2599
2600                 intel_uc_resume(dev_priv);
2601
2602                 i915_gem_init_swizzling(dev_priv);
2603                 i915_gem_restore_fences(dev_priv);
2604
2605                 enable_rpm_wakeref_asserts(dev_priv);
2606
2607                 return ret;
2608         }
2609
2610         enable_rpm_wakeref_asserts(dev_priv);
2611         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2612
2613         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2614                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2615
2616         dev_priv->runtime_pm.suspended = true;
2617
2618         /*
2619          * FIXME: We really should find a document that references the arguments
2620          * used below!
2621          */
2622         if (IS_BROADWELL(dev_priv)) {
2623                 /*
2624                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2625                  * being detected, and the call we do at intel_runtime_resume()
2626                  * won't be able to restore them. Since PCI_D3hot matches the
2627                  * actual specification and appears to be working, use it.
2628                  */
2629                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2630         } else {
2631                 /*
2632                  * current versions of firmware which depend on this opregion
2633                  * notification have repurposed the D1 definition to mean
2634                  * "runtime suspended" vs. what you would normally expect (D3)
2635                  * to distinguish it from notifications that might be sent via
2636                  * the suspend path.
2637                  */
2638                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2639         }
2640
2641         assert_forcewakes_inactive(dev_priv);
2642
2643         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2644                 intel_hpd_poll_init(dev_priv);
2645
2646         DRM_DEBUG_KMS("Device suspended\n");
2647         return 0;
2648 }
2649
2650 static int intel_runtime_resume(struct device *kdev)
2651 {
2652         struct pci_dev *pdev = to_pci_dev(kdev);
2653         struct drm_device *dev = pci_get_drvdata(pdev);
2654         struct drm_i915_private *dev_priv = to_i915(dev);
2655         int ret = 0;
2656
2657         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2658                 return -ENODEV;
2659
2660         DRM_DEBUG_KMS("Resuming device\n");
2661
2662         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2663         disable_rpm_wakeref_asserts(dev_priv);
2664
2665         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2666         dev_priv->runtime_pm.suspended = false;
2667         if (intel_uncore_unclaimed_mmio(dev_priv))
2668                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2669
2670         if (IS_GEN9_LP(dev_priv)) {
2671                 bxt_disable_dc9(dev_priv);
2672                 bxt_display_core_init(dev_priv, true);
2673                 if (dev_priv->csr.dmc_payload &&
2674                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2675                         gen9_enable_dc5(dev_priv);
2676         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2677                 hsw_disable_pc8(dev_priv);
2678         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2679                 ret = vlv_resume_prepare(dev_priv, true);
2680         }
2681
2682         intel_uncore_runtime_resume(dev_priv);
2683
2684         intel_runtime_pm_enable_interrupts(dev_priv);
2685
2686         intel_uc_resume(dev_priv);
2687
2688         /*
2689          * No point of rolling back things in case of an error, as the best
2690          * we can do is to hope that things will still work (and disable RPM).
2691          */
2692         i915_gem_init_swizzling(dev_priv);
2693         i915_gem_restore_fences(dev_priv);
2694
2695         /*
2696          * On VLV/CHV display interrupts are part of the display
2697          * power well, so hpd is reinitialized from there. For
2698          * everyone else do it here.
2699          */
2700         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2701                 intel_hpd_init(dev_priv);
2702
2703         intel_enable_ipc(dev_priv);
2704
2705         enable_rpm_wakeref_asserts(dev_priv);
2706
2707         if (ret)
2708                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2709         else
2710                 DRM_DEBUG_KMS("Device resumed\n");
2711
2712         return ret;
2713 }
2714
2715 const struct dev_pm_ops i915_pm_ops = {
2716         /*
2717          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2718          * PMSG_RESUME]
2719          */
2720         .suspend = i915_pm_suspend,
2721         .suspend_late = i915_pm_suspend_late,
2722         .resume_early = i915_pm_resume_early,
2723         .resume = i915_pm_resume,
2724
2725         /*
2726          * S4 event handlers
2727          * @freeze, @freeze_late    : called (1) before creating the
2728          *                            hibernation image [PMSG_FREEZE] and
2729          *                            (2) after rebooting, before restoring
2730          *                            the image [PMSG_QUIESCE]
2731          * @thaw, @thaw_early       : called (1) after creating the hibernation
2732          *                            image, before writing it [PMSG_THAW]
2733          *                            and (2) after failing to create or
2734          *                            restore the image [PMSG_RECOVER]
2735          * @poweroff, @poweroff_late: called after writing the hibernation
2736          *                            image, before rebooting [PMSG_HIBERNATE]
2737          * @restore, @restore_early : called after rebooting and restoring the
2738          *                            hibernation image [PMSG_RESTORE]
2739          */
2740         .freeze = i915_pm_freeze,
2741         .freeze_late = i915_pm_freeze_late,
2742         .thaw_early = i915_pm_thaw_early,
2743         .thaw = i915_pm_thaw,
2744         .poweroff = i915_pm_suspend,
2745         .poweroff_late = i915_pm_poweroff_late,
2746         .restore_early = i915_pm_restore_early,
2747         .restore = i915_pm_restore,
2748
2749         /* S0ix (via runtime suspend) event handlers */
2750         .runtime_suspend = intel_runtime_suspend,
2751         .runtime_resume = intel_runtime_resume,
2752 };
2753
2754 static const struct vm_operations_struct i915_gem_vm_ops = {
2755         .fault = i915_gem_fault,
2756         .open = drm_gem_vm_open,
2757         .close = drm_gem_vm_close,
2758 };
2759
2760 static const struct file_operations i915_driver_fops = {
2761         .owner = THIS_MODULE,
2762         .open = drm_open,
2763         .release = drm_release,
2764         .unlocked_ioctl = drm_ioctl,
2765         .mmap = drm_gem_mmap,
2766         .poll = drm_poll,
2767         .read = drm_read,
2768         .compat_ioctl = i915_compat_ioctl,
2769         .llseek = noop_llseek,
2770 };
2771
2772 static int
2773 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2774                           struct drm_file *file)
2775 {
2776         return -ENODEV;
2777 }
2778
2779 static const struct drm_ioctl_desc i915_ioctls[] = {
2780         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2781         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2782         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2783         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2784         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2785         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2786         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2787         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2788         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2789         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2790         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2791         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2792         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2793         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2794         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2795         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2796         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2797         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2798         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2799         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2800         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2801         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2802         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2803         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2804         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2805         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2806         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2807         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2808         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2809         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2810         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2811         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2812         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2813         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2814         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2815         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2816         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2817         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2818         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2819         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2820         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2821         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2822         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2823         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2824         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2825         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2826         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2827         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2828         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2829         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2830         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2831         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2832         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2833         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2834         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2835 };
2836
2837 static struct drm_driver driver = {
2838         /* Don't use MTRRs here; the Xserver or userspace app should
2839          * deal with them for Intel hardware.
2840          */
2841         .driver_features =
2842             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2843             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2844         .release = i915_driver_release,
2845         .open = i915_driver_open,
2846         .lastclose = i915_driver_lastclose,
2847         .postclose = i915_driver_postclose,
2848
2849         .gem_close_object = i915_gem_close_object,
2850         .gem_free_object_unlocked = i915_gem_free_object,
2851         .gem_vm_ops = &i915_gem_vm_ops,
2852
2853         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2854         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2855         .gem_prime_export = i915_gem_prime_export,
2856         .gem_prime_import = i915_gem_prime_import,
2857
2858         .dumb_create = i915_gem_dumb_create,
2859         .dumb_map_offset = i915_gem_mmap_gtt,
2860         .ioctls = i915_ioctls,
2861         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2862         .fops = &i915_driver_fops,
2863         .name = DRIVER_NAME,
2864         .desc = DRIVER_DESC,
2865         .date = DRIVER_DATE,
2866         .major = DRIVER_MAJOR,
2867         .minor = DRIVER_MINOR,
2868         .patchlevel = DRIVER_PATCHLEVEL,
2869 };
2870
2871 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2872 #include "selftests/mock_drm.c"
2873 #endif