drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_query.h"
  53 #include "i915_vgpu.h"
  54 #include "intel_drv.h"
  55 #include "intel_uc.h"
  56
  57 static struct drm_driver driver;
  58
  59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  60 static unsigned int i915_load_fail_count;
  61
  62 bool __i915_inject_load_failure(const char *func, int line)
  63 {
  64         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  65                 return false;
  66
  67         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  68                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  69                          i915_modparams.inject_load_failure, func, line);
  70                 return true;
  71         }
  72
  73         return false;
  74 }
  75 #endif
  76
  77 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  78 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  79                     "providing the dmesg log by booting with drm.debug=0xf"
  80
  81 void
  82 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  83               const char *fmt, ...)
  84 {
  85         static bool shown_bug_once;
  86         struct device *kdev = dev_priv->drm.dev;
  87         bool is_error = level[1] <= KERN_ERR[1];
  88         bool is_debug = level[1] == KERN_DEBUG[1];
  89         struct va_format vaf;
  90         va_list args;
  91
  92         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  93                 return;
  94
  95         va_start(args, fmt);
  96
  97         vaf.fmt = fmt;
  98         vaf.va = &args;
  99
 100         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 101                    __builtin_return_address(0), &vaf);
 102
 103         if (is_error && !shown_bug_once) {
 104                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 105                 shown_bug_once = true;
 106         }
 107
 108         va_end(args);
 109 }
 110
 111 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 112 {
 113 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
 114         return i915_modparams.inject_load_failure &&
 115                i915_load_fail_count == i915_modparams.inject_load_failure;
 116 #else
 117         return false;
 118 #endif
 119 }
 120
 121 #define i915_load_error(dev_priv, fmt, ...)                                  \
 122         __i915_printk(dev_priv,                                              \
 123                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 124                       fmt, ##__VA_ARGS__)
 125
 126 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 127 static enum intel_pch
 128 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 129 {
 130         switch (id) {
 131         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 132                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 133                 WARN_ON(!IS_GEN5(dev_priv));
 134                 return PCH_IBX;
 135         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 136                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 137                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 138                 return PCH_CPT;
 139         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 140                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 141                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 142                 /* PantherPoint is CPT compatible */
 143                 return PCH_CPT;
 144         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 145                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 146                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 147                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 148                 return PCH_LPT;
 149         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 150                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 151                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 152                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 153                 return PCH_LPT;
 154         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 155                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 156                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 157                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 158                 /* WildcatPoint is LPT compatible */
 159                 return PCH_LPT;
 160         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 161                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 162                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 163                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 164                 /* WildcatPoint is LPT compatible */
 165                 return PCH_LPT;
 166         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 167                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 168                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 169                 return PCH_SPT;
 170         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 171                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 172                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 173                 return PCH_SPT;
 174         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 175                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 176                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 177                         !IS_COFFEELAKE(dev_priv));
 178                 return PCH_KBP;
 179         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 180                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 181                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 182                 return PCH_CNP;
 183         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 184                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 185                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 186                 return PCH_CNP;
 187         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 188                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 189                 WARN_ON(!IS_ICELAKE(dev_priv));
 190                 return PCH_ICP;
 191         default:
 192                 return PCH_NONE;
 193         }
 194 }
 195
 196 static bool intel_is_virt_pch(unsigned short id,
 197                               unsigned short svendor, unsigned short sdevice)
 198 {
 199         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 200                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 201                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 202                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 203                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 204 }
 205
 206 static unsigned short
 207 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 208 {
 209         unsigned short id = 0;
 210
 211         /*
 212          * In a virtualized passthrough environment we can be in a
 213          * setup where the ISA bridge is not able to be passed through.
 214          * In this case, a south bridge can be emulated and we have to
 215          * make an educated guess as to which PCH is really there.
 216          */
 217
 218         if (IS_GEN5(dev_priv))
 219                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 220         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 221                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 222         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 223                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 224         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 225                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 226         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 227                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 228         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 229                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 230
 231         if (id)
 232                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 233         else
 234                 DRM_DEBUG_KMS("Assuming no PCH\n");
 235
 236         return id;
 237 }
 238
 239 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 240 {
 241         struct pci_dev *pch = NULL;
 242
 243         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 244          * (which really amounts to a PCH but no South Display).
 245          */
 246         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 247                 dev_priv->pch_type = PCH_NOP;
 248                 return;
 249         }
 250
 251         /*
 252          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 253          * make graphics device passthrough work easy for VMM, that only
 254          * need to expose ISA bridge to let driver know the real hardware
 255          * underneath. This is a requirement from virtualization team.
 256          *
 257          * In some virtualized environments (e.g. XEN), there is irrelevant
 258          * ISA bridge in the system. To work reliably, we should scan trhough
 259          * all the ISA bridge devices and check for the first match, instead
 260          * of only checking the first one.
 261          */
 262         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 263                 unsigned short id;
 264                 enum intel_pch pch_type;
 265
 266                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 267                         continue;
 268
 269                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 270
 271                 pch_type = intel_pch_type(dev_priv, id);
 272                 if (pch_type != PCH_NONE) {
 273                         dev_priv->pch_type = pch_type;
 274                         dev_priv->pch_id = id;
 275                         break;
 276                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 277                                          pch->subsystem_device)) {
 278                         id = intel_virt_detect_pch(dev_priv);
 279                         if (id) {
 280                                 pch_type = intel_pch_type(dev_priv, id);
 281                                 if (WARN_ON(pch_type == PCH_NONE))
 282                                         pch_type = PCH_NOP;
 283                         } else {
 284                                 pch_type = PCH_NOP;
 285                         }
 286                         dev_priv->pch_type = pch_type;
 287                         dev_priv->pch_id = id;
 288                         break;
 289                 }
 290         }
 291         if (!pch)
 292                 DRM_DEBUG_KMS("No PCH found.\n");
 293
 294         pci_dev_put(pch);
 295 }
 296
 297 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 298                                struct drm_file *file_priv)
 299 {
 300         struct drm_i915_private *dev_priv = to_i915(dev);
 301         struct pci_dev *pdev = dev_priv->drm.pdev;
 302         drm_i915_getparam_t *param = data;
 303         int value;
 304
 305         switch (param->param) {
 306         case I915_PARAM_IRQ_ACTIVE:
 307         case I915_PARAM_ALLOW_BATCHBUFFER:
 308         case I915_PARAM_LAST_DISPATCH:
 309         case I915_PARAM_HAS_EXEC_CONSTANTS:
 310                 /* Reject all old ums/dri params. */
 311                 return -ENODEV;
 312         case I915_PARAM_CHIPSET_ID:
 313                 value = pdev->device;
 314                 break;
 315         case I915_PARAM_REVISION:
 316                 value = pdev->revision;
 317                 break;
 318         case I915_PARAM_NUM_FENCES_AVAIL:
 319                 value = dev_priv->num_fence_regs;
 320                 break;
 321         case I915_PARAM_HAS_OVERLAY:
 322                 value = dev_priv->overlay ? 1 : 0;
 323                 break;
 324         case I915_PARAM_HAS_BSD:
 325                 value = !!dev_priv->engine[VCS];
 326                 break;
 327         case I915_PARAM_HAS_BLT:
 328                 value = !!dev_priv->engine[BCS];
 329                 break;
 330         case I915_PARAM_HAS_VEBOX:
 331                 value = !!dev_priv->engine[VECS];
 332                 break;
 333         case I915_PARAM_HAS_BSD2:
 334                 value = !!dev_priv->engine[VCS2];
 335                 break;
 336         case I915_PARAM_HAS_LLC:
 337                 value = HAS_LLC(dev_priv);
 338                 break;
 339         case I915_PARAM_HAS_WT:
 340                 value = HAS_WT(dev_priv);
 341                 break;
 342         case I915_PARAM_HAS_ALIASING_PPGTT:
 343                 value = USES_PPGTT(dev_priv);
 344                 break;
 345         case I915_PARAM_HAS_SEMAPHORES:
 346                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 347                 break;
 348         case I915_PARAM_HAS_SECURE_BATCHES:
 349                 value = capable(CAP_SYS_ADMIN);
 350                 break;
 351         case I915_PARAM_CMD_PARSER_VERSION:
 352                 value = i915_cmd_parser_get_version(dev_priv);
 353                 break;
 354         case I915_PARAM_SUBSLICE_TOTAL:
 355                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 356                 if (!value)
 357                         return -ENODEV;
 358                 break;
 359         case I915_PARAM_EU_TOTAL:
 360                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 361                 if (!value)
 362                         return -ENODEV;
 363                 break;
 364         case I915_PARAM_HAS_GPU_RESET:
 365                 value = i915_modparams.enable_hangcheck &&
 366                         intel_has_gpu_reset(dev_priv);
 367                 if (value && intel_has_reset_engine(dev_priv))
 368                         value = 2;
 369                 break;
 370         case I915_PARAM_HAS_RESOURCE_STREAMER:
 371                 value = HAS_RESOURCE_STREAMER(dev_priv);
 372                 break;
 373         case I915_PARAM_HAS_POOLED_EU:
 374                 value = HAS_POOLED_EU(dev_priv);
 375                 break;
 376         case I915_PARAM_MIN_EU_IN_POOL:
 377                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 378                 break;
 379         case I915_PARAM_HUC_STATUS:
 380                 intel_runtime_pm_get(dev_priv);
 381                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 382                 intel_runtime_pm_put(dev_priv);
 383                 break;
 384         case I915_PARAM_MMAP_GTT_VERSION:
 385                 /* Though we've started our numbering from 1, and so class all
 386                  * earlier versions as 0, in effect their value is undefined as
 387                  * the ioctl will report EINVAL for the unknown param!
 388                  */
 389                 value = i915_gem_mmap_gtt_version();
 390                 break;
 391         case I915_PARAM_HAS_SCHEDULER:
 392                 value = dev_priv->caps.scheduler;
 393                 break;
 394
 395         case I915_PARAM_MMAP_VERSION:
 396                 /* Remember to bump this if the version changes! */
 397         case I915_PARAM_HAS_GEM:
 398         case I915_PARAM_HAS_PAGEFLIPPING:
 399         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 400         case I915_PARAM_HAS_RELAXED_FENCING:
 401         case I915_PARAM_HAS_COHERENT_RINGS:
 402         case I915_PARAM_HAS_RELAXED_DELTA:
 403         case I915_PARAM_HAS_GEN7_SOL_RESET:
 404         case I915_PARAM_HAS_WAIT_TIMEOUT:
 405         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 406         case I915_PARAM_HAS_PINNED_BATCHES:
 407         case I915_PARAM_HAS_EXEC_NO_RELOC:
 408         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 409         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 410         case I915_PARAM_HAS_EXEC_SOFTPIN:
 411         case I915_PARAM_HAS_EXEC_ASYNC:
 412         case I915_PARAM_HAS_EXEC_FENCE:
 413         case I915_PARAM_HAS_EXEC_CAPTURE:
 414         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 415         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 416                 /* For the time being all of these are always true;
 417                  * if some supported hardware does not have one of these
 418                  * features this value needs to be provided from
 419                  * INTEL_INFO(), a feature macro, or similar.
 420                  */
 421                 value = 1;
 422                 break;
 423         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 424                 value = intel_engines_has_context_isolation(dev_priv);
 425                 break;
 426         case I915_PARAM_SLICE_MASK:
 427                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 428                 if (!value)
 429                         return -ENODEV;
 430                 break;
 431         case I915_PARAM_SUBSLICE_MASK:
 432                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 433                 if (!value)
 434                         return -ENODEV;
 435                 break;
 436         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 437                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 438                 break;
 439         default:
 440                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 441                 return -EINVAL;
 442         }
 443
 444         if (put_user(value, param->value))
 445                 return -EFAULT;
 446
 447         return 0;
 448 }
 449
 450 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 451 {
 452         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 453         if (!dev_priv->bridge_dev) {
 454                 DRM_ERROR("bridge device not found\n");
 455                 return -1;
 456         }
 457         return 0;
 458 }
 459
 460 /* Allocate space for the MCH regs if needed, return nonzero on error */
 461 static int
 462 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 463 {
 464         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 465         u32 temp_lo, temp_hi = 0;
 466         u64 mchbar_addr;
 467         int ret;
 468
 469         if (INTEL_GEN(dev_priv) >= 4)
 470                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 471         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 472         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 473
 474         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 475 #ifdef CONFIG_PNP
 476         if (mchbar_addr &&
 477             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 478                 return 0;
 479 #endif
 480
 481         /* Get some space for it */
 482         dev_priv->mch_res.name = "i915 MCHBAR";
 483         dev_priv->mch_res.flags = IORESOURCE_MEM;
 484         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 485                                      &dev_priv->mch_res,
 486                                      MCHBAR_SIZE, MCHBAR_SIZE,
 487                                      PCIBIOS_MIN_MEM,
 488                                      0, pcibios_align_resource,
 489                                      dev_priv->bridge_dev);
 490         if (ret) {
 491                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 492                 dev_priv->mch_res.start = 0;
 493                 return ret;
 494         }
 495
 496         if (INTEL_GEN(dev_priv) >= 4)
 497                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 498                                        upper_32_bits(dev_priv->mch_res.start));
 499
 500         pci_write_config_dword(dev_priv->bridge_dev, reg,
 501                                lower_32_bits(dev_priv->mch_res.start));
 502         return 0;
 503 }
 504
 505 /* Setup MCHBAR if possible, return true if we should disable it again */
 506 static void
 507 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 508 {
 509         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 510         u32 temp;
 511         bool enabled;
 512
 513         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 514                 return;
 515
 516         dev_priv->mchbar_need_disable = false;
 517
 518         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 519                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 520                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 521         } else {
 522                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 523                 enabled = temp & 1;
 524         }
 525
 526         /* If it's already enabled, don't have to do anything */
 527         if (enabled)
 528                 return;
 529
 530         if (intel_alloc_mchbar_resource(dev_priv))
 531                 return;
 532
 533         dev_priv->mchbar_need_disable = true;
 534
 535         /* Space is allocated or reserved, so enable it. */
 536         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 537                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 538                                        temp | DEVEN_MCHBAR_EN);
 539         } else {
 540                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 541                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 542         }
 543 }
 544
 545 static void
 546 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 547 {
 548         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 549
 550         if (dev_priv->mchbar_need_disable) {
 551                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 552                         u32 deven_val;
 553
 554                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 555                                               &deven_val);
 556                         deven_val &= ~DEVEN_MCHBAR_EN;
 557                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 558                                                deven_val);
 559                 } else {
 560                         u32 mchbar_val;
 561
 562                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 563                                               &mchbar_val);
 564                         mchbar_val &= ~1;
 565                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 566                                                mchbar_val);
 567                 }
 568         }
 569
 570         if (dev_priv->mch_res.start)
 571                 release_resource(&dev_priv->mch_res);
 572 }
 573
 574 /* true = enable decode, false = disable decoder */
 575 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 576 {
 577         struct drm_i915_private *dev_priv = cookie;
 578
 579         intel_modeset_vga_set_state(dev_priv, state);
 580         if (state)
 581                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 582                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 583         else
 584                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 585 }
 586
 587 static int i915_resume_switcheroo(struct drm_device *dev);
 588 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 589
 590 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 591 {
 592         struct drm_device *dev = pci_get_drvdata(pdev);
 593         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 594
 595         if (state == VGA_SWITCHEROO_ON) {
 596                 pr_info("switched on\n");
 597                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 598                 /* i915 resume handler doesn't set to D0 */
 599                 pci_set_power_state(pdev, PCI_D0);
 600                 i915_resume_switcheroo(dev);
 601                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 602         } else {
 603                 pr_info("switched off\n");
 604                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 605                 i915_suspend_switcheroo(dev, pmm);
 606                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 607         }
 608 }
 609
 610 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 611 {
 612         struct drm_device *dev = pci_get_drvdata(pdev);
 613
 614         /*
 615          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 616          * locking inversion with the driver load path. And the access here is
 617          * completely racy anyway. So don't bother with locking for now.
 618          */
 619         return dev->open_count == 0;
 620 }
 621
 622 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 623         .set_gpu_state = i915_switcheroo_set_state,
 624         .reprobe = NULL,
 625         .can_switch = i915_switcheroo_can_switch,
 626 };
 627
 628 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 629 {
 630         /* Flush any outstanding unpin_work. */
 631         i915_gem_drain_workqueue(dev_priv);
 632
 633         mutex_lock(&dev_priv->drm.struct_mutex);
 634         intel_uc_fini_hw(dev_priv);
 635         intel_uc_fini(dev_priv);
 636         i915_gem_cleanup_engines(dev_priv);
 637         i915_gem_contexts_fini(dev_priv);
 638         mutex_unlock(&dev_priv->drm.struct_mutex);
 639
 640         intel_uc_fini_misc(dev_priv);
 641         i915_gem_cleanup_userptr(dev_priv);
 642
 643         i915_gem_drain_freed_objects(dev_priv);
 644
 645         WARN_ON(!list_empty(&dev_priv->contexts.list));
 646 }
 647
 648 static int i915_load_modeset_init(struct drm_device *dev)
 649 {
 650         struct drm_i915_private *dev_priv = to_i915(dev);
 651         struct pci_dev *pdev = dev_priv->drm.pdev;
 652         int ret;
 653
 654         if (i915_inject_load_failure())
 655                 return -ENODEV;
 656
 657         intel_bios_init(dev_priv);
 658
 659         /* If we have > 1 VGA cards, then we need to arbitrate access
 660          * to the common VGA resources.
 661          *
 662          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 663          * then we do not take part in VGA arbitration and the
 664          * vga_client_register() fails with -ENODEV.
 665          */
 666         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 667         if (ret && ret != -ENODEV)
 668                 goto out;
 669
 670         intel_register_dsm_handler();
 671
 672         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 673         if (ret)
 674                 goto cleanup_vga_client;
 675
 676         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 677         intel_update_rawclk(dev_priv);
 678
 679         intel_power_domains_init_hw(dev_priv, false);
 680
 681         intel_csr_ucode_init(dev_priv);
 682
 683         ret = intel_irq_install(dev_priv);
 684         if (ret)
 685                 goto cleanup_csr;
 686
 687         intel_setup_gmbus(dev_priv);
 688
 689         /* Important: The output setup functions called by modeset_init need
 690          * working irqs for e.g. gmbus and dp aux transfers. */
 691         ret = intel_modeset_init(dev);
 692         if (ret)
 693                 goto cleanup_irq;
 694
 695         intel_uc_init_fw(dev_priv);
 696
 697         ret = i915_gem_init(dev_priv);
 698         if (ret)
 699                 goto cleanup_uc;
 700
 701         intel_setup_overlay(dev_priv);
 702
 703         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 704                 return 0;
 705
 706         ret = intel_fbdev_init(dev);
 707         if (ret)
 708                 goto cleanup_gem;
 709
 710         /* Only enable hotplug handling once the fbdev is fully set up. */
 711         intel_hpd_init(dev_priv);
 712
 713         return 0;
 714
 715 cleanup_gem:
 716         if (i915_gem_suspend(dev_priv))
 717                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 718         i915_gem_fini(dev_priv);
 719 cleanup_uc:
 720         intel_uc_fini_fw(dev_priv);
 721 cleanup_irq:
 722         drm_irq_uninstall(dev);
 723         intel_teardown_gmbus(dev_priv);
 724 cleanup_csr:
 725         intel_csr_ucode_fini(dev_priv);
 726         intel_power_domains_fini(dev_priv);
 727         vga_switcheroo_unregister_client(pdev);
 728 cleanup_vga_client:
 729         vga_client_register(pdev, NULL, NULL, NULL);
 730 out:
 731         return ret;
 732 }
 733
 734 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 735 {
 736         struct apertures_struct *ap;
 737         struct pci_dev *pdev = dev_priv->drm.pdev;
 738         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 739         bool primary;
 740         int ret;
 741
 742         ap = alloc_apertures(1);
 743         if (!ap)
 744                 return -ENOMEM;
 745
 746         ap->ranges[0].base = ggtt->gmadr.start;
 747         ap->ranges[0].size = ggtt->mappable_end;
 748
 749         primary =
 750                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 751
 752         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 753
 754         kfree(ap);
 755
 756         return ret;
 757 }
 758
 759 #if !defined(CONFIG_VGA_CONSOLE)
 760 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 761 {
 762         return 0;
 763 }
 764 #elif !defined(CONFIG_DUMMY_CONSOLE)
 765 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 766 {
 767         return -ENODEV;
 768 }
 769 #else
 770 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 771 {
 772         int ret = 0;
 773
 774         DRM_INFO("Replacing VGA console driver\n");
 775
 776         console_lock();
 777         if (con_is_bound(&vga_con))
 778                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 779         if (ret == 0) {
 780                 ret = do_unregister_con_driver(&vga_con);
 781
 782                 /* Ignore "already unregistered". */
 783                 if (ret == -ENODEV)
 784                         ret = 0;
 785         }
 786         console_unlock();
 787
 788         return ret;
 789 }
 790 #endif
 791
 792 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 793 {
 794         /*
 795          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 796          * CHV x1 PHY (DP/HDMI D)
 797          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 798          */
 799         if (IS_CHERRYVIEW(dev_priv)) {
 800                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 801                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 802         } else if (IS_VALLEYVIEW(dev_priv)) {
 803                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 804         }
 805 }
 806
 807 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 808 {
 809         /*
 810          * The i915 workqueue is primarily used for batched retirement of
 811          * requests (and thus managing bo) once the task has been completed
 812          * by the GPU. i915_retire_requests() is called directly when we
 813          * need high-priority retirement, such as waiting for an explicit
 814          * bo.
 815          *
 816          * It is also used for periodic low-priority events, such as
 817          * idle-timers and recording error state.
 818          *
 819          * All tasks on the workqueue are expected to acquire the dev mutex
 820          * so there is no point in running more than one instance of the
 821          * workqueue at any time.  Use an ordered one.
 822          */
 823         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 824         if (dev_priv->wq == NULL)
 825                 goto out_err;
 826
 827         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 828         if (dev_priv->hotplug.dp_wq == NULL)
 829                 goto out_free_wq;
 830
 831         return 0;
 832
 833 out_free_wq:
 834         destroy_workqueue(dev_priv->wq);
 835 out_err:
 836         DRM_ERROR("Failed to allocate workqueues.\n");
 837
 838         return -ENOMEM;
 839 }
 840
 841 static void i915_engines_cleanup(struct drm_i915_private *i915)
 842 {
 843         struct intel_engine_cs *engine;
 844         enum intel_engine_id id;
 845
 846         for_each_engine(engine, i915, id)
 847                 kfree(engine);
 848 }
 849
 850 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 851 {
 852         destroy_workqueue(dev_priv->hotplug.dp_wq);
 853         destroy_workqueue(dev_priv->wq);
 854 }
 855
 856 /*
 857  * We don't keep the workarounds for pre-production hardware, so we expect our
 858  * driver to fail on these machines in one way or another. A little warning on
 859  * dmesg may help both the user and the bug triagers.
 860  *
 861  * Our policy for removing pre-production workarounds is to keep the
 862  * current gen workarounds as a guide to the bring-up of the next gen
 863  * (workarounds have a habit of persisting!). Anything older than that
 864  * should be removed along with the complications they introduce.
 865  */
 866 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 867 {
 868         bool pre = false;
 869
 870         pre |= IS_HSW_EARLY_SDV(dev_priv);
 871         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 872         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 873
 874         if (pre) {
 875                 DRM_ERROR("This is a pre-production stepping. "
 876                           "It may not be fully functional.\n");
 877                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 878         }
 879 }
 880
 881 /**
 882  * i915_driver_init_early - setup state not requiring device access
 883  * @dev_priv: device private
 884  * @ent: the matching pci_device_id
 885  *
 886  * Initialize everything that is a "SW-only" state, that is state not
 887  * requiring accessing the device or exposing the driver via kernel internal
 888  * or userspace interfaces. Example steps belonging here: lock initialization,
 889  * system memory allocation, setting up device specific attributes and
 890  * function hooks not requiring accessing the device.
 891  */
 892 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 893                                   const struct pci_device_id *ent)
 894 {
 895         const struct intel_device_info *match_info =
 896                 (struct intel_device_info *)ent->driver_data;
 897         struct intel_device_info *device_info;
 898         int ret = 0;
 899
 900         if (i915_inject_load_failure())
 901                 return -ENODEV;
 902
 903         /* Setup the write-once "constant" device info */
 904         device_info = mkwrite_device_info(dev_priv);
 905         memcpy(device_info, match_info, sizeof(*device_info));
 906         device_info->device_id = dev_priv->drm.pdev->device;
 907
 908         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 909                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 910         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 911         spin_lock_init(&dev_priv->irq_lock);
 912         spin_lock_init(&dev_priv->gpu_error.lock);
 913         mutex_init(&dev_priv->backlight_lock);
 914         spin_lock_init(&dev_priv->uncore.lock);
 915
 916         mutex_init(&dev_priv->sb_lock);
 917         mutex_init(&dev_priv->modeset_restore_lock);
 918         mutex_init(&dev_priv->av_mutex);
 919         mutex_init(&dev_priv->wm.wm_mutex);
 920         mutex_init(&dev_priv->pps_mutex);
 921
 922         intel_uc_init_early(dev_priv);
 923         i915_memcpy_init_early(dev_priv);
 924
 925         ret = i915_workqueues_init(dev_priv);
 926         if (ret < 0)
 927                 goto err_engines;
 928
 929         /* This must be called before any calls to HAS_PCH_* */
 930         intel_detect_pch(dev_priv);
 931
 932         intel_pm_setup(dev_priv);
 933         intel_init_dpio(dev_priv);
 934         intel_power_domains_init(dev_priv);
 935         intel_irq_init(dev_priv);
 936         intel_hangcheck_init(dev_priv);
 937         intel_init_display_hooks(dev_priv);
 938         intel_init_clock_gating_hooks(dev_priv);
 939         intel_init_audio_hooks(dev_priv);
 940         ret = i915_gem_load_init(dev_priv);
 941         if (ret < 0)
 942                 goto err_irq;
 943
 944         intel_display_crc_init(dev_priv);
 945
 946         intel_detect_preproduction_hw(dev_priv);
 947
 948         return 0;
 949
 950 err_irq:
 951         intel_irq_fini(dev_priv);
 952         i915_workqueues_cleanup(dev_priv);
 953 err_engines:
 954         i915_engines_cleanup(dev_priv);
 955         return ret;
 956 }
 957
 958 /**
 959  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 960  * @dev_priv: device private
 961  */
 962 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 963 {
 964         i915_gem_load_cleanup(dev_priv);
 965         intel_irq_fini(dev_priv);
 966         i915_workqueues_cleanup(dev_priv);
 967         i915_engines_cleanup(dev_priv);
 968 }
 969
 970 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 971 {
 972         struct pci_dev *pdev = dev_priv->drm.pdev;
 973         int mmio_bar;
 974         int mmio_size;
 975
 976         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 977         /*
 978          * Before gen4, the registers and the GTT are behind different BARs.
 979          * However, from gen4 onwards, the registers and the GTT are shared
 980          * in the same BAR, so we want to restrict this ioremap from
 981          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 982          * the register BAR remains the same size for all the earlier
 983          * generations up to Ironlake.
 984          */
 985         if (INTEL_GEN(dev_priv) < 5)
 986                 mmio_size = 512 * 1024;
 987         else
 988                 mmio_size = 2 * 1024 * 1024;
 989         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 990         if (dev_priv->regs == NULL) {
 991                 DRM_ERROR("failed to map registers\n");
 992
 993                 return -EIO;
 994         }
 995
 996         /* Try to make sure MCHBAR is enabled before poking at it */
 997         intel_setup_mchbar(dev_priv);
 998
 999         return 0;
1000 }
1001
1002 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
1003 {
1004         struct pci_dev *pdev = dev_priv->drm.pdev;
1005
1006         intel_teardown_mchbar(dev_priv);
1007         pci_iounmap(pdev, dev_priv->regs);
1008 }
1009
1010 /**
1011  * i915_driver_init_mmio - setup device MMIO
1012  * @dev_priv: device private
1013  *
1014  * Setup minimal device state necessary for MMIO accesses later in the
1015  * initialization sequence. The setup here should avoid any other device-wide
1016  * side effects or exposing the driver via kernel internal or user space
1017  * interfaces.
1018  */
1019 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1020 {
1021         int ret;
1022
1023         if (i915_inject_load_failure())
1024                 return -ENODEV;
1025
1026         if (i915_get_bridge_dev(dev_priv))
1027                 return -EIO;
1028
1029         ret = i915_mmio_setup(dev_priv);
1030         if (ret < 0)
1031                 goto err_bridge;
1032
1033         intel_uncore_init(dev_priv);
1034
1035         intel_uc_init_mmio(dev_priv);
1036
1037         ret = intel_engines_init_mmio(dev_priv);
1038         if (ret)
1039                 goto err_uncore;
1040
1041         i915_gem_init_mmio(dev_priv);
1042
1043         return 0;
1044
1045 err_uncore:
1046         intel_uncore_fini(dev_priv);
1047 err_bridge:
1048         pci_dev_put(dev_priv->bridge_dev);
1049
1050         return ret;
1051 }
1052
1053 /**
1054  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1055  * @dev_priv: device private
1056  */
1057 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1058 {
1059         intel_uncore_fini(dev_priv);
1060         i915_mmio_cleanup(dev_priv);
1061         pci_dev_put(dev_priv->bridge_dev);
1062 }
1063
1064 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1065 {
1066         /*
1067          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1068          * user's requested state against the hardware/driver capabilities.  We
1069          * do this now so that we can print out any log messages once rather
1070          * than every time we check intel_enable_ppgtt().
1071          */
1072         i915_modparams.enable_ppgtt =
1073                 intel_sanitize_enable_ppgtt(dev_priv,
1074                                             i915_modparams.enable_ppgtt);
1075         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1076
1077         intel_uc_sanitize_options(dev_priv);
1078
1079         intel_gvt_sanitize_options(dev_priv);
1080 }
1081
1082 /**
1083  * i915_driver_init_hw - setup state requiring device access
1084  * @dev_priv: device private
1085  *
1086  * Setup state that requires accessing the device, but doesn't require
1087  * exposing the driver via kernel internal or userspace interfaces.
1088  */
1089 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1090 {
1091         struct pci_dev *pdev = dev_priv->drm.pdev;
1092         int ret;
1093
1094         if (i915_inject_load_failure())
1095                 return -ENODEV;
1096
1097         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1098
1099         intel_sanitize_options(dev_priv);
1100
1101         i915_perf_init(dev_priv);
1102
1103         ret = i915_ggtt_probe_hw(dev_priv);
1104         if (ret)
1105                 return ret;
1106
1107         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1108          * otherwise the vga fbdev driver falls over. */
1109         ret = i915_kick_out_firmware_fb(dev_priv);
1110         if (ret) {
1111                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1112                 goto out_ggtt;
1113         }
1114
1115         ret = i915_kick_out_vgacon(dev_priv);
1116         if (ret) {
1117                 DRM_ERROR("failed to remove conflicting VGA console\n");
1118                 goto out_ggtt;
1119         }
1120
1121         ret = i915_ggtt_init_hw(dev_priv);
1122         if (ret)
1123                 return ret;
1124
1125         ret = i915_ggtt_enable_hw(dev_priv);
1126         if (ret) {
1127                 DRM_ERROR("failed to enable GGTT\n");
1128                 goto out_ggtt;
1129         }
1130
1131         pci_set_master(pdev);
1132
1133         /* overlay on gen2 is broken and can't address above 1G */
1134         if (IS_GEN2(dev_priv)) {
1135                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1136                 if (ret) {
1137                         DRM_ERROR("failed to set DMA mask\n");
1138
1139                         goto out_ggtt;
1140                 }
1141         }
1142
1143         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1144          * using 32bit addressing, overwriting memory if HWS is located
1145          * above 4GB.
1146          *
1147          * The documentation also mentions an issue with undefined
1148          * behaviour if any general state is accessed within a page above 4GB,
1149          * which also needs to be handled carefully.
1150          */
1151         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1152                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1153
1154                 if (ret) {
1155                         DRM_ERROR("failed to set DMA mask\n");
1156
1157                         goto out_ggtt;
1158                 }
1159         }
1160
1161         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1162                            PM_QOS_DEFAULT_VALUE);
1163
1164         intel_uncore_sanitize(dev_priv);
1165
1166         intel_opregion_setup(dev_priv);
1167
1168         i915_gem_load_init_fences(dev_priv);
1169
1170         /* On the 945G/GM, the chipset reports the MSI capability on the
1171          * integrated graphics even though the support isn't actually there
1172          * according to the published specs.  It doesn't appear to function
1173          * correctly in testing on 945G.
1174          * This may be a side effect of MSI having been made available for PEG
1175          * and the registers being closely associated.
1176          *
1177          * According to chipset errata, on the 965GM, MSI interrupts may
1178          * be lost or delayed, and was defeatured. MSI interrupts seem to
1179          * get lost on g4x as well, and interrupt delivery seems to stay
1180          * properly dead afterwards. So we'll just disable them for all
1181          * pre-gen5 chipsets.
1182          */
1183         if (INTEL_GEN(dev_priv) >= 5) {
1184                 if (pci_enable_msi(pdev) < 0)
1185                         DRM_DEBUG_DRIVER("can't enable MSI");
1186         }
1187
1188         ret = intel_gvt_init(dev_priv);
1189         if (ret)
1190                 goto out_ggtt;
1191
1192         return 0;
1193
1194 out_ggtt:
1195         i915_ggtt_cleanup_hw(dev_priv);
1196
1197         return ret;
1198 }
1199
1200 /**
1201  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1202  * @dev_priv: device private
1203  */
1204 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1205 {
1206         struct pci_dev *pdev = dev_priv->drm.pdev;
1207
1208         i915_perf_fini(dev_priv);
1209
1210         if (pdev->msi_enabled)
1211                 pci_disable_msi(pdev);
1212
1213         pm_qos_remove_request(&dev_priv->pm_qos);
1214         i915_ggtt_cleanup_hw(dev_priv);
1215 }
1216
1217 /**
1218  * i915_driver_register - register the driver with the rest of the system
1219  * @dev_priv: device private
1220  *
1221  * Perform any steps necessary to make the driver available via kernel
1222  * internal or userspace interfaces.
1223  */
1224 static void i915_driver_register(struct drm_i915_private *dev_priv)
1225 {
1226         struct drm_device *dev = &dev_priv->drm;
1227
1228         i915_gem_shrinker_register(dev_priv);
1229         i915_pmu_register(dev_priv);
1230
1231         /*
1232          * Notify a valid surface after modesetting,
1233          * when running inside a VM.
1234          */
1235         if (intel_vgpu_active(dev_priv))
1236                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1237
1238         /* Reveal our presence to userspace */
1239         if (drm_dev_register(dev, 0) == 0) {
1240                 i915_debugfs_register(dev_priv);
1241                 i915_guc_log_register(dev_priv);
1242                 i915_setup_sysfs(dev_priv);
1243
1244                 /* Depends on sysfs having been initialized */
1245                 i915_perf_register(dev_priv);
1246         } else
1247                 DRM_ERROR("Failed to register driver for userspace access!\n");
1248
1249         if (INTEL_INFO(dev_priv)->num_pipes) {
1250                 /* Must be done after probing outputs */
1251                 intel_opregion_register(dev_priv);
1252                 acpi_video_register();
1253         }
1254
1255         if (IS_GEN5(dev_priv))
1256                 intel_gpu_ips_init(dev_priv);
1257
1258         intel_audio_init(dev_priv);
1259
1260         /*
1261          * Some ports require correctly set-up hpd registers for detection to
1262          * work properly (leading to ghost connected connector status), e.g. VGA
1263          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1264          * irqs are fully enabled. We do it last so that the async config
1265          * cannot run before the connectors are registered.
1266          */
1267         intel_fbdev_initial_config_async(dev);
1268
1269         /*
1270          * We need to coordinate the hotplugs with the asynchronous fbdev
1271          * configuration, for which we use the fbdev->async_cookie.
1272          */
1273         if (INTEL_INFO(dev_priv)->num_pipes)
1274                 drm_kms_helper_poll_init(dev);
1275 }
1276
1277 /**
1278  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1279  * @dev_priv: device private
1280  */
1281 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1282 {
1283         intel_fbdev_unregister(dev_priv);
1284         intel_audio_deinit(dev_priv);
1285
1286         /*
1287          * After flushing the fbdev (incl. a late async config which will
1288          * have delayed queuing of a hotplug event), then flush the hotplug
1289          * events.
1290          */
1291         drm_kms_helper_poll_fini(&dev_priv->drm);
1292
1293         intel_gpu_ips_teardown();
1294         acpi_video_unregister();
1295         intel_opregion_unregister(dev_priv);
1296
1297         i915_perf_unregister(dev_priv);
1298         i915_pmu_unregister(dev_priv);
1299
1300         i915_teardown_sysfs(dev_priv);
1301         i915_guc_log_unregister(dev_priv);
1302         drm_dev_unregister(&dev_priv->drm);
1303
1304         i915_gem_shrinker_unregister(dev_priv);
1305 }
1306
1307 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1308 {
1309         if (drm_debug & DRM_UT_DRIVER) {
1310                 struct drm_printer p = drm_debug_printer("i915 device info:");
1311
1312                 intel_device_info_dump(&dev_priv->info, &p);
1313                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1314         }
1315
1316         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1317                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1318         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1319                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1320 }
1321
1322 /**
1323  * i915_driver_load - setup chip and create an initial config
1324  * @pdev: PCI device
1325  * @ent: matching PCI ID entry
1326  *
1327  * The driver load routine has to do several things:
1328  *   - drive output discovery via intel_modeset_init()
1329  *   - initialize the memory manager
1330  *   - allocate initial config memory
1331  *   - setup the DRM framebuffer with the allocated memory
1332  */
1333 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1334 {
1335         const struct intel_device_info *match_info =
1336                 (struct intel_device_info *)ent->driver_data;
1337         struct drm_i915_private *dev_priv;
1338         int ret;
1339
1340         /* Enable nuclear pageflip on ILK+ */
1341         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1342                 driver.driver_features &= ~DRIVER_ATOMIC;
1343
1344         ret = -ENOMEM;
1345         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1346         if (dev_priv)
1347                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1348         if (ret) {
1349                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1350                 goto out_free;
1351         }
1352
1353         dev_priv->drm.pdev = pdev;
1354         dev_priv->drm.dev_private = dev_priv;
1355
1356         ret = pci_enable_device(pdev);
1357         if (ret)
1358                 goto out_fini;
1359
1360         pci_set_drvdata(pdev, &dev_priv->drm);
1361         /*
1362          * Disable the system suspend direct complete optimization, which can
1363          * leave the device suspended skipping the driver's suspend handlers
1364          * if the device was already runtime suspended. This is needed due to
1365          * the difference in our runtime and system suspend sequence and
1366          * becaue the HDA driver may require us to enable the audio power
1367          * domain during system suspend.
1368          */
1369         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1370
1371         ret = i915_driver_init_early(dev_priv, ent);
1372         if (ret < 0)
1373                 goto out_pci_disable;
1374
1375         intel_runtime_pm_get(dev_priv);
1376
1377         ret = i915_driver_init_mmio(dev_priv);
1378         if (ret < 0)
1379                 goto out_runtime_pm_put;
1380
1381         ret = i915_driver_init_hw(dev_priv);
1382         if (ret < 0)
1383                 goto out_cleanup_mmio;
1384
1385         /*
1386          * TODO: move the vblank init and parts of modeset init steps into one
1387          * of the i915_driver_init_/i915_driver_register functions according
1388          * to the role/effect of the given init step.
1389          */
1390         if (INTEL_INFO(dev_priv)->num_pipes) {
1391                 ret = drm_vblank_init(&dev_priv->drm,
1392                                       INTEL_INFO(dev_priv)->num_pipes);
1393                 if (ret)
1394                         goto out_cleanup_hw;
1395         }
1396
1397         ret = i915_load_modeset_init(&dev_priv->drm);
1398         if (ret < 0)
1399                 goto out_cleanup_hw;
1400
1401         i915_driver_register(dev_priv);
1402
1403         intel_runtime_pm_enable(dev_priv);
1404
1405         intel_init_ipc(dev_priv);
1406
1407         intel_runtime_pm_put(dev_priv);
1408
1409         i915_welcome_messages(dev_priv);
1410
1411         return 0;
1412
1413 out_cleanup_hw:
1414         i915_driver_cleanup_hw(dev_priv);
1415 out_cleanup_mmio:
1416         i915_driver_cleanup_mmio(dev_priv);
1417 out_runtime_pm_put:
1418         intel_runtime_pm_put(dev_priv);
1419         i915_driver_cleanup_early(dev_priv);
1420 out_pci_disable:
1421         pci_disable_device(pdev);
1422 out_fini:
1423         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1424         drm_dev_fini(&dev_priv->drm);
1425 out_free:
1426         kfree(dev_priv);
1427         return ret;
1428 }
1429
1430 void i915_driver_unload(struct drm_device *dev)
1431 {
1432         struct drm_i915_private *dev_priv = to_i915(dev);
1433         struct pci_dev *pdev = dev_priv->drm.pdev;
1434
1435         i915_driver_unregister(dev_priv);
1436
1437         if (i915_gem_suspend(dev_priv))
1438                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1439
1440         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1441
1442         drm_atomic_helper_shutdown(dev);
1443
1444         intel_gvt_cleanup(dev_priv);
1445
1446         intel_modeset_cleanup(dev);
1447
1448         intel_bios_cleanup(dev_priv);
1449
1450         vga_switcheroo_unregister_client(pdev);
1451         vga_client_register(pdev, NULL, NULL, NULL);
1452
1453         intel_csr_ucode_fini(dev_priv);
1454
1455         /* Free error state after interrupts are fully disabled. */
1456         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1457         i915_reset_error_state(dev_priv);
1458
1459         i915_gem_fini(dev_priv);
1460         intel_uc_fini_fw(dev_priv);
1461         intel_fbc_cleanup_cfb(dev_priv);
1462
1463         intel_power_domains_fini(dev_priv);
1464
1465         i915_driver_cleanup_hw(dev_priv);
1466         i915_driver_cleanup_mmio(dev_priv);
1467
1468         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1469 }
1470
1471 static void i915_driver_release(struct drm_device *dev)
1472 {
1473         struct drm_i915_private *dev_priv = to_i915(dev);
1474
1475         i915_driver_cleanup_early(dev_priv);
1476         drm_dev_fini(&dev_priv->drm);
1477
1478         kfree(dev_priv);
1479 }
1480
1481 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1482 {
1483         struct drm_i915_private *i915 = to_i915(dev);
1484         int ret;
1485
1486         ret = i915_gem_open(i915, file);
1487         if (ret)
1488                 return ret;
1489
1490         return 0;
1491 }
1492
1493 /**
1494  * i915_driver_lastclose - clean up after all DRM clients have exited
1495  * @dev: DRM device
1496  *
1497  * Take care of cleaning up after all DRM clients have exited.  In the
1498  * mode setting case, we want to restore the kernel's initial mode (just
1499  * in case the last client left us in a bad state).
1500  *
1501  * Additionally, in the non-mode setting case, we'll tear down the GTT
1502  * and DMA structures, since the kernel won't be using them, and clea
1503  * up any GEM state.
1504  */
1505 static void i915_driver_lastclose(struct drm_device *dev)
1506 {
1507         intel_fbdev_restore_mode(dev);
1508         vga_switcheroo_process_delayed_switch();
1509 }
1510
1511 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1512 {
1513         struct drm_i915_file_private *file_priv = file->driver_priv;
1514
1515         mutex_lock(&dev->struct_mutex);
1516         i915_gem_context_close(file);
1517         i915_gem_release(dev, file);
1518         mutex_unlock(&dev->struct_mutex);
1519
1520         kfree(file_priv);
1521 }
1522
1523 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1524 {
1525         struct drm_device *dev = &dev_priv->drm;
1526         struct intel_encoder *encoder;
1527
1528         drm_modeset_lock_all(dev);
1529         for_each_intel_encoder(dev, encoder)
1530                 if (encoder->suspend)
1531                         encoder->suspend(encoder);
1532         drm_modeset_unlock_all(dev);
1533 }
1534
1535 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1536                               bool rpm_resume);
1537 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1538
1539 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1540 {
1541 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1542         if (acpi_target_system_state() < ACPI_STATE_S3)
1543                 return true;
1544 #endif
1545         return false;
1546 }
1547
1548 static int i915_drm_suspend(struct drm_device *dev)
1549 {
1550         struct drm_i915_private *dev_priv = to_i915(dev);
1551         struct pci_dev *pdev = dev_priv->drm.pdev;
1552         pci_power_t opregion_target_state;
1553         int error;
1554
1555         /* ignore lid events during suspend */
1556         mutex_lock(&dev_priv->modeset_restore_lock);
1557         dev_priv->modeset_restore = MODESET_SUSPENDED;
1558         mutex_unlock(&dev_priv->modeset_restore_lock);
1559
1560         disable_rpm_wakeref_asserts(dev_priv);
1561
1562         /* We do a lot of poking in a lot of registers, make sure they work
1563          * properly. */
1564         intel_display_set_init_power(dev_priv, true);
1565
1566         drm_kms_helper_poll_disable(dev);
1567
1568         pci_save_state(pdev);
1569
1570         error = i915_gem_suspend(dev_priv);
1571         if (error) {
1572                 dev_err(&pdev->dev,
1573                         "GEM idle failed, resume might fail\n");
1574                 goto out;
1575         }
1576
1577         intel_display_suspend(dev);
1578
1579         intel_dp_mst_suspend(dev);
1580
1581         intel_runtime_pm_disable_interrupts(dev_priv);
1582         intel_hpd_cancel_work(dev_priv);
1583
1584         intel_suspend_encoders(dev_priv);
1585
1586         intel_suspend_hw(dev_priv);
1587
1588         i915_gem_suspend_gtt_mappings(dev_priv);
1589
1590         i915_save_state(dev_priv);
1591
1592         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1593         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1594
1595         intel_uncore_suspend(dev_priv);
1596         intel_opregion_unregister(dev_priv);
1597
1598         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1599
1600         dev_priv->suspend_count++;
1601
1602         intel_csr_ucode_suspend(dev_priv);
1603
1604 out:
1605         enable_rpm_wakeref_asserts(dev_priv);
1606
1607         return error;
1608 }
1609
1610 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1611 {
1612         struct drm_i915_private *dev_priv = to_i915(dev);
1613         struct pci_dev *pdev = dev_priv->drm.pdev;
1614         int ret;
1615
1616         disable_rpm_wakeref_asserts(dev_priv);
1617
1618         intel_display_set_init_power(dev_priv, false);
1619
1620         /*
1621          * In case of firmware assisted context save/restore don't manually
1622          * deinit the power domains. This also means the CSR/DMC firmware will
1623          * stay active, it will power down any HW resources as required and
1624          * also enable deeper system power states that would be blocked if the
1625          * firmware was inactive.
1626          */
1627         if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
1628             dev_priv->csr.dmc_payload == NULL) {
1629                 intel_power_domains_suspend(dev_priv);
1630                 dev_priv->power_domains_suspended = true;
1631         }
1632
1633         ret = 0;
1634         if (IS_GEN9_LP(dev_priv))
1635                 bxt_enable_dc9(dev_priv);
1636         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1637                 hsw_enable_pc8(dev_priv);
1638         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1639                 ret = vlv_suspend_complete(dev_priv);
1640
1641         if (ret) {
1642                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1643                 if (dev_priv->power_domains_suspended) {
1644                         intel_power_domains_init_hw(dev_priv, true);
1645                         dev_priv->power_domains_suspended = false;
1646                 }
1647
1648                 goto out;
1649         }
1650
1651         pci_disable_device(pdev);
1652         /*
1653          * During hibernation on some platforms the BIOS may try to access
1654          * the device even though it's already in D3 and hang the machine. So
1655          * leave the device in D0 on those platforms and hope the BIOS will
1656          * power down the device properly. The issue was seen on multiple old
1657          * GENs with different BIOS vendors, so having an explicit blacklist
1658          * is inpractical; apply the workaround on everything pre GEN6. The
1659          * platforms where the issue was seen:
1660          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1661          * Fujitsu FSC S7110
1662          * Acer Aspire 1830T
1663          */
1664         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1665                 pci_set_power_state(pdev, PCI_D3hot);
1666
1667 out:
1668         enable_rpm_wakeref_asserts(dev_priv);
1669
1670         return ret;
1671 }
1672
1673 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1674 {
1675         int error;
1676
1677         if (!dev) {
1678                 DRM_ERROR("dev: %p\n", dev);
1679                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1680                 return -ENODEV;
1681         }
1682
1683         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1684                          state.event != PM_EVENT_FREEZE))
1685                 return -EINVAL;
1686
1687         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1688                 return 0;
1689
1690         error = i915_drm_suspend(dev);
1691         if (error)
1692                 return error;
1693
1694         return i915_drm_suspend_late(dev, false);
1695 }
1696
1697 static int i915_drm_resume(struct drm_device *dev)
1698 {
1699         struct drm_i915_private *dev_priv = to_i915(dev);
1700         int ret;
1701
1702         disable_rpm_wakeref_asserts(dev_priv);
1703         intel_sanitize_gt_powersave(dev_priv);
1704
1705         ret = i915_ggtt_enable_hw(dev_priv);
1706         if (ret)
1707                 DRM_ERROR("failed to re-enable GGTT\n");
1708
1709         intel_csr_ucode_resume(dev_priv);
1710
1711         i915_restore_state(dev_priv);
1712         intel_pps_unlock_regs_wa(dev_priv);
1713         intel_opregion_setup(dev_priv);
1714
1715         intel_init_pch_refclk(dev_priv);
1716
1717         /*
1718          * Interrupts have to be enabled before any batches are run. If not the
1719          * GPU will hang. i915_gem_init_hw() will initiate batches to
1720          * update/restore the context.
1721          *
1722          * drm_mode_config_reset() needs AUX interrupts.
1723          *
1724          * Modeset enabling in intel_modeset_init_hw() also needs working
1725          * interrupts.
1726          */
1727         intel_runtime_pm_enable_interrupts(dev_priv);
1728
1729         drm_mode_config_reset(dev);
1730
1731         i915_gem_resume(dev_priv);
1732
1733         intel_modeset_init_hw(dev);
1734         intel_init_clock_gating(dev_priv);
1735
1736         spin_lock_irq(&dev_priv->irq_lock);
1737         if (dev_priv->display.hpd_irq_setup)
1738                 dev_priv->display.hpd_irq_setup(dev_priv);
1739         spin_unlock_irq(&dev_priv->irq_lock);
1740
1741         intel_dp_mst_resume(dev);
1742
1743         intel_display_resume(dev);
1744
1745         drm_kms_helper_poll_enable(dev);
1746
1747         /*
1748          * ... but also need to make sure that hotplug processing
1749          * doesn't cause havoc. Like in the driver load code we don't
1750          * bother with the tiny race here where we might loose hotplug
1751          * notifications.
1752          * */
1753         intel_hpd_init(dev_priv);
1754
1755         intel_opregion_register(dev_priv);
1756
1757         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1758
1759         mutex_lock(&dev_priv->modeset_restore_lock);
1760         dev_priv->modeset_restore = MODESET_DONE;
1761         mutex_unlock(&dev_priv->modeset_restore_lock);
1762
1763         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1764
1765         enable_rpm_wakeref_asserts(dev_priv);
1766
1767         return 0;
1768 }
1769
1770 static int i915_drm_resume_early(struct drm_device *dev)
1771 {
1772         struct drm_i915_private *dev_priv = to_i915(dev);
1773         struct pci_dev *pdev = dev_priv->drm.pdev;
1774         int ret;
1775
1776         /*
1777          * We have a resume ordering issue with the snd-hda driver also
1778          * requiring our device to be power up. Due to the lack of a
1779          * parent/child relationship we currently solve this with an early
1780          * resume hook.
1781          *
1782          * FIXME: This should be solved with a special hdmi sink device or
1783          * similar so that power domains can be employed.
1784          */
1785
1786         /*
1787          * Note that we need to set the power state explicitly, since we
1788          * powered off the device during freeze and the PCI core won't power
1789          * it back up for us during thaw. Powering off the device during
1790          * freeze is not a hard requirement though, and during the
1791          * suspend/resume phases the PCI core makes sure we get here with the
1792          * device powered on. So in case we change our freeze logic and keep
1793          * the device powered we can also remove the following set power state
1794          * call.
1795          */
1796         ret = pci_set_power_state(pdev, PCI_D0);
1797         if (ret) {
1798                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1799                 goto out;
1800         }
1801
1802         /*
1803          * Note that pci_enable_device() first enables any parent bridge
1804          * device and only then sets the power state for this device. The
1805          * bridge enabling is a nop though, since bridge devices are resumed
1806          * first. The order of enabling power and enabling the device is
1807          * imposed by the PCI core as described above, so here we preserve the
1808          * same order for the freeze/thaw phases.
1809          *
1810          * TODO: eventually we should remove pci_disable_device() /
1811          * pci_enable_enable_device() from suspend/resume. Due to how they
1812          * depend on the device enable refcount we can't anyway depend on them
1813          * disabling/enabling the device.
1814          */
1815         if (pci_enable_device(pdev)) {
1816                 ret = -EIO;
1817                 goto out;
1818         }
1819
1820         pci_set_master(pdev);
1821
1822         disable_rpm_wakeref_asserts(dev_priv);
1823
1824         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1825                 ret = vlv_resume_prepare(dev_priv, false);
1826         if (ret)
1827                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1828                           ret);
1829
1830         intel_uncore_resume_early(dev_priv);
1831
1832         if (IS_GEN9_LP(dev_priv)) {
1833                 gen9_sanitize_dc_state(dev_priv);
1834                 bxt_disable_dc9(dev_priv);
1835         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1836                 hsw_disable_pc8(dev_priv);
1837         }
1838
1839         intel_uncore_sanitize(dev_priv);
1840
1841         if (dev_priv->power_domains_suspended)
1842                 intel_power_domains_init_hw(dev_priv, true);
1843         else
1844                 intel_display_set_init_power(dev_priv, true);
1845
1846         i915_gem_sanitize(dev_priv);
1847
1848         enable_rpm_wakeref_asserts(dev_priv);
1849
1850 out:
1851         dev_priv->power_domains_suspended = false;
1852
1853         return ret;
1854 }
1855
1856 static int i915_resume_switcheroo(struct drm_device *dev)
1857 {
1858         int ret;
1859
1860         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1861                 return 0;
1862
1863         ret = i915_drm_resume_early(dev);
1864         if (ret)
1865                 return ret;
1866
1867         return i915_drm_resume(dev);
1868 }
1869
1870 /**
1871  * i915_reset - reset chip after a hang
1872  * @i915: #drm_i915_private to reset
1873  * @flags: Instructions
1874  *
1875  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1876  * on failure.
1877  *
1878  * Caller must hold the struct_mutex.
1879  *
1880  * Procedure is fairly simple:
1881  *   - reset the chip using the reset reg
1882  *   - re-init context state
1883  *   - re-init hardware status page
1884  *   - re-init ring buffer
1885  *   - re-init interrupt state
1886  *   - re-init display
1887  */
1888 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1889 {
1890         struct i915_gpu_error *error = &i915->gpu_error;
1891         int ret;
1892         int i;
1893
1894         might_sleep();
1895         lockdep_assert_held(&i915->drm.struct_mutex);
1896         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1897
1898         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1899                 return;
1900
1901         /* Clear any previous failed attempts at recovery. Time to try again. */
1902         if (!i915_gem_unset_wedged(i915))
1903                 goto wakeup;
1904
1905         if (!(flags & I915_RESET_QUIET))
1906                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1907         error->reset_count++;
1908
1909         disable_irq(i915->drm.irq);
1910         ret = i915_gem_reset_prepare(i915);
1911         if (ret) {
1912                 dev_err(i915->drm.dev, "GPU recovery failed\n");
1913                 goto taint;
1914         }
1915
1916         if (!intel_has_gpu_reset(i915)) {
1917                 if (i915_modparams.reset)
1918                         dev_err(i915->drm.dev, "GPU reset not supported\n");
1919                 else
1920                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1921                 goto error;
1922         }
1923
1924         for (i = 0; i < 3; i++) {
1925                 ret = intel_gpu_reset(i915, ALL_ENGINES);
1926                 if (ret == 0)
1927                         break;
1928
1929                 msleep(100);
1930         }
1931         if (ret) {
1932                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1933                 goto taint;
1934         }
1935
1936         /* Ok, now get things going again... */
1937
1938         /*
1939          * Everything depends on having the GTT running, so we need to start
1940          * there.
1941          */
1942         ret = i915_ggtt_enable_hw(i915);
1943         if (ret) {
1944                 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1945                           ret);
1946                 goto error;
1947         }
1948
1949         i915_gem_reset(i915);
1950         intel_overlay_reset(i915);
1951
1952         /*
1953          * Next we need to restore the context, but we don't use those
1954          * yet either...
1955          *
1956          * Ring buffer needs to be re-initialized in the KMS case, or if X
1957          * was running at the time of the reset (i.e. we weren't VT
1958          * switched away).
1959          */
1960         ret = i915_gem_init_hw(i915);
1961         if (ret) {
1962                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1963                           ret);
1964                 goto error;
1965         }
1966
1967         i915_queue_hangcheck(i915);
1968
1969 finish:
1970         i915_gem_reset_finish(i915);
1971         enable_irq(i915->drm.irq);
1972
1973 wakeup:
1974         clear_bit(I915_RESET_HANDOFF, &error->flags);
1975         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1976         return;
1977
1978 taint:
1979         /*
1980          * History tells us that if we cannot reset the GPU now, we
1981          * never will. This then impacts everything that is run
1982          * subsequently. On failing the reset, we mark the driver
1983          * as wedged, preventing further execution on the GPU.
1984          * We also want to go one step further and add a taint to the
1985          * kernel so that any subsequent faults can be traced back to
1986          * this failure. This is important for CI, where if the
1987          * GPU/driver fails we would like to reboot and restart testing
1988          * rather than continue on into oblivion. For everyone else,
1989          * the system should still plod along, but they have been warned!
1990          */
1991         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1992 error:
1993         i915_gem_set_wedged(i915);
1994         i915_retire_requests(i915);
1995         intel_gpu_reset(i915, ALL_ENGINES);
1996         goto finish;
1997 }
1998
1999 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2000                                         struct intel_engine_cs *engine)
2001 {
2002         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2003 }
2004
2005 /**
2006  * i915_reset_engine - reset GPU engine to recover from a hang
2007  * @engine: engine to reset
2008  * @flags: options
2009  *
2010  * Reset a specific GPU engine. Useful if a hang is detected.
2011  * Returns zero on successful reset or otherwise an error code.
2012  *
2013  * Procedure is:
2014  *  - identifies the request that caused the hang and it is dropped
2015  *  - reset engine (which will force the engine to idle)
2016  *  - re-init/configure engine
2017  */
2018 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
2019 {
2020         struct i915_gpu_error *error = &engine->i915->gpu_error;
2021         struct i915_request *active_request;
2022         int ret;
2023
2024         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2025
2026         active_request = i915_gem_reset_prepare_engine(engine);
2027         if (IS_ERR_OR_NULL(active_request)) {
2028                 /* Either the previous reset failed, or we pardon the reset. */
2029                 ret = PTR_ERR(active_request);
2030                 goto out;
2031         }
2032
2033         if (!(flags & I915_RESET_QUIET)) {
2034                 dev_notice(engine->i915->drm.dev,
2035                            "Resetting %s after gpu hang\n", engine->name);
2036         }
2037         error->reset_engine_count[engine->id]++;
2038
2039         if (!engine->i915->guc.execbuf_client)
2040                 ret = intel_gt_reset_engine(engine->i915, engine);
2041         else
2042                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2043         if (ret) {
2044                 /* If we fail here, we expect to fallback to a global reset */
2045                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2046                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2047                                  engine->name, ret);
2048                 goto out;
2049         }
2050
2051         /*
2052          * The request that caused the hang is stuck on elsp, we know the
2053          * active request and can drop it, adjust head to skip the offending
2054          * request to resume executing remaining requests in the queue.
2055          */
2056         i915_gem_reset_engine(engine, active_request);
2057
2058         /*
2059          * The engine and its registers (and workarounds in case of render)
2060          * have been reset to their default values. Follow the init_ring
2061          * process to program RING_MODE, HWSP and re-enable submission.
2062          */
2063         ret = engine->init_hw(engine);
2064         if (ret)
2065                 goto out;
2066
2067 out:
2068         i915_gem_reset_finish_engine(engine);
2069         return ret;
2070 }
2071
2072 static int i915_pm_suspend(struct device *kdev)
2073 {
2074         struct pci_dev *pdev = to_pci_dev(kdev);
2075         struct drm_device *dev = pci_get_drvdata(pdev);
2076
2077         if (!dev) {
2078                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2079                 return -ENODEV;
2080         }
2081
2082         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2083                 return 0;
2084
2085         return i915_drm_suspend(dev);
2086 }
2087
2088 static int i915_pm_suspend_late(struct device *kdev)
2089 {
2090         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2091
2092         /*
2093          * We have a suspend ordering issue with the snd-hda driver also
2094          * requiring our device to be power up. Due to the lack of a
2095          * parent/child relationship we currently solve this with an late
2096          * suspend hook.
2097          *
2098          * FIXME: This should be solved with a special hdmi sink device or
2099          * similar so that power domains can be employed.
2100          */
2101         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2102                 return 0;
2103
2104         return i915_drm_suspend_late(dev, false);
2105 }
2106
2107 static int i915_pm_poweroff_late(struct device *kdev)
2108 {
2109         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2110
2111         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2112                 return 0;
2113
2114         return i915_drm_suspend_late(dev, true);
2115 }
2116
2117 static int i915_pm_resume_early(struct device *kdev)
2118 {
2119         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2120
2121         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2122                 return 0;
2123
2124         return i915_drm_resume_early(dev);
2125 }
2126
2127 static int i915_pm_resume(struct device *kdev)
2128 {
2129         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2130
2131         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2132                 return 0;
2133
2134         return i915_drm_resume(dev);
2135 }
2136
2137 /* freeze: before creating the hibernation_image */
2138 static int i915_pm_freeze(struct device *kdev)
2139 {
2140         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2141         int ret;
2142
2143         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2144                 ret = i915_drm_suspend(dev);
2145                 if (ret)
2146                         return ret;
2147         }
2148
2149         ret = i915_gem_freeze(kdev_to_i915(kdev));
2150         if (ret)
2151                 return ret;
2152
2153         return 0;
2154 }
2155
2156 static int i915_pm_freeze_late(struct device *kdev)
2157 {
2158         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2159         int ret;
2160
2161         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2162                 ret = i915_drm_suspend_late(dev, true);
2163                 if (ret)
2164                         return ret;
2165         }
2166
2167         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2168         if (ret)
2169                 return ret;
2170
2171         return 0;
2172 }
2173
2174 /* thaw: called after creating the hibernation image, but before turning off. */
2175 static int i915_pm_thaw_early(struct device *kdev)
2176 {
2177         return i915_pm_resume_early(kdev);
2178 }
2179
2180 static int i915_pm_thaw(struct device *kdev)
2181 {
2182         return i915_pm_resume(kdev);
2183 }
2184
2185 /* restore: called after loading the hibernation image. */
2186 static int i915_pm_restore_early(struct device *kdev)
2187 {
2188         return i915_pm_resume_early(kdev);
2189 }
2190
2191 static int i915_pm_restore(struct device *kdev)
2192 {
2193         return i915_pm_resume(kdev);
2194 }
2195
2196 /*
2197  * Save all Gunit registers that may be lost after a D3 and a subsequent
2198  * S0i[R123] transition. The list of registers needing a save/restore is
2199  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2200  * registers in the following way:
2201  * - Driver: saved/restored by the driver
2202  * - Punit : saved/restored by the Punit firmware
2203  * - No, w/o marking: no need to save/restore, since the register is R/O or
2204  *                    used internally by the HW in a way that doesn't depend
2205  *                    keeping the content across a suspend/resume.
2206  * - Debug : used for debugging
2207  *
2208  * We save/restore all registers marked with 'Driver', with the following
2209  * exceptions:
2210  * - Registers out of use, including also registers marked with 'Debug'.
2211  *   These have no effect on the driver's operation, so we don't save/restore
2212  *   them to reduce the overhead.
2213  * - Registers that are fully setup by an initialization function called from
2214  *   the resume path. For example many clock gating and RPS/RC6 registers.
2215  * - Registers that provide the right functionality with their reset defaults.
2216  *
2217  * TODO: Except for registers that based on the above 3 criteria can be safely
2218  * ignored, we save/restore all others, practically treating the HW context as
2219  * a black-box for the driver. Further investigation is needed to reduce the
2220  * saved/restored registers even further, by following the same 3 criteria.
2221  */
2222 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2223 {
2224         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2225         int i;
2226
2227         /* GAM 0x4000-0x4770 */
2228         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2229         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2230         s->arb_mode             = I915_READ(ARB_MODE);
2231         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2232         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2233
2234         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2235                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2236
2237         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2238         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2239
2240         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2241         s->ecochk               = I915_READ(GAM_ECOCHK);
2242         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2243         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2244
2245         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2246
2247         /* MBC 0x9024-0x91D0, 0x8500 */
2248         s->g3dctl               = I915_READ(VLV_G3DCTL);
2249         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2250         s->mbctl                = I915_READ(GEN6_MBCTL);
2251
2252         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2253         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2254         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2255         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2256         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2257         s->rstctl               = I915_READ(GEN6_RSTCTL);
2258         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2259
2260         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2261         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2262         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2263         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2264         s->ecobus               = I915_READ(ECOBUS);
2265         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2266         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2267         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2268         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2269         s->rcedata              = I915_READ(VLV_RCEDATA);
2270         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2271
2272         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2273         s->gt_imr               = I915_READ(GTIMR);
2274         s->gt_ier               = I915_READ(GTIER);
2275         s->pm_imr               = I915_READ(GEN6_PMIMR);
2276         s->pm_ier               = I915_READ(GEN6_PMIER);
2277
2278         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2279                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2280
2281         /* GT SA CZ domain, 0x100000-0x138124 */
2282         s->tilectl              = I915_READ(TILECTL);
2283         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2284         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2285         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2286         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2287
2288         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2289         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2290         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2291         s->pcbr                 = I915_READ(VLV_PCBR);
2292         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2293
2294         /*
2295          * Not saving any of:
2296          * DFT,         0x9800-0x9EC0
2297          * SARB,        0xB000-0xB1FC
2298          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2299          * PCI CFG
2300          */
2301 }
2302
2303 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2304 {
2305         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2306         u32 val;
2307         int i;
2308
2309         /* GAM 0x4000-0x4770 */
2310         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2311         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2312         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2313         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2314         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2315
2316         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2317                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2318
2319         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2320         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2321
2322         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2323         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2324         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2325         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2326
2327         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2328
2329         /* MBC 0x9024-0x91D0, 0x8500 */
2330         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2331         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2332         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2333
2334         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2335         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2336         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2337         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2338         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2339         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2340         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2341
2342         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2343         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2344         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2345         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2346         I915_WRITE(ECOBUS,              s->ecobus);
2347         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2348         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2349         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2350         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2351         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2352         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2353
2354         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2355         I915_WRITE(GTIMR,               s->gt_imr);
2356         I915_WRITE(GTIER,               s->gt_ier);
2357         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2358         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2359
2360         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2361                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2362
2363         /* GT SA CZ domain, 0x100000-0x138124 */
2364         I915_WRITE(TILECTL,                     s->tilectl);
2365         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2366         /*
2367          * Preserve the GT allow wake and GFX force clock bit, they are not
2368          * be restored, as they are used to control the s0ix suspend/resume
2369          * sequence by the caller.
2370          */
2371         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2372         val &= VLV_GTLC_ALLOWWAKEREQ;
2373         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2374         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2375
2376         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2377         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2378         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2379         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2380
2381         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2382
2383         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2384         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2385         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2386         I915_WRITE(VLV_PCBR,                    s->pcbr);
2387         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2388 }
2389
2390 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2391                                   u32 mask, u32 val)
2392 {
2393         /* The HW does not like us polling for PW_STATUS frequently, so
2394          * use the sleeping loop rather than risk the busy spin within
2395          * intel_wait_for_register().
2396          *
2397          * Transitioning between RC6 states should be at most 2ms (see
2398          * valleyview_enable_rps) so use a 3ms timeout.
2399          */
2400         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2401                         3);
2402 }
2403
2404 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2405 {
2406         u32 val;
2407         int err;
2408
2409         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2410         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2411         if (force_on)
2412                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2413         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2414
2415         if (!force_on)
2416                 return 0;
2417
2418         err = intel_wait_for_register(dev_priv,
2419                                       VLV_GTLC_SURVIVABILITY_REG,
2420                                       VLV_GFX_CLK_STATUS_BIT,
2421                                       VLV_GFX_CLK_STATUS_BIT,
2422                                       20);
2423         if (err)
2424                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2425                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2426
2427         return err;
2428 }
2429
2430 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2431 {
2432         u32 mask;
2433         u32 val;
2434         int err;
2435
2436         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2437         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2438         if (allow)
2439                 val |= VLV_GTLC_ALLOWWAKEREQ;
2440         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2441         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2442
2443         mask = VLV_GTLC_ALLOWWAKEACK;
2444         val = allow ? mask : 0;
2445
2446         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2447         if (err)
2448                 DRM_ERROR("timeout disabling GT waking\n");
2449
2450         return err;
2451 }
2452
2453 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2454                                   bool wait_for_on)
2455 {
2456         u32 mask;
2457         u32 val;
2458
2459         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2460         val = wait_for_on ? mask : 0;
2461
2462         /*
2463          * RC6 transitioning can be delayed up to 2 msec (see
2464          * valleyview_enable_rps), use 3 msec for safety.
2465          */
2466         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2467                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2468                           onoff(wait_for_on));
2469 }
2470
2471 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2472 {
2473         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2474                 return;
2475
2476         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2477         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2478 }
2479
2480 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2481 {
2482         u32 mask;
2483         int err;
2484
2485         /*
2486          * Bspec defines the following GT well on flags as debug only, so
2487          * don't treat them as hard failures.
2488          */
2489         vlv_wait_for_gt_wells(dev_priv, false);
2490
2491         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2492         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2493
2494         vlv_check_no_gt_access(dev_priv);
2495
2496         err = vlv_force_gfx_clock(dev_priv, true);
2497         if (err)
2498                 goto err1;
2499
2500         err = vlv_allow_gt_wake(dev_priv, false);
2501         if (err)
2502                 goto err2;
2503
2504         if (!IS_CHERRYVIEW(dev_priv))
2505                 vlv_save_gunit_s0ix_state(dev_priv);
2506
2507         err = vlv_force_gfx_clock(dev_priv, false);
2508         if (err)
2509                 goto err2;
2510
2511         return 0;
2512
2513 err2:
2514         /* For safety always re-enable waking and disable gfx clock forcing */
2515         vlv_allow_gt_wake(dev_priv, true);
2516 err1:
2517         vlv_force_gfx_clock(dev_priv, false);
2518
2519         return err;
2520 }
2521
2522 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2523                                 bool rpm_resume)
2524 {
2525         int err;
2526         int ret;
2527
2528         /*
2529          * If any of the steps fail just try to continue, that's the best we
2530          * can do at this point. Return the first error code (which will also
2531          * leave RPM permanently disabled).
2532          */
2533         ret = vlv_force_gfx_clock(dev_priv, true);
2534
2535         if (!IS_CHERRYVIEW(dev_priv))
2536                 vlv_restore_gunit_s0ix_state(dev_priv);
2537
2538         err = vlv_allow_gt_wake(dev_priv, true);
2539         if (!ret)
2540                 ret = err;
2541
2542         err = vlv_force_gfx_clock(dev_priv, false);
2543         if (!ret)
2544                 ret = err;
2545
2546         vlv_check_no_gt_access(dev_priv);
2547
2548         if (rpm_resume)
2549                 intel_init_clock_gating(dev_priv);
2550
2551         return ret;
2552 }
2553
2554 static int intel_runtime_suspend(struct device *kdev)
2555 {
2556         struct pci_dev *pdev = to_pci_dev(kdev);
2557         struct drm_device *dev = pci_get_drvdata(pdev);
2558         struct drm_i915_private *dev_priv = to_i915(dev);
2559         int ret;
2560
2561         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2562                 return -ENODEV;
2563
2564         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2565                 return -ENODEV;
2566
2567         DRM_DEBUG_KMS("Suspending device\n");
2568
2569         disable_rpm_wakeref_asserts(dev_priv);
2570
2571         /*
2572          * We are safe here against re-faults, since the fault handler takes
2573          * an RPM reference.
2574          */
2575         i915_gem_runtime_suspend(dev_priv);
2576
2577         intel_uc_suspend(dev_priv);
2578
2579         intel_runtime_pm_disable_interrupts(dev_priv);
2580
2581         intel_uncore_suspend(dev_priv);
2582
2583         ret = 0;
2584         if (IS_GEN9_LP(dev_priv)) {
2585                 bxt_display_core_uninit(dev_priv);
2586                 bxt_enable_dc9(dev_priv);
2587         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2588                 hsw_enable_pc8(dev_priv);
2589         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2590                 ret = vlv_suspend_complete(dev_priv);
2591         }
2592
2593         if (ret) {
2594                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2595                 intel_uncore_runtime_resume(dev_priv);
2596
2597                 intel_runtime_pm_enable_interrupts(dev_priv);
2598
2599                 intel_uc_resume(dev_priv);
2600
2601                 i915_gem_init_swizzling(dev_priv);
2602                 i915_gem_restore_fences(dev_priv);
2603
2604                 enable_rpm_wakeref_asserts(dev_priv);
2605
2606                 return ret;
2607         }
2608
2609         enable_rpm_wakeref_asserts(dev_priv);
2610         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2611
2612         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2613                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2614
2615         dev_priv->runtime_pm.suspended = true;
2616
2617         /*
2618          * FIXME: We really should find a document that references the arguments
2619          * used below!
2620          */
2621         if (IS_BROADWELL(dev_priv)) {
2622                 /*
2623                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2624                  * being detected, and the call we do at intel_runtime_resume()
2625                  * won't be able to restore them. Since PCI_D3hot matches the
2626                  * actual specification and appears to be working, use it.
2627                  */
2628                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2629         } else {
2630                 /*
2631                  * current versions of firmware which depend on this opregion
2632                  * notification have repurposed the D1 definition to mean
2633                  * "runtime suspended" vs. what you would normally expect (D3)
2634                  * to distinguish it from notifications that might be sent via
2635                  * the suspend path.
2636                  */
2637                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2638         }
2639
2640         assert_forcewakes_inactive(dev_priv);
2641
2642         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2643                 intel_hpd_poll_init(dev_priv);
2644
2645         DRM_DEBUG_KMS("Device suspended\n");
2646         return 0;
2647 }
2648
2649 static int intel_runtime_resume(struct device *kdev)
2650 {
2651         struct pci_dev *pdev = to_pci_dev(kdev);
2652         struct drm_device *dev = pci_get_drvdata(pdev);
2653         struct drm_i915_private *dev_priv = to_i915(dev);
2654         int ret = 0;
2655
2656         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2657                 return -ENODEV;
2658
2659         DRM_DEBUG_KMS("Resuming device\n");
2660
2661         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2662         disable_rpm_wakeref_asserts(dev_priv);
2663
2664         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2665         dev_priv->runtime_pm.suspended = false;
2666         if (intel_uncore_unclaimed_mmio(dev_priv))
2667                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2668
2669         if (IS_GEN9_LP(dev_priv)) {
2670                 bxt_disable_dc9(dev_priv);
2671                 bxt_display_core_init(dev_priv, true);
2672                 if (dev_priv->csr.dmc_payload &&
2673                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2674                         gen9_enable_dc5(dev_priv);
2675         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2676                 hsw_disable_pc8(dev_priv);
2677         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2678                 ret = vlv_resume_prepare(dev_priv, true);
2679         }
2680
2681         intel_uncore_runtime_resume(dev_priv);
2682
2683         intel_runtime_pm_enable_interrupts(dev_priv);
2684
2685         intel_uc_resume(dev_priv);
2686
2687         /*
2688          * No point of rolling back things in case of an error, as the best
2689          * we can do is to hope that things will still work (and disable RPM).
2690          */
2691         i915_gem_init_swizzling(dev_priv);
2692         i915_gem_restore_fences(dev_priv);
2693
2694         /*
2695          * On VLV/CHV display interrupts are part of the display
2696          * power well, so hpd is reinitialized from there. For
2697          * everyone else do it here.
2698          */
2699         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2700                 intel_hpd_init(dev_priv);
2701
2702         intel_enable_ipc(dev_priv);
2703
2704         enable_rpm_wakeref_asserts(dev_priv);
2705
2706         if (ret)
2707                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2708         else
2709                 DRM_DEBUG_KMS("Device resumed\n");
2710
2711         return ret;
2712 }
2713
2714 const struct dev_pm_ops i915_pm_ops = {
2715         /*
2716          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2717          * PMSG_RESUME]
2718          */
2719         .suspend = i915_pm_suspend,
2720         .suspend_late = i915_pm_suspend_late,
2721         .resume_early = i915_pm_resume_early,
2722         .resume = i915_pm_resume,
2723
2724         /*
2725          * S4 event handlers
2726          * @freeze, @freeze_late    : called (1) before creating the
2727          *                            hibernation image [PMSG_FREEZE] and
2728          *                            (2) after rebooting, before restoring
2729          *                            the image [PMSG_QUIESCE]
2730          * @thaw, @thaw_early       : called (1) after creating the hibernation
2731          *                            image, before writing it [PMSG_THAW]
2732          *                            and (2) after failing to create or
2733          *                            restore the image [PMSG_RECOVER]
2734          * @poweroff, @poweroff_late: called after writing the hibernation
2735          *                            image, before rebooting [PMSG_HIBERNATE]
2736          * @restore, @restore_early : called after rebooting and restoring the
2737          *                            hibernation image [PMSG_RESTORE]
2738          */
2739         .freeze = i915_pm_freeze,
2740         .freeze_late = i915_pm_freeze_late,
2741         .thaw_early = i915_pm_thaw_early,
2742         .thaw = i915_pm_thaw,
2743         .poweroff = i915_pm_suspend,
2744         .poweroff_late = i915_pm_poweroff_late,
2745         .restore_early = i915_pm_restore_early,
2746         .restore = i915_pm_restore,
2747
2748         /* S0ix (via runtime suspend) event handlers */
2749         .runtime_suspend = intel_runtime_suspend,
2750         .runtime_resume = intel_runtime_resume,
2751 };
2752
2753 static const struct vm_operations_struct i915_gem_vm_ops = {
2754         .fault = i915_gem_fault,
2755         .open = drm_gem_vm_open,
2756         .close = drm_gem_vm_close,
2757 };
2758
2759 static const struct file_operations i915_driver_fops = {
2760         .owner = THIS_MODULE,
2761         .open = drm_open,
2762         .release = drm_release,
2763         .unlocked_ioctl = drm_ioctl,
2764         .mmap = drm_gem_mmap,
2765         .poll = drm_poll,
2766         .read = drm_read,
2767         .compat_ioctl = i915_compat_ioctl,
2768         .llseek = noop_llseek,
2769 };
2770
2771 static int
2772 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2773                           struct drm_file *file)
2774 {
2775         return -ENODEV;
2776 }
2777
2778 static const struct drm_ioctl_desc i915_ioctls[] = {
2779         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2780         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2781         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2782         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2783         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2784         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2785         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2786         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2787         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2788         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2789         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2790         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2791         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2792         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2793         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2794         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2795         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2796         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2797         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2798         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2799         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2800         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2801         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2802         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2803         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2804         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2805         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2806         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2807         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2808         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2809         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2810         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2811         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2812         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2813         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2814         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2815         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2816         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2817         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2818         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2819         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2820         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2821         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2822         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2823         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2824         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2825         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2826         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2827         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2828         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2829         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2830         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2831         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2832         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2833         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2834         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2835 };
2836
2837 static struct drm_driver driver = {
2838         /* Don't use MTRRs here; the Xserver or userspace app should
2839          * deal with them for Intel hardware.
2840          */
2841         .driver_features =
2842             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2843             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2844         .release = i915_driver_release,
2845         .open = i915_driver_open,
2846         .lastclose = i915_driver_lastclose,
2847         .postclose = i915_driver_postclose,
2848
2849         .gem_close_object = i915_gem_close_object,
2850         .gem_free_object_unlocked = i915_gem_free_object,
2851         .gem_vm_ops = &i915_gem_vm_ops,
2852
2853         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2854         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2855         .gem_prime_export = i915_gem_prime_export,
2856         .gem_prime_import = i915_gem_prime_import,
2857
2858         .dumb_create = i915_gem_dumb_create,
2859         .dumb_map_offset = i915_gem_mmap_gtt,
2860         .ioctls = i915_ioctls,
2861         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2862         .fops = &i915_driver_fops,
2863         .name = DRIVER_NAME,
2864         .desc = DRIVER_DESC,
2865         .date = DRIVER_DATE,
2866         .major = DRIVER_MAJOR,
2867         .minor = DRIVER_MINOR,
2868         .patchlevel = DRIVER_PATCHLEVEL,
2869 };
2870
2871 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2872 #include "selftests/mock_drm.c"
2873 #endif