drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_irq.h>
  47 #include <drm/drm_probe_helper.h>
  48 #include <drm/i915_drm.h>
  49
  50 #include "display/intel_acpi.h"
  51 #include "display/intel_audio.h"
  52 #include "display/intel_bw.h"
  53 #include "display/intel_cdclk.h"
  54 #include "display/intel_display_types.h"
  55 #include "display/intel_dp.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_gmbus.h"
  58 #include "display/intel_hotplug.h"
  59 #include "display/intel_overlay.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_sprite.h"
  62
  63 #include "gem/i915_gem_context.h"
  64 #include "gem/i915_gem_ioctls.h"
  65 #include "gt/intel_gt.h"
  66 #include "gt/intel_gt_pm.h"
  67
  68 #include "i915_debugfs.h"
  69 #include "i915_drv.h"
  70 #include "i915_irq.h"
  71 #include "i915_memcpy.h"
  72 #include "i915_perf.h"
  73 #include "i915_query.h"
  74 #include "i915_suspend.h"
  75 #include "i915_sysfs.h"
  76 #include "i915_trace.h"
  77 #include "i915_vgpu.h"
  78 #include "intel_csr.h"
  79 #include "intel_pm.h"
  80
  81 static struct drm_driver driver;
  82
  83 struct vlv_s0ix_state {
  84         /* GAM */
  85         u32 wr_watermark;
  86         u32 gfx_prio_ctrl;
  87         u32 arb_mode;
  88         u32 gfx_pend_tlb0;
  89         u32 gfx_pend_tlb1;
  90         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
  91         u32 media_max_req_count;
  92         u32 gfx_max_req_count;
  93         u32 render_hwsp;
  94         u32 ecochk;
  95         u32 bsd_hwsp;
  96         u32 blt_hwsp;
  97         u32 tlb_rd_addr;
  98
  99         /* MBC */
 100         u32 g3dctl;
 101         u32 gsckgctl;
 102         u32 mbctl;
 103
 104         /* GCP */
 105         u32 ucgctl1;
 106         u32 ucgctl3;
 107         u32 rcgctl1;
 108         u32 rcgctl2;
 109         u32 rstctl;
 110         u32 misccpctl;
 111
 112         /* GPM */
 113         u32 gfxpause;
 114         u32 rpdeuhwtc;
 115         u32 rpdeuc;
 116         u32 ecobus;
 117         u32 pwrdwnupctl;
 118         u32 rp_down_timeout;
 119         u32 rp_deucsw;
 120         u32 rcubmabdtmr;
 121         u32 rcedata;
 122         u32 spare2gh;
 123
 124         /* Display 1 CZ domain */
 125         u32 gt_imr;
 126         u32 gt_ier;
 127         u32 pm_imr;
 128         u32 pm_ier;
 129         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
 130
 131         /* GT SA CZ domain */
 132         u32 tilectl;
 133         u32 gt_fifoctl;
 134         u32 gtlc_wake_ctrl;
 135         u32 gtlc_survive;
 136         u32 pmwgicz;
 137
 138         /* Display 2 CZ domain */
 139         u32 gu_ctl0;
 140         u32 gu_ctl1;
 141         u32 pcbr;
 142         u32 clock_gate_dis2;
 143 };
 144
 145 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 146 {
 147         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 148
 149         dev_priv->bridge_dev =
 150                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 151         if (!dev_priv->bridge_dev) {
 152                 DRM_ERROR("bridge device not found\n");
 153                 return -1;
 154         }
 155         return 0;
 156 }
 157
 158 /* Allocate space for the MCH regs if needed, return nonzero on error */
 159 static int
 160 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 161 {
 162         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 163         u32 temp_lo, temp_hi = 0;
 164         u64 mchbar_addr;
 165         int ret;
 166
 167         if (INTEL_GEN(dev_priv) >= 4)
 168                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 169         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 170         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 171
 172         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 173 #ifdef CONFIG_PNP
 174         if (mchbar_addr &&
 175             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 176                 return 0;
 177 #endif
 178
 179         /* Get some space for it */
 180         dev_priv->mch_res.name = "i915 MCHBAR";
 181         dev_priv->mch_res.flags = IORESOURCE_MEM;
 182         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 183                                      &dev_priv->mch_res,
 184                                      MCHBAR_SIZE, MCHBAR_SIZE,
 185                                      PCIBIOS_MIN_MEM,
 186                                      0, pcibios_align_resource,
 187                                      dev_priv->bridge_dev);
 188         if (ret) {
 189                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 190                 dev_priv->mch_res.start = 0;
 191                 return ret;
 192         }
 193
 194         if (INTEL_GEN(dev_priv) >= 4)
 195                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 196                                        upper_32_bits(dev_priv->mch_res.start));
 197
 198         pci_write_config_dword(dev_priv->bridge_dev, reg,
 199                                lower_32_bits(dev_priv->mch_res.start));
 200         return 0;
 201 }
 202
 203 /* Setup MCHBAR if possible, return true if we should disable it again */
 204 static void
 205 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 206 {
 207         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 208         u32 temp;
 209         bool enabled;
 210
 211         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 212                 return;
 213
 214         dev_priv->mchbar_need_disable = false;
 215
 216         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 217                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 218                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 219         } else {
 220                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 221                 enabled = temp & 1;
 222         }
 223
 224         /* If it's already enabled, don't have to do anything */
 225         if (enabled)
 226                 return;
 227
 228         if (intel_alloc_mchbar_resource(dev_priv))
 229                 return;
 230
 231         dev_priv->mchbar_need_disable = true;
 232
 233         /* Space is allocated or reserved, so enable it. */
 234         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 235                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 236                                        temp | DEVEN_MCHBAR_EN);
 237         } else {
 238                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 239                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 240         }
 241 }
 242
 243 static void
 244 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 245 {
 246         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 247
 248         if (dev_priv->mchbar_need_disable) {
 249                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 250                         u32 deven_val;
 251
 252                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 253                                               &deven_val);
 254                         deven_val &= ~DEVEN_MCHBAR_EN;
 255                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 256                                                deven_val);
 257                 } else {
 258                         u32 mchbar_val;
 259
 260                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 261                                               &mchbar_val);
 262                         mchbar_val &= ~1;
 263                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 264                                                mchbar_val);
 265                 }
 266         }
 267
 268         if (dev_priv->mch_res.start)
 269                 release_resource(&dev_priv->mch_res);
 270 }
 271
 272 /* true = enable decode, false = disable decoder */
 273 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 274 {
 275         struct drm_i915_private *dev_priv = cookie;
 276
 277         intel_modeset_vga_set_state(dev_priv, state);
 278         if (state)
 279                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 280                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 281         else
 282                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 283 }
 284
 285 static int i915_resume_switcheroo(struct drm_i915_private *i915);
 286 static int i915_suspend_switcheroo(struct drm_i915_private *i915,
 287                                    pm_message_t state);
 288
 289 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 290 {
 291         struct drm_i915_private *i915 = pdev_to_i915(pdev);
 292         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 293
 294         if (!i915) {
 295                 dev_err(&pdev->dev, "DRM not initialized, aborting switch.\n");
 296                 return;
 297         }
 298
 299         if (state == VGA_SWITCHEROO_ON) {
 300                 pr_info("switched on\n");
 301                 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
 302                 /* i915 resume handler doesn't set to D0 */
 303                 pci_set_power_state(pdev, PCI_D0);
 304                 i915_resume_switcheroo(i915);
 305                 i915->drm.switch_power_state = DRM_SWITCH_POWER_ON;
 306         } else {
 307                 pr_info("switched off\n");
 308                 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
 309                 i915_suspend_switcheroo(i915, pmm);
 310                 i915->drm.switch_power_state = DRM_SWITCH_POWER_OFF;
 311         }
 312 }
 313
 314 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 315 {
 316         struct drm_i915_private *i915 = pdev_to_i915(pdev);
 317
 318         /*
 319          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 320          * locking inversion with the driver load path. And the access here is
 321          * completely racy anyway. So don't bother with locking for now.
 322          */
 323         return i915 && i915->drm.open_count == 0;
 324 }
 325
 326 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 327         .set_gpu_state = i915_switcheroo_set_state,
 328         .reprobe = NULL,
 329         .can_switch = i915_switcheroo_can_switch,
 330 };
 331
 332 static int i915_driver_modeset_probe(struct drm_device *dev)
 333 {
 334         struct drm_i915_private *dev_priv = to_i915(dev);
 335         struct pci_dev *pdev = dev_priv->drm.pdev;
 336         int ret;
 337
 338         if (i915_inject_probe_failure(dev_priv))
 339                 return -ENODEV;
 340
 341         if (HAS_DISPLAY(dev_priv)) {
 342                 ret = drm_vblank_init(&dev_priv->drm,
 343                                       INTEL_INFO(dev_priv)->num_pipes);
 344                 if (ret)
 345                         goto out;
 346         }
 347
 348         intel_bios_init(dev_priv);
 349
 350         /* If we have > 1 VGA cards, then we need to arbitrate access
 351          * to the common VGA resources.
 352          *
 353          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 354          * then we do not take part in VGA arbitration and the
 355          * vga_client_register() fails with -ENODEV.
 356          */
 357         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 358         if (ret && ret != -ENODEV)
 359                 goto out;
 360
 361         intel_register_dsm_handler();
 362
 363         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 364         if (ret)
 365                 goto cleanup_vga_client;
 366
 367         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 368         intel_update_rawclk(dev_priv);
 369
 370         intel_power_domains_init_hw(dev_priv, false);
 371
 372         intel_csr_ucode_init(dev_priv);
 373
 374         ret = intel_irq_install(dev_priv);
 375         if (ret)
 376                 goto cleanup_csr;
 377
 378         intel_gmbus_setup(dev_priv);
 379
 380         /* Important: The output setup functions called by modeset_init need
 381          * working irqs for e.g. gmbus and dp aux transfers. */
 382         ret = intel_modeset_init(dev);
 383         if (ret)
 384                 goto cleanup_irq;
 385
 386         ret = i915_gem_init(dev_priv);
 387         if (ret)
 388                 goto cleanup_modeset;
 389
 390         intel_overlay_setup(dev_priv);
 391
 392         if (!HAS_DISPLAY(dev_priv))
 393                 return 0;
 394
 395         ret = intel_fbdev_init(dev);
 396         if (ret)
 397                 goto cleanup_gem;
 398
 399         /* Only enable hotplug handling once the fbdev is fully set up. */
 400         intel_hpd_init(dev_priv);
 401
 402         intel_init_ipc(dev_priv);
 403
 404         return 0;
 405
 406 cleanup_gem:
 407         i915_gem_suspend(dev_priv);
 408         i915_gem_driver_remove(dev_priv);
 409         i915_gem_driver_release(dev_priv);
 410 cleanup_modeset:
 411         intel_modeset_driver_remove(dev);
 412 cleanup_irq:
 413         intel_irq_uninstall(dev_priv);
 414         intel_gmbus_teardown(dev_priv);
 415 cleanup_csr:
 416         intel_csr_ucode_fini(dev_priv);
 417         intel_power_domains_driver_remove(dev_priv);
 418         vga_switcheroo_unregister_client(pdev);
 419 cleanup_vga_client:
 420         vga_client_register(pdev, NULL, NULL, NULL);
 421 out:
 422         return ret;
 423 }
 424
 425 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 426 {
 427         struct apertures_struct *ap;
 428         struct pci_dev *pdev = dev_priv->drm.pdev;
 429         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 430         bool primary;
 431         int ret;
 432
 433         ap = alloc_apertures(1);
 434         if (!ap)
 435                 return -ENOMEM;
 436
 437         ap->ranges[0].base = ggtt->gmadr.start;
 438         ap->ranges[0].size = ggtt->mappable_end;
 439
 440         primary =
 441                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 442
 443         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 444
 445         kfree(ap);
 446
 447         return ret;
 448 }
 449
 450 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 451 {
 452         /*
 453          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 454          * CHV x1 PHY (DP/HDMI D)
 455          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 456          */
 457         if (IS_CHERRYVIEW(dev_priv)) {
 458                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 459                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 460         } else if (IS_VALLEYVIEW(dev_priv)) {
 461                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 462         }
 463 }
 464
 465 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 466 {
 467         /*
 468          * The i915 workqueue is primarily used for batched retirement of
 469          * requests (and thus managing bo) once the task has been completed
 470          * by the GPU. i915_retire_requests() is called directly when we
 471          * need high-priority retirement, such as waiting for an explicit
 472          * bo.
 473          *
 474          * It is also used for periodic low-priority events, such as
 475          * idle-timers and recording error state.
 476          *
 477          * All tasks on the workqueue are expected to acquire the dev mutex
 478          * so there is no point in running more than one instance of the
 479          * workqueue at any time.  Use an ordered one.
 480          */
 481         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 482         if (dev_priv->wq == NULL)
 483                 goto out_err;
 484
 485         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 486         if (dev_priv->hotplug.dp_wq == NULL)
 487                 goto out_free_wq;
 488
 489         return 0;
 490
 491 out_free_wq:
 492         destroy_workqueue(dev_priv->wq);
 493 out_err:
 494         DRM_ERROR("Failed to allocate workqueues.\n");
 495
 496         return -ENOMEM;
 497 }
 498
 499 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 500 {
 501         destroy_workqueue(dev_priv->hotplug.dp_wq);
 502         destroy_workqueue(dev_priv->wq);
 503 }
 504
 505 /*
 506  * We don't keep the workarounds for pre-production hardware, so we expect our
 507  * driver to fail on these machines in one way or another. A little warning on
 508  * dmesg may help both the user and the bug triagers.
 509  *
 510  * Our policy for removing pre-production workarounds is to keep the
 511  * current gen workarounds as a guide to the bring-up of the next gen
 512  * (workarounds have a habit of persisting!). Anything older than that
 513  * should be removed along with the complications they introduce.
 514  */
 515 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 516 {
 517         bool pre = false;
 518
 519         pre |= IS_HSW_EARLY_SDV(dev_priv);
 520         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 521         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 522         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 523
 524         if (pre) {
 525                 DRM_ERROR("This is a pre-production stepping. "
 526                           "It may not be fully functional.\n");
 527                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 528         }
 529 }
 530
 531 static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
 532 {
 533         if (!IS_VALLEYVIEW(i915))
 534                 return 0;
 535
 536         /* we write all the values in the struct, so no need to zero it out */
 537         i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state),
 538                                        GFP_KERNEL);
 539         if (!i915->vlv_s0ix_state)
 540                 return -ENOMEM;
 541
 542         return 0;
 543 }
 544
 545 static void vlv_free_s0ix_state(struct drm_i915_private *i915)
 546 {
 547         if (!i915->vlv_s0ix_state)
 548                 return;
 549
 550         kfree(i915->vlv_s0ix_state);
 551         i915->vlv_s0ix_state = NULL;
 552 }
 553
 554 /**
 555  * i915_driver_early_probe - setup state not requiring device access
 556  * @dev_priv: device private
 557  *
 558  * Initialize everything that is a "SW-only" state, that is state not
 559  * requiring accessing the device or exposing the driver via kernel internal
 560  * or userspace interfaces. Example steps belonging here: lock initialization,
 561  * system memory allocation, setting up device specific attributes and
 562  * function hooks not requiring accessing the device.
 563  */
 564 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 565 {
 566         int ret = 0;
 567
 568         if (i915_inject_probe_failure(dev_priv))
 569                 return -ENODEV;
 570
 571         intel_device_info_subplatform_init(dev_priv);
 572
 573         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 574         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 575
 576         spin_lock_init(&dev_priv->irq_lock);
 577         spin_lock_init(&dev_priv->gpu_error.lock);
 578         mutex_init(&dev_priv->backlight_lock);
 579
 580         mutex_init(&dev_priv->sb_lock);
 581         pm_qos_add_request(&dev_priv->sb_qos,
 582                            PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
 583
 584         mutex_init(&dev_priv->av_mutex);
 585         mutex_init(&dev_priv->wm.wm_mutex);
 586         mutex_init(&dev_priv->pps_mutex);
 587         mutex_init(&dev_priv->hdcp_comp_mutex);
 588
 589         i915_memcpy_init_early(dev_priv);
 590         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 591
 592         ret = i915_workqueues_init(dev_priv);
 593         if (ret < 0)
 594                 return ret;
 595
 596         ret = vlv_alloc_s0ix_state(dev_priv);
 597         if (ret < 0)
 598                 goto err_workqueues;
 599
 600         intel_wopcm_init_early(&dev_priv->wopcm);
 601
 602         intel_gt_init_early(&dev_priv->gt, dev_priv);
 603
 604         ret = i915_gem_init_early(dev_priv);
 605         if (ret < 0)
 606                 goto err_gt;
 607
 608         /* This must be called before any calls to HAS_PCH_* */
 609         intel_detect_pch(dev_priv);
 610
 611         intel_pm_setup(dev_priv);
 612         intel_init_dpio(dev_priv);
 613         ret = intel_power_domains_init(dev_priv);
 614         if (ret < 0)
 615                 goto err_gem;
 616         intel_irq_init(dev_priv);
 617         intel_init_display_hooks(dev_priv);
 618         intel_init_clock_gating_hooks(dev_priv);
 619         intel_init_audio_hooks(dev_priv);
 620         intel_display_crc_init(dev_priv);
 621
 622         intel_detect_preproduction_hw(dev_priv);
 623
 624         return 0;
 625
 626 err_gem:
 627         i915_gem_cleanup_early(dev_priv);
 628 err_gt:
 629         intel_gt_driver_late_release(&dev_priv->gt);
 630         vlv_free_s0ix_state(dev_priv);
 631 err_workqueues:
 632         i915_workqueues_cleanup(dev_priv);
 633         return ret;
 634 }
 635
 636 /**
 637  * i915_driver_late_release - cleanup the setup done in
 638  *                             i915_driver_early_probe()
 639  * @dev_priv: device private
 640  */
 641 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 642 {
 643         intel_irq_fini(dev_priv);
 644         intel_power_domains_cleanup(dev_priv);
 645         i915_gem_cleanup_early(dev_priv);
 646         intel_gt_driver_late_release(&dev_priv->gt);
 647         vlv_free_s0ix_state(dev_priv);
 648         i915_workqueues_cleanup(dev_priv);
 649
 650         pm_qos_remove_request(&dev_priv->sb_qos);
 651         mutex_destroy(&dev_priv->sb_lock);
 652 }
 653
 654 /**
 655  * i915_driver_mmio_probe - setup device MMIO
 656  * @dev_priv: device private
 657  *
 658  * Setup minimal device state necessary for MMIO accesses later in the
 659  * initialization sequence. The setup here should avoid any other device-wide
 660  * side effects or exposing the driver via kernel internal or user space
 661  * interfaces.
 662  */
 663 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 664 {
 665         int ret;
 666
 667         if (i915_inject_probe_failure(dev_priv))
 668                 return -ENODEV;
 669
 670         if (i915_get_bridge_dev(dev_priv))
 671                 return -EIO;
 672
 673         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 674         if (ret < 0)
 675                 goto err_bridge;
 676
 677         /* Try to make sure MCHBAR is enabled before poking at it */
 678         intel_setup_mchbar(dev_priv);
 679
 680         intel_device_info_init_mmio(dev_priv);
 681
 682         intel_uncore_prune_mmio_domains(&dev_priv->uncore);
 683
 684         intel_uc_init_mmio(&dev_priv->gt.uc);
 685
 686         ret = intel_engines_init_mmio(dev_priv);
 687         if (ret)
 688                 goto err_uncore;
 689
 690         i915_gem_init_mmio(dev_priv);
 691
 692         return 0;
 693
 694 err_uncore:
 695         intel_teardown_mchbar(dev_priv);
 696         intel_uncore_fini_mmio(&dev_priv->uncore);
 697 err_bridge:
 698         pci_dev_put(dev_priv->bridge_dev);
 699
 700         return ret;
 701 }
 702
 703 /**
 704  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 705  * @dev_priv: device private
 706  */
 707 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 708 {
 709         intel_engines_cleanup(dev_priv);
 710         intel_teardown_mchbar(dev_priv);
 711         intel_uncore_fini_mmio(&dev_priv->uncore);
 712         pci_dev_put(dev_priv->bridge_dev);
 713 }
 714
 715 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 716 {
 717         intel_gvt_sanitize_options(dev_priv);
 718 }
 719
 720 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
 721
 722 static const char *intel_dram_type_str(enum intel_dram_type type)
 723 {
 724         static const char * const str[] = {
 725                 DRAM_TYPE_STR(UNKNOWN),
 726                 DRAM_TYPE_STR(DDR3),
 727                 DRAM_TYPE_STR(DDR4),
 728                 DRAM_TYPE_STR(LPDDR3),
 729                 DRAM_TYPE_STR(LPDDR4),
 730         };
 731
 732         if (type >= ARRAY_SIZE(str))
 733                 type = INTEL_DRAM_UNKNOWN;
 734
 735         return str[type];
 736 }
 737
 738 #undef DRAM_TYPE_STR
 739
 740 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
 741 {
 742         return dimm->ranks * 64 / (dimm->width ?: 1);
 743 }
 744
 745 /* Returns total GB for the whole DIMM */
 746 static int skl_get_dimm_size(u16 val)
 747 {
 748         return val & SKL_DRAM_SIZE_MASK;
 749 }
 750
 751 static int skl_get_dimm_width(u16 val)
 752 {
 753         if (skl_get_dimm_size(val) == 0)
 754                 return 0;
 755
 756         switch (val & SKL_DRAM_WIDTH_MASK) {
 757         case SKL_DRAM_WIDTH_X8:
 758         case SKL_DRAM_WIDTH_X16:
 759         case SKL_DRAM_WIDTH_X32:
 760                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
 761                 return 8 << val;
 762         default:
 763                 MISSING_CASE(val);
 764                 return 0;
 765         }
 766 }
 767
 768 static int skl_get_dimm_ranks(u16 val)
 769 {
 770         if (skl_get_dimm_size(val) == 0)
 771                 return 0;
 772
 773         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
 774
 775         return val + 1;
 776 }
 777
 778 /* Returns total GB for the whole DIMM */
 779 static int cnl_get_dimm_size(u16 val)
 780 {
 781         return (val & CNL_DRAM_SIZE_MASK) / 2;
 782 }
 783
 784 static int cnl_get_dimm_width(u16 val)
 785 {
 786         if (cnl_get_dimm_size(val) == 0)
 787                 return 0;
 788
 789         switch (val & CNL_DRAM_WIDTH_MASK) {
 790         case CNL_DRAM_WIDTH_X8:
 791         case CNL_DRAM_WIDTH_X16:
 792         case CNL_DRAM_WIDTH_X32:
 793                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
 794                 return 8 << val;
 795         default:
 796                 MISSING_CASE(val);
 797                 return 0;
 798         }
 799 }
 800
 801 static int cnl_get_dimm_ranks(u16 val)
 802 {
 803         if (cnl_get_dimm_size(val) == 0)
 804                 return 0;
 805
 806         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
 807
 808         return val + 1;
 809 }
 810
 811 static bool
 812 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
 813 {
 814         /* Convert total GB to Gb per DRAM device */
 815         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
 816 }
 817
 818 static void
 819 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
 820                        struct dram_dimm_info *dimm,
 821                        int channel, char dimm_name, u16 val)
 822 {
 823         if (INTEL_GEN(dev_priv) >= 10) {
 824                 dimm->size = cnl_get_dimm_size(val);
 825                 dimm->width = cnl_get_dimm_width(val);
 826                 dimm->ranks = cnl_get_dimm_ranks(val);
 827         } else {
 828                 dimm->size = skl_get_dimm_size(val);
 829                 dimm->width = skl_get_dimm_width(val);
 830                 dimm->ranks = skl_get_dimm_ranks(val);
 831         }
 832
 833         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
 834                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
 835                       yesno(skl_is_16gb_dimm(dimm)));
 836 }
 837
 838 static int
 839 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
 840                           struct dram_channel_info *ch,
 841                           int channel, u32 val)
 842 {
 843         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
 844                                channel, 'L', val & 0xffff);
 845         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
 846                                channel, 'S', val >> 16);
 847
 848         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
 849                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
 850                 return -EINVAL;
 851         }
 852
 853         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
 854                 ch->ranks = 2;
 855         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
 856                 ch->ranks = 2;
 857         else
 858                 ch->ranks = 1;
 859
 860         ch->is_16gb_dimm =
 861                 skl_is_16gb_dimm(&ch->dimm_l) ||
 862                 skl_is_16gb_dimm(&ch->dimm_s);
 863
 864         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
 865                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
 866
 867         return 0;
 868 }
 869
 870 static bool
 871 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
 872                         const struct dram_channel_info *ch1)
 873 {
 874         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
 875                 (ch0->dimm_s.size == 0 ||
 876                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
 877 }
 878
 879 static int
 880 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 881 {
 882         struct dram_info *dram_info = &dev_priv->dram_info;
 883         struct dram_channel_info ch0 = {}, ch1 = {};
 884         u32 val;
 885         int ret;
 886
 887         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 888         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
 889         if (ret == 0)
 890                 dram_info->num_channels++;
 891
 892         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 893         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
 894         if (ret == 0)
 895                 dram_info->num_channels++;
 896
 897         if (dram_info->num_channels == 0) {
 898                 DRM_INFO("Number of memory channels is zero\n");
 899                 return -EINVAL;
 900         }
 901
 902         /*
 903          * If any of the channel is single rank channel, worst case output
 904          * will be same as if single rank memory, so consider single rank
 905          * memory.
 906          */
 907         if (ch0.ranks == 1 || ch1.ranks == 1)
 908                 dram_info->ranks = 1;
 909         else
 910                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
 911
 912         if (dram_info->ranks == 0) {
 913                 DRM_INFO("couldn't get memory rank information\n");
 914                 return -EINVAL;
 915         }
 916
 917         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
 918
 919         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
 920
 921         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
 922                       yesno(dram_info->symmetric_memory));
 923         return 0;
 924 }
 925
 926 static enum intel_dram_type
 927 skl_get_dram_type(struct drm_i915_private *dev_priv)
 928 {
 929         u32 val;
 930
 931         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 932
 933         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
 934         case SKL_DRAM_DDR_TYPE_DDR3:
 935                 return INTEL_DRAM_DDR3;
 936         case SKL_DRAM_DDR_TYPE_DDR4:
 937                 return INTEL_DRAM_DDR4;
 938         case SKL_DRAM_DDR_TYPE_LPDDR3:
 939                 return INTEL_DRAM_LPDDR3;
 940         case SKL_DRAM_DDR_TYPE_LPDDR4:
 941                 return INTEL_DRAM_LPDDR4;
 942         default:
 943                 MISSING_CASE(val);
 944                 return INTEL_DRAM_UNKNOWN;
 945         }
 946 }
 947
 948 static int
 949 skl_get_dram_info(struct drm_i915_private *dev_priv)
 950 {
 951         struct dram_info *dram_info = &dev_priv->dram_info;
 952         u32 mem_freq_khz, val;
 953         int ret;
 954
 955         dram_info->type = skl_get_dram_type(dev_priv);
 956         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
 957
 958         ret = skl_dram_get_channels_info(dev_priv);
 959         if (ret)
 960                 return ret;
 961
 962         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
 963         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
 964                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 965
 966         dram_info->bandwidth_kbps = dram_info->num_channels *
 967                                                         mem_freq_khz * 8;
 968
 969         if (dram_info->bandwidth_kbps == 0) {
 970                 DRM_INFO("Couldn't get system memory bandwidth\n");
 971                 return -EINVAL;
 972         }
 973
 974         dram_info->valid = true;
 975         return 0;
 976 }
 977
 978 /* Returns Gb per DRAM device */
 979 static int bxt_get_dimm_size(u32 val)
 980 {
 981         switch (val & BXT_DRAM_SIZE_MASK) {
 982         case BXT_DRAM_SIZE_4GBIT:
 983                 return 4;
 984         case BXT_DRAM_SIZE_6GBIT:
 985                 return 6;
 986         case BXT_DRAM_SIZE_8GBIT:
 987                 return 8;
 988         case BXT_DRAM_SIZE_12GBIT:
 989                 return 12;
 990         case BXT_DRAM_SIZE_16GBIT:
 991                 return 16;
 992         default:
 993                 MISSING_CASE(val);
 994                 return 0;
 995         }
 996 }
 997
 998 static int bxt_get_dimm_width(u32 val)
 999 {
1000         if (!bxt_get_dimm_size(val))
1001                 return 0;
1002
1003         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1004
1005         return 8 << val;
1006 }
1007
1008 static int bxt_get_dimm_ranks(u32 val)
1009 {
1010         if (!bxt_get_dimm_size(val))
1011                 return 0;
1012
1013         switch (val & BXT_DRAM_RANK_MASK) {
1014         case BXT_DRAM_RANK_SINGLE:
1015                 return 1;
1016         case BXT_DRAM_RANK_DUAL:
1017                 return 2;
1018         default:
1019                 MISSING_CASE(val);
1020                 return 0;
1021         }
1022 }
1023
1024 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1025 {
1026         if (!bxt_get_dimm_size(val))
1027                 return INTEL_DRAM_UNKNOWN;
1028
1029         switch (val & BXT_DRAM_TYPE_MASK) {
1030         case BXT_DRAM_TYPE_DDR3:
1031                 return INTEL_DRAM_DDR3;
1032         case BXT_DRAM_TYPE_LPDDR3:
1033                 return INTEL_DRAM_LPDDR3;
1034         case BXT_DRAM_TYPE_DDR4:
1035                 return INTEL_DRAM_DDR4;
1036         case BXT_DRAM_TYPE_LPDDR4:
1037                 return INTEL_DRAM_LPDDR4;
1038         default:
1039                 MISSING_CASE(val);
1040                 return INTEL_DRAM_UNKNOWN;
1041         }
1042 }
1043
1044 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1045                               u32 val)
1046 {
1047         dimm->width = bxt_get_dimm_width(val);
1048         dimm->ranks = bxt_get_dimm_ranks(val);
1049
1050         /*
1051          * Size in register is Gb per DRAM device. Convert to total
1052          * GB to match the way we report this for non-LP platforms.
1053          */
1054         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1055 }
1056
1057 static int
1058 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1059 {
1060         struct dram_info *dram_info = &dev_priv->dram_info;
1061         u32 dram_channels;
1062         u32 mem_freq_khz, val;
1063         u8 num_active_channels;
1064         int i;
1065
1066         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1067         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1068                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1069
1070         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1071         num_active_channels = hweight32(dram_channels);
1072
1073         /* Each active bit represents 4-byte channel */
1074         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1075
1076         if (dram_info->bandwidth_kbps == 0) {
1077                 DRM_INFO("Couldn't get system memory bandwidth\n");
1078                 return -EINVAL;
1079         }
1080
1081         /*
1082          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1083          */
1084         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1085                 struct dram_dimm_info dimm;
1086                 enum intel_dram_type type;
1087
1088                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1089                 if (val == 0xFFFFFFFF)
1090                         continue;
1091
1092                 dram_info->num_channels++;
1093
1094                 bxt_get_dimm_info(&dimm, val);
1095                 type = bxt_get_dimm_type(val);
1096
1097                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1098                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1099                         dram_info->type != type);
1100
1101                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1102                               i - BXT_D_CR_DRP0_DUNIT_START,
1103                               dimm.size, dimm.width, dimm.ranks,
1104                               intel_dram_type_str(type));
1105
1106                 /*
1107                  * If any of the channel is single rank channel,
1108                  * worst case output will be same as if single rank
1109                  * memory, so consider single rank memory.
1110                  */
1111                 if (dram_info->ranks == 0)
1112                         dram_info->ranks = dimm.ranks;
1113                 else if (dimm.ranks == 1)
1114                         dram_info->ranks = 1;
1115
1116                 if (type != INTEL_DRAM_UNKNOWN)
1117                         dram_info->type = type;
1118         }
1119
1120         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1121             dram_info->ranks == 0) {
1122                 DRM_INFO("couldn't get memory information\n");
1123                 return -EINVAL;
1124         }
1125
1126         dram_info->valid = true;
1127         return 0;
1128 }
1129
1130 static void
1131 intel_get_dram_info(struct drm_i915_private *dev_priv)
1132 {
1133         struct dram_info *dram_info = &dev_priv->dram_info;
1134         int ret;
1135
1136         /*
1137          * Assume 16Gb DIMMs are present until proven otherwise.
1138          * This is only used for the level 0 watermark latency
1139          * w/a which does not apply to bxt/glk.
1140          */
1141         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1142
1143         if (INTEL_GEN(dev_priv) < 9)
1144                 return;
1145
1146         if (IS_GEN9_LP(dev_priv))
1147                 ret = bxt_get_dram_info(dev_priv);
1148         else
1149                 ret = skl_get_dram_info(dev_priv);
1150         if (ret)
1151                 return;
1152
1153         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1154                       dram_info->bandwidth_kbps,
1155                       dram_info->num_channels);
1156
1157         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1158                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1159 }
1160
1161 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1162 {
1163         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1164         const unsigned int sets[4] = { 1, 1, 2, 2 };
1165
1166         return EDRAM_NUM_BANKS(cap) *
1167                 ways[EDRAM_WAYS_IDX(cap)] *
1168                 sets[EDRAM_SETS_IDX(cap)];
1169 }
1170
1171 static void edram_detect(struct drm_i915_private *dev_priv)
1172 {
1173         u32 edram_cap = 0;
1174
1175         if (!(IS_HASWELL(dev_priv) ||
1176               IS_BROADWELL(dev_priv) ||
1177               INTEL_GEN(dev_priv) >= 9))
1178                 return;
1179
1180         edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1181
1182         /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1183
1184         if (!(edram_cap & EDRAM_ENABLED))
1185                 return;
1186
1187         /*
1188          * The needed capability bits for size calculation are not there with
1189          * pre gen9 so return 128MB always.
1190          */
1191         if (INTEL_GEN(dev_priv) < 9)
1192                 dev_priv->edram_size_mb = 128;
1193         else
1194                 dev_priv->edram_size_mb =
1195                         gen9_edram_size_mb(dev_priv, edram_cap);
1196
1197         dev_info(dev_priv->drm.dev,
1198                  "Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1199 }
1200
1201 /**
1202  * i915_driver_hw_probe - setup state requiring device access
1203  * @dev_priv: device private
1204  *
1205  * Setup state that requires accessing the device, but doesn't require
1206  * exposing the driver via kernel internal or userspace interfaces.
1207  */
1208 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
1209 {
1210         struct pci_dev *pdev = dev_priv->drm.pdev;
1211         int ret;
1212
1213         if (i915_inject_probe_failure(dev_priv))
1214                 return -ENODEV;
1215
1216         intel_device_info_runtime_init(dev_priv);
1217
1218         if (HAS_PPGTT(dev_priv)) {
1219                 if (intel_vgpu_active(dev_priv) &&
1220                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1221                         i915_report_error(dev_priv,
1222                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1223                         return -ENXIO;
1224                 }
1225         }
1226
1227         if (HAS_EXECLISTS(dev_priv)) {
1228                 /*
1229                  * Older GVT emulation depends upon intercepting CSB mmio,
1230                  * which we no longer use, preferring to use the HWSP cache
1231                  * instead.
1232                  */
1233                 if (intel_vgpu_active(dev_priv) &&
1234                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1235                         i915_report_error(dev_priv,
1236                                           "old vGPU host found, support for HWSP emulation required\n");
1237                         return -ENXIO;
1238                 }
1239         }
1240
1241         intel_sanitize_options(dev_priv);
1242
1243         /* needs to be done before ggtt probe */
1244         edram_detect(dev_priv);
1245
1246         i915_perf_init(dev_priv);
1247
1248         ret = i915_ggtt_probe_hw(dev_priv);
1249         if (ret)
1250                 goto err_perf;
1251
1252         /*
1253          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1254          * otherwise the vga fbdev driver falls over.
1255          */
1256         ret = i915_kick_out_firmware_fb(dev_priv);
1257         if (ret) {
1258                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1259                 goto err_ggtt;
1260         }
1261
1262         ret = vga_remove_vgacon(pdev);
1263         if (ret) {
1264                 DRM_ERROR("failed to remove conflicting VGA console\n");
1265                 goto err_ggtt;
1266         }
1267
1268         ret = i915_ggtt_init_hw(dev_priv);
1269         if (ret)
1270                 goto err_ggtt;
1271
1272         intel_gt_init_hw(dev_priv);
1273
1274         ret = i915_ggtt_enable_hw(dev_priv);
1275         if (ret) {
1276                 DRM_ERROR("failed to enable GGTT\n");
1277                 goto err_ggtt;
1278         }
1279
1280         pci_set_master(pdev);
1281
1282         /*
1283          * We don't have a max segment size, so set it to the max so sg's
1284          * debugging layer doesn't complain
1285          */
1286         dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1287
1288         /* overlay on gen2 is broken and can't address above 1G */
1289         if (IS_GEN(dev_priv, 2)) {
1290                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1291                 if (ret) {
1292                         DRM_ERROR("failed to set DMA mask\n");
1293
1294                         goto err_ggtt;
1295                 }
1296         }
1297
1298         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1299          * using 32bit addressing, overwriting memory if HWS is located
1300          * above 4GB.
1301          *
1302          * The documentation also mentions an issue with undefined
1303          * behaviour if any general state is accessed within a page above 4GB,
1304          * which also needs to be handled carefully.
1305          */
1306         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1307                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1308
1309                 if (ret) {
1310                         DRM_ERROR("failed to set DMA mask\n");
1311
1312                         goto err_ggtt;
1313                 }
1314         }
1315
1316         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1317                            PM_QOS_DEFAULT_VALUE);
1318
1319         /* BIOS often leaves RC6 enabled, but disable it for hw init */
1320         intel_sanitize_gt_powersave(dev_priv);
1321
1322         intel_gt_init_workarounds(dev_priv);
1323
1324         /* On the 945G/GM, the chipset reports the MSI capability on the
1325          * integrated graphics even though the support isn't actually there
1326          * according to the published specs.  It doesn't appear to function
1327          * correctly in testing on 945G.
1328          * This may be a side effect of MSI having been made available for PEG
1329          * and the registers being closely associated.
1330          *
1331          * According to chipset errata, on the 965GM, MSI interrupts may
1332          * be lost or delayed, and was defeatured. MSI interrupts seem to
1333          * get lost on g4x as well, and interrupt delivery seems to stay
1334          * properly dead afterwards. So we'll just disable them for all
1335          * pre-gen5 chipsets.
1336          *
1337          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1338          * interrupts even when in MSI mode. This results in spurious
1339          * interrupt warnings if the legacy irq no. is shared with another
1340          * device. The kernel then disables that interrupt source and so
1341          * prevents the other device from working properly.
1342          */
1343         if (INTEL_GEN(dev_priv) >= 5) {
1344                 if (pci_enable_msi(pdev) < 0)
1345                         DRM_DEBUG_DRIVER("can't enable MSI");
1346         }
1347
1348         ret = intel_gvt_init(dev_priv);
1349         if (ret)
1350                 goto err_msi;
1351
1352         intel_opregion_setup(dev_priv);
1353         /*
1354          * Fill the dram structure to get the system raw bandwidth and
1355          * dram info. This will be used for memory latency calculation.
1356          */
1357         intel_get_dram_info(dev_priv);
1358
1359         intel_bw_init_hw(dev_priv);
1360
1361         return 0;
1362
1363 err_msi:
1364         if (pdev->msi_enabled)
1365                 pci_disable_msi(pdev);
1366         pm_qos_remove_request(&dev_priv->pm_qos);
1367 err_ggtt:
1368         i915_ggtt_driver_release(dev_priv);
1369 err_perf:
1370         i915_perf_fini(dev_priv);
1371         return ret;
1372 }
1373
1374 /**
1375  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
1376  * @dev_priv: device private
1377  */
1378 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
1379 {
1380         struct pci_dev *pdev = dev_priv->drm.pdev;
1381
1382         i915_perf_fini(dev_priv);
1383
1384         if (pdev->msi_enabled)
1385                 pci_disable_msi(pdev);
1386
1387         pm_qos_remove_request(&dev_priv->pm_qos);
1388 }
1389
1390 /**
1391  * i915_driver_register - register the driver with the rest of the system
1392  * @dev_priv: device private
1393  *
1394  * Perform any steps necessary to make the driver available via kernel
1395  * internal or userspace interfaces.
1396  */
1397 static void i915_driver_register(struct drm_i915_private *dev_priv)
1398 {
1399         struct drm_device *dev = &dev_priv->drm;
1400
1401         i915_gem_driver_register(dev_priv);
1402         i915_pmu_register(dev_priv);
1403
1404         /*
1405          * Notify a valid surface after modesetting,
1406          * when running inside a VM.
1407          */
1408         if (intel_vgpu_active(dev_priv))
1409                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1410
1411         /* Reveal our presence to userspace */
1412         if (drm_dev_register(dev, 0) == 0) {
1413                 i915_debugfs_register(dev_priv);
1414                 i915_setup_sysfs(dev_priv);
1415
1416                 /* Depends on sysfs having been initialized */
1417                 i915_perf_register(dev_priv);
1418         } else
1419                 DRM_ERROR("Failed to register driver for userspace access!\n");
1420
1421         if (HAS_DISPLAY(dev_priv)) {
1422                 /* Must be done after probing outputs */
1423                 intel_opregion_register(dev_priv);
1424                 acpi_video_register();
1425         }
1426
1427         if (IS_GEN(dev_priv, 5))
1428                 intel_gpu_ips_init(dev_priv);
1429
1430         intel_audio_init(dev_priv);
1431
1432         /*
1433          * Some ports require correctly set-up hpd registers for detection to
1434          * work properly (leading to ghost connected connector status), e.g. VGA
1435          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1436          * irqs are fully enabled. We do it last so that the async config
1437          * cannot run before the connectors are registered.
1438          */
1439         intel_fbdev_initial_config_async(dev);
1440
1441         /*
1442          * We need to coordinate the hotplugs with the asynchronous fbdev
1443          * configuration, for which we use the fbdev->async_cookie.
1444          */
1445         if (HAS_DISPLAY(dev_priv))
1446                 drm_kms_helper_poll_init(dev);
1447
1448         intel_power_domains_enable(dev_priv);
1449         intel_runtime_pm_enable(&dev_priv->runtime_pm);
1450 }
1451
1452 /**
1453  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1454  * @dev_priv: device private
1455  */
1456 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1457 {
1458         intel_runtime_pm_disable(&dev_priv->runtime_pm);
1459         intel_power_domains_disable(dev_priv);
1460
1461         intel_fbdev_unregister(dev_priv);
1462         intel_audio_deinit(dev_priv);
1463
1464         /*
1465          * After flushing the fbdev (incl. a late async config which will
1466          * have delayed queuing of a hotplug event), then flush the hotplug
1467          * events.
1468          */
1469         drm_kms_helper_poll_fini(&dev_priv->drm);
1470
1471         intel_gpu_ips_teardown();
1472         acpi_video_unregister();
1473         intel_opregion_unregister(dev_priv);
1474
1475         i915_perf_unregister(dev_priv);
1476         i915_pmu_unregister(dev_priv);
1477
1478         i915_teardown_sysfs(dev_priv);
1479         drm_dev_unplug(&dev_priv->drm);
1480
1481         i915_gem_driver_unregister(dev_priv);
1482 }
1483
1484 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1485 {
1486         if (drm_debug & DRM_UT_DRIVER) {
1487                 struct drm_printer p = drm_debug_printer("i915 device info:");
1488
1489                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1490                            INTEL_DEVID(dev_priv),
1491                            INTEL_REVID(dev_priv),
1492                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1493                            intel_subplatform(RUNTIME_INFO(dev_priv),
1494                                              INTEL_INFO(dev_priv)->platform),
1495                            INTEL_GEN(dev_priv));
1496
1497                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1498                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1499         }
1500
1501         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1502                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1503         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1504                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1505         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1506                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1507 }
1508
1509 static struct drm_i915_private *
1510 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1511 {
1512         const struct intel_device_info *match_info =
1513                 (struct intel_device_info *)ent->driver_data;
1514         struct intel_device_info *device_info;
1515         struct drm_i915_private *i915;
1516         int err;
1517
1518         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1519         if (!i915)
1520                 return ERR_PTR(-ENOMEM);
1521
1522         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1523         if (err) {
1524                 kfree(i915);
1525                 return ERR_PTR(err);
1526         }
1527
1528         i915->drm.dev_private = i915;
1529
1530         i915->drm.pdev = pdev;
1531         pci_set_drvdata(pdev, i915);
1532
1533         /* Setup the write-once "constant" device info */
1534         device_info = mkwrite_device_info(i915);
1535         memcpy(device_info, match_info, sizeof(*device_info));
1536         RUNTIME_INFO(i915)->device_id = pdev->device;
1537
1538         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1539
1540         return i915;
1541 }
1542
1543 static void i915_driver_destroy(struct drm_i915_private *i915)
1544 {
1545         struct pci_dev *pdev = i915->drm.pdev;
1546
1547         drm_dev_fini(&i915->drm);
1548         kfree(i915);
1549
1550         /* And make sure we never chase our dangling pointer from pci_dev */
1551         pci_set_drvdata(pdev, NULL);
1552 }
1553
1554 /**
1555  * i915_driver_probe - setup chip and create an initial config
1556  * @pdev: PCI device
1557  * @ent: matching PCI ID entry
1558  *
1559  * The driver probe routine has to do several things:
1560  *   - drive output discovery via intel_modeset_init()
1561  *   - initialize the memory manager
1562  *   - allocate initial config memory
1563  *   - setup the DRM framebuffer with the allocated memory
1564  */
1565 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1566 {
1567         const struct intel_device_info *match_info =
1568                 (struct intel_device_info *)ent->driver_data;
1569         struct drm_i915_private *dev_priv;
1570         int ret;
1571
1572         dev_priv = i915_driver_create(pdev, ent);
1573         if (IS_ERR(dev_priv))
1574                 return PTR_ERR(dev_priv);
1575
1576         /* Disable nuclear pageflip by default on pre-ILK */
1577         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1578                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1579
1580         ret = pci_enable_device(pdev);
1581         if (ret)
1582                 goto out_fini;
1583
1584         ret = i915_driver_early_probe(dev_priv);
1585         if (ret < 0)
1586                 goto out_pci_disable;
1587
1588         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1589
1590         i915_detect_vgpu(dev_priv);
1591
1592         ret = i915_driver_mmio_probe(dev_priv);
1593         if (ret < 0)
1594                 goto out_runtime_pm_put;
1595
1596         ret = i915_driver_hw_probe(dev_priv);
1597         if (ret < 0)
1598                 goto out_cleanup_mmio;
1599
1600         ret = i915_driver_modeset_probe(&dev_priv->drm);
1601         if (ret < 0)
1602                 goto out_cleanup_hw;
1603
1604         i915_driver_register(dev_priv);
1605
1606         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1607
1608         i915_welcome_messages(dev_priv);
1609
1610         return 0;
1611
1612 out_cleanup_hw:
1613         i915_driver_hw_remove(dev_priv);
1614         i915_ggtt_driver_release(dev_priv);
1615
1616         /* Paranoia: make sure we have disabled everything before we exit. */
1617         intel_sanitize_gt_powersave(dev_priv);
1618 out_cleanup_mmio:
1619         i915_driver_mmio_release(dev_priv);
1620 out_runtime_pm_put:
1621         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1622         i915_driver_late_release(dev_priv);
1623 out_pci_disable:
1624         pci_disable_device(pdev);
1625 out_fini:
1626         i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret);
1627         i915_driver_destroy(dev_priv);
1628         return ret;
1629 }
1630
1631 void i915_driver_remove(struct drm_i915_private *i915)
1632 {
1633         struct pci_dev *pdev = i915->drm.pdev;
1634
1635         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1636
1637         i915_driver_unregister(i915);
1638
1639         /*
1640          * After unregistering the device to prevent any new users, cancel
1641          * all in-flight requests so that we can quickly unbind the active
1642          * resources.
1643          */
1644         intel_gt_set_wedged(&i915->gt);
1645
1646         /* Flush any external code that still may be under the RCU lock */
1647         synchronize_rcu();
1648
1649         i915_gem_suspend(i915);
1650
1651         drm_atomic_helper_shutdown(&i915->drm);
1652
1653         intel_gvt_driver_remove(i915);
1654
1655         intel_modeset_driver_remove(&i915->drm);
1656
1657         intel_bios_driver_remove(i915);
1658
1659         vga_switcheroo_unregister_client(pdev);
1660         vga_client_register(pdev, NULL, NULL, NULL);
1661
1662         intel_csr_ucode_fini(i915);
1663
1664         /* Free error state after interrupts are fully disabled. */
1665         cancel_delayed_work_sync(&i915->gt.hangcheck.work);
1666         i915_reset_error_state(i915);
1667
1668         i915_gem_driver_remove(i915);
1669
1670         intel_power_domains_driver_remove(i915);
1671
1672         i915_driver_hw_remove(i915);
1673
1674         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1675 }
1676
1677 static void i915_driver_release(struct drm_device *dev)
1678 {
1679         struct drm_i915_private *dev_priv = to_i915(dev);
1680         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1681
1682         disable_rpm_wakeref_asserts(rpm);
1683
1684         i915_gem_driver_release(dev_priv);
1685
1686         i915_ggtt_driver_release(dev_priv);
1687
1688         /* Paranoia: make sure we have disabled everything before we exit. */
1689         intel_sanitize_gt_powersave(dev_priv);
1690
1691         i915_driver_mmio_release(dev_priv);
1692
1693         enable_rpm_wakeref_asserts(rpm);
1694         intel_runtime_pm_driver_release(rpm);
1695
1696         i915_driver_late_release(dev_priv);
1697         i915_driver_destroy(dev_priv);
1698 }
1699
1700 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1701 {
1702         struct drm_i915_private *i915 = to_i915(dev);
1703         int ret;
1704
1705         ret = i915_gem_open(i915, file);
1706         if (ret)
1707                 return ret;
1708
1709         return 0;
1710 }
1711
1712 /**
1713  * i915_driver_lastclose - clean up after all DRM clients have exited
1714  * @dev: DRM device
1715  *
1716  * Take care of cleaning up after all DRM clients have exited.  In the
1717  * mode setting case, we want to restore the kernel's initial mode (just
1718  * in case the last client left us in a bad state).
1719  *
1720  * Additionally, in the non-mode setting case, we'll tear down the GTT
1721  * and DMA structures, since the kernel won't be using them, and clea
1722  * up any GEM state.
1723  */
1724 static void i915_driver_lastclose(struct drm_device *dev)
1725 {
1726         intel_fbdev_restore_mode(dev);
1727         vga_switcheroo_process_delayed_switch();
1728 }
1729
1730 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1731 {
1732         struct drm_i915_file_private *file_priv = file->driver_priv;
1733
1734         mutex_lock(&dev->struct_mutex);
1735         i915_gem_context_close(file);
1736         i915_gem_release(dev, file);
1737         mutex_unlock(&dev->struct_mutex);
1738
1739         kfree(file_priv);
1740
1741         /* Catch up with all the deferred frees from "this" client */
1742         i915_gem_flush_free_objects(to_i915(dev));
1743 }
1744
1745 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1746 {
1747         struct drm_device *dev = &dev_priv->drm;
1748         struct intel_encoder *encoder;
1749
1750         drm_modeset_lock_all(dev);
1751         for_each_intel_encoder(dev, encoder)
1752                 if (encoder->suspend)
1753                         encoder->suspend(encoder);
1754         drm_modeset_unlock_all(dev);
1755 }
1756
1757 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1758                               bool rpm_resume);
1759 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1760
1761 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1762 {
1763 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1764         if (acpi_target_system_state() < ACPI_STATE_S3)
1765                 return true;
1766 #endif
1767         return false;
1768 }
1769
1770 static int i915_drm_prepare(struct drm_device *dev)
1771 {
1772         struct drm_i915_private *i915 = to_i915(dev);
1773
1774         /*
1775          * NB intel_display_suspend() may issue new requests after we've
1776          * ostensibly marked the GPU as ready-to-sleep here. We need to
1777          * split out that work and pull it forward so that after point,
1778          * the GPU is not woken again.
1779          */
1780         i915_gem_suspend(i915);
1781
1782         return 0;
1783 }
1784
1785 static int i915_drm_suspend(struct drm_device *dev)
1786 {
1787         struct drm_i915_private *dev_priv = to_i915(dev);
1788         struct pci_dev *pdev = dev_priv->drm.pdev;
1789         pci_power_t opregion_target_state;
1790
1791         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1792
1793         /* We do a lot of poking in a lot of registers, make sure they work
1794          * properly. */
1795         intel_power_domains_disable(dev_priv);
1796
1797         drm_kms_helper_poll_disable(dev);
1798
1799         pci_save_state(pdev);
1800
1801         intel_display_suspend(dev);
1802
1803         intel_dp_mst_suspend(dev_priv);
1804
1805         intel_runtime_pm_disable_interrupts(dev_priv);
1806         intel_hpd_cancel_work(dev_priv);
1807
1808         intel_suspend_encoders(dev_priv);
1809
1810         intel_suspend_hw(dev_priv);
1811
1812         i915_gem_suspend_gtt_mappings(dev_priv);
1813
1814         i915_save_state(dev_priv);
1815
1816         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1817         intel_opregion_suspend(dev_priv, opregion_target_state);
1818
1819         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1820
1821         dev_priv->suspend_count++;
1822
1823         intel_csr_ucode_suspend(dev_priv);
1824
1825         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1826
1827         return 0;
1828 }
1829
1830 static enum i915_drm_suspend_mode
1831 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1832 {
1833         if (hibernate)
1834                 return I915_DRM_SUSPEND_HIBERNATE;
1835
1836         if (suspend_to_idle(dev_priv))
1837                 return I915_DRM_SUSPEND_IDLE;
1838
1839         return I915_DRM_SUSPEND_MEM;
1840 }
1841
1842 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1843 {
1844         struct drm_i915_private *dev_priv = to_i915(dev);
1845         struct pci_dev *pdev = dev_priv->drm.pdev;
1846         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1847         int ret = 0;
1848
1849         disable_rpm_wakeref_asserts(rpm);
1850
1851         i915_gem_suspend_late(dev_priv);
1852
1853         intel_uncore_suspend(&dev_priv->uncore);
1854
1855         intel_power_domains_suspend(dev_priv,
1856                                     get_suspend_mode(dev_priv, hibernation));
1857
1858         intel_display_power_suspend_late(dev_priv);
1859
1860         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1861                 ret = vlv_suspend_complete(dev_priv);
1862
1863         if (ret) {
1864                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1865                 intel_power_domains_resume(dev_priv);
1866
1867                 goto out;
1868         }
1869
1870         pci_disable_device(pdev);
1871         /*
1872          * During hibernation on some platforms the BIOS may try to access
1873          * the device even though it's already in D3 and hang the machine. So
1874          * leave the device in D0 on those platforms and hope the BIOS will
1875          * power down the device properly. The issue was seen on multiple old
1876          * GENs with different BIOS vendors, so having an explicit blacklist
1877          * is inpractical; apply the workaround on everything pre GEN6. The
1878          * platforms where the issue was seen:
1879          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1880          * Fujitsu FSC S7110
1881          * Acer Aspire 1830T
1882          */
1883         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1884                 pci_set_power_state(pdev, PCI_D3hot);
1885
1886 out:
1887         enable_rpm_wakeref_asserts(rpm);
1888         if (!dev_priv->uncore.user_forcewake_count)
1889                 intel_runtime_pm_driver_release(rpm);
1890
1891         return ret;
1892 }
1893
1894 static int
1895 i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1896 {
1897         int error;
1898
1899         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1900                          state.event != PM_EVENT_FREEZE))
1901                 return -EINVAL;
1902
1903         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1904                 return 0;
1905
1906         error = i915_drm_suspend(&i915->drm);
1907         if (error)
1908                 return error;
1909
1910         return i915_drm_suspend_late(&i915->drm, false);
1911 }
1912
1913 static int i915_drm_resume(struct drm_device *dev)
1914 {
1915         struct drm_i915_private *dev_priv = to_i915(dev);
1916         int ret;
1917
1918         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1919         intel_sanitize_gt_powersave(dev_priv);
1920
1921         i915_gem_sanitize(dev_priv);
1922
1923         ret = i915_ggtt_enable_hw(dev_priv);
1924         if (ret)
1925                 DRM_ERROR("failed to re-enable GGTT\n");
1926
1927         intel_csr_ucode_resume(dev_priv);
1928
1929         i915_restore_state(dev_priv);
1930         intel_pps_unlock_regs_wa(dev_priv);
1931
1932         intel_init_pch_refclk(dev_priv);
1933
1934         /*
1935          * Interrupts have to be enabled before any batches are run. If not the
1936          * GPU will hang. i915_gem_init_hw() will initiate batches to
1937          * update/restore the context.
1938          *
1939          * drm_mode_config_reset() needs AUX interrupts.
1940          *
1941          * Modeset enabling in intel_modeset_init_hw() also needs working
1942          * interrupts.
1943          */
1944         intel_runtime_pm_enable_interrupts(dev_priv);
1945
1946         drm_mode_config_reset(dev);
1947
1948         i915_gem_resume(dev_priv);
1949
1950         intel_modeset_init_hw(dev);
1951         intel_init_clock_gating(dev_priv);
1952
1953         spin_lock_irq(&dev_priv->irq_lock);
1954         if (dev_priv->display.hpd_irq_setup)
1955                 dev_priv->display.hpd_irq_setup(dev_priv);
1956         spin_unlock_irq(&dev_priv->irq_lock);
1957
1958         intel_dp_mst_resume(dev_priv);
1959
1960         intel_display_resume(dev);
1961
1962         drm_kms_helper_poll_enable(dev);
1963
1964         /*
1965          * ... but also need to make sure that hotplug processing
1966          * doesn't cause havoc. Like in the driver load code we don't
1967          * bother with the tiny race here where we might lose hotplug
1968          * notifications.
1969          * */
1970         intel_hpd_init(dev_priv);
1971
1972         intel_opregion_resume(dev_priv);
1973
1974         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1975
1976         intel_power_domains_enable(dev_priv);
1977
1978         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1979
1980         return 0;
1981 }
1982
1983 static int i915_drm_resume_early(struct drm_device *dev)
1984 {
1985         struct drm_i915_private *dev_priv = to_i915(dev);
1986         struct pci_dev *pdev = dev_priv->drm.pdev;
1987         int ret;
1988
1989         /*
1990          * We have a resume ordering issue with the snd-hda driver also
1991          * requiring our device to be power up. Due to the lack of a
1992          * parent/child relationship we currently solve this with an early
1993          * resume hook.
1994          *
1995          * FIXME: This should be solved with a special hdmi sink device or
1996          * similar so that power domains can be employed.
1997          */
1998
1999         /*
2000          * Note that we need to set the power state explicitly, since we
2001          * powered off the device during freeze and the PCI core won't power
2002          * it back up for us during thaw. Powering off the device during
2003          * freeze is not a hard requirement though, and during the
2004          * suspend/resume phases the PCI core makes sure we get here with the
2005          * device powered on. So in case we change our freeze logic and keep
2006          * the device powered we can also remove the following set power state
2007          * call.
2008          */
2009         ret = pci_set_power_state(pdev, PCI_D0);
2010         if (ret) {
2011                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2012                 return ret;
2013         }
2014
2015         /*
2016          * Note that pci_enable_device() first enables any parent bridge
2017          * device and only then sets the power state for this device. The
2018          * bridge enabling is a nop though, since bridge devices are resumed
2019          * first. The order of enabling power and enabling the device is
2020          * imposed by the PCI core as described above, so here we preserve the
2021          * same order for the freeze/thaw phases.
2022          *
2023          * TODO: eventually we should remove pci_disable_device() /
2024          * pci_enable_enable_device() from suspend/resume. Due to how they
2025          * depend on the device enable refcount we can't anyway depend on them
2026          * disabling/enabling the device.
2027          */
2028         if (pci_enable_device(pdev))
2029                 return -EIO;
2030
2031         pci_set_master(pdev);
2032
2033         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2034
2035         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2036                 ret = vlv_resume_prepare(dev_priv, false);
2037         if (ret)
2038                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2039                           ret);
2040
2041         intel_uncore_resume_early(&dev_priv->uncore);
2042
2043         intel_gt_check_and_clear_faults(&dev_priv->gt);
2044
2045         intel_display_power_resume_early(dev_priv);
2046
2047         intel_sanitize_gt_powersave(dev_priv);
2048
2049         intel_power_domains_resume(dev_priv);
2050
2051         intel_gt_sanitize(&dev_priv->gt, true);
2052
2053         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2054
2055         return ret;
2056 }
2057
2058 static int i915_resume_switcheroo(struct drm_i915_private *i915)
2059 {
2060         int ret;
2061
2062         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2063                 return 0;
2064
2065         ret = i915_drm_resume_early(&i915->drm);
2066         if (ret)
2067                 return ret;
2068
2069         return i915_drm_resume(&i915->drm);
2070 }
2071
2072 static int i915_pm_prepare(struct device *kdev)
2073 {
2074         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2075
2076         if (!i915) {
2077                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2078                 return -ENODEV;
2079         }
2080
2081         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2082                 return 0;
2083
2084         return i915_drm_prepare(&i915->drm);
2085 }
2086
2087 static int i915_pm_suspend(struct device *kdev)
2088 {
2089         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2090
2091         if (!i915) {
2092                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2093                 return -ENODEV;
2094         }
2095
2096         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2097                 return 0;
2098
2099         return i915_drm_suspend(&i915->drm);
2100 }
2101
2102 static int i915_pm_suspend_late(struct device *kdev)
2103 {
2104         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2105
2106         /*
2107          * We have a suspend ordering issue with the snd-hda driver also
2108          * requiring our device to be power up. Due to the lack of a
2109          * parent/child relationship we currently solve this with an late
2110          * suspend hook.
2111          *
2112          * FIXME: This should be solved with a special hdmi sink device or
2113          * similar so that power domains can be employed.
2114          */
2115         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2116                 return 0;
2117
2118         return i915_drm_suspend_late(&i915->drm, false);
2119 }
2120
2121 static int i915_pm_poweroff_late(struct device *kdev)
2122 {
2123         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2124
2125         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2126                 return 0;
2127
2128         return i915_drm_suspend_late(&i915->drm, true);
2129 }
2130
2131 static int i915_pm_resume_early(struct device *kdev)
2132 {
2133         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2134
2135         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2136                 return 0;
2137
2138         return i915_drm_resume_early(&i915->drm);
2139 }
2140
2141 static int i915_pm_resume(struct device *kdev)
2142 {
2143         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2144
2145         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2146                 return 0;
2147
2148         return i915_drm_resume(&i915->drm);
2149 }
2150
2151 /* freeze: before creating the hibernation_image */
2152 static int i915_pm_freeze(struct device *kdev)
2153 {
2154         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2155         int ret;
2156
2157         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2158                 ret = i915_drm_suspend(&i915->drm);
2159                 if (ret)
2160                         return ret;
2161         }
2162
2163         ret = i915_gem_freeze(i915);
2164         if (ret)
2165                 return ret;
2166
2167         return 0;
2168 }
2169
2170 static int i915_pm_freeze_late(struct device *kdev)
2171 {
2172         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2173         int ret;
2174
2175         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2176                 ret = i915_drm_suspend_late(&i915->drm, true);
2177                 if (ret)
2178                         return ret;
2179         }
2180
2181         ret = i915_gem_freeze_late(i915);
2182         if (ret)
2183                 return ret;
2184
2185         return 0;
2186 }
2187
2188 /* thaw: called after creating the hibernation image, but before turning off. */
2189 static int i915_pm_thaw_early(struct device *kdev)
2190 {
2191         return i915_pm_resume_early(kdev);
2192 }
2193
2194 static int i915_pm_thaw(struct device *kdev)
2195 {
2196         return i915_pm_resume(kdev);
2197 }
2198
2199 /* restore: called after loading the hibernation image. */
2200 static int i915_pm_restore_early(struct device *kdev)
2201 {
2202         return i915_pm_resume_early(kdev);
2203 }
2204
2205 static int i915_pm_restore(struct device *kdev)
2206 {
2207         return i915_pm_resume(kdev);
2208 }
2209
2210 /*
2211  * Save all Gunit registers that may be lost after a D3 and a subsequent
2212  * S0i[R123] transition. The list of registers needing a save/restore is
2213  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2214  * registers in the following way:
2215  * - Driver: saved/restored by the driver
2216  * - Punit : saved/restored by the Punit firmware
2217  * - No, w/o marking: no need to save/restore, since the register is R/O or
2218  *                    used internally by the HW in a way that doesn't depend
2219  *                    keeping the content across a suspend/resume.
2220  * - Debug : used for debugging
2221  *
2222  * We save/restore all registers marked with 'Driver', with the following
2223  * exceptions:
2224  * - Registers out of use, including also registers marked with 'Debug'.
2225  *   These have no effect on the driver's operation, so we don't save/restore
2226  *   them to reduce the overhead.
2227  * - Registers that are fully setup by an initialization function called from
2228  *   the resume path. For example many clock gating and RPS/RC6 registers.
2229  * - Registers that provide the right functionality with their reset defaults.
2230  *
2231  * TODO: Except for registers that based on the above 3 criteria can be safely
2232  * ignored, we save/restore all others, practically treating the HW context as
2233  * a black-box for the driver. Further investigation is needed to reduce the
2234  * saved/restored registers even further, by following the same 3 criteria.
2235  */
2236 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2237 {
2238         struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2239         int i;
2240
2241         if (!s)
2242                 return;
2243
2244         /* GAM 0x4000-0x4770 */
2245         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2246         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2247         s->arb_mode             = I915_READ(ARB_MODE);
2248         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2249         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2250
2251         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2252                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2253
2254         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2255         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2256
2257         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2258         s->ecochk               = I915_READ(GAM_ECOCHK);
2259         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2260         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2261
2262         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2263
2264         /* MBC 0x9024-0x91D0, 0x8500 */
2265         s->g3dctl               = I915_READ(VLV_G3DCTL);
2266         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2267         s->mbctl                = I915_READ(GEN6_MBCTL);
2268
2269         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2270         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2271         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2272         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2273         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2274         s->rstctl               = I915_READ(GEN6_RSTCTL);
2275         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2276
2277         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2278         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2279         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2280         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2281         s->ecobus               = I915_READ(ECOBUS);
2282         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2283         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2284         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2285         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2286         s->rcedata              = I915_READ(VLV_RCEDATA);
2287         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2288
2289         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2290         s->gt_imr               = I915_READ(GTIMR);
2291         s->gt_ier               = I915_READ(GTIER);
2292         s->pm_imr               = I915_READ(GEN6_PMIMR);
2293         s->pm_ier               = I915_READ(GEN6_PMIER);
2294
2295         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2296                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2297
2298         /* GT SA CZ domain, 0x100000-0x138124 */
2299         s->tilectl              = I915_READ(TILECTL);
2300         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2301         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2302         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2303         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2304
2305         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2306         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2307         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2308         s->pcbr                 = I915_READ(VLV_PCBR);
2309         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2310
2311         /*
2312          * Not saving any of:
2313          * DFT,         0x9800-0x9EC0
2314          * SARB,        0xB000-0xB1FC
2315          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2316          * PCI CFG
2317          */
2318 }
2319
2320 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2321 {
2322         struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2323         u32 val;
2324         int i;
2325
2326         if (!s)
2327                 return;
2328
2329         /* GAM 0x4000-0x4770 */
2330         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2331         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2332         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2333         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2334         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2335
2336         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2337                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2338
2339         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2340         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2341
2342         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2343         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2344         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2345         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2346
2347         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2348
2349         /* MBC 0x9024-0x91D0, 0x8500 */
2350         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2351         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2352         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2353
2354         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2355         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2356         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2357         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2358         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2359         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2360         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2361
2362         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2363         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2364         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2365         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2366         I915_WRITE(ECOBUS,              s->ecobus);
2367         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2368         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2369         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2370         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2371         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2372         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2373
2374         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2375         I915_WRITE(GTIMR,               s->gt_imr);
2376         I915_WRITE(GTIER,               s->gt_ier);
2377         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2378         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2379
2380         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2381                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2382
2383         /* GT SA CZ domain, 0x100000-0x138124 */
2384         I915_WRITE(TILECTL,                     s->tilectl);
2385         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2386         /*
2387          * Preserve the GT allow wake and GFX force clock bit, they are not
2388          * be restored, as they are used to control the s0ix suspend/resume
2389          * sequence by the caller.
2390          */
2391         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2392         val &= VLV_GTLC_ALLOWWAKEREQ;
2393         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2394         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2395
2396         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2397         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2398         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2399         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2400
2401         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2402
2403         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2404         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2405         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2406         I915_WRITE(VLV_PCBR,                    s->pcbr);
2407         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2408 }
2409
2410 static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
2411                                   u32 mask, u32 val)
2412 {
2413         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2414         u32 reg_value;
2415         int ret;
2416
2417         /* The HW does not like us polling for PW_STATUS frequently, so
2418          * use the sleeping loop rather than risk the busy spin within
2419          * intel_wait_for_register().
2420          *
2421          * Transitioning between RC6 states should be at most 2ms (see
2422          * valleyview_enable_rps) so use a 3ms timeout.
2423          */
2424         ret = wait_for(((reg_value =
2425                          intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
2426                        == val, 3);
2427
2428         /* just trace the final value */
2429         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2430
2431         return ret;
2432 }
2433
2434 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2435 {
2436         u32 val;
2437         int err;
2438
2439         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2440         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2441         if (force_on)
2442                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2443         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2444
2445         if (!force_on)
2446                 return 0;
2447
2448         err = intel_wait_for_register(&dev_priv->uncore,
2449                                       VLV_GTLC_SURVIVABILITY_REG,
2450                                       VLV_GFX_CLK_STATUS_BIT,
2451                                       VLV_GFX_CLK_STATUS_BIT,
2452                                       20);
2453         if (err)
2454                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2455                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2456
2457         return err;
2458 }
2459
2460 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2461 {
2462         u32 mask;
2463         u32 val;
2464         int err;
2465
2466         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2467         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2468         if (allow)
2469                 val |= VLV_GTLC_ALLOWWAKEREQ;
2470         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2471         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2472
2473         mask = VLV_GTLC_ALLOWWAKEACK;
2474         val = allow ? mask : 0;
2475
2476         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2477         if (err)
2478                 DRM_ERROR("timeout disabling GT waking\n");
2479
2480         return err;
2481 }
2482
2483 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2484                                   bool wait_for_on)
2485 {
2486         u32 mask;
2487         u32 val;
2488
2489         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2490         val = wait_for_on ? mask : 0;
2491
2492         /*
2493          * RC6 transitioning can be delayed up to 2 msec (see
2494          * valleyview_enable_rps), use 3 msec for safety.
2495          *
2496          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2497          * reset and we are trying to force the machine to sleep.
2498          */
2499         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2500                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2501                                  onoff(wait_for_on));
2502 }
2503
2504 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2505 {
2506         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2507                 return;
2508
2509         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2510         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2511 }
2512
2513 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2514 {
2515         u32 mask;
2516         int err;
2517
2518         /*
2519          * Bspec defines the following GT well on flags as debug only, so
2520          * don't treat them as hard failures.
2521          */
2522         vlv_wait_for_gt_wells(dev_priv, false);
2523
2524         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2525         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2526
2527         vlv_check_no_gt_access(dev_priv);
2528
2529         err = vlv_force_gfx_clock(dev_priv, true);
2530         if (err)
2531                 goto err1;
2532
2533         err = vlv_allow_gt_wake(dev_priv, false);
2534         if (err)
2535                 goto err2;
2536
2537         vlv_save_gunit_s0ix_state(dev_priv);
2538
2539         err = vlv_force_gfx_clock(dev_priv, false);
2540         if (err)
2541                 goto err2;
2542
2543         return 0;
2544
2545 err2:
2546         /* For safety always re-enable waking and disable gfx clock forcing */
2547         vlv_allow_gt_wake(dev_priv, true);
2548 err1:
2549         vlv_force_gfx_clock(dev_priv, false);
2550
2551         return err;
2552 }
2553
2554 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2555                                 bool rpm_resume)
2556 {
2557         int err;
2558         int ret;
2559
2560         /*
2561          * If any of the steps fail just try to continue, that's the best we
2562          * can do at this point. Return the first error code (which will also
2563          * leave RPM permanently disabled).
2564          */
2565         ret = vlv_force_gfx_clock(dev_priv, true);
2566
2567         vlv_restore_gunit_s0ix_state(dev_priv);
2568
2569         err = vlv_allow_gt_wake(dev_priv, true);
2570         if (!ret)
2571                 ret = err;
2572
2573         err = vlv_force_gfx_clock(dev_priv, false);
2574         if (!ret)
2575                 ret = err;
2576
2577         vlv_check_no_gt_access(dev_priv);
2578
2579         if (rpm_resume)
2580                 intel_init_clock_gating(dev_priv);
2581
2582         return ret;
2583 }
2584
2585 static int intel_runtime_suspend(struct device *kdev)
2586 {
2587         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2588         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2589         int ret = 0;
2590
2591         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2592                 return -ENODEV;
2593
2594         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2595                 return -ENODEV;
2596
2597         DRM_DEBUG_KMS("Suspending device\n");
2598
2599         disable_rpm_wakeref_asserts(rpm);
2600
2601         /*
2602          * We are safe here against re-faults, since the fault handler takes
2603          * an RPM reference.
2604          */
2605         i915_gem_runtime_suspend(dev_priv);
2606
2607         intel_gt_runtime_suspend(&dev_priv->gt);
2608
2609         intel_runtime_pm_disable_interrupts(dev_priv);
2610
2611         intel_uncore_suspend(&dev_priv->uncore);
2612
2613         intel_display_power_suspend(dev_priv);
2614
2615         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2616                 ret = vlv_suspend_complete(dev_priv);
2617
2618         if (ret) {
2619                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2620                 intel_uncore_runtime_resume(&dev_priv->uncore);
2621
2622                 intel_runtime_pm_enable_interrupts(dev_priv);
2623
2624                 intel_gt_runtime_resume(&dev_priv->gt);
2625
2626                 i915_gem_restore_fences(dev_priv);
2627
2628                 enable_rpm_wakeref_asserts(rpm);
2629
2630                 return ret;
2631         }
2632
2633         enable_rpm_wakeref_asserts(rpm);
2634         intel_runtime_pm_driver_release(rpm);
2635
2636         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2637                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2638
2639         rpm->suspended = true;
2640
2641         /*
2642          * FIXME: We really should find a document that references the arguments
2643          * used below!
2644          */
2645         if (IS_BROADWELL(dev_priv)) {
2646                 /*
2647                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2648                  * being detected, and the call we do at intel_runtime_resume()
2649                  * won't be able to restore them. Since PCI_D3hot matches the
2650                  * actual specification and appears to be working, use it.
2651                  */
2652                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2653         } else {
2654                 /*
2655                  * current versions of firmware which depend on this opregion
2656                  * notification have repurposed the D1 definition to mean
2657                  * "runtime suspended" vs. what you would normally expect (D3)
2658                  * to distinguish it from notifications that might be sent via
2659                  * the suspend path.
2660                  */
2661                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2662         }
2663
2664         assert_forcewakes_inactive(&dev_priv->uncore);
2665
2666         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2667                 intel_hpd_poll_init(dev_priv);
2668
2669         DRM_DEBUG_KMS("Device suspended\n");
2670         return 0;
2671 }
2672
2673 static int intel_runtime_resume(struct device *kdev)
2674 {
2675         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2676         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2677         int ret = 0;
2678
2679         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2680                 return -ENODEV;
2681
2682         DRM_DEBUG_KMS("Resuming device\n");
2683
2684         WARN_ON_ONCE(atomic_read(&rpm->wakeref_count));
2685         disable_rpm_wakeref_asserts(rpm);
2686
2687         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2688         rpm->suspended = false;
2689         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2690                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2691
2692         intel_display_power_resume(dev_priv);
2693
2694         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2695                 ret = vlv_resume_prepare(dev_priv, true);
2696
2697         intel_uncore_runtime_resume(&dev_priv->uncore);
2698
2699         intel_runtime_pm_enable_interrupts(dev_priv);
2700
2701         /*
2702          * No point of rolling back things in case of an error, as the best
2703          * we can do is to hope that things will still work (and disable RPM).
2704          */
2705         intel_gt_runtime_resume(&dev_priv->gt);
2706         i915_gem_restore_fences(dev_priv);
2707
2708         /*
2709          * On VLV/CHV display interrupts are part of the display
2710          * power well, so hpd is reinitialized from there. For
2711          * everyone else do it here.
2712          */
2713         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2714                 intel_hpd_init(dev_priv);
2715
2716         intel_enable_ipc(dev_priv);
2717
2718         enable_rpm_wakeref_asserts(rpm);
2719
2720         if (ret)
2721                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2722         else
2723                 DRM_DEBUG_KMS("Device resumed\n");
2724
2725         return ret;
2726 }
2727
2728 const struct dev_pm_ops i915_pm_ops = {
2729         /*
2730          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2731          * PMSG_RESUME]
2732          */
2733         .prepare = i915_pm_prepare,
2734         .suspend = i915_pm_suspend,
2735         .suspend_late = i915_pm_suspend_late,
2736         .resume_early = i915_pm_resume_early,
2737         .resume = i915_pm_resume,
2738
2739         /*
2740          * S4 event handlers
2741          * @freeze, @freeze_late    : called (1) before creating the
2742          *                            hibernation image [PMSG_FREEZE] and
2743          *                            (2) after rebooting, before restoring
2744          *                            the image [PMSG_QUIESCE]
2745          * @thaw, @thaw_early       : called (1) after creating the hibernation
2746          *                            image, before writing it [PMSG_THAW]
2747          *                            and (2) after failing to create or
2748          *                            restore the image [PMSG_RECOVER]
2749          * @poweroff, @poweroff_late: called after writing the hibernation
2750          *                            image, before rebooting [PMSG_HIBERNATE]
2751          * @restore, @restore_early : called after rebooting and restoring the
2752          *                            hibernation image [PMSG_RESTORE]
2753          */
2754         .freeze = i915_pm_freeze,
2755         .freeze_late = i915_pm_freeze_late,
2756         .thaw_early = i915_pm_thaw_early,
2757         .thaw = i915_pm_thaw,
2758         .poweroff = i915_pm_suspend,
2759         .poweroff_late = i915_pm_poweroff_late,
2760         .restore_early = i915_pm_restore_early,
2761         .restore = i915_pm_restore,
2762
2763         /* S0ix (via runtime suspend) event handlers */
2764         .runtime_suspend = intel_runtime_suspend,
2765         .runtime_resume = intel_runtime_resume,
2766 };
2767
2768 static const struct vm_operations_struct i915_gem_vm_ops = {
2769         .fault = i915_gem_fault,
2770         .open = drm_gem_vm_open,
2771         .close = drm_gem_vm_close,
2772 };
2773
2774 static const struct file_operations i915_driver_fops = {
2775         .owner = THIS_MODULE,
2776         .open = drm_open,
2777         .release = drm_release,
2778         .unlocked_ioctl = drm_ioctl,
2779         .mmap = drm_gem_mmap,
2780         .poll = drm_poll,
2781         .read = drm_read,
2782         .compat_ioctl = i915_compat_ioctl,
2783         .llseek = noop_llseek,
2784 };
2785
2786 static int
2787 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2788                           struct drm_file *file)
2789 {
2790         return -ENODEV;
2791 }
2792
2793 static const struct drm_ioctl_desc i915_ioctls[] = {
2794         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2795         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2796         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2797         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2798         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2799         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2800         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
2801         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2802         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2803         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2804         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2805         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2806         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2807         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2808         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2809         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2810         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2811         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2812         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2813         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
2814         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2815         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2816         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
2817         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2818         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2819         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
2820         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2821         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2822         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2823         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2824         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2825         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2826         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2827         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2828         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2829         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2830         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2831         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2832         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2833         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2834         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2835         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2836         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2837         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2838         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
2839         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2840         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2841         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2842         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2843         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2844         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2845         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2846         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2847         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
2848         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
2849         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
2850         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
2851         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
2852 };
2853
2854 static struct drm_driver driver = {
2855         /* Don't use MTRRs here; the Xserver or userspace app should
2856          * deal with them for Intel hardware.
2857          */
2858         .driver_features =
2859             DRIVER_GEM |
2860             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2861         .release = i915_driver_release,
2862         .open = i915_driver_open,
2863         .lastclose = i915_driver_lastclose,
2864         .postclose = i915_driver_postclose,
2865
2866         .gem_close_object = i915_gem_close_object,
2867         .gem_free_object_unlocked = i915_gem_free_object,
2868         .gem_vm_ops = &i915_gem_vm_ops,
2869
2870         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2871         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2872         .gem_prime_export = i915_gem_prime_export,
2873         .gem_prime_import = i915_gem_prime_import,
2874
2875         .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
2876         .get_scanout_position = i915_get_crtc_scanoutpos,
2877
2878         .dumb_create = i915_gem_dumb_create,
2879         .dumb_map_offset = i915_gem_mmap_gtt,
2880         .ioctls = i915_ioctls,
2881         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2882         .fops = &i915_driver_fops,
2883         .name = DRIVER_NAME,
2884         .desc = DRIVER_DESC,
2885         .date = DRIVER_DATE,
2886         .major = DRIVER_MAJOR,
2887         .minor = DRIVER_MINOR,
2888         .patchlevel = DRIVER_PATCHLEVEL,
2889 };
2890
2891 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2892 #include "selftests/mock_drm.c"
2893 #endif