drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_irq.h>
  47 #include <drm/drm_probe_helper.h>
  48 #include <drm/i915_drm.h>
  49
  50 #include "display/intel_acpi.h"
  51 #include "display/intel_audio.h"
  52 #include "display/intel_bw.h"
  53 #include "display/intel_cdclk.h"
  54 #include "display/intel_display_types.h"
  55 #include "display/intel_dp.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_gmbus.h"
  58 #include "display/intel_hotplug.h"
  59 #include "display/intel_overlay.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_sprite.h"
  62
  63 #include "gem/i915_gem_context.h"
  64 #include "gem/i915_gem_ioctls.h"
  65 #include "gt/intel_gt.h"
  66 #include "gt/intel_gt_pm.h"
  67
  68 #include "i915_debugfs.h"
  69 #include "i915_drv.h"
  70 #include "i915_irq.h"
  71 #include "i915_memcpy.h"
  72 #include "i915_perf.h"
  73 #include "i915_query.h"
  74 #include "i915_suspend.h"
  75 #include "i915_sysfs.h"
  76 #include "i915_trace.h"
  77 #include "i915_vgpu.h"
  78 #include "intel_csr.h"
  79 #include "intel_pm.h"
  80
  81 static struct drm_driver driver;
  82
  83 struct vlv_s0ix_state {
  84         /* GAM */
  85         u32 wr_watermark;
  86         u32 gfx_prio_ctrl;
  87         u32 arb_mode;
  88         u32 gfx_pend_tlb0;
  89         u32 gfx_pend_tlb1;
  90         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
  91         u32 media_max_req_count;
  92         u32 gfx_max_req_count;
  93         u32 render_hwsp;
  94         u32 ecochk;
  95         u32 bsd_hwsp;
  96         u32 blt_hwsp;
  97         u32 tlb_rd_addr;
  98
  99         /* MBC */
 100         u32 g3dctl;
 101         u32 gsckgctl;
 102         u32 mbctl;
 103
 104         /* GCP */
 105         u32 ucgctl1;
 106         u32 ucgctl3;
 107         u32 rcgctl1;
 108         u32 rcgctl2;
 109         u32 rstctl;
 110         u32 misccpctl;
 111
 112         /* GPM */
 113         u32 gfxpause;
 114         u32 rpdeuhwtc;
 115         u32 rpdeuc;
 116         u32 ecobus;
 117         u32 pwrdwnupctl;
 118         u32 rp_down_timeout;
 119         u32 rp_deucsw;
 120         u32 rcubmabdtmr;
 121         u32 rcedata;
 122         u32 spare2gh;
 123
 124         /* Display 1 CZ domain */
 125         u32 gt_imr;
 126         u32 gt_ier;
 127         u32 pm_imr;
 128         u32 pm_ier;
 129         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
 130
 131         /* GT SA CZ domain */
 132         u32 tilectl;
 133         u32 gt_fifoctl;
 134         u32 gtlc_wake_ctrl;
 135         u32 gtlc_survive;
 136         u32 pmwgicz;
 137
 138         /* Display 2 CZ domain */
 139         u32 gu_ctl0;
 140         u32 gu_ctl1;
 141         u32 pcbr;
 142         u32 clock_gate_dis2;
 143 };
 144
 145 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 146 {
 147         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 148
 149         dev_priv->bridge_dev =
 150                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 151         if (!dev_priv->bridge_dev) {
 152                 DRM_ERROR("bridge device not found\n");
 153                 return -1;
 154         }
 155         return 0;
 156 }
 157
 158 /* Allocate space for the MCH regs if needed, return nonzero on error */
 159 static int
 160 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 161 {
 162         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 163         u32 temp_lo, temp_hi = 0;
 164         u64 mchbar_addr;
 165         int ret;
 166
 167         if (INTEL_GEN(dev_priv) >= 4)
 168                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 169         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 170         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 171
 172         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 173 #ifdef CONFIG_PNP
 174         if (mchbar_addr &&
 175             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 176                 return 0;
 177 #endif
 178
 179         /* Get some space for it */
 180         dev_priv->mch_res.name = "i915 MCHBAR";
 181         dev_priv->mch_res.flags = IORESOURCE_MEM;
 182         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 183                                      &dev_priv->mch_res,
 184                                      MCHBAR_SIZE, MCHBAR_SIZE,
 185                                      PCIBIOS_MIN_MEM,
 186                                      0, pcibios_align_resource,
 187                                      dev_priv->bridge_dev);
 188         if (ret) {
 189                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 190                 dev_priv->mch_res.start = 0;
 191                 return ret;
 192         }
 193
 194         if (INTEL_GEN(dev_priv) >= 4)
 195                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 196                                        upper_32_bits(dev_priv->mch_res.start));
 197
 198         pci_write_config_dword(dev_priv->bridge_dev, reg,
 199                                lower_32_bits(dev_priv->mch_res.start));
 200         return 0;
 201 }
 202
 203 /* Setup MCHBAR if possible, return true if we should disable it again */
 204 static void
 205 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 206 {
 207         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 208         u32 temp;
 209         bool enabled;
 210
 211         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 212                 return;
 213
 214         dev_priv->mchbar_need_disable = false;
 215
 216         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 217                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 218                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 219         } else {
 220                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 221                 enabled = temp & 1;
 222         }
 223
 224         /* If it's already enabled, don't have to do anything */
 225         if (enabled)
 226                 return;
 227
 228         if (intel_alloc_mchbar_resource(dev_priv))
 229                 return;
 230
 231         dev_priv->mchbar_need_disable = true;
 232
 233         /* Space is allocated or reserved, so enable it. */
 234         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 235                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 236                                        temp | DEVEN_MCHBAR_EN);
 237         } else {
 238                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 239                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 240         }
 241 }
 242
 243 static void
 244 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 245 {
 246         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 247
 248         if (dev_priv->mchbar_need_disable) {
 249                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 250                         u32 deven_val;
 251
 252                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 253                                               &deven_val);
 254                         deven_val &= ~DEVEN_MCHBAR_EN;
 255                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 256                                                deven_val);
 257                 } else {
 258                         u32 mchbar_val;
 259
 260                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 261                                               &mchbar_val);
 262                         mchbar_val &= ~1;
 263                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 264                                                mchbar_val);
 265                 }
 266         }
 267
 268         if (dev_priv->mch_res.start)
 269                 release_resource(&dev_priv->mch_res);
 270 }
 271
 272 /* true = enable decode, false = disable decoder */
 273 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 274 {
 275         struct drm_i915_private *dev_priv = cookie;
 276
 277         intel_modeset_vga_set_state(dev_priv, state);
 278         if (state)
 279                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 280                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 281         else
 282                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 283 }
 284
 285 static int i915_resume_switcheroo(struct drm_i915_private *i915);
 286 static int i915_suspend_switcheroo(struct drm_i915_private *i915,
 287                                    pm_message_t state);
 288
 289 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 290 {
 291         struct drm_i915_private *i915 = pdev_to_i915(pdev);
 292         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 293
 294         if (!i915) {
 295                 dev_err(&pdev->dev, "DRM not initialized, aborting switch.\n");
 296                 return;
 297         }
 298
 299         if (state == VGA_SWITCHEROO_ON) {
 300                 pr_info("switched on\n");
 301                 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
 302                 /* i915 resume handler doesn't set to D0 */
 303                 pci_set_power_state(pdev, PCI_D0);
 304                 i915_resume_switcheroo(i915);
 305                 i915->drm.switch_power_state = DRM_SWITCH_POWER_ON;
 306         } else {
 307                 pr_info("switched off\n");
 308                 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
 309                 i915_suspend_switcheroo(i915, pmm);
 310                 i915->drm.switch_power_state = DRM_SWITCH_POWER_OFF;
 311         }
 312 }
 313
 314 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 315 {
 316         struct drm_i915_private *i915 = pdev_to_i915(pdev);
 317
 318         /*
 319          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 320          * locking inversion with the driver load path. And the access here is
 321          * completely racy anyway. So don't bother with locking for now.
 322          */
 323         return i915 && i915->drm.open_count == 0;
 324 }
 325
 326 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 327         .set_gpu_state = i915_switcheroo_set_state,
 328         .reprobe = NULL,
 329         .can_switch = i915_switcheroo_can_switch,
 330 };
 331
 332 static int i915_driver_modeset_probe(struct drm_i915_private *i915)
 333 {
 334         struct pci_dev *pdev = i915->drm.pdev;
 335         int ret;
 336
 337         if (i915_inject_probe_failure(i915))
 338                 return -ENODEV;
 339
 340         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
 341                 ret = drm_vblank_init(&i915->drm,
 342                                       INTEL_NUM_PIPES(i915));
 343                 if (ret)
 344                         goto out;
 345         }
 346
 347         intel_bios_init(i915);
 348
 349         /* If we have > 1 VGA cards, then we need to arbitrate access
 350          * to the common VGA resources.
 351          *
 352          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 353          * then we do not take part in VGA arbitration and the
 354          * vga_client_register() fails with -ENODEV.
 355          */
 356         ret = vga_client_register(pdev, i915, NULL, i915_vga_set_decode);
 357         if (ret && ret != -ENODEV)
 358                 goto out;
 359
 360         intel_register_dsm_handler();
 361
 362         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 363         if (ret)
 364                 goto cleanup_vga_client;
 365
 366         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 367         intel_update_rawclk(i915);
 368
 369         intel_power_domains_init_hw(i915, false);
 370
 371         intel_csr_ucode_init(i915);
 372
 373         ret = intel_irq_install(i915);
 374         if (ret)
 375                 goto cleanup_csr;
 376
 377         intel_gmbus_setup(i915);
 378
 379         /* Important: The output setup functions called by modeset_init need
 380          * working irqs for e.g. gmbus and dp aux transfers. */
 381         ret = intel_modeset_init(i915);
 382         if (ret)
 383                 goto cleanup_irq;
 384
 385         ret = i915_gem_init(i915);
 386         if (ret)
 387                 goto cleanup_modeset;
 388
 389         intel_overlay_setup(i915);
 390
 391         if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915))
 392                 return 0;
 393
 394         ret = intel_fbdev_init(&i915->drm);
 395         if (ret)
 396                 goto cleanup_gem;
 397
 398         /* Only enable hotplug handling once the fbdev is fully set up. */
 399         intel_hpd_init(i915);
 400
 401         intel_init_ipc(i915);
 402
 403         return 0;
 404
 405 cleanup_gem:
 406         i915_gem_suspend(i915);
 407         i915_gem_driver_remove(i915);
 408         i915_gem_driver_release(i915);
 409 cleanup_modeset:
 410         intel_modeset_driver_remove(i915);
 411 cleanup_irq:
 412         intel_irq_uninstall(i915);
 413         intel_gmbus_teardown(i915);
 414 cleanup_csr:
 415         intel_csr_ucode_fini(i915);
 416         intel_power_domains_driver_remove(i915);
 417         vga_switcheroo_unregister_client(pdev);
 418 cleanup_vga_client:
 419         vga_client_register(pdev, NULL, NULL, NULL);
 420 out:
 421         return ret;
 422 }
 423
 424 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 425 {
 426         struct apertures_struct *ap;
 427         struct pci_dev *pdev = dev_priv->drm.pdev;
 428         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 429         bool primary;
 430         int ret;
 431
 432         ap = alloc_apertures(1);
 433         if (!ap)
 434                 return -ENOMEM;
 435
 436         ap->ranges[0].base = ggtt->gmadr.start;
 437         ap->ranges[0].size = ggtt->mappable_end;
 438
 439         primary =
 440                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 441
 442         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 443
 444         kfree(ap);
 445
 446         return ret;
 447 }
 448
 449 static void i915_driver_modeset_remove(struct drm_i915_private *i915)
 450 {
 451         struct pci_dev *pdev = i915->drm.pdev;
 452
 453         intel_modeset_driver_remove(i915);
 454
 455         intel_bios_driver_remove(i915);
 456
 457         vga_switcheroo_unregister_client(pdev);
 458         vga_client_register(pdev, NULL, NULL, NULL);
 459
 460         intel_csr_ucode_fini(i915);
 461 }
 462
 463 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 464 {
 465         /*
 466          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 467          * CHV x1 PHY (DP/HDMI D)
 468          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 469          */
 470         if (IS_CHERRYVIEW(dev_priv)) {
 471                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 472                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 473         } else if (IS_VALLEYVIEW(dev_priv)) {
 474                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 475         }
 476 }
 477
 478 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 479 {
 480         /*
 481          * The i915 workqueue is primarily used for batched retirement of
 482          * requests (and thus managing bo) once the task has been completed
 483          * by the GPU. i915_retire_requests() is called directly when we
 484          * need high-priority retirement, such as waiting for an explicit
 485          * bo.
 486          *
 487          * It is also used for periodic low-priority events, such as
 488          * idle-timers and recording error state.
 489          *
 490          * All tasks on the workqueue are expected to acquire the dev mutex
 491          * so there is no point in running more than one instance of the
 492          * workqueue at any time.  Use an ordered one.
 493          */
 494         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 495         if (dev_priv->wq == NULL)
 496                 goto out_err;
 497
 498         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 499         if (dev_priv->hotplug.dp_wq == NULL)
 500                 goto out_free_wq;
 501
 502         return 0;
 503
 504 out_free_wq:
 505         destroy_workqueue(dev_priv->wq);
 506 out_err:
 507         DRM_ERROR("Failed to allocate workqueues.\n");
 508
 509         return -ENOMEM;
 510 }
 511
 512 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 513 {
 514         destroy_workqueue(dev_priv->hotplug.dp_wq);
 515         destroy_workqueue(dev_priv->wq);
 516 }
 517
 518 /*
 519  * We don't keep the workarounds for pre-production hardware, so we expect our
 520  * driver to fail on these machines in one way or another. A little warning on
 521  * dmesg may help both the user and the bug triagers.
 522  *
 523  * Our policy for removing pre-production workarounds is to keep the
 524  * current gen workarounds as a guide to the bring-up of the next gen
 525  * (workarounds have a habit of persisting!). Anything older than that
 526  * should be removed along with the complications they introduce.
 527  */
 528 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 529 {
 530         bool pre = false;
 531
 532         pre |= IS_HSW_EARLY_SDV(dev_priv);
 533         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 534         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 535         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 536
 537         if (pre) {
 538                 DRM_ERROR("This is a pre-production stepping. "
 539                           "It may not be fully functional.\n");
 540                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 541         }
 542 }
 543
 544 static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
 545 {
 546         if (!IS_VALLEYVIEW(i915))
 547                 return 0;
 548
 549         /* we write all the values in the struct, so no need to zero it out */
 550         i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state),
 551                                        GFP_KERNEL);
 552         if (!i915->vlv_s0ix_state)
 553                 return -ENOMEM;
 554
 555         return 0;
 556 }
 557
 558 static void vlv_free_s0ix_state(struct drm_i915_private *i915)
 559 {
 560         if (!i915->vlv_s0ix_state)
 561                 return;
 562
 563         kfree(i915->vlv_s0ix_state);
 564         i915->vlv_s0ix_state = NULL;
 565 }
 566
 567 /**
 568  * i915_driver_early_probe - setup state not requiring device access
 569  * @dev_priv: device private
 570  *
 571  * Initialize everything that is a "SW-only" state, that is state not
 572  * requiring accessing the device or exposing the driver via kernel internal
 573  * or userspace interfaces. Example steps belonging here: lock initialization,
 574  * system memory allocation, setting up device specific attributes and
 575  * function hooks not requiring accessing the device.
 576  */
 577 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 578 {
 579         int ret = 0;
 580
 581         if (i915_inject_probe_failure(dev_priv))
 582                 return -ENODEV;
 583
 584         intel_device_info_subplatform_init(dev_priv);
 585
 586         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 587         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 588
 589         spin_lock_init(&dev_priv->irq_lock);
 590         spin_lock_init(&dev_priv->gpu_error.lock);
 591         mutex_init(&dev_priv->backlight_lock);
 592
 593         mutex_init(&dev_priv->sb_lock);
 594         pm_qos_add_request(&dev_priv->sb_qos,
 595                            PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
 596
 597         mutex_init(&dev_priv->av_mutex);
 598         mutex_init(&dev_priv->wm.wm_mutex);
 599         mutex_init(&dev_priv->pps_mutex);
 600         mutex_init(&dev_priv->hdcp_comp_mutex);
 601
 602         i915_memcpy_init_early(dev_priv);
 603         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 604
 605         ret = i915_workqueues_init(dev_priv);
 606         if (ret < 0)
 607                 return ret;
 608
 609         ret = vlv_alloc_s0ix_state(dev_priv);
 610         if (ret < 0)
 611                 goto err_workqueues;
 612
 613         intel_wopcm_init_early(&dev_priv->wopcm);
 614
 615         intel_gt_init_early(&dev_priv->gt, dev_priv);
 616
 617         ret = i915_gem_init_early(dev_priv);
 618         if (ret < 0)
 619                 goto err_gt;
 620
 621         /* This must be called before any calls to HAS_PCH_* */
 622         intel_detect_pch(dev_priv);
 623
 624         intel_pm_setup(dev_priv);
 625         intel_init_dpio(dev_priv);
 626         ret = intel_power_domains_init(dev_priv);
 627         if (ret < 0)
 628                 goto err_gem;
 629         intel_irq_init(dev_priv);
 630         intel_init_display_hooks(dev_priv);
 631         intel_init_clock_gating_hooks(dev_priv);
 632         intel_init_audio_hooks(dev_priv);
 633         intel_display_crc_init(dev_priv);
 634
 635         intel_detect_preproduction_hw(dev_priv);
 636
 637         return 0;
 638
 639 err_gem:
 640         i915_gem_cleanup_early(dev_priv);
 641 err_gt:
 642         intel_gt_driver_late_release(&dev_priv->gt);
 643         vlv_free_s0ix_state(dev_priv);
 644 err_workqueues:
 645         i915_workqueues_cleanup(dev_priv);
 646         return ret;
 647 }
 648
 649 /**
 650  * i915_driver_late_release - cleanup the setup done in
 651  *                             i915_driver_early_probe()
 652  * @dev_priv: device private
 653  */
 654 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 655 {
 656         intel_irq_fini(dev_priv);
 657         intel_power_domains_cleanup(dev_priv);
 658         i915_gem_cleanup_early(dev_priv);
 659         intel_gt_driver_late_release(&dev_priv->gt);
 660         vlv_free_s0ix_state(dev_priv);
 661         i915_workqueues_cleanup(dev_priv);
 662
 663         pm_qos_remove_request(&dev_priv->sb_qos);
 664         mutex_destroy(&dev_priv->sb_lock);
 665 }
 666
 667 /**
 668  * i915_driver_mmio_probe - setup device MMIO
 669  * @dev_priv: device private
 670  *
 671  * Setup minimal device state necessary for MMIO accesses later in the
 672  * initialization sequence. The setup here should avoid any other device-wide
 673  * side effects or exposing the driver via kernel internal or user space
 674  * interfaces.
 675  */
 676 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 677 {
 678         int ret;
 679
 680         if (i915_inject_probe_failure(dev_priv))
 681                 return -ENODEV;
 682
 683         if (i915_get_bridge_dev(dev_priv))
 684                 return -EIO;
 685
 686         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 687         if (ret < 0)
 688                 goto err_bridge;
 689
 690         /* Try to make sure MCHBAR is enabled before poking at it */
 691         intel_setup_mchbar(dev_priv);
 692
 693         intel_device_info_init_mmio(dev_priv);
 694
 695         intel_uncore_prune_mmio_domains(&dev_priv->uncore);
 696
 697         intel_uc_init_mmio(&dev_priv->gt.uc);
 698
 699         ret = intel_engines_init_mmio(dev_priv);
 700         if (ret)
 701                 goto err_uncore;
 702
 703         i915_gem_init_mmio(dev_priv);
 704
 705         return 0;
 706
 707 err_uncore:
 708         intel_teardown_mchbar(dev_priv);
 709         intel_uncore_fini_mmio(&dev_priv->uncore);
 710 err_bridge:
 711         pci_dev_put(dev_priv->bridge_dev);
 712
 713         return ret;
 714 }
 715
 716 /**
 717  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 718  * @dev_priv: device private
 719  */
 720 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 721 {
 722         intel_engines_cleanup(dev_priv);
 723         intel_teardown_mchbar(dev_priv);
 724         intel_uncore_fini_mmio(&dev_priv->uncore);
 725         pci_dev_put(dev_priv->bridge_dev);
 726 }
 727
 728 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 729 {
 730         intel_gvt_sanitize_options(dev_priv);
 731 }
 732
 733 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
 734
 735 static const char *intel_dram_type_str(enum intel_dram_type type)
 736 {
 737         static const char * const str[] = {
 738                 DRAM_TYPE_STR(UNKNOWN),
 739                 DRAM_TYPE_STR(DDR3),
 740                 DRAM_TYPE_STR(DDR4),
 741                 DRAM_TYPE_STR(LPDDR3),
 742                 DRAM_TYPE_STR(LPDDR4),
 743         };
 744
 745         if (type >= ARRAY_SIZE(str))
 746                 type = INTEL_DRAM_UNKNOWN;
 747
 748         return str[type];
 749 }
 750
 751 #undef DRAM_TYPE_STR
 752
 753 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
 754 {
 755         return dimm->ranks * 64 / (dimm->width ?: 1);
 756 }
 757
 758 /* Returns total GB for the whole DIMM */
 759 static int skl_get_dimm_size(u16 val)
 760 {
 761         return val & SKL_DRAM_SIZE_MASK;
 762 }
 763
 764 static int skl_get_dimm_width(u16 val)
 765 {
 766         if (skl_get_dimm_size(val) == 0)
 767                 return 0;
 768
 769         switch (val & SKL_DRAM_WIDTH_MASK) {
 770         case SKL_DRAM_WIDTH_X8:
 771         case SKL_DRAM_WIDTH_X16:
 772         case SKL_DRAM_WIDTH_X32:
 773                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
 774                 return 8 << val;
 775         default:
 776                 MISSING_CASE(val);
 777                 return 0;
 778         }
 779 }
 780
 781 static int skl_get_dimm_ranks(u16 val)
 782 {
 783         if (skl_get_dimm_size(val) == 0)
 784                 return 0;
 785
 786         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
 787
 788         return val + 1;
 789 }
 790
 791 /* Returns total GB for the whole DIMM */
 792 static int cnl_get_dimm_size(u16 val)
 793 {
 794         return (val & CNL_DRAM_SIZE_MASK) / 2;
 795 }
 796
 797 static int cnl_get_dimm_width(u16 val)
 798 {
 799         if (cnl_get_dimm_size(val) == 0)
 800                 return 0;
 801
 802         switch (val & CNL_DRAM_WIDTH_MASK) {
 803         case CNL_DRAM_WIDTH_X8:
 804         case CNL_DRAM_WIDTH_X16:
 805         case CNL_DRAM_WIDTH_X32:
 806                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
 807                 return 8 << val;
 808         default:
 809                 MISSING_CASE(val);
 810                 return 0;
 811         }
 812 }
 813
 814 static int cnl_get_dimm_ranks(u16 val)
 815 {
 816         if (cnl_get_dimm_size(val) == 0)
 817                 return 0;
 818
 819         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
 820
 821         return val + 1;
 822 }
 823
 824 static bool
 825 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
 826 {
 827         /* Convert total GB to Gb per DRAM device */
 828         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
 829 }
 830
 831 static void
 832 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
 833                        struct dram_dimm_info *dimm,
 834                        int channel, char dimm_name, u16 val)
 835 {
 836         if (INTEL_GEN(dev_priv) >= 10) {
 837                 dimm->size = cnl_get_dimm_size(val);
 838                 dimm->width = cnl_get_dimm_width(val);
 839                 dimm->ranks = cnl_get_dimm_ranks(val);
 840         } else {
 841                 dimm->size = skl_get_dimm_size(val);
 842                 dimm->width = skl_get_dimm_width(val);
 843                 dimm->ranks = skl_get_dimm_ranks(val);
 844         }
 845
 846         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
 847                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
 848                       yesno(skl_is_16gb_dimm(dimm)));
 849 }
 850
 851 static int
 852 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
 853                           struct dram_channel_info *ch,
 854                           int channel, u32 val)
 855 {
 856         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
 857                                channel, 'L', val & 0xffff);
 858         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
 859                                channel, 'S', val >> 16);
 860
 861         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
 862                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
 863                 return -EINVAL;
 864         }
 865
 866         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
 867                 ch->ranks = 2;
 868         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
 869                 ch->ranks = 2;
 870         else
 871                 ch->ranks = 1;
 872
 873         ch->is_16gb_dimm =
 874                 skl_is_16gb_dimm(&ch->dimm_l) ||
 875                 skl_is_16gb_dimm(&ch->dimm_s);
 876
 877         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
 878                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
 879
 880         return 0;
 881 }
 882
 883 static bool
 884 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
 885                         const struct dram_channel_info *ch1)
 886 {
 887         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
 888                 (ch0->dimm_s.size == 0 ||
 889                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
 890 }
 891
 892 static int
 893 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 894 {
 895         struct dram_info *dram_info = &dev_priv->dram_info;
 896         struct dram_channel_info ch0 = {}, ch1 = {};
 897         u32 val;
 898         int ret;
 899
 900         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 901         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
 902         if (ret == 0)
 903                 dram_info->num_channels++;
 904
 905         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 906         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
 907         if (ret == 0)
 908                 dram_info->num_channels++;
 909
 910         if (dram_info->num_channels == 0) {
 911                 DRM_INFO("Number of memory channels is zero\n");
 912                 return -EINVAL;
 913         }
 914
 915         /*
 916          * If any of the channel is single rank channel, worst case output
 917          * will be same as if single rank memory, so consider single rank
 918          * memory.
 919          */
 920         if (ch0.ranks == 1 || ch1.ranks == 1)
 921                 dram_info->ranks = 1;
 922         else
 923                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
 924
 925         if (dram_info->ranks == 0) {
 926                 DRM_INFO("couldn't get memory rank information\n");
 927                 return -EINVAL;
 928         }
 929
 930         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
 931
 932         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
 933
 934         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
 935                       yesno(dram_info->symmetric_memory));
 936         return 0;
 937 }
 938
 939 static enum intel_dram_type
 940 skl_get_dram_type(struct drm_i915_private *dev_priv)
 941 {
 942         u32 val;
 943
 944         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 945
 946         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
 947         case SKL_DRAM_DDR_TYPE_DDR3:
 948                 return INTEL_DRAM_DDR3;
 949         case SKL_DRAM_DDR_TYPE_DDR4:
 950                 return INTEL_DRAM_DDR4;
 951         case SKL_DRAM_DDR_TYPE_LPDDR3:
 952                 return INTEL_DRAM_LPDDR3;
 953         case SKL_DRAM_DDR_TYPE_LPDDR4:
 954                 return INTEL_DRAM_LPDDR4;
 955         default:
 956                 MISSING_CASE(val);
 957                 return INTEL_DRAM_UNKNOWN;
 958         }
 959 }
 960
 961 static int
 962 skl_get_dram_info(struct drm_i915_private *dev_priv)
 963 {
 964         struct dram_info *dram_info = &dev_priv->dram_info;
 965         u32 mem_freq_khz, val;
 966         int ret;
 967
 968         dram_info->type = skl_get_dram_type(dev_priv);
 969         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
 970
 971         ret = skl_dram_get_channels_info(dev_priv);
 972         if (ret)
 973                 return ret;
 974
 975         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
 976         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
 977                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 978
 979         dram_info->bandwidth_kbps = dram_info->num_channels *
 980                                                         mem_freq_khz * 8;
 981
 982         if (dram_info->bandwidth_kbps == 0) {
 983                 DRM_INFO("Couldn't get system memory bandwidth\n");
 984                 return -EINVAL;
 985         }
 986
 987         dram_info->valid = true;
 988         return 0;
 989 }
 990
 991 /* Returns Gb per DRAM device */
 992 static int bxt_get_dimm_size(u32 val)
 993 {
 994         switch (val & BXT_DRAM_SIZE_MASK) {
 995         case BXT_DRAM_SIZE_4GBIT:
 996                 return 4;
 997         case BXT_DRAM_SIZE_6GBIT:
 998                 return 6;
 999         case BXT_DRAM_SIZE_8GBIT:
1000                 return 8;
1001         case BXT_DRAM_SIZE_12GBIT:
1002                 return 12;
1003         case BXT_DRAM_SIZE_16GBIT:
1004                 return 16;
1005         default:
1006                 MISSING_CASE(val);
1007                 return 0;
1008         }
1009 }
1010
1011 static int bxt_get_dimm_width(u32 val)
1012 {
1013         if (!bxt_get_dimm_size(val))
1014                 return 0;
1015
1016         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1017
1018         return 8 << val;
1019 }
1020
1021 static int bxt_get_dimm_ranks(u32 val)
1022 {
1023         if (!bxt_get_dimm_size(val))
1024                 return 0;
1025
1026         switch (val & BXT_DRAM_RANK_MASK) {
1027         case BXT_DRAM_RANK_SINGLE:
1028                 return 1;
1029         case BXT_DRAM_RANK_DUAL:
1030                 return 2;
1031         default:
1032                 MISSING_CASE(val);
1033                 return 0;
1034         }
1035 }
1036
1037 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1038 {
1039         if (!bxt_get_dimm_size(val))
1040                 return INTEL_DRAM_UNKNOWN;
1041
1042         switch (val & BXT_DRAM_TYPE_MASK) {
1043         case BXT_DRAM_TYPE_DDR3:
1044                 return INTEL_DRAM_DDR3;
1045         case BXT_DRAM_TYPE_LPDDR3:
1046                 return INTEL_DRAM_LPDDR3;
1047         case BXT_DRAM_TYPE_DDR4:
1048                 return INTEL_DRAM_DDR4;
1049         case BXT_DRAM_TYPE_LPDDR4:
1050                 return INTEL_DRAM_LPDDR4;
1051         default:
1052                 MISSING_CASE(val);
1053                 return INTEL_DRAM_UNKNOWN;
1054         }
1055 }
1056
1057 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1058                               u32 val)
1059 {
1060         dimm->width = bxt_get_dimm_width(val);
1061         dimm->ranks = bxt_get_dimm_ranks(val);
1062
1063         /*
1064          * Size in register is Gb per DRAM device. Convert to total
1065          * GB to match the way we report this for non-LP platforms.
1066          */
1067         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1068 }
1069
1070 static int
1071 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1072 {
1073         struct dram_info *dram_info = &dev_priv->dram_info;
1074         u32 dram_channels;
1075         u32 mem_freq_khz, val;
1076         u8 num_active_channels;
1077         int i;
1078
1079         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1080         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1081                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1082
1083         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1084         num_active_channels = hweight32(dram_channels);
1085
1086         /* Each active bit represents 4-byte channel */
1087         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1088
1089         if (dram_info->bandwidth_kbps == 0) {
1090                 DRM_INFO("Couldn't get system memory bandwidth\n");
1091                 return -EINVAL;
1092         }
1093
1094         /*
1095          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1096          */
1097         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1098                 struct dram_dimm_info dimm;
1099                 enum intel_dram_type type;
1100
1101                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1102                 if (val == 0xFFFFFFFF)
1103                         continue;
1104
1105                 dram_info->num_channels++;
1106
1107                 bxt_get_dimm_info(&dimm, val);
1108                 type = bxt_get_dimm_type(val);
1109
1110                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1111                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1112                         dram_info->type != type);
1113
1114                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1115                               i - BXT_D_CR_DRP0_DUNIT_START,
1116                               dimm.size, dimm.width, dimm.ranks,
1117                               intel_dram_type_str(type));
1118
1119                 /*
1120                  * If any of the channel is single rank channel,
1121                  * worst case output will be same as if single rank
1122                  * memory, so consider single rank memory.
1123                  */
1124                 if (dram_info->ranks == 0)
1125                         dram_info->ranks = dimm.ranks;
1126                 else if (dimm.ranks == 1)
1127                         dram_info->ranks = 1;
1128
1129                 if (type != INTEL_DRAM_UNKNOWN)
1130                         dram_info->type = type;
1131         }
1132
1133         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1134             dram_info->ranks == 0) {
1135                 DRM_INFO("couldn't get memory information\n");
1136                 return -EINVAL;
1137         }
1138
1139         dram_info->valid = true;
1140         return 0;
1141 }
1142
1143 static void
1144 intel_get_dram_info(struct drm_i915_private *dev_priv)
1145 {
1146         struct dram_info *dram_info = &dev_priv->dram_info;
1147         int ret;
1148
1149         /*
1150          * Assume 16Gb DIMMs are present until proven otherwise.
1151          * This is only used for the level 0 watermark latency
1152          * w/a which does not apply to bxt/glk.
1153          */
1154         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1155
1156         if (INTEL_GEN(dev_priv) < 9)
1157                 return;
1158
1159         if (IS_GEN9_LP(dev_priv))
1160                 ret = bxt_get_dram_info(dev_priv);
1161         else
1162                 ret = skl_get_dram_info(dev_priv);
1163         if (ret)
1164                 return;
1165
1166         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1167                       dram_info->bandwidth_kbps,
1168                       dram_info->num_channels);
1169
1170         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1171                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1172 }
1173
1174 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1175 {
1176         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1177         const unsigned int sets[4] = { 1, 1, 2, 2 };
1178
1179         return EDRAM_NUM_BANKS(cap) *
1180                 ways[EDRAM_WAYS_IDX(cap)] *
1181                 sets[EDRAM_SETS_IDX(cap)];
1182 }
1183
1184 static void edram_detect(struct drm_i915_private *dev_priv)
1185 {
1186         u32 edram_cap = 0;
1187
1188         if (!(IS_HASWELL(dev_priv) ||
1189               IS_BROADWELL(dev_priv) ||
1190               INTEL_GEN(dev_priv) >= 9))
1191                 return;
1192
1193         edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1194
1195         /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1196
1197         if (!(edram_cap & EDRAM_ENABLED))
1198                 return;
1199
1200         /*
1201          * The needed capability bits for size calculation are not there with
1202          * pre gen9 so return 128MB always.
1203          */
1204         if (INTEL_GEN(dev_priv) < 9)
1205                 dev_priv->edram_size_mb = 128;
1206         else
1207                 dev_priv->edram_size_mb =
1208                         gen9_edram_size_mb(dev_priv, edram_cap);
1209
1210         dev_info(dev_priv->drm.dev,
1211                  "Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1212 }
1213
1214 /**
1215  * i915_driver_hw_probe - setup state requiring device access
1216  * @dev_priv: device private
1217  *
1218  * Setup state that requires accessing the device, but doesn't require
1219  * exposing the driver via kernel internal or userspace interfaces.
1220  */
1221 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
1222 {
1223         struct pci_dev *pdev = dev_priv->drm.pdev;
1224         int ret;
1225
1226         if (i915_inject_probe_failure(dev_priv))
1227                 return -ENODEV;
1228
1229         intel_device_info_runtime_init(dev_priv);
1230
1231         if (HAS_PPGTT(dev_priv)) {
1232                 if (intel_vgpu_active(dev_priv) &&
1233                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1234                         i915_report_error(dev_priv,
1235                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1236                         return -ENXIO;
1237                 }
1238         }
1239
1240         if (HAS_EXECLISTS(dev_priv)) {
1241                 /*
1242                  * Older GVT emulation depends upon intercepting CSB mmio,
1243                  * which we no longer use, preferring to use the HWSP cache
1244                  * instead.
1245                  */
1246                 if (intel_vgpu_active(dev_priv) &&
1247                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1248                         i915_report_error(dev_priv,
1249                                           "old vGPU host found, support for HWSP emulation required\n");
1250                         return -ENXIO;
1251                 }
1252         }
1253
1254         intel_sanitize_options(dev_priv);
1255
1256         /* needs to be done before ggtt probe */
1257         edram_detect(dev_priv);
1258
1259         i915_perf_init(dev_priv);
1260
1261         ret = i915_ggtt_probe_hw(dev_priv);
1262         if (ret)
1263                 goto err_perf;
1264
1265         /*
1266          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1267          * otherwise the vga fbdev driver falls over.
1268          */
1269         ret = i915_kick_out_firmware_fb(dev_priv);
1270         if (ret) {
1271                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1272                 goto err_ggtt;
1273         }
1274
1275         ret = vga_remove_vgacon(pdev);
1276         if (ret) {
1277                 DRM_ERROR("failed to remove conflicting VGA console\n");
1278                 goto err_ggtt;
1279         }
1280
1281         ret = i915_ggtt_init_hw(dev_priv);
1282         if (ret)
1283                 goto err_ggtt;
1284
1285         intel_gt_init_hw_early(dev_priv);
1286
1287         ret = i915_ggtt_enable_hw(dev_priv);
1288         if (ret) {
1289                 DRM_ERROR("failed to enable GGTT\n");
1290                 goto err_ggtt;
1291         }
1292
1293         pci_set_master(pdev);
1294
1295         /*
1296          * We don't have a max segment size, so set it to the max so sg's
1297          * debugging layer doesn't complain
1298          */
1299         dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1300
1301         /* overlay on gen2 is broken and can't address above 1G */
1302         if (IS_GEN(dev_priv, 2)) {
1303                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1304                 if (ret) {
1305                         DRM_ERROR("failed to set DMA mask\n");
1306
1307                         goto err_ggtt;
1308                 }
1309         }
1310
1311         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1312          * using 32bit addressing, overwriting memory if HWS is located
1313          * above 4GB.
1314          *
1315          * The documentation also mentions an issue with undefined
1316          * behaviour if any general state is accessed within a page above 4GB,
1317          * which also needs to be handled carefully.
1318          */
1319         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1320                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1321
1322                 if (ret) {
1323                         DRM_ERROR("failed to set DMA mask\n");
1324
1325                         goto err_ggtt;
1326                 }
1327         }
1328
1329         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1330                            PM_QOS_DEFAULT_VALUE);
1331
1332         intel_gt_init_workarounds(dev_priv);
1333
1334         /* On the 945G/GM, the chipset reports the MSI capability on the
1335          * integrated graphics even though the support isn't actually there
1336          * according to the published specs.  It doesn't appear to function
1337          * correctly in testing on 945G.
1338          * This may be a side effect of MSI having been made available for PEG
1339          * and the registers being closely associated.
1340          *
1341          * According to chipset errata, on the 965GM, MSI interrupts may
1342          * be lost or delayed, and was defeatured. MSI interrupts seem to
1343          * get lost on g4x as well, and interrupt delivery seems to stay
1344          * properly dead afterwards. So we'll just disable them for all
1345          * pre-gen5 chipsets.
1346          *
1347          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1348          * interrupts even when in MSI mode. This results in spurious
1349          * interrupt warnings if the legacy irq no. is shared with another
1350          * device. The kernel then disables that interrupt source and so
1351          * prevents the other device from working properly.
1352          */
1353         if (INTEL_GEN(dev_priv) >= 5) {
1354                 if (pci_enable_msi(pdev) < 0)
1355                         DRM_DEBUG_DRIVER("can't enable MSI");
1356         }
1357
1358         ret = intel_gvt_init(dev_priv);
1359         if (ret)
1360                 goto err_msi;
1361
1362         intel_opregion_setup(dev_priv);
1363         /*
1364          * Fill the dram structure to get the system raw bandwidth and
1365          * dram info. This will be used for memory latency calculation.
1366          */
1367         intel_get_dram_info(dev_priv);
1368
1369         intel_bw_init_hw(dev_priv);
1370
1371         return 0;
1372
1373 err_msi:
1374         if (pdev->msi_enabled)
1375                 pci_disable_msi(pdev);
1376         pm_qos_remove_request(&dev_priv->pm_qos);
1377 err_ggtt:
1378         i915_ggtt_driver_release(dev_priv);
1379 err_perf:
1380         i915_perf_fini(dev_priv);
1381         return ret;
1382 }
1383
1384 /**
1385  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
1386  * @dev_priv: device private
1387  */
1388 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
1389 {
1390         struct pci_dev *pdev = dev_priv->drm.pdev;
1391
1392         i915_perf_fini(dev_priv);
1393
1394         if (pdev->msi_enabled)
1395                 pci_disable_msi(pdev);
1396
1397         pm_qos_remove_request(&dev_priv->pm_qos);
1398 }
1399
1400 /**
1401  * i915_driver_register - register the driver with the rest of the system
1402  * @dev_priv: device private
1403  *
1404  * Perform any steps necessary to make the driver available via kernel
1405  * internal or userspace interfaces.
1406  */
1407 static void i915_driver_register(struct drm_i915_private *dev_priv)
1408 {
1409         struct drm_device *dev = &dev_priv->drm;
1410
1411         i915_gem_driver_register(dev_priv);
1412         i915_pmu_register(dev_priv);
1413
1414         /*
1415          * Notify a valid surface after modesetting,
1416          * when running inside a VM.
1417          */
1418         if (intel_vgpu_active(dev_priv))
1419                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1420
1421         /* Reveal our presence to userspace */
1422         if (drm_dev_register(dev, 0) == 0) {
1423                 i915_debugfs_register(dev_priv);
1424                 i915_setup_sysfs(dev_priv);
1425
1426                 /* Depends on sysfs having been initialized */
1427                 i915_perf_register(dev_priv);
1428         } else
1429                 DRM_ERROR("Failed to register driver for userspace access!\n");
1430
1431         if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
1432                 /* Must be done after probing outputs */
1433                 intel_opregion_register(dev_priv);
1434                 acpi_video_register();
1435         }
1436
1437         intel_gt_driver_register(&dev_priv->gt);
1438
1439         intel_audio_init(dev_priv);
1440
1441         /*
1442          * Some ports require correctly set-up hpd registers for detection to
1443          * work properly (leading to ghost connected connector status), e.g. VGA
1444          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1445          * irqs are fully enabled. We do it last so that the async config
1446          * cannot run before the connectors are registered.
1447          */
1448         intel_fbdev_initial_config_async(dev);
1449
1450         /*
1451          * We need to coordinate the hotplugs with the asynchronous fbdev
1452          * configuration, for which we use the fbdev->async_cookie.
1453          */
1454         if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv))
1455                 drm_kms_helper_poll_init(dev);
1456
1457         intel_power_domains_enable(dev_priv);
1458         intel_runtime_pm_enable(&dev_priv->runtime_pm);
1459 }
1460
1461 /**
1462  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1463  * @dev_priv: device private
1464  */
1465 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1466 {
1467         intel_runtime_pm_disable(&dev_priv->runtime_pm);
1468         intel_power_domains_disable(dev_priv);
1469
1470         intel_fbdev_unregister(dev_priv);
1471         intel_audio_deinit(dev_priv);
1472
1473         /*
1474          * After flushing the fbdev (incl. a late async config which will
1475          * have delayed queuing of a hotplug event), then flush the hotplug
1476          * events.
1477          */
1478         drm_kms_helper_poll_fini(&dev_priv->drm);
1479
1480         intel_gt_driver_unregister(&dev_priv->gt);
1481         acpi_video_unregister();
1482         intel_opregion_unregister(dev_priv);
1483
1484         i915_perf_unregister(dev_priv);
1485         i915_pmu_unregister(dev_priv);
1486
1487         i915_teardown_sysfs(dev_priv);
1488         drm_dev_unplug(&dev_priv->drm);
1489
1490         i915_gem_driver_unregister(dev_priv);
1491 }
1492
1493 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1494 {
1495         if (drm_debug & DRM_UT_DRIVER) {
1496                 struct drm_printer p = drm_debug_printer("i915 device info:");
1497
1498                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1499                            INTEL_DEVID(dev_priv),
1500                            INTEL_REVID(dev_priv),
1501                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1502                            intel_subplatform(RUNTIME_INFO(dev_priv),
1503                                              INTEL_INFO(dev_priv)->platform),
1504                            INTEL_GEN(dev_priv));
1505
1506                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1507                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1508         }
1509
1510         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1511                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1512         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1513                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1514         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1515                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1516 }
1517
1518 static struct drm_i915_private *
1519 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1520 {
1521         const struct intel_device_info *match_info =
1522                 (struct intel_device_info *)ent->driver_data;
1523         struct intel_device_info *device_info;
1524         struct drm_i915_private *i915;
1525         int err;
1526
1527         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1528         if (!i915)
1529                 return ERR_PTR(-ENOMEM);
1530
1531         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1532         if (err) {
1533                 kfree(i915);
1534                 return ERR_PTR(err);
1535         }
1536
1537         i915->drm.dev_private = i915;
1538
1539         i915->drm.pdev = pdev;
1540         pci_set_drvdata(pdev, i915);
1541
1542         /* Setup the write-once "constant" device info */
1543         device_info = mkwrite_device_info(i915);
1544         memcpy(device_info, match_info, sizeof(*device_info));
1545         RUNTIME_INFO(i915)->device_id = pdev->device;
1546
1547         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1548
1549         return i915;
1550 }
1551
1552 static void i915_driver_destroy(struct drm_i915_private *i915)
1553 {
1554         struct pci_dev *pdev = i915->drm.pdev;
1555
1556         drm_dev_fini(&i915->drm);
1557         kfree(i915);
1558
1559         /* And make sure we never chase our dangling pointer from pci_dev */
1560         pci_set_drvdata(pdev, NULL);
1561 }
1562
1563 /**
1564  * i915_driver_probe - setup chip and create an initial config
1565  * @pdev: PCI device
1566  * @ent: matching PCI ID entry
1567  *
1568  * The driver probe routine has to do several things:
1569  *   - drive output discovery via intel_modeset_init()
1570  *   - initialize the memory manager
1571  *   - allocate initial config memory
1572  *   - setup the DRM framebuffer with the allocated memory
1573  */
1574 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1575 {
1576         const struct intel_device_info *match_info =
1577                 (struct intel_device_info *)ent->driver_data;
1578         struct drm_i915_private *dev_priv;
1579         int ret;
1580
1581         dev_priv = i915_driver_create(pdev, ent);
1582         if (IS_ERR(dev_priv))
1583                 return PTR_ERR(dev_priv);
1584
1585         /* Disable nuclear pageflip by default on pre-ILK */
1586         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1587                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1588
1589         ret = pci_enable_device(pdev);
1590         if (ret)
1591                 goto out_fini;
1592
1593         ret = i915_driver_early_probe(dev_priv);
1594         if (ret < 0)
1595                 goto out_pci_disable;
1596
1597         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1598
1599         i915_detect_vgpu(dev_priv);
1600
1601         ret = i915_driver_mmio_probe(dev_priv);
1602         if (ret < 0)
1603                 goto out_runtime_pm_put;
1604
1605         ret = i915_driver_hw_probe(dev_priv);
1606         if (ret < 0)
1607                 goto out_cleanup_mmio;
1608
1609         ret = i915_driver_modeset_probe(dev_priv);
1610         if (ret < 0)
1611                 goto out_cleanup_hw;
1612
1613         i915_driver_register(dev_priv);
1614
1615         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1616
1617         i915_welcome_messages(dev_priv);
1618
1619         return 0;
1620
1621 out_cleanup_hw:
1622         i915_driver_hw_remove(dev_priv);
1623         i915_ggtt_driver_release(dev_priv);
1624 out_cleanup_mmio:
1625         i915_driver_mmio_release(dev_priv);
1626 out_runtime_pm_put:
1627         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1628         i915_driver_late_release(dev_priv);
1629 out_pci_disable:
1630         pci_disable_device(pdev);
1631 out_fini:
1632         i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret);
1633         i915_driver_destroy(dev_priv);
1634         return ret;
1635 }
1636
1637 void i915_driver_remove(struct drm_i915_private *i915)
1638 {
1639         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1640
1641         i915_driver_unregister(i915);
1642
1643         /*
1644          * After unregistering the device to prevent any new users, cancel
1645          * all in-flight requests so that we can quickly unbind the active
1646          * resources.
1647          */
1648         intel_gt_set_wedged(&i915->gt);
1649
1650         /* Flush any external code that still may be under the RCU lock */
1651         synchronize_rcu();
1652
1653         i915_gem_suspend(i915);
1654
1655         drm_atomic_helper_shutdown(&i915->drm);
1656
1657         intel_gvt_driver_remove(i915);
1658
1659         i915_driver_modeset_remove(i915);
1660
1661         /* Free error state after interrupts are fully disabled. */
1662         cancel_delayed_work_sync(&i915->gt.hangcheck.work);
1663         i915_reset_error_state(i915);
1664
1665         i915_gem_driver_remove(i915);
1666
1667         intel_power_domains_driver_remove(i915);
1668
1669         i915_driver_hw_remove(i915);
1670
1671         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1672 }
1673
1674 static void i915_driver_release(struct drm_device *dev)
1675 {
1676         struct drm_i915_private *dev_priv = to_i915(dev);
1677         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1678
1679         disable_rpm_wakeref_asserts(rpm);
1680
1681         i915_gem_driver_release(dev_priv);
1682
1683         i915_ggtt_driver_release(dev_priv);
1684
1685         i915_driver_mmio_release(dev_priv);
1686
1687         enable_rpm_wakeref_asserts(rpm);
1688         intel_runtime_pm_driver_release(rpm);
1689
1690         i915_driver_late_release(dev_priv);
1691         i915_driver_destroy(dev_priv);
1692 }
1693
1694 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1695 {
1696         struct drm_i915_private *i915 = to_i915(dev);
1697         int ret;
1698
1699         ret = i915_gem_open(i915, file);
1700         if (ret)
1701                 return ret;
1702
1703         return 0;
1704 }
1705
1706 /**
1707  * i915_driver_lastclose - clean up after all DRM clients have exited
1708  * @dev: DRM device
1709  *
1710  * Take care of cleaning up after all DRM clients have exited.  In the
1711  * mode setting case, we want to restore the kernel's initial mode (just
1712  * in case the last client left us in a bad state).
1713  *
1714  * Additionally, in the non-mode setting case, we'll tear down the GTT
1715  * and DMA structures, since the kernel won't be using them, and clea
1716  * up any GEM state.
1717  */
1718 static void i915_driver_lastclose(struct drm_device *dev)
1719 {
1720         intel_fbdev_restore_mode(dev);
1721         vga_switcheroo_process_delayed_switch();
1722 }
1723
1724 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1725 {
1726         struct drm_i915_file_private *file_priv = file->driver_priv;
1727
1728         mutex_lock(&dev->struct_mutex);
1729         i915_gem_context_close(file);
1730         i915_gem_release(dev, file);
1731         mutex_unlock(&dev->struct_mutex);
1732
1733         kfree_rcu(file_priv, rcu);
1734
1735         /* Catch up with all the deferred frees from "this" client */
1736         i915_gem_flush_free_objects(to_i915(dev));
1737 }
1738
1739 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1740 {
1741         struct drm_device *dev = &dev_priv->drm;
1742         struct intel_encoder *encoder;
1743
1744         drm_modeset_lock_all(dev);
1745         for_each_intel_encoder(dev, encoder)
1746                 if (encoder->suspend)
1747                         encoder->suspend(encoder);
1748         drm_modeset_unlock_all(dev);
1749 }
1750
1751 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1752                               bool rpm_resume);
1753 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1754
1755 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1756 {
1757 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1758         if (acpi_target_system_state() < ACPI_STATE_S3)
1759                 return true;
1760 #endif
1761         return false;
1762 }
1763
1764 static int i915_drm_prepare(struct drm_device *dev)
1765 {
1766         struct drm_i915_private *i915 = to_i915(dev);
1767
1768         /*
1769          * NB intel_display_suspend() may issue new requests after we've
1770          * ostensibly marked the GPU as ready-to-sleep here. We need to
1771          * split out that work and pull it forward so that after point,
1772          * the GPU is not woken again.
1773          */
1774         i915_gem_suspend(i915);
1775
1776         return 0;
1777 }
1778
1779 static int i915_drm_suspend(struct drm_device *dev)
1780 {
1781         struct drm_i915_private *dev_priv = to_i915(dev);
1782         struct pci_dev *pdev = dev_priv->drm.pdev;
1783         pci_power_t opregion_target_state;
1784
1785         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1786
1787         /* We do a lot of poking in a lot of registers, make sure they work
1788          * properly. */
1789         intel_power_domains_disable(dev_priv);
1790
1791         drm_kms_helper_poll_disable(dev);
1792
1793         pci_save_state(pdev);
1794
1795         intel_display_suspend(dev);
1796
1797         intel_dp_mst_suspend(dev_priv);
1798
1799         intel_runtime_pm_disable_interrupts(dev_priv);
1800         intel_hpd_cancel_work(dev_priv);
1801
1802         intel_suspend_encoders(dev_priv);
1803
1804         intel_suspend_hw(dev_priv);
1805
1806         i915_gem_suspend_gtt_mappings(dev_priv);
1807
1808         i915_save_state(dev_priv);
1809
1810         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1811         intel_opregion_suspend(dev_priv, opregion_target_state);
1812
1813         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1814
1815         dev_priv->suspend_count++;
1816
1817         intel_csr_ucode_suspend(dev_priv);
1818
1819         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1820
1821         return 0;
1822 }
1823
1824 static enum i915_drm_suspend_mode
1825 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1826 {
1827         if (hibernate)
1828                 return I915_DRM_SUSPEND_HIBERNATE;
1829
1830         if (suspend_to_idle(dev_priv))
1831                 return I915_DRM_SUSPEND_IDLE;
1832
1833         return I915_DRM_SUSPEND_MEM;
1834 }
1835
1836 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1837 {
1838         struct drm_i915_private *dev_priv = to_i915(dev);
1839         struct pci_dev *pdev = dev_priv->drm.pdev;
1840         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1841         int ret = 0;
1842
1843         disable_rpm_wakeref_asserts(rpm);
1844
1845         i915_gem_suspend_late(dev_priv);
1846
1847         intel_uncore_suspend(&dev_priv->uncore);
1848
1849         intel_power_domains_suspend(dev_priv,
1850                                     get_suspend_mode(dev_priv, hibernation));
1851
1852         intel_display_power_suspend_late(dev_priv);
1853
1854         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1855                 ret = vlv_suspend_complete(dev_priv);
1856
1857         if (ret) {
1858                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1859                 intel_power_domains_resume(dev_priv);
1860
1861                 goto out;
1862         }
1863
1864         pci_disable_device(pdev);
1865         /*
1866          * During hibernation on some platforms the BIOS may try to access
1867          * the device even though it's already in D3 and hang the machine. So
1868          * leave the device in D0 on those platforms and hope the BIOS will
1869          * power down the device properly. The issue was seen on multiple old
1870          * GENs with different BIOS vendors, so having an explicit blacklist
1871          * is inpractical; apply the workaround on everything pre GEN6. The
1872          * platforms where the issue was seen:
1873          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1874          * Fujitsu FSC S7110
1875          * Acer Aspire 1830T
1876          */
1877         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1878                 pci_set_power_state(pdev, PCI_D3hot);
1879
1880 out:
1881         enable_rpm_wakeref_asserts(rpm);
1882         if (!dev_priv->uncore.user_forcewake_count)
1883                 intel_runtime_pm_driver_release(rpm);
1884
1885         return ret;
1886 }
1887
1888 static int
1889 i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1890 {
1891         int error;
1892
1893         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1894                          state.event != PM_EVENT_FREEZE))
1895                 return -EINVAL;
1896
1897         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1898                 return 0;
1899
1900         error = i915_drm_suspend(&i915->drm);
1901         if (error)
1902                 return error;
1903
1904         return i915_drm_suspend_late(&i915->drm, false);
1905 }
1906
1907 static int i915_drm_resume(struct drm_device *dev)
1908 {
1909         struct drm_i915_private *dev_priv = to_i915(dev);
1910         int ret;
1911
1912         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1913         intel_gt_pm_disable(&dev_priv->gt);
1914
1915         i915_gem_sanitize(dev_priv);
1916
1917         ret = i915_ggtt_enable_hw(dev_priv);
1918         if (ret)
1919                 DRM_ERROR("failed to re-enable GGTT\n");
1920
1921         mutex_lock(&dev_priv->drm.struct_mutex);
1922         i915_gem_restore_gtt_mappings(dev_priv);
1923         i915_gem_restore_fences(dev_priv);
1924         mutex_unlock(&dev_priv->drm.struct_mutex);
1925
1926         intel_csr_ucode_resume(dev_priv);
1927
1928         i915_restore_state(dev_priv);
1929         intel_pps_unlock_regs_wa(dev_priv);
1930
1931         intel_init_pch_refclk(dev_priv);
1932
1933         /*
1934          * Interrupts have to be enabled before any batches are run. If not the
1935          * GPU will hang. i915_gem_init_hw() will initiate batches to
1936          * update/restore the context.
1937          *
1938          * drm_mode_config_reset() needs AUX interrupts.
1939          *
1940          * Modeset enabling in intel_modeset_init_hw() also needs working
1941          * interrupts.
1942          */
1943         intel_runtime_pm_enable_interrupts(dev_priv);
1944
1945         drm_mode_config_reset(dev);
1946
1947         i915_gem_resume(dev_priv);
1948
1949         intel_modeset_init_hw(dev_priv);
1950         intel_init_clock_gating(dev_priv);
1951
1952         spin_lock_irq(&dev_priv->irq_lock);
1953         if (dev_priv->display.hpd_irq_setup)
1954                 dev_priv->display.hpd_irq_setup(dev_priv);
1955         spin_unlock_irq(&dev_priv->irq_lock);
1956
1957         intel_dp_mst_resume(dev_priv);
1958
1959         intel_display_resume(dev);
1960
1961         drm_kms_helper_poll_enable(dev);
1962
1963         /*
1964          * ... but also need to make sure that hotplug processing
1965          * doesn't cause havoc. Like in the driver load code we don't
1966          * bother with the tiny race here where we might lose hotplug
1967          * notifications.
1968          * */
1969         intel_hpd_init(dev_priv);
1970
1971         intel_opregion_resume(dev_priv);
1972
1973         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1974
1975         intel_power_domains_enable(dev_priv);
1976
1977         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1978
1979         return 0;
1980 }
1981
1982 static int i915_drm_resume_early(struct drm_device *dev)
1983 {
1984         struct drm_i915_private *dev_priv = to_i915(dev);
1985         struct pci_dev *pdev = dev_priv->drm.pdev;
1986         int ret;
1987
1988         /*
1989          * We have a resume ordering issue with the snd-hda driver also
1990          * requiring our device to be power up. Due to the lack of a
1991          * parent/child relationship we currently solve this with an early
1992          * resume hook.
1993          *
1994          * FIXME: This should be solved with a special hdmi sink device or
1995          * similar so that power domains can be employed.
1996          */
1997
1998         /*
1999          * Note that we need to set the power state explicitly, since we
2000          * powered off the device during freeze and the PCI core won't power
2001          * it back up for us during thaw. Powering off the device during
2002          * freeze is not a hard requirement though, and during the
2003          * suspend/resume phases the PCI core makes sure we get here with the
2004          * device powered on. So in case we change our freeze logic and keep
2005          * the device powered we can also remove the following set power state
2006          * call.
2007          */
2008         ret = pci_set_power_state(pdev, PCI_D0);
2009         if (ret) {
2010                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2011                 return ret;
2012         }
2013
2014         /*
2015          * Note that pci_enable_device() first enables any parent bridge
2016          * device and only then sets the power state for this device. The
2017          * bridge enabling is a nop though, since bridge devices are resumed
2018          * first. The order of enabling power and enabling the device is
2019          * imposed by the PCI core as described above, so here we preserve the
2020          * same order for the freeze/thaw phases.
2021          *
2022          * TODO: eventually we should remove pci_disable_device() /
2023          * pci_enable_enable_device() from suspend/resume. Due to how they
2024          * depend on the device enable refcount we can't anyway depend on them
2025          * disabling/enabling the device.
2026          */
2027         if (pci_enable_device(pdev))
2028                 return -EIO;
2029
2030         pci_set_master(pdev);
2031
2032         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2033
2034         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2035                 ret = vlv_resume_prepare(dev_priv, false);
2036         if (ret)
2037                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2038                           ret);
2039
2040         intel_uncore_resume_early(&dev_priv->uncore);
2041
2042         intel_gt_check_and_clear_faults(&dev_priv->gt);
2043
2044         intel_display_power_resume_early(dev_priv);
2045
2046         intel_gt_pm_disable(&dev_priv->gt);
2047
2048         intel_power_domains_resume(dev_priv);
2049
2050         intel_gt_sanitize(&dev_priv->gt, true);
2051
2052         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2053
2054         return ret;
2055 }
2056
2057 static int i915_resume_switcheroo(struct drm_i915_private *i915)
2058 {
2059         int ret;
2060
2061         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2062                 return 0;
2063
2064         ret = i915_drm_resume_early(&i915->drm);
2065         if (ret)
2066                 return ret;
2067
2068         return i915_drm_resume(&i915->drm);
2069 }
2070
2071 static int i915_pm_prepare(struct device *kdev)
2072 {
2073         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2074
2075         if (!i915) {
2076                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2077                 return -ENODEV;
2078         }
2079
2080         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2081                 return 0;
2082
2083         return i915_drm_prepare(&i915->drm);
2084 }
2085
2086 static int i915_pm_suspend(struct device *kdev)
2087 {
2088         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2089
2090         if (!i915) {
2091                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2092                 return -ENODEV;
2093         }
2094
2095         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2096                 return 0;
2097
2098         return i915_drm_suspend(&i915->drm);
2099 }
2100
2101 static int i915_pm_suspend_late(struct device *kdev)
2102 {
2103         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2104
2105         /*
2106          * We have a suspend ordering issue with the snd-hda driver also
2107          * requiring our device to be power up. Due to the lack of a
2108          * parent/child relationship we currently solve this with an late
2109          * suspend hook.
2110          *
2111          * FIXME: This should be solved with a special hdmi sink device or
2112          * similar so that power domains can be employed.
2113          */
2114         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2115                 return 0;
2116
2117         return i915_drm_suspend_late(&i915->drm, false);
2118 }
2119
2120 static int i915_pm_poweroff_late(struct device *kdev)
2121 {
2122         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2123
2124         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2125                 return 0;
2126
2127         return i915_drm_suspend_late(&i915->drm, true);
2128 }
2129
2130 static int i915_pm_resume_early(struct device *kdev)
2131 {
2132         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2133
2134         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2135                 return 0;
2136
2137         return i915_drm_resume_early(&i915->drm);
2138 }
2139
2140 static int i915_pm_resume(struct device *kdev)
2141 {
2142         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2143
2144         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2145                 return 0;
2146
2147         return i915_drm_resume(&i915->drm);
2148 }
2149
2150 /* freeze: before creating the hibernation_image */
2151 static int i915_pm_freeze(struct device *kdev)
2152 {
2153         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2154         int ret;
2155
2156         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2157                 ret = i915_drm_suspend(&i915->drm);
2158                 if (ret)
2159                         return ret;
2160         }
2161
2162         ret = i915_gem_freeze(i915);
2163         if (ret)
2164                 return ret;
2165
2166         return 0;
2167 }
2168
2169 static int i915_pm_freeze_late(struct device *kdev)
2170 {
2171         struct drm_i915_private *i915 = kdev_to_i915(kdev);
2172         int ret;
2173
2174         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2175                 ret = i915_drm_suspend_late(&i915->drm, true);
2176                 if (ret)
2177                         return ret;
2178         }
2179
2180         ret = i915_gem_freeze_late(i915);
2181         if (ret)
2182                 return ret;
2183
2184         return 0;
2185 }
2186
2187 /* thaw: called after creating the hibernation image, but before turning off. */
2188 static int i915_pm_thaw_early(struct device *kdev)
2189 {
2190         return i915_pm_resume_early(kdev);
2191 }
2192
2193 static int i915_pm_thaw(struct device *kdev)
2194 {
2195         return i915_pm_resume(kdev);
2196 }
2197
2198 /* restore: called after loading the hibernation image. */
2199 static int i915_pm_restore_early(struct device *kdev)
2200 {
2201         return i915_pm_resume_early(kdev);
2202 }
2203
2204 static int i915_pm_restore(struct device *kdev)
2205 {
2206         return i915_pm_resume(kdev);
2207 }
2208
2209 /*
2210  * Save all Gunit registers that may be lost after a D3 and a subsequent
2211  * S0i[R123] transition. The list of registers needing a save/restore is
2212  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2213  * registers in the following way:
2214  * - Driver: saved/restored by the driver
2215  * - Punit : saved/restored by the Punit firmware
2216  * - No, w/o marking: no need to save/restore, since the register is R/O or
2217  *                    used internally by the HW in a way that doesn't depend
2218  *                    keeping the content across a suspend/resume.
2219  * - Debug : used for debugging
2220  *
2221  * We save/restore all registers marked with 'Driver', with the following
2222  * exceptions:
2223  * - Registers out of use, including also registers marked with 'Debug'.
2224  *   These have no effect on the driver's operation, so we don't save/restore
2225  *   them to reduce the overhead.
2226  * - Registers that are fully setup by an initialization function called from
2227  *   the resume path. For example many clock gating and RPS/RC6 registers.
2228  * - Registers that provide the right functionality with their reset defaults.
2229  *
2230  * TODO: Except for registers that based on the above 3 criteria can be safely
2231  * ignored, we save/restore all others, practically treating the HW context as
2232  * a black-box for the driver. Further investigation is needed to reduce the
2233  * saved/restored registers even further, by following the same 3 criteria.
2234  */
2235 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2236 {
2237         struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2238         int i;
2239
2240         if (!s)
2241                 return;
2242
2243         /* GAM 0x4000-0x4770 */
2244         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2245         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2246         s->arb_mode             = I915_READ(ARB_MODE);
2247         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2248         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2249
2250         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2251                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2252
2253         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2254         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2255
2256         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2257         s->ecochk               = I915_READ(GAM_ECOCHK);
2258         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2259         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2260
2261         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2262
2263         /* MBC 0x9024-0x91D0, 0x8500 */
2264         s->g3dctl               = I915_READ(VLV_G3DCTL);
2265         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2266         s->mbctl                = I915_READ(GEN6_MBCTL);
2267
2268         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2269         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2270         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2271         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2272         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2273         s->rstctl               = I915_READ(GEN6_RSTCTL);
2274         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2275
2276         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2277         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2278         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2279         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2280         s->ecobus               = I915_READ(ECOBUS);
2281         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2282         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2283         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2284         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2285         s->rcedata              = I915_READ(VLV_RCEDATA);
2286         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2287
2288         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2289         s->gt_imr               = I915_READ(GTIMR);
2290         s->gt_ier               = I915_READ(GTIER);
2291         s->pm_imr               = I915_READ(GEN6_PMIMR);
2292         s->pm_ier               = I915_READ(GEN6_PMIER);
2293
2294         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2295                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2296
2297         /* GT SA CZ domain, 0x100000-0x138124 */
2298         s->tilectl              = I915_READ(TILECTL);
2299         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2300         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2301         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2302         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2303
2304         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2305         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2306         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2307         s->pcbr                 = I915_READ(VLV_PCBR);
2308         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2309
2310         /*
2311          * Not saving any of:
2312          * DFT,         0x9800-0x9EC0
2313          * SARB,        0xB000-0xB1FC
2314          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2315          * PCI CFG
2316          */
2317 }
2318
2319 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2320 {
2321         struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2322         u32 val;
2323         int i;
2324
2325         if (!s)
2326                 return;
2327
2328         /* GAM 0x4000-0x4770 */
2329         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2330         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2331         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2332         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2333         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2334
2335         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2336                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2337
2338         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2339         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2340
2341         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2342         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2343         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2344         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2345
2346         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2347
2348         /* MBC 0x9024-0x91D0, 0x8500 */
2349         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2350         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2351         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2352
2353         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2354         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2355         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2356         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2357         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2358         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2359         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2360
2361         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2362         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2363         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2364         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2365         I915_WRITE(ECOBUS,              s->ecobus);
2366         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2367         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2368         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2369         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2370         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2371         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2372
2373         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2374         I915_WRITE(GTIMR,               s->gt_imr);
2375         I915_WRITE(GTIER,               s->gt_ier);
2376         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2377         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2378
2379         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2380                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2381
2382         /* GT SA CZ domain, 0x100000-0x138124 */
2383         I915_WRITE(TILECTL,                     s->tilectl);
2384         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2385         /*
2386          * Preserve the GT allow wake and GFX force clock bit, they are not
2387          * be restored, as they are used to control the s0ix suspend/resume
2388          * sequence by the caller.
2389          */
2390         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2391         val &= VLV_GTLC_ALLOWWAKEREQ;
2392         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2393         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2394
2395         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2396         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2397         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2398         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2399
2400         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2401
2402         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2403         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2404         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2405         I915_WRITE(VLV_PCBR,                    s->pcbr);
2406         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2407 }
2408
2409 static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
2410                                   u32 mask, u32 val)
2411 {
2412         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2413         u32 reg_value;
2414         int ret;
2415
2416         /* The HW does not like us polling for PW_STATUS frequently, so
2417          * use the sleeping loop rather than risk the busy spin within
2418          * intel_wait_for_register().
2419          *
2420          * Transitioning between RC6 states should be at most 2ms (see
2421          * valleyview_enable_rps) so use a 3ms timeout.
2422          */
2423         ret = wait_for(((reg_value =
2424                          intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
2425                        == val, 3);
2426
2427         /* just trace the final value */
2428         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2429
2430         return ret;
2431 }
2432
2433 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2434 {
2435         u32 val;
2436         int err;
2437
2438         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2439         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2440         if (force_on)
2441                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2442         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2443
2444         if (!force_on)
2445                 return 0;
2446
2447         err = intel_wait_for_register(&dev_priv->uncore,
2448                                       VLV_GTLC_SURVIVABILITY_REG,
2449                                       VLV_GFX_CLK_STATUS_BIT,
2450                                       VLV_GFX_CLK_STATUS_BIT,
2451                                       20);
2452         if (err)
2453                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2454                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2455
2456         return err;
2457 }
2458
2459 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2460 {
2461         u32 mask;
2462         u32 val;
2463         int err;
2464
2465         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2466         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2467         if (allow)
2468                 val |= VLV_GTLC_ALLOWWAKEREQ;
2469         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2470         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2471
2472         mask = VLV_GTLC_ALLOWWAKEACK;
2473         val = allow ? mask : 0;
2474
2475         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2476         if (err)
2477                 DRM_ERROR("timeout disabling GT waking\n");
2478
2479         return err;
2480 }
2481
2482 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2483                                   bool wait_for_on)
2484 {
2485         u32 mask;
2486         u32 val;
2487
2488         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2489         val = wait_for_on ? mask : 0;
2490
2491         /*
2492          * RC6 transitioning can be delayed up to 2 msec (see
2493          * valleyview_enable_rps), use 3 msec for safety.
2494          *
2495          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2496          * reset and we are trying to force the machine to sleep.
2497          */
2498         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2499                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2500                                  onoff(wait_for_on));
2501 }
2502
2503 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2504 {
2505         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2506                 return;
2507
2508         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2509         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2510 }
2511
2512 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2513 {
2514         u32 mask;
2515         int err;
2516
2517         /*
2518          * Bspec defines the following GT well on flags as debug only, so
2519          * don't treat them as hard failures.
2520          */
2521         vlv_wait_for_gt_wells(dev_priv, false);
2522
2523         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2524         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2525
2526         vlv_check_no_gt_access(dev_priv);
2527
2528         err = vlv_force_gfx_clock(dev_priv, true);
2529         if (err)
2530                 goto err1;
2531
2532         err = vlv_allow_gt_wake(dev_priv, false);
2533         if (err)
2534                 goto err2;
2535
2536         vlv_save_gunit_s0ix_state(dev_priv);
2537
2538         err = vlv_force_gfx_clock(dev_priv, false);
2539         if (err)
2540                 goto err2;
2541
2542         return 0;
2543
2544 err2:
2545         /* For safety always re-enable waking and disable gfx clock forcing */
2546         vlv_allow_gt_wake(dev_priv, true);
2547 err1:
2548         vlv_force_gfx_clock(dev_priv, false);
2549
2550         return err;
2551 }
2552
2553 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2554                                 bool rpm_resume)
2555 {
2556         int err;
2557         int ret;
2558
2559         /*
2560          * If any of the steps fail just try to continue, that's the best we
2561          * can do at this point. Return the first error code (which will also
2562          * leave RPM permanently disabled).
2563          */
2564         ret = vlv_force_gfx_clock(dev_priv, true);
2565
2566         vlv_restore_gunit_s0ix_state(dev_priv);
2567
2568         err = vlv_allow_gt_wake(dev_priv, true);
2569         if (!ret)
2570                 ret = err;
2571
2572         err = vlv_force_gfx_clock(dev_priv, false);
2573         if (!ret)
2574                 ret = err;
2575
2576         vlv_check_no_gt_access(dev_priv);
2577
2578         if (rpm_resume)
2579                 intel_init_clock_gating(dev_priv);
2580
2581         return ret;
2582 }
2583
2584 static int intel_runtime_suspend(struct device *kdev)
2585 {
2586         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2587         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2588         int ret = 0;
2589
2590         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2591                 return -ENODEV;
2592
2593         DRM_DEBUG_KMS("Suspending device\n");
2594
2595         disable_rpm_wakeref_asserts(rpm);
2596
2597         /*
2598          * We are safe here against re-faults, since the fault handler takes
2599          * an RPM reference.
2600          */
2601         i915_gem_runtime_suspend(dev_priv);
2602
2603         intel_gt_runtime_suspend(&dev_priv->gt);
2604
2605         intel_runtime_pm_disable_interrupts(dev_priv);
2606
2607         intel_uncore_suspend(&dev_priv->uncore);
2608
2609         intel_display_power_suspend(dev_priv);
2610
2611         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2612                 ret = vlv_suspend_complete(dev_priv);
2613
2614         if (ret) {
2615                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2616                 intel_uncore_runtime_resume(&dev_priv->uncore);
2617
2618                 intel_runtime_pm_enable_interrupts(dev_priv);
2619
2620                 intel_gt_runtime_resume(&dev_priv->gt);
2621
2622                 i915_gem_restore_fences(dev_priv);
2623
2624                 enable_rpm_wakeref_asserts(rpm);
2625
2626                 return ret;
2627         }
2628
2629         enable_rpm_wakeref_asserts(rpm);
2630         intel_runtime_pm_driver_release(rpm);
2631
2632         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2633                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2634
2635         rpm->suspended = true;
2636
2637         /*
2638          * FIXME: We really should find a document that references the arguments
2639          * used below!
2640          */
2641         if (IS_BROADWELL(dev_priv)) {
2642                 /*
2643                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2644                  * being detected, and the call we do at intel_runtime_resume()
2645                  * won't be able to restore them. Since PCI_D3hot matches the
2646                  * actual specification and appears to be working, use it.
2647                  */
2648                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2649         } else {
2650                 /*
2651                  * current versions of firmware which depend on this opregion
2652                  * notification have repurposed the D1 definition to mean
2653                  * "runtime suspended" vs. what you would normally expect (D3)
2654                  * to distinguish it from notifications that might be sent via
2655                  * the suspend path.
2656                  */
2657                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2658         }
2659
2660         assert_forcewakes_inactive(&dev_priv->uncore);
2661
2662         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2663                 intel_hpd_poll_init(dev_priv);
2664
2665         DRM_DEBUG_KMS("Device suspended\n");
2666         return 0;
2667 }
2668
2669 static int intel_runtime_resume(struct device *kdev)
2670 {
2671         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2672         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2673         int ret = 0;
2674
2675         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2676                 return -ENODEV;
2677
2678         DRM_DEBUG_KMS("Resuming device\n");
2679
2680         WARN_ON_ONCE(atomic_read(&rpm->wakeref_count));
2681         disable_rpm_wakeref_asserts(rpm);
2682
2683         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2684         rpm->suspended = false;
2685         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2686                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2687
2688         intel_display_power_resume(dev_priv);
2689
2690         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2691                 ret = vlv_resume_prepare(dev_priv, true);
2692
2693         intel_uncore_runtime_resume(&dev_priv->uncore);
2694
2695         intel_runtime_pm_enable_interrupts(dev_priv);
2696
2697         /*
2698          * No point of rolling back things in case of an error, as the best
2699          * we can do is to hope that things will still work (and disable RPM).
2700          */
2701         intel_gt_runtime_resume(&dev_priv->gt);
2702         i915_gem_restore_fences(dev_priv);
2703
2704         /*
2705          * On VLV/CHV display interrupts are part of the display
2706          * power well, so hpd is reinitialized from there. For
2707          * everyone else do it here.
2708          */
2709         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2710                 intel_hpd_init(dev_priv);
2711
2712         intel_enable_ipc(dev_priv);
2713
2714         enable_rpm_wakeref_asserts(rpm);
2715
2716         if (ret)
2717                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2718         else
2719                 DRM_DEBUG_KMS("Device resumed\n");
2720
2721         return ret;
2722 }
2723
2724 const struct dev_pm_ops i915_pm_ops = {
2725         /*
2726          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2727          * PMSG_RESUME]
2728          */
2729         .prepare = i915_pm_prepare,
2730         .suspend = i915_pm_suspend,
2731         .suspend_late = i915_pm_suspend_late,
2732         .resume_early = i915_pm_resume_early,
2733         .resume = i915_pm_resume,
2734
2735         /*
2736          * S4 event handlers
2737          * @freeze, @freeze_late    : called (1) before creating the
2738          *                            hibernation image [PMSG_FREEZE] and
2739          *                            (2) after rebooting, before restoring
2740          *                            the image [PMSG_QUIESCE]
2741          * @thaw, @thaw_early       : called (1) after creating the hibernation
2742          *                            image, before writing it [PMSG_THAW]
2743          *                            and (2) after failing to create or
2744          *                            restore the image [PMSG_RECOVER]
2745          * @poweroff, @poweroff_late: called after writing the hibernation
2746          *                            image, before rebooting [PMSG_HIBERNATE]
2747          * @restore, @restore_early : called after rebooting and restoring the
2748          *                            hibernation image [PMSG_RESTORE]
2749          */
2750         .freeze = i915_pm_freeze,
2751         .freeze_late = i915_pm_freeze_late,
2752         .thaw_early = i915_pm_thaw_early,
2753         .thaw = i915_pm_thaw,
2754         .poweroff = i915_pm_suspend,
2755         .poweroff_late = i915_pm_poweroff_late,
2756         .restore_early = i915_pm_restore_early,
2757         .restore = i915_pm_restore,
2758
2759         /* S0ix (via runtime suspend) event handlers */
2760         .runtime_suspend = intel_runtime_suspend,
2761         .runtime_resume = intel_runtime_resume,
2762 };
2763
2764 static const struct vm_operations_struct i915_gem_vm_ops = {
2765         .fault = i915_gem_fault,
2766         .open = drm_gem_vm_open,
2767         .close = drm_gem_vm_close,
2768 };
2769
2770 static const struct file_operations i915_driver_fops = {
2771         .owner = THIS_MODULE,
2772         .open = drm_open,
2773         .release = drm_release,
2774         .unlocked_ioctl = drm_ioctl,
2775         .mmap = drm_gem_mmap,
2776         .poll = drm_poll,
2777         .read = drm_read,
2778         .compat_ioctl = i915_compat_ioctl,
2779         .llseek = noop_llseek,
2780 };
2781
2782 static int
2783 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2784                           struct drm_file *file)
2785 {
2786         return -ENODEV;
2787 }
2788
2789 static const struct drm_ioctl_desc i915_ioctls[] = {
2790         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2791         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2792         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2793         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2794         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2795         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2796         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
2797         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2798         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2799         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2800         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2801         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2802         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2803         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2804         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2805         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2806         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2807         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2808         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2809         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
2810         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2811         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2812         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
2813         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2814         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2815         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
2816         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2817         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2818         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2819         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2820         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2821         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2822         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2823         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2824         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2825         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2826         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2827         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2828         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2829         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2830         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2831         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2832         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2833         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2834         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
2835         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2836         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2837         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2838         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2839         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2840         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2841         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2842         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2843         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
2844         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
2845         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
2846         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
2847         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
2848 };
2849
2850 static struct drm_driver driver = {
2851         /* Don't use MTRRs here; the Xserver or userspace app should
2852          * deal with them for Intel hardware.
2853          */
2854         .driver_features =
2855             DRIVER_GEM |
2856             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2857         .release = i915_driver_release,
2858         .open = i915_driver_open,
2859         .lastclose = i915_driver_lastclose,
2860         .postclose = i915_driver_postclose,
2861
2862         .gem_close_object = i915_gem_close_object,
2863         .gem_free_object_unlocked = i915_gem_free_object,
2864         .gem_vm_ops = &i915_gem_vm_ops,
2865
2866         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2867         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2868         .gem_prime_export = i915_gem_prime_export,
2869         .gem_prime_import = i915_gem_prime_import,
2870
2871         .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
2872         .get_scanout_position = i915_get_crtc_scanoutpos,
2873
2874         .dumb_create = i915_gem_dumb_create,
2875         .dumb_map_offset = i915_gem_mmap_gtt,
2876         .ioctls = i915_ioctls,
2877         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2878         .fops = &i915_driver_fops,
2879         .name = DRIVER_NAME,
2880         .desc = DRIVER_DESC,
2881         .date = DRIVER_DATE,
2882         .major = DRIVER_MAJOR,
2883         .minor = DRIVER_MINOR,
2884         .patchlevel = DRIVER_PATCHLEVEL,
2885 };
2886
2887 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2888 #include "selftests/mock_drm.c"
2889 #endif