drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41 #include <acpi/video.h>
  42
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_irq.h>
  46 #include <drm/drm_managed.h>
  47 #include <drm/drm_probe_helper.h>
  48
  49 #include "display/intel_acpi.h"
  50 #include "display/intel_audio.h"
  51 #include "display/intel_bw.h"
  52 #include "display/intel_cdclk.h"
  53 #include "display/intel_csr.h"
  54 #include "display/intel_display_debugfs.h"
  55 #include "display/intel_display_types.h"
  56 #include "display/intel_dp.h"
  57 #include "display/intel_fbdev.h"
  58 #include "display/intel_hotplug.h"
  59 #include "display/intel_overlay.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_sprite.h"
  62 #include "display/intel_vga.h"
  63
  64 #include "gem/i915_gem_context.h"
  65 #include "gem/i915_gem_ioctls.h"
  66 #include "gem/i915_gem_mman.h"
  67 #include "gt/intel_gt.h"
  68 #include "gt/intel_gt_pm.h"
  69 #include "gt/intel_rc6.h"
  70
  71 #include "i915_debugfs.h"
  72 #include "i915_drv.h"
  73 #include "i915_ioc32.h"
  74 #include "i915_irq.h"
  75 #include "i915_memcpy.h"
  76 #include "i915_perf.h"
  77 #include "i915_query.h"
  78 #include "i915_suspend.h"
  79 #include "i915_switcheroo.h"
  80 #include "i915_sysfs.h"
  81 #include "i915_trace.h"
  82 #include "i915_vgpu.h"
  83 #include "intel_dram.h"
  84 #include "intel_gvt.h"
  85 #include "intel_memory_region.h"
  86 #include "intel_pm.h"
  87 #include "intel_sideband.h"
  88 #include "vlv_suspend.h"
  89
  90 static const struct drm_driver driver;
  91
  92 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  93 {
  94         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
  95
  96         dev_priv->bridge_dev =
  97                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
  98         if (!dev_priv->bridge_dev) {
  99                 drm_err(&dev_priv->drm, "bridge device not found\n");
 100                 return -1;
 101         }
 102         return 0;
 103 }
 104
 105 /* Allocate space for the MCH regs if needed, return nonzero on error */
 106 static int
 107 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 108 {
 109         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 110         u32 temp_lo, temp_hi = 0;
 111         u64 mchbar_addr;
 112         int ret;
 113
 114         if (INTEL_GEN(dev_priv) >= 4)
 115                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 116         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 117         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 118
 119         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 120 #ifdef CONFIG_PNP
 121         if (mchbar_addr &&
 122             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 123                 return 0;
 124 #endif
 125
 126         /* Get some space for it */
 127         dev_priv->mch_res.name = "i915 MCHBAR";
 128         dev_priv->mch_res.flags = IORESOURCE_MEM;
 129         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 130                                      &dev_priv->mch_res,
 131                                      MCHBAR_SIZE, MCHBAR_SIZE,
 132                                      PCIBIOS_MIN_MEM,
 133                                      0, pcibios_align_resource,
 134                                      dev_priv->bridge_dev);
 135         if (ret) {
 136                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 137                 dev_priv->mch_res.start = 0;
 138                 return ret;
 139         }
 140
 141         if (INTEL_GEN(dev_priv) >= 4)
 142                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 143                                        upper_32_bits(dev_priv->mch_res.start));
 144
 145         pci_write_config_dword(dev_priv->bridge_dev, reg,
 146                                lower_32_bits(dev_priv->mch_res.start));
 147         return 0;
 148 }
 149
 150 /* Setup MCHBAR if possible, return true if we should disable it again */
 151 static void
 152 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 153 {
 154         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 155         u32 temp;
 156         bool enabled;
 157
 158         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 159                 return;
 160
 161         dev_priv->mchbar_need_disable = false;
 162
 163         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 164                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 165                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 166         } else {
 167                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 168                 enabled = temp & 1;
 169         }
 170
 171         /* If it's already enabled, don't have to do anything */
 172         if (enabled)
 173                 return;
 174
 175         if (intel_alloc_mchbar_resource(dev_priv))
 176                 return;
 177
 178         dev_priv->mchbar_need_disable = true;
 179
 180         /* Space is allocated or reserved, so enable it. */
 181         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 182                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 183                                        temp | DEVEN_MCHBAR_EN);
 184         } else {
 185                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 186                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 187         }
 188 }
 189
 190 static void
 191 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 192 {
 193         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 194
 195         if (dev_priv->mchbar_need_disable) {
 196                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 197                         u32 deven_val;
 198
 199                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 200                                               &deven_val);
 201                         deven_val &= ~DEVEN_MCHBAR_EN;
 202                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 203                                                deven_val);
 204                 } else {
 205                         u32 mchbar_val;
 206
 207                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 208                                               &mchbar_val);
 209                         mchbar_val &= ~1;
 210                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 211                                                mchbar_val);
 212                 }
 213         }
 214
 215         if (dev_priv->mch_res.start)
 216                 release_resource(&dev_priv->mch_res);
 217 }
 218
 219 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 220 {
 221         /*
 222          * The i915 workqueue is primarily used for batched retirement of
 223          * requests (and thus managing bo) once the task has been completed
 224          * by the GPU. i915_retire_requests() is called directly when we
 225          * need high-priority retirement, such as waiting for an explicit
 226          * bo.
 227          *
 228          * It is also used for periodic low-priority events, such as
 229          * idle-timers and recording error state.
 230          *
 231          * All tasks on the workqueue are expected to acquire the dev mutex
 232          * so there is no point in running more than one instance of the
 233          * workqueue at any time.  Use an ordered one.
 234          */
 235         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 236         if (dev_priv->wq == NULL)
 237                 goto out_err;
 238
 239         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 240         if (dev_priv->hotplug.dp_wq == NULL)
 241                 goto out_free_wq;
 242
 243         return 0;
 244
 245 out_free_wq:
 246         destroy_workqueue(dev_priv->wq);
 247 out_err:
 248         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 249
 250         return -ENOMEM;
 251 }
 252
 253 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 254 {
 255         destroy_workqueue(dev_priv->hotplug.dp_wq);
 256         destroy_workqueue(dev_priv->wq);
 257 }
 258
 259 /*
 260  * We don't keep the workarounds for pre-production hardware, so we expect our
 261  * driver to fail on these machines in one way or another. A little warning on
 262  * dmesg may help both the user and the bug triagers.
 263  *
 264  * Our policy for removing pre-production workarounds is to keep the
 265  * current gen workarounds as a guide to the bring-up of the next gen
 266  * (workarounds have a habit of persisting!). Anything older than that
 267  * should be removed along with the complications they introduce.
 268  */
 269 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 270 {
 271         bool pre = false;
 272
 273         pre |= IS_HSW_EARLY_SDV(dev_priv);
 274         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 275         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 276         pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0);
 277         pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
 278
 279         if (pre) {
 280                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 281                           "It may not be fully functional.\n");
 282                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 283         }
 284 }
 285
 286 static void sanitize_gpu(struct drm_i915_private *i915)
 287 {
 288         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 289                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 290 }
 291
 292 /**
 293  * i915_driver_early_probe - setup state not requiring device access
 294  * @dev_priv: device private
 295  *
 296  * Initialize everything that is a "SW-only" state, that is state not
 297  * requiring accessing the device or exposing the driver via kernel internal
 298  * or userspace interfaces. Example steps belonging here: lock initialization,
 299  * system memory allocation, setting up device specific attributes and
 300  * function hooks not requiring accessing the device.
 301  */
 302 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 303 {
 304         int ret = 0;
 305
 306         if (i915_inject_probe_failure(dev_priv))
 307                 return -ENODEV;
 308
 309         intel_device_info_subplatform_init(dev_priv);
 310
 311         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 312         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 313
 314         spin_lock_init(&dev_priv->irq_lock);
 315         spin_lock_init(&dev_priv->gpu_error.lock);
 316         mutex_init(&dev_priv->backlight_lock);
 317
 318         mutex_init(&dev_priv->sb_lock);
 319         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 320
 321         mutex_init(&dev_priv->av_mutex);
 322         mutex_init(&dev_priv->wm.wm_mutex);
 323         mutex_init(&dev_priv->pps_mutex);
 324         mutex_init(&dev_priv->hdcp_comp_mutex);
 325
 326         i915_memcpy_init_early(dev_priv);
 327         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 328
 329         ret = i915_workqueues_init(dev_priv);
 330         if (ret < 0)
 331                 return ret;
 332
 333         ret = vlv_suspend_init(dev_priv);
 334         if (ret < 0)
 335                 goto err_workqueues;
 336
 337         intel_wopcm_init_early(&dev_priv->wopcm);
 338
 339         intel_gt_init_early(&dev_priv->gt, dev_priv);
 340
 341         i915_gem_init_early(dev_priv);
 342
 343         /* This must be called before any calls to HAS_PCH_* */
 344         intel_detect_pch(dev_priv);
 345
 346         intel_pm_setup(dev_priv);
 347         ret = intel_power_domains_init(dev_priv);
 348         if (ret < 0)
 349                 goto err_gem;
 350         intel_irq_init(dev_priv);
 351         intel_init_display_hooks(dev_priv);
 352         intel_init_clock_gating_hooks(dev_priv);
 353         intel_init_audio_hooks(dev_priv);
 354
 355         intel_detect_preproduction_hw(dev_priv);
 356
 357         return 0;
 358
 359 err_gem:
 360         i915_gem_cleanup_early(dev_priv);
 361         intel_gt_driver_late_release(&dev_priv->gt);
 362         vlv_suspend_cleanup(dev_priv);
 363 err_workqueues:
 364         i915_workqueues_cleanup(dev_priv);
 365         return ret;
 366 }
 367
 368 /**
 369  * i915_driver_late_release - cleanup the setup done in
 370  *                             i915_driver_early_probe()
 371  * @dev_priv: device private
 372  */
 373 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 374 {
 375         intel_irq_fini(dev_priv);
 376         intel_power_domains_cleanup(dev_priv);
 377         i915_gem_cleanup_early(dev_priv);
 378         intel_gt_driver_late_release(&dev_priv->gt);
 379         vlv_suspend_cleanup(dev_priv);
 380         i915_workqueues_cleanup(dev_priv);
 381
 382         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 383         mutex_destroy(&dev_priv->sb_lock);
 384
 385         i915_params_free(&dev_priv->params);
 386 }
 387
 388 /**
 389  * i915_driver_mmio_probe - setup device MMIO
 390  * @dev_priv: device private
 391  *
 392  * Setup minimal device state necessary for MMIO accesses later in the
 393  * initialization sequence. The setup here should avoid any other device-wide
 394  * side effects or exposing the driver via kernel internal or user space
 395  * interfaces.
 396  */
 397 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 398 {
 399         int ret;
 400
 401         if (i915_inject_probe_failure(dev_priv))
 402                 return -ENODEV;
 403
 404         if (i915_get_bridge_dev(dev_priv))
 405                 return -EIO;
 406
 407         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 408         if (ret < 0)
 409                 goto err_bridge;
 410
 411         /* Try to make sure MCHBAR is enabled before poking at it */
 412         intel_setup_mchbar(dev_priv);
 413
 414         ret = intel_gt_init_mmio(&dev_priv->gt);
 415         if (ret)
 416                 goto err_uncore;
 417
 418         /* As early as possible, scrub existing GPU state before clobbering */
 419         sanitize_gpu(dev_priv);
 420
 421         return 0;
 422
 423 err_uncore:
 424         intel_teardown_mchbar(dev_priv);
 425         intel_uncore_fini_mmio(&dev_priv->uncore);
 426 err_bridge:
 427         pci_dev_put(dev_priv->bridge_dev);
 428
 429         return ret;
 430 }
 431
 432 /**
 433  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 434  * @dev_priv: device private
 435  */
 436 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 437 {
 438         intel_teardown_mchbar(dev_priv);
 439         intel_uncore_fini_mmio(&dev_priv->uncore);
 440         pci_dev_put(dev_priv->bridge_dev);
 441 }
 442
 443 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 444 {
 445         intel_gvt_sanitize_options(dev_priv);
 446 }
 447
 448 /**
 449  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 450  * platform
 451  * @i915: valid i915 instance
 452  *
 453  * Set the dma max segment size, device and coherent masks.  The dma mask set
 454  * needs to occur before i915_ggtt_probe_hw.
 455  *
 456  * A couple of platforms have special needs.  Address them as well.
 457  *
 458  */
 459 static int i915_set_dma_info(struct drm_i915_private *i915)
 460 {
 461         struct pci_dev *pdev = i915->drm.pdev;
 462         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 463         int ret;
 464
 465         GEM_BUG_ON(!mask_size);
 466
 467         /*
 468          * We don't have a max segment size, so set it to the max so sg's
 469          * debugging layer doesn't complain
 470          */
 471         dma_set_max_seg_size(&pdev->dev, UINT_MAX);
 472
 473         ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
 474         if (ret)
 475                 goto mask_err;
 476
 477         /* overlay on gen2 is broken and can't address above 1G */
 478         if (IS_GEN(i915, 2))
 479                 mask_size = 30;
 480
 481         /*
 482          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 483          * using 32bit addressing, overwriting memory if HWS is located
 484          * above 4GB.
 485          *
 486          * The documentation also mentions an issue with undefined
 487          * behaviour if any general state is accessed within a page above 4GB,
 488          * which also needs to be handled carefully.
 489          */
 490         if (IS_I965G(i915) || IS_I965GM(i915))
 491                 mask_size = 32;
 492
 493         ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
 494         if (ret)
 495                 goto mask_err;
 496
 497         return 0;
 498
 499 mask_err:
 500         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 501         return ret;
 502 }
 503
 504 /**
 505  * i915_driver_hw_probe - setup state requiring device access
 506  * @dev_priv: device private
 507  *
 508  * Setup state that requires accessing the device, but doesn't require
 509  * exposing the driver via kernel internal or userspace interfaces.
 510  */
 511 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 512 {
 513         struct pci_dev *pdev = dev_priv->drm.pdev;
 514         int ret;
 515
 516         if (i915_inject_probe_failure(dev_priv))
 517                 return -ENODEV;
 518
 519         intel_device_info_runtime_init(dev_priv);
 520
 521         if (HAS_PPGTT(dev_priv)) {
 522                 if (intel_vgpu_active(dev_priv) &&
 523                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 524                         i915_report_error(dev_priv,
 525                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 526                         return -ENXIO;
 527                 }
 528         }
 529
 530         if (HAS_EXECLISTS(dev_priv)) {
 531                 /*
 532                  * Older GVT emulation depends upon intercepting CSB mmio,
 533                  * which we no longer use, preferring to use the HWSP cache
 534                  * instead.
 535                  */
 536                 if (intel_vgpu_active(dev_priv) &&
 537                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 538                         i915_report_error(dev_priv,
 539                                           "old vGPU host found, support for HWSP emulation required\n");
 540                         return -ENXIO;
 541                 }
 542         }
 543
 544         intel_sanitize_options(dev_priv);
 545
 546         /* needs to be done before ggtt probe */
 547         intel_dram_edram_detect(dev_priv);
 548
 549         ret = i915_set_dma_info(dev_priv);
 550         if (ret)
 551                 return ret;
 552
 553         i915_perf_init(dev_priv);
 554
 555         ret = i915_ggtt_probe_hw(dev_priv);
 556         if (ret)
 557                 goto err_perf;
 558
 559         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
 560         if (ret)
 561                 goto err_ggtt;
 562
 563         ret = i915_ggtt_init_hw(dev_priv);
 564         if (ret)
 565                 goto err_ggtt;
 566
 567         ret = intel_memory_regions_hw_probe(dev_priv);
 568         if (ret)
 569                 goto err_ggtt;
 570
 571         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 572
 573         ret = i915_ggtt_enable_hw(dev_priv);
 574         if (ret) {
 575                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 576                 goto err_mem_regions;
 577         }
 578
 579         pci_set_master(pdev);
 580
 581         cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 582
 583         intel_gt_init_workarounds(dev_priv);
 584
 585         /* On the 945G/GM, the chipset reports the MSI capability on the
 586          * integrated graphics even though the support isn't actually there
 587          * according to the published specs.  It doesn't appear to function
 588          * correctly in testing on 945G.
 589          * This may be a side effect of MSI having been made available for PEG
 590          * and the registers being closely associated.
 591          *
 592          * According to chipset errata, on the 965GM, MSI interrupts may
 593          * be lost or delayed, and was defeatured. MSI interrupts seem to
 594          * get lost on g4x as well, and interrupt delivery seems to stay
 595          * properly dead afterwards. So we'll just disable them for all
 596          * pre-gen5 chipsets.
 597          *
 598          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 599          * interrupts even when in MSI mode. This results in spurious
 600          * interrupt warnings if the legacy irq no. is shared with another
 601          * device. The kernel then disables that interrupt source and so
 602          * prevents the other device from working properly.
 603          */
 604         if (INTEL_GEN(dev_priv) >= 5) {
 605                 if (pci_enable_msi(pdev) < 0)
 606                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 607         }
 608
 609         ret = intel_gvt_init(dev_priv);
 610         if (ret)
 611                 goto err_msi;
 612
 613         intel_opregion_setup(dev_priv);
 614         /*
 615          * Fill the dram structure to get the system raw bandwidth and
 616          * dram info. This will be used for memory latency calculation.
 617          */
 618         intel_dram_detect(dev_priv);
 619
 620         intel_pcode_init(dev_priv);
 621
 622         intel_bw_init_hw(dev_priv);
 623
 624         return 0;
 625
 626 err_msi:
 627         if (pdev->msi_enabled)
 628                 pci_disable_msi(pdev);
 629         cpu_latency_qos_remove_request(&dev_priv->pm_qos);
 630 err_mem_regions:
 631         intel_memory_regions_driver_release(dev_priv);
 632 err_ggtt:
 633         i915_ggtt_driver_release(dev_priv);
 634 err_perf:
 635         i915_perf_fini(dev_priv);
 636         return ret;
 637 }
 638
 639 /**
 640  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 641  * @dev_priv: device private
 642  */
 643 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 644 {
 645         struct pci_dev *pdev = dev_priv->drm.pdev;
 646
 647         i915_perf_fini(dev_priv);
 648
 649         if (pdev->msi_enabled)
 650                 pci_disable_msi(pdev);
 651
 652         cpu_latency_qos_remove_request(&dev_priv->pm_qos);
 653 }
 654
 655 /**
 656  * i915_driver_register - register the driver with the rest of the system
 657  * @dev_priv: device private
 658  *
 659  * Perform any steps necessary to make the driver available via kernel
 660  * internal or userspace interfaces.
 661  */
 662 static void i915_driver_register(struct drm_i915_private *dev_priv)
 663 {
 664         struct drm_device *dev = &dev_priv->drm;
 665
 666         i915_gem_driver_register(dev_priv);
 667         i915_pmu_register(dev_priv);
 668
 669         intel_vgpu_register(dev_priv);
 670
 671         /* Reveal our presence to userspace */
 672         if (drm_dev_register(dev, 0) == 0) {
 673                 i915_debugfs_register(dev_priv);
 674                 if (HAS_DISPLAY(dev_priv))
 675                         intel_display_debugfs_register(dev_priv);
 676                 i915_setup_sysfs(dev_priv);
 677
 678                 /* Depends on sysfs having been initialized */
 679                 i915_perf_register(dev_priv);
 680         } else
 681                 drm_err(&dev_priv->drm,
 682                         "Failed to register driver for userspace access!\n");
 683
 684         if (HAS_DISPLAY(dev_priv)) {
 685                 /* Must be done after probing outputs */
 686                 intel_opregion_register(dev_priv);
 687                 acpi_video_register();
 688         }
 689
 690         intel_gt_driver_register(&dev_priv->gt);
 691
 692         intel_audio_init(dev_priv);
 693
 694         /*
 695          * Some ports require correctly set-up hpd registers for detection to
 696          * work properly (leading to ghost connected connector status), e.g. VGA
 697          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 698          * irqs are fully enabled. We do it last so that the async config
 699          * cannot run before the connectors are registered.
 700          */
 701         intel_fbdev_initial_config_async(dev);
 702
 703         /*
 704          * We need to coordinate the hotplugs with the asynchronous fbdev
 705          * configuration, for which we use the fbdev->async_cookie.
 706          */
 707         if (HAS_DISPLAY(dev_priv))
 708                 drm_kms_helper_poll_init(dev);
 709
 710         intel_power_domains_enable(dev_priv);
 711         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 712
 713         intel_register_dsm_handler();
 714
 715         if (i915_switcheroo_register(dev_priv))
 716                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 717 }
 718
 719 /**
 720  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 721  * @dev_priv: device private
 722  */
 723 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 724 {
 725         i915_switcheroo_unregister(dev_priv);
 726
 727         intel_unregister_dsm_handler();
 728
 729         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 730         intel_power_domains_disable(dev_priv);
 731
 732         intel_fbdev_unregister(dev_priv);
 733         intel_audio_deinit(dev_priv);
 734
 735         /*
 736          * After flushing the fbdev (incl. a late async config which will
 737          * have delayed queuing of a hotplug event), then flush the hotplug
 738          * events.
 739          */
 740         drm_kms_helper_poll_fini(&dev_priv->drm);
 741
 742         intel_gt_driver_unregister(&dev_priv->gt);
 743         acpi_video_unregister();
 744         intel_opregion_unregister(dev_priv);
 745
 746         i915_perf_unregister(dev_priv);
 747         i915_pmu_unregister(dev_priv);
 748
 749         i915_teardown_sysfs(dev_priv);
 750         drm_dev_unplug(&dev_priv->drm);
 751
 752         i915_gem_driver_unregister(dev_priv);
 753 }
 754
 755 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 756 {
 757         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 758                 struct drm_printer p = drm_debug_printer("i915 device info:");
 759
 760                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 761                            INTEL_DEVID(dev_priv),
 762                            INTEL_REVID(dev_priv),
 763                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 764                            intel_subplatform(RUNTIME_INFO(dev_priv),
 765                                              INTEL_INFO(dev_priv)->platform),
 766                            INTEL_GEN(dev_priv));
 767
 768                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 769                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 770                 intel_gt_info_print(&dev_priv->gt.info, &p);
 771         }
 772
 773         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 774                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 775         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 776                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 777         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 778                 drm_info(&dev_priv->drm,
 779                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 780 }
 781
 782 static struct drm_i915_private *
 783 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 784 {
 785         const struct intel_device_info *match_info =
 786                 (struct intel_device_info *)ent->driver_data;
 787         struct intel_device_info *device_info;
 788         struct drm_i915_private *i915;
 789
 790         i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
 791                                   struct drm_i915_private, drm);
 792         if (IS_ERR(i915))
 793                 return i915;
 794
 795         i915->drm.pdev = pdev;
 796         pci_set_drvdata(pdev, i915);
 797
 798         /* Device parameters start as a copy of module parameters. */
 799         i915_params_copy(&i915->params, &i915_modparams);
 800
 801         /* Setup the write-once "constant" device info */
 802         device_info = mkwrite_device_info(i915);
 803         memcpy(device_info, match_info, sizeof(*device_info));
 804         RUNTIME_INFO(i915)->device_id = pdev->device;
 805
 806         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
 807
 808         return i915;
 809 }
 810
 811 /**
 812  * i915_driver_probe - setup chip and create an initial config
 813  * @pdev: PCI device
 814  * @ent: matching PCI ID entry
 815  *
 816  * The driver probe routine has to do several things:
 817  *   - drive output discovery via intel_modeset_init()
 818  *   - initialize the memory manager
 819  *   - allocate initial config memory
 820  *   - setup the DRM framebuffer with the allocated memory
 821  */
 822 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 823 {
 824         const struct intel_device_info *match_info =
 825                 (struct intel_device_info *)ent->driver_data;
 826         struct drm_i915_private *i915;
 827         int ret;
 828
 829         i915 = i915_driver_create(pdev, ent);
 830         if (IS_ERR(i915))
 831                 return PTR_ERR(i915);
 832
 833         /* Disable nuclear pageflip by default on pre-ILK */
 834         if (!i915->params.nuclear_pageflip && match_info->gen < 5)
 835                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 836
 837         /*
 838          * Check if we support fake LMEM -- for now we only unleash this for
 839          * the live selftests(test-and-exit).
 840          */
 841 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 842         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 843                 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
 844                     i915->params.fake_lmem_start) {
 845                         mkwrite_device_info(i915)->memory_regions =
 846                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
 847                         GEM_BUG_ON(!HAS_LMEM(i915));
 848                 }
 849         }
 850 #endif
 851
 852         ret = pci_enable_device(pdev);
 853         if (ret)
 854                 goto out_fini;
 855
 856         ret = i915_driver_early_probe(i915);
 857         if (ret < 0)
 858                 goto out_pci_disable;
 859
 860         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 861
 862         intel_vgpu_detect(i915);
 863
 864         ret = i915_driver_mmio_probe(i915);
 865         if (ret < 0)
 866                 goto out_runtime_pm_put;
 867
 868         ret = i915_driver_hw_probe(i915);
 869         if (ret < 0)
 870                 goto out_cleanup_mmio;
 871
 872         ret = intel_modeset_init_noirq(i915);
 873         if (ret < 0)
 874                 goto out_cleanup_hw;
 875
 876         ret = intel_irq_install(i915);
 877         if (ret)
 878                 goto out_cleanup_modeset;
 879
 880         ret = intel_modeset_init_nogem(i915);
 881         if (ret)
 882                 goto out_cleanup_irq;
 883
 884         ret = i915_gem_init(i915);
 885         if (ret)
 886                 goto out_cleanup_modeset2;
 887
 888         ret = intel_modeset_init(i915);
 889         if (ret)
 890                 goto out_cleanup_gem;
 891
 892         i915_driver_register(i915);
 893
 894         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 895
 896         i915_welcome_messages(i915);
 897
 898         i915->do_release = true;
 899
 900         return 0;
 901
 902 out_cleanup_gem:
 903         i915_gem_suspend(i915);
 904         i915_gem_driver_remove(i915);
 905         i915_gem_driver_release(i915);
 906 out_cleanup_modeset2:
 907         /* FIXME clean up the error path */
 908         intel_modeset_driver_remove(i915);
 909         intel_irq_uninstall(i915);
 910         intel_modeset_driver_remove_noirq(i915);
 911         goto out_cleanup_modeset;
 912 out_cleanup_irq:
 913         intel_irq_uninstall(i915);
 914 out_cleanup_modeset:
 915         intel_modeset_driver_remove_nogem(i915);
 916 out_cleanup_hw:
 917         i915_driver_hw_remove(i915);
 918         intel_memory_regions_driver_release(i915);
 919         i915_ggtt_driver_release(i915);
 920 out_cleanup_mmio:
 921         i915_driver_mmio_release(i915);
 922 out_runtime_pm_put:
 923         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 924         i915_driver_late_release(i915);
 925 out_pci_disable:
 926         pci_disable_device(pdev);
 927 out_fini:
 928         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 929         return ret;
 930 }
 931
 932 void i915_driver_remove(struct drm_i915_private *i915)
 933 {
 934         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 935
 936         i915_driver_unregister(i915);
 937
 938         /* Flush any external code that still may be under the RCU lock */
 939         synchronize_rcu();
 940
 941         i915_gem_suspend(i915);
 942
 943         drm_atomic_helper_shutdown(&i915->drm);
 944
 945         intel_gvt_driver_remove(i915);
 946
 947         intel_modeset_driver_remove(i915);
 948
 949         intel_irq_uninstall(i915);
 950
 951         intel_modeset_driver_remove_noirq(i915);
 952
 953         i915_reset_error_state(i915);
 954         i915_gem_driver_remove(i915);
 955
 956         intel_modeset_driver_remove_nogem(i915);
 957
 958         i915_driver_hw_remove(i915);
 959
 960         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 961 }
 962
 963 static void i915_driver_release(struct drm_device *dev)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(dev);
 966         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 967
 968         if (!dev_priv->do_release)
 969                 return;
 970
 971         disable_rpm_wakeref_asserts(rpm);
 972
 973         i915_gem_driver_release(dev_priv);
 974
 975         intel_memory_regions_driver_release(dev_priv);
 976         i915_ggtt_driver_release(dev_priv);
 977         i915_gem_drain_freed_objects(dev_priv);
 978
 979         i915_driver_mmio_release(dev_priv);
 980
 981         enable_rpm_wakeref_asserts(rpm);
 982         intel_runtime_pm_driver_release(rpm);
 983
 984         i915_driver_late_release(dev_priv);
 985 }
 986
 987 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 988 {
 989         struct drm_i915_private *i915 = to_i915(dev);
 990         int ret;
 991
 992         ret = i915_gem_open(i915, file);
 993         if (ret)
 994                 return ret;
 995
 996         return 0;
 997 }
 998
 999 /**
1000  * i915_driver_lastclose - clean up after all DRM clients have exited
1001  * @dev: DRM device
1002  *
1003  * Take care of cleaning up after all DRM clients have exited.  In the
1004  * mode setting case, we want to restore the kernel's initial mode (just
1005  * in case the last client left us in a bad state).
1006  *
1007  * Additionally, in the non-mode setting case, we'll tear down the GTT
1008  * and DMA structures, since the kernel won't be using them, and clea
1009  * up any GEM state.
1010  */
1011 static void i915_driver_lastclose(struct drm_device *dev)
1012 {
1013         intel_fbdev_restore_mode(dev);
1014         vga_switcheroo_process_delayed_switch();
1015 }
1016
1017 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1018 {
1019         struct drm_i915_file_private *file_priv = file->driver_priv;
1020
1021         i915_gem_context_close(file);
1022
1023         kfree_rcu(file_priv, rcu);
1024
1025         /* Catch up with all the deferred frees from "this" client */
1026         i915_gem_flush_free_objects(to_i915(dev));
1027 }
1028
1029 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1030 {
1031         struct drm_device *dev = &dev_priv->drm;
1032         struct intel_encoder *encoder;
1033
1034         drm_modeset_lock_all(dev);
1035         for_each_intel_encoder(dev, encoder)
1036                 if (encoder->suspend)
1037                         encoder->suspend(encoder);
1038         drm_modeset_unlock_all(dev);
1039 }
1040
1041 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1042 {
1043         struct drm_device *dev = &dev_priv->drm;
1044         struct intel_encoder *encoder;
1045
1046         drm_modeset_lock_all(dev);
1047         for_each_intel_encoder(dev, encoder)
1048                 if (encoder->shutdown)
1049                         encoder->shutdown(encoder);
1050         drm_modeset_unlock_all(dev);
1051 }
1052
1053 void i915_driver_shutdown(struct drm_i915_private *i915)
1054 {
1055         i915_gem_suspend(i915);
1056
1057         drm_kms_helper_poll_disable(&i915->drm);
1058
1059         drm_atomic_helper_shutdown(&i915->drm);
1060
1061         intel_dp_mst_suspend(i915);
1062
1063         intel_runtime_pm_disable_interrupts(i915);
1064         intel_hpd_cancel_work(i915);
1065
1066         intel_suspend_encoders(i915);
1067         intel_shutdown_encoders(i915);
1068 }
1069
1070 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1071 {
1072 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1073         if (acpi_target_system_state() < ACPI_STATE_S3)
1074                 return true;
1075 #endif
1076         return false;
1077 }
1078
1079 static int i915_drm_prepare(struct drm_device *dev)
1080 {
1081         struct drm_i915_private *i915 = to_i915(dev);
1082
1083         /*
1084          * NB intel_display_suspend() may issue new requests after we've
1085          * ostensibly marked the GPU as ready-to-sleep here. We need to
1086          * split out that work and pull it forward so that after point,
1087          * the GPU is not woken again.
1088          */
1089         i915_gem_suspend(i915);
1090
1091         return 0;
1092 }
1093
1094 static int i915_drm_suspend(struct drm_device *dev)
1095 {
1096         struct drm_i915_private *dev_priv = to_i915(dev);
1097         struct pci_dev *pdev = dev_priv->drm.pdev;
1098         pci_power_t opregion_target_state;
1099
1100         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1101
1102         /* We do a lot of poking in a lot of registers, make sure they work
1103          * properly. */
1104         intel_power_domains_disable(dev_priv);
1105
1106         drm_kms_helper_poll_disable(dev);
1107
1108         pci_save_state(pdev);
1109
1110         intel_display_suspend(dev);
1111
1112         intel_dp_mst_suspend(dev_priv);
1113
1114         intel_runtime_pm_disable_interrupts(dev_priv);
1115         intel_hpd_cancel_work(dev_priv);
1116
1117         intel_suspend_encoders(dev_priv);
1118
1119         intel_suspend_hw(dev_priv);
1120
1121         i915_ggtt_suspend(&dev_priv->ggtt);
1122
1123         i915_save_display(dev_priv);
1124
1125         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1126         intel_opregion_suspend(dev_priv, opregion_target_state);
1127
1128         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1129
1130         dev_priv->suspend_count++;
1131
1132         intel_csr_ucode_suspend(dev_priv);
1133
1134         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1135
1136         return 0;
1137 }
1138
1139 static enum i915_drm_suspend_mode
1140 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1141 {
1142         if (hibernate)
1143                 return I915_DRM_SUSPEND_HIBERNATE;
1144
1145         if (suspend_to_idle(dev_priv))
1146                 return I915_DRM_SUSPEND_IDLE;
1147
1148         return I915_DRM_SUSPEND_MEM;
1149 }
1150
1151 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1152 {
1153         struct drm_i915_private *dev_priv = to_i915(dev);
1154         struct pci_dev *pdev = dev_priv->drm.pdev;
1155         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1156         int ret;
1157
1158         disable_rpm_wakeref_asserts(rpm);
1159
1160         i915_gem_suspend_late(dev_priv);
1161
1162         intel_uncore_suspend(&dev_priv->uncore);
1163
1164         intel_power_domains_suspend(dev_priv,
1165                                     get_suspend_mode(dev_priv, hibernation));
1166
1167         intel_display_power_suspend_late(dev_priv);
1168
1169         ret = vlv_suspend_complete(dev_priv);
1170         if (ret) {
1171                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1172                 intel_power_domains_resume(dev_priv);
1173
1174                 goto out;
1175         }
1176
1177         pci_disable_device(pdev);
1178         /*
1179          * During hibernation on some platforms the BIOS may try to access
1180          * the device even though it's already in D3 and hang the machine. So
1181          * leave the device in D0 on those platforms and hope the BIOS will
1182          * power down the device properly. The issue was seen on multiple old
1183          * GENs with different BIOS vendors, so having an explicit blacklist
1184          * is inpractical; apply the workaround on everything pre GEN6. The
1185          * platforms where the issue was seen:
1186          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1187          * Fujitsu FSC S7110
1188          * Acer Aspire 1830T
1189          */
1190         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1191                 pci_set_power_state(pdev, PCI_D3hot);
1192
1193 out:
1194         enable_rpm_wakeref_asserts(rpm);
1195         if (!dev_priv->uncore.user_forcewake_count)
1196                 intel_runtime_pm_driver_release(rpm);
1197
1198         return ret;
1199 }
1200
1201 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1202 {
1203         int error;
1204
1205         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1206                              state.event != PM_EVENT_FREEZE))
1207                 return -EINVAL;
1208
1209         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1210                 return 0;
1211
1212         error = i915_drm_suspend(&i915->drm);
1213         if (error)
1214                 return error;
1215
1216         return i915_drm_suspend_late(&i915->drm, false);
1217 }
1218
1219 static int i915_drm_resume(struct drm_device *dev)
1220 {
1221         struct drm_i915_private *dev_priv = to_i915(dev);
1222         int ret;
1223
1224         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1225
1226         sanitize_gpu(dev_priv);
1227
1228         ret = i915_ggtt_enable_hw(dev_priv);
1229         if (ret)
1230                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1231
1232         i915_ggtt_resume(&dev_priv->ggtt);
1233
1234         intel_csr_ucode_resume(dev_priv);
1235
1236         i915_restore_display(dev_priv);
1237         intel_pps_unlock_regs_wa(dev_priv);
1238
1239         intel_init_pch_refclk(dev_priv);
1240
1241         /*
1242          * Interrupts have to be enabled before any batches are run. If not the
1243          * GPU will hang. i915_gem_init_hw() will initiate batches to
1244          * update/restore the context.
1245          *
1246          * drm_mode_config_reset() needs AUX interrupts.
1247          *
1248          * Modeset enabling in intel_modeset_init_hw() also needs working
1249          * interrupts.
1250          */
1251         intel_runtime_pm_enable_interrupts(dev_priv);
1252
1253         drm_mode_config_reset(dev);
1254
1255         i915_gem_resume(dev_priv);
1256
1257         intel_modeset_init_hw(dev_priv);
1258         intel_init_clock_gating(dev_priv);
1259         intel_hpd_init(dev_priv);
1260
1261         /* MST sideband requires HPD interrupts enabled */
1262         intel_dp_mst_resume(dev_priv);
1263         intel_display_resume(dev);
1264
1265         intel_hpd_poll_disable(dev_priv);
1266         drm_kms_helper_poll_enable(dev);
1267
1268         intel_opregion_resume(dev_priv);
1269
1270         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1271
1272         intel_power_domains_enable(dev_priv);
1273
1274         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1275
1276         return 0;
1277 }
1278
1279 static int i915_drm_resume_early(struct drm_device *dev)
1280 {
1281         struct drm_i915_private *dev_priv = to_i915(dev);
1282         struct pci_dev *pdev = dev_priv->drm.pdev;
1283         int ret;
1284
1285         /*
1286          * We have a resume ordering issue with the snd-hda driver also
1287          * requiring our device to be power up. Due to the lack of a
1288          * parent/child relationship we currently solve this with an early
1289          * resume hook.
1290          *
1291          * FIXME: This should be solved with a special hdmi sink device or
1292          * similar so that power domains can be employed.
1293          */
1294
1295         /*
1296          * Note that we need to set the power state explicitly, since we
1297          * powered off the device during freeze and the PCI core won't power
1298          * it back up for us during thaw. Powering off the device during
1299          * freeze is not a hard requirement though, and during the
1300          * suspend/resume phases the PCI core makes sure we get here with the
1301          * device powered on. So in case we change our freeze logic and keep
1302          * the device powered we can also remove the following set power state
1303          * call.
1304          */
1305         ret = pci_set_power_state(pdev, PCI_D0);
1306         if (ret) {
1307                 drm_err(&dev_priv->drm,
1308                         "failed to set PCI D0 power state (%d)\n", ret);
1309                 return ret;
1310         }
1311
1312         /*
1313          * Note that pci_enable_device() first enables any parent bridge
1314          * device and only then sets the power state for this device. The
1315          * bridge enabling is a nop though, since bridge devices are resumed
1316          * first. The order of enabling power and enabling the device is
1317          * imposed by the PCI core as described above, so here we preserve the
1318          * same order for the freeze/thaw phases.
1319          *
1320          * TODO: eventually we should remove pci_disable_device() /
1321          * pci_enable_enable_device() from suspend/resume. Due to how they
1322          * depend on the device enable refcount we can't anyway depend on them
1323          * disabling/enabling the device.
1324          */
1325         if (pci_enable_device(pdev))
1326                 return -EIO;
1327
1328         pci_set_master(pdev);
1329
1330         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1331
1332         ret = vlv_resume_prepare(dev_priv, false);
1333         if (ret)
1334                 drm_err(&dev_priv->drm,
1335                         "Resume prepare failed: %d, continuing anyway\n", ret);
1336
1337         intel_uncore_resume_early(&dev_priv->uncore);
1338
1339         intel_gt_check_and_clear_faults(&dev_priv->gt);
1340
1341         intel_display_power_resume_early(dev_priv);
1342
1343         intel_power_domains_resume(dev_priv);
1344
1345         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1346
1347         return ret;
1348 }
1349
1350 int i915_resume_switcheroo(struct drm_i915_private *i915)
1351 {
1352         int ret;
1353
1354         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1355                 return 0;
1356
1357         ret = i915_drm_resume_early(&i915->drm);
1358         if (ret)
1359                 return ret;
1360
1361         return i915_drm_resume(&i915->drm);
1362 }
1363
1364 static int i915_pm_prepare(struct device *kdev)
1365 {
1366         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1367
1368         if (!i915) {
1369                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1370                 return -ENODEV;
1371         }
1372
1373         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1374                 return 0;
1375
1376         return i915_drm_prepare(&i915->drm);
1377 }
1378
1379 static int i915_pm_suspend(struct device *kdev)
1380 {
1381         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1382
1383         if (!i915) {
1384                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1385                 return -ENODEV;
1386         }
1387
1388         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1389                 return 0;
1390
1391         return i915_drm_suspend(&i915->drm);
1392 }
1393
1394 static int i915_pm_suspend_late(struct device *kdev)
1395 {
1396         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1397
1398         /*
1399          * We have a suspend ordering issue with the snd-hda driver also
1400          * requiring our device to be power up. Due to the lack of a
1401          * parent/child relationship we currently solve this with an late
1402          * suspend hook.
1403          *
1404          * FIXME: This should be solved with a special hdmi sink device or
1405          * similar so that power domains can be employed.
1406          */
1407         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1408                 return 0;
1409
1410         return i915_drm_suspend_late(&i915->drm, false);
1411 }
1412
1413 static int i915_pm_poweroff_late(struct device *kdev)
1414 {
1415         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1416
1417         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1418                 return 0;
1419
1420         return i915_drm_suspend_late(&i915->drm, true);
1421 }
1422
1423 static int i915_pm_resume_early(struct device *kdev)
1424 {
1425         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1426
1427         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1428                 return 0;
1429
1430         return i915_drm_resume_early(&i915->drm);
1431 }
1432
1433 static int i915_pm_resume(struct device *kdev)
1434 {
1435         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1436
1437         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1438                 return 0;
1439
1440         return i915_drm_resume(&i915->drm);
1441 }
1442
1443 /* freeze: before creating the hibernation_image */
1444 static int i915_pm_freeze(struct device *kdev)
1445 {
1446         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1447         int ret;
1448
1449         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1450                 ret = i915_drm_suspend(&i915->drm);
1451                 if (ret)
1452                         return ret;
1453         }
1454
1455         ret = i915_gem_freeze(i915);
1456         if (ret)
1457                 return ret;
1458
1459         return 0;
1460 }
1461
1462 static int i915_pm_freeze_late(struct device *kdev)
1463 {
1464         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1465         int ret;
1466
1467         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1468                 ret = i915_drm_suspend_late(&i915->drm, true);
1469                 if (ret)
1470                         return ret;
1471         }
1472
1473         ret = i915_gem_freeze_late(i915);
1474         if (ret)
1475                 return ret;
1476
1477         return 0;
1478 }
1479
1480 /* thaw: called after creating the hibernation image, but before turning off. */
1481 static int i915_pm_thaw_early(struct device *kdev)
1482 {
1483         return i915_pm_resume_early(kdev);
1484 }
1485
1486 static int i915_pm_thaw(struct device *kdev)
1487 {
1488         return i915_pm_resume(kdev);
1489 }
1490
1491 /* restore: called after loading the hibernation image. */
1492 static int i915_pm_restore_early(struct device *kdev)
1493 {
1494         return i915_pm_resume_early(kdev);
1495 }
1496
1497 static int i915_pm_restore(struct device *kdev)
1498 {
1499         return i915_pm_resume(kdev);
1500 }
1501
1502 static int intel_runtime_suspend(struct device *kdev)
1503 {
1504         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1505         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1506         int ret;
1507
1508         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1509                 return -ENODEV;
1510
1511         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1512
1513         disable_rpm_wakeref_asserts(rpm);
1514
1515         /*
1516          * We are safe here against re-faults, since the fault handler takes
1517          * an RPM reference.
1518          */
1519         i915_gem_runtime_suspend(dev_priv);
1520
1521         intel_gt_runtime_suspend(&dev_priv->gt);
1522
1523         intel_runtime_pm_disable_interrupts(dev_priv);
1524
1525         intel_uncore_suspend(&dev_priv->uncore);
1526
1527         intel_display_power_suspend(dev_priv);
1528
1529         ret = vlv_suspend_complete(dev_priv);
1530         if (ret) {
1531                 drm_err(&dev_priv->drm,
1532                         "Runtime suspend failed, disabling it (%d)\n", ret);
1533                 intel_uncore_runtime_resume(&dev_priv->uncore);
1534
1535                 intel_runtime_pm_enable_interrupts(dev_priv);
1536
1537                 intel_gt_runtime_resume(&dev_priv->gt);
1538
1539                 enable_rpm_wakeref_asserts(rpm);
1540
1541                 return ret;
1542         }
1543
1544         enable_rpm_wakeref_asserts(rpm);
1545         intel_runtime_pm_driver_release(rpm);
1546
1547         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1548                 drm_err(&dev_priv->drm,
1549                         "Unclaimed access detected prior to suspending\n");
1550
1551         rpm->suspended = true;
1552
1553         /*
1554          * FIXME: We really should find a document that references the arguments
1555          * used below!
1556          */
1557         if (IS_BROADWELL(dev_priv)) {
1558                 /*
1559                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1560                  * being detected, and the call we do at intel_runtime_resume()
1561                  * won't be able to restore them. Since PCI_D3hot matches the
1562                  * actual specification and appears to be working, use it.
1563                  */
1564                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1565         } else {
1566                 /*
1567                  * current versions of firmware which depend on this opregion
1568                  * notification have repurposed the D1 definition to mean
1569                  * "runtime suspended" vs. what you would normally expect (D3)
1570                  * to distinguish it from notifications that might be sent via
1571                  * the suspend path.
1572                  */
1573                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1574         }
1575
1576         assert_forcewakes_inactive(&dev_priv->uncore);
1577
1578         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1579                 intel_hpd_poll_enable(dev_priv);
1580
1581         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1582         return 0;
1583 }
1584
1585 static int intel_runtime_resume(struct device *kdev)
1586 {
1587         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1588         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1589         int ret;
1590
1591         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1592                 return -ENODEV;
1593
1594         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1595
1596         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1597         disable_rpm_wakeref_asserts(rpm);
1598
1599         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1600         rpm->suspended = false;
1601         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1602                 drm_dbg(&dev_priv->drm,
1603                         "Unclaimed access during suspend, bios?\n");
1604
1605         intel_display_power_resume(dev_priv);
1606
1607         ret = vlv_resume_prepare(dev_priv, true);
1608
1609         intel_uncore_runtime_resume(&dev_priv->uncore);
1610
1611         intel_runtime_pm_enable_interrupts(dev_priv);
1612
1613         /*
1614          * No point of rolling back things in case of an error, as the best
1615          * we can do is to hope that things will still work (and disable RPM).
1616          */
1617         intel_gt_runtime_resume(&dev_priv->gt);
1618
1619         /*
1620          * On VLV/CHV display interrupts are part of the display
1621          * power well, so hpd is reinitialized from there. For
1622          * everyone else do it here.
1623          */
1624         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1625                 intel_hpd_init(dev_priv);
1626                 intel_hpd_poll_disable(dev_priv);
1627         }
1628
1629         intel_enable_ipc(dev_priv);
1630
1631         enable_rpm_wakeref_asserts(rpm);
1632
1633         if (ret)
1634                 drm_err(&dev_priv->drm,
1635                         "Runtime resume failed, disabling it (%d)\n", ret);
1636         else
1637                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1638
1639         return ret;
1640 }
1641
1642 const struct dev_pm_ops i915_pm_ops = {
1643         /*
1644          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1645          * PMSG_RESUME]
1646          */
1647         .prepare = i915_pm_prepare,
1648         .suspend = i915_pm_suspend,
1649         .suspend_late = i915_pm_suspend_late,
1650         .resume_early = i915_pm_resume_early,
1651         .resume = i915_pm_resume,
1652
1653         /*
1654          * S4 event handlers
1655          * @freeze, @freeze_late    : called (1) before creating the
1656          *                            hibernation image [PMSG_FREEZE] and
1657          *                            (2) after rebooting, before restoring
1658          *                            the image [PMSG_QUIESCE]
1659          * @thaw, @thaw_early       : called (1) after creating the hibernation
1660          *                            image, before writing it [PMSG_THAW]
1661          *                            and (2) after failing to create or
1662          *                            restore the image [PMSG_RECOVER]
1663          * @poweroff, @poweroff_late: called after writing the hibernation
1664          *                            image, before rebooting [PMSG_HIBERNATE]
1665          * @restore, @restore_early : called after rebooting and restoring the
1666          *                            hibernation image [PMSG_RESTORE]
1667          */
1668         .freeze = i915_pm_freeze,
1669         .freeze_late = i915_pm_freeze_late,
1670         .thaw_early = i915_pm_thaw_early,
1671         .thaw = i915_pm_thaw,
1672         .poweroff = i915_pm_suspend,
1673         .poweroff_late = i915_pm_poweroff_late,
1674         .restore_early = i915_pm_restore_early,
1675         .restore = i915_pm_restore,
1676
1677         /* S0ix (via runtime suspend) event handlers */
1678         .runtime_suspend = intel_runtime_suspend,
1679         .runtime_resume = intel_runtime_resume,
1680 };
1681
1682 static const struct file_operations i915_driver_fops = {
1683         .owner = THIS_MODULE,
1684         .open = drm_open,
1685         .release = drm_release_noglobal,
1686         .unlocked_ioctl = drm_ioctl,
1687         .mmap = i915_gem_mmap,
1688         .poll = drm_poll,
1689         .read = drm_read,
1690         .compat_ioctl = i915_ioc32_compat_ioctl,
1691         .llseek = noop_llseek,
1692 };
1693
1694 static int
1695 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1696                           struct drm_file *file)
1697 {
1698         return -ENODEV;
1699 }
1700
1701 static const struct drm_ioctl_desc i915_ioctls[] = {
1702         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1703         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1704         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1705         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1706         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1707         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1708         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1709         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1710         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1711         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1712         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1713         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1714         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1715         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1716         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1717         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1718         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1719         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1720         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
1721         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1722         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1723         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1724         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1725         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1726         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1727         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1728         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1729         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1730         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1731         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1732         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1733         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1734         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1735         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1736         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1738         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1739         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1740         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1741         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1742         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1743         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1744         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1745         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1746         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1747         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1748         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1749         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1750         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1751         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1752         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1753         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1754         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1755         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1756         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1757         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1758         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1759         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1760 };
1761
1762 static const struct drm_driver driver = {
1763         /* Don't use MTRRs here; the Xserver or userspace app should
1764          * deal with them for Intel hardware.
1765          */
1766         .driver_features =
1767             DRIVER_GEM |
1768             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1769             DRIVER_SYNCOBJ_TIMELINE,
1770         .release = i915_driver_release,
1771         .open = i915_driver_open,
1772         .lastclose = i915_driver_lastclose,
1773         .postclose = i915_driver_postclose,
1774
1775         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1776         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1777         .gem_prime_import = i915_gem_prime_import,
1778
1779         .dumb_create = i915_gem_dumb_create,
1780         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1781
1782         .ioctls = i915_ioctls,
1783         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1784         .fops = &i915_driver_fops,
1785         .name = DRIVER_NAME,
1786         .desc = DRIVER_DESC,
1787         .date = DRIVER_DATE,
1788         .major = DRIVER_MAJOR,
1789         .minor = DRIVER_MINOR,
1790         .patchlevel = DRIVER_PATCHLEVEL,
1791 };