drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/apple-gmux.h>
  39 #include <linux/console.h>
  40 #include <linux/module.h>
  41 #include <linux/pm_runtime.h>
  42 #include <linux/vgaarb.h>
  43 #include <linux/vga_switcheroo.h>
  44 #include <drm/drm_crtc_helper.h>
  45
  46 static struct drm_driver driver;
  47
  48 #define GEN_DEFAULT_PIPEOFFSETS \
  49         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  50                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  51         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  52                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  53         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  54
  55 #define GEN_CHV_PIPEOFFSETS \
  56         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  57                           CHV_PIPE_C_OFFSET }, \
  58         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  59                            CHV_TRANSCODER_C_OFFSET, }, \
  60         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  61                              CHV_PALETTE_C_OFFSET }
  62
  63 #define CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  65
  66 #define IVB_CURSOR_OFFSETS \
  67         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  68
  69 #define BDW_COLORS \
  70         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  71
  72 static const struct intel_device_info intel_i830_info = {
  73         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  74         .has_overlay = 1, .overlay_needs_physical = 1,
  75         .ring_mask = RENDER_RING,
  76         GEN_DEFAULT_PIPEOFFSETS,
  77         CURSOR_OFFSETS,
  78 };
  79
  80 static const struct intel_device_info intel_845g_info = {
  81         .gen = 2, .num_pipes = 1,
  82         .has_overlay = 1, .overlay_needs_physical = 1,
  83         .ring_mask = RENDER_RING,
  84         GEN_DEFAULT_PIPEOFFSETS,
  85         CURSOR_OFFSETS,
  86 };
  87
  88 static const struct intel_device_info intel_i85x_info = {
  89         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  90         .cursor_needs_physical = 1,
  91         .has_overlay = 1, .overlay_needs_physical = 1,
  92         .has_fbc = 1,
  93         .ring_mask = RENDER_RING,
  94         GEN_DEFAULT_PIPEOFFSETS,
  95         CURSOR_OFFSETS,
  96 };
  97
  98 static const struct intel_device_info intel_i865g_info = {
  99         .gen = 2, .num_pipes = 1,
 100         .has_overlay = 1, .overlay_needs_physical = 1,
 101         .ring_mask = RENDER_RING,
 102         GEN_DEFAULT_PIPEOFFSETS,
 103         CURSOR_OFFSETS,
 104 };
 105
 106 static const struct intel_device_info intel_i915g_info = {
 107         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 108         .has_overlay = 1, .overlay_needs_physical = 1,
 109         .ring_mask = RENDER_RING,
 110         GEN_DEFAULT_PIPEOFFSETS,
 111         CURSOR_OFFSETS,
 112 };
 113 static const struct intel_device_info intel_i915gm_info = {
 114         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 115         .cursor_needs_physical = 1,
 116         .has_overlay = 1, .overlay_needs_physical = 1,
 117         .supports_tv = 1,
 118         .has_fbc = 1,
 119         .ring_mask = RENDER_RING,
 120         GEN_DEFAULT_PIPEOFFSETS,
 121         CURSOR_OFFSETS,
 122 };
 123 static const struct intel_device_info intel_i945g_info = {
 124         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 125         .has_overlay = 1, .overlay_needs_physical = 1,
 126         .ring_mask = RENDER_RING,
 127         GEN_DEFAULT_PIPEOFFSETS,
 128         CURSOR_OFFSETS,
 129 };
 130 static const struct intel_device_info intel_i945gm_info = {
 131         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 132         .has_hotplug = 1, .cursor_needs_physical = 1,
 133         .has_overlay = 1, .overlay_needs_physical = 1,
 134         .supports_tv = 1,
 135         .has_fbc = 1,
 136         .ring_mask = RENDER_RING,
 137         GEN_DEFAULT_PIPEOFFSETS,
 138         CURSOR_OFFSETS,
 139 };
 140
 141 static const struct intel_device_info intel_i965g_info = {
 142         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 143         .has_hotplug = 1,
 144         .has_overlay = 1,
 145         .ring_mask = RENDER_RING,
 146         GEN_DEFAULT_PIPEOFFSETS,
 147         CURSOR_OFFSETS,
 148 };
 149
 150 static const struct intel_device_info intel_i965gm_info = {
 151         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 152         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 153         .has_overlay = 1,
 154         .supports_tv = 1,
 155         .ring_mask = RENDER_RING,
 156         GEN_DEFAULT_PIPEOFFSETS,
 157         CURSOR_OFFSETS,
 158 };
 159
 160 static const struct intel_device_info intel_g33_info = {
 161         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 162         .need_gfx_hws = 1, .has_hotplug = 1,
 163         .has_overlay = 1,
 164         .ring_mask = RENDER_RING,
 165         GEN_DEFAULT_PIPEOFFSETS,
 166         CURSOR_OFFSETS,
 167 };
 168
 169 static const struct intel_device_info intel_g45_info = {
 170         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 171         .has_pipe_cxsr = 1, .has_hotplug = 1,
 172         .ring_mask = RENDER_RING | BSD_RING,
 173         GEN_DEFAULT_PIPEOFFSETS,
 174         CURSOR_OFFSETS,
 175 };
 176
 177 static const struct intel_device_info intel_gm45_info = {
 178         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 179         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 180         .has_pipe_cxsr = 1, .has_hotplug = 1,
 181         .supports_tv = 1,
 182         .ring_mask = RENDER_RING | BSD_RING,
 183         GEN_DEFAULT_PIPEOFFSETS,
 184         CURSOR_OFFSETS,
 185 };
 186
 187 static const struct intel_device_info intel_pineview_info = {
 188         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 189         .need_gfx_hws = 1, .has_hotplug = 1,
 190         .has_overlay = 1,
 191         GEN_DEFAULT_PIPEOFFSETS,
 192         CURSOR_OFFSETS,
 193 };
 194
 195 static const struct intel_device_info intel_ironlake_d_info = {
 196         .gen = 5, .num_pipes = 2,
 197         .need_gfx_hws = 1, .has_hotplug = 1,
 198         .ring_mask = RENDER_RING | BSD_RING,
 199         GEN_DEFAULT_PIPEOFFSETS,
 200         CURSOR_OFFSETS,
 201 };
 202
 203 static const struct intel_device_info intel_ironlake_m_info = {
 204         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 205         .need_gfx_hws = 1, .has_hotplug = 1,
 206         .has_fbc = 1,
 207         .ring_mask = RENDER_RING | BSD_RING,
 208         GEN_DEFAULT_PIPEOFFSETS,
 209         CURSOR_OFFSETS,
 210 };
 211
 212 static const struct intel_device_info intel_sandybridge_d_info = {
 213         .gen = 6, .num_pipes = 2,
 214         .need_gfx_hws = 1, .has_hotplug = 1,
 215         .has_fbc = 1,
 216         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 217         .has_llc = 1,
 218         GEN_DEFAULT_PIPEOFFSETS,
 219         CURSOR_OFFSETS,
 220 };
 221
 222 static const struct intel_device_info intel_sandybridge_m_info = {
 223         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 224         .need_gfx_hws = 1, .has_hotplug = 1,
 225         .has_fbc = 1,
 226         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 227         .has_llc = 1,
 228         GEN_DEFAULT_PIPEOFFSETS,
 229         CURSOR_OFFSETS,
 230 };
 231
 232 #define GEN7_FEATURES  \
 233         .gen = 7, .num_pipes = 3, \
 234         .need_gfx_hws = 1, .has_hotplug = 1, \
 235         .has_fbc = 1, \
 236         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 237         .has_llc = 1, \
 238         GEN_DEFAULT_PIPEOFFSETS, \
 239         IVB_CURSOR_OFFSETS
 240
 241 static const struct intel_device_info intel_ivybridge_d_info = {
 242         GEN7_FEATURES,
 243         .is_ivybridge = 1,
 244 };
 245
 246 static const struct intel_device_info intel_ivybridge_m_info = {
 247         GEN7_FEATURES,
 248         .is_ivybridge = 1,
 249         .is_mobile = 1,
 250 };
 251
 252 static const struct intel_device_info intel_ivybridge_q_info = {
 253         GEN7_FEATURES,
 254         .is_ivybridge = 1,
 255         .num_pipes = 0, /* legal, last one wins */
 256 };
 257
 258 #define VLV_FEATURES  \
 259         .gen = 7, .num_pipes = 2, \
 260         .need_gfx_hws = 1, .has_hotplug = 1, \
 261         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 262         .display_mmio_offset = VLV_DISPLAY_BASE, \
 263         GEN_DEFAULT_PIPEOFFSETS, \
 264         CURSOR_OFFSETS
 265
 266 static const struct intel_device_info intel_valleyview_m_info = {
 267         VLV_FEATURES,
 268         .is_valleyview = 1,
 269         .is_mobile = 1,
 270 };
 271
 272 static const struct intel_device_info intel_valleyview_d_info = {
 273         VLV_FEATURES,
 274         .is_valleyview = 1,
 275 };
 276
 277 #define HSW_FEATURES  \
 278         GEN7_FEATURES, \
 279         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 280         .has_ddi = 1, \
 281         .has_fpga_dbg = 1
 282
 283 static const struct intel_device_info intel_haswell_d_info = {
 284         HSW_FEATURES,
 285         .is_haswell = 1,
 286 };
 287
 288 static const struct intel_device_info intel_haswell_m_info = {
 289         HSW_FEATURES,
 290         .is_haswell = 1,
 291         .is_mobile = 1,
 292 };
 293
 294 #define BDW_FEATURES \
 295         HSW_FEATURES, \
 296         BDW_COLORS
 297
 298 static const struct intel_device_info intel_broadwell_d_info = {
 299         BDW_FEATURES,
 300         .gen = 8,
 301 };
 302
 303 static const struct intel_device_info intel_broadwell_m_info = {
 304         BDW_FEATURES,
 305         .gen = 8, .is_mobile = 1,
 306 };
 307
 308 static const struct intel_device_info intel_broadwell_gt3d_info = {
 309         BDW_FEATURES,
 310         .gen = 8,
 311         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 312 };
 313
 314 static const struct intel_device_info intel_broadwell_gt3m_info = {
 315         BDW_FEATURES,
 316         .gen = 8, .is_mobile = 1,
 317         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 318 };
 319
 320 static const struct intel_device_info intel_cherryview_info = {
 321         .gen = 8, .num_pipes = 3,
 322         .need_gfx_hws = 1, .has_hotplug = 1,
 323         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 324         .is_cherryview = 1,
 325         .display_mmio_offset = VLV_DISPLAY_BASE,
 326         GEN_CHV_PIPEOFFSETS,
 327         CURSOR_OFFSETS,
 328 };
 329
 330 static const struct intel_device_info intel_skylake_info = {
 331         BDW_FEATURES,
 332         .is_skylake = 1,
 333         .gen = 9,
 334 };
 335
 336 static const struct intel_device_info intel_skylake_gt3_info = {
 337         BDW_FEATURES,
 338         .is_skylake = 1,
 339         .gen = 9,
 340         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 341 };
 342
 343 static const struct intel_device_info intel_broxton_info = {
 344         .is_preliminary = 1,
 345         .is_broxton = 1,
 346         .gen = 9,
 347         .need_gfx_hws = 1, .has_hotplug = 1,
 348         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 349         .num_pipes = 3,
 350         .has_ddi = 1,
 351         .has_fpga_dbg = 1,
 352         .has_fbc = 1,
 353         GEN_DEFAULT_PIPEOFFSETS,
 354         IVB_CURSOR_OFFSETS,
 355         BDW_COLORS,
 356 };
 357
 358 static const struct intel_device_info intel_kabylake_info = {
 359         BDW_FEATURES,
 360         .is_preliminary = 1,
 361         .is_kabylake = 1,
 362         .gen = 9,
 363 };
 364
 365 static const struct intel_device_info intel_kabylake_gt3_info = {
 366         BDW_FEATURES,
 367         .is_preliminary = 1,
 368         .is_kabylake = 1,
 369         .gen = 9,
 370         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 371 };
 372
 373 /*
 374  * Make sure any device matches here are from most specific to most
 375  * general.  For example, since the Quanta match is based on the subsystem
 376  * and subvendor IDs, we need it to come before the more general IVB
 377  * PCI ID matches, otherwise we'll use the wrong info struct above.
 378  */
 379 static const struct pci_device_id pciidlist[] = {
 380         INTEL_I830_IDS(&intel_i830_info),
 381         INTEL_I845G_IDS(&intel_845g_info),
 382         INTEL_I85X_IDS(&intel_i85x_info),
 383         INTEL_I865G_IDS(&intel_i865g_info),
 384         INTEL_I915G_IDS(&intel_i915g_info),
 385         INTEL_I915GM_IDS(&intel_i915gm_info),
 386         INTEL_I945G_IDS(&intel_i945g_info),
 387         INTEL_I945GM_IDS(&intel_i945gm_info),
 388         INTEL_I965G_IDS(&intel_i965g_info),
 389         INTEL_G33_IDS(&intel_g33_info),
 390         INTEL_I965GM_IDS(&intel_i965gm_info),
 391         INTEL_GM45_IDS(&intel_gm45_info),
 392         INTEL_G45_IDS(&intel_g45_info),
 393         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 394         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 395         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 396         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
 397         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
 398         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 399         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 400         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
 401         INTEL_HSW_D_IDS(&intel_haswell_d_info),
 402         INTEL_HSW_M_IDS(&intel_haswell_m_info),
 403         INTEL_VLV_M_IDS(&intel_valleyview_m_info),
 404         INTEL_VLV_D_IDS(&intel_valleyview_d_info),
 405         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
 406         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
 407         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
 408         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
 409         INTEL_CHV_IDS(&intel_cherryview_info),
 410         INTEL_SKL_GT1_IDS(&intel_skylake_info),
 411         INTEL_SKL_GT2_IDS(&intel_skylake_info),
 412         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 413         INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
 414         INTEL_BXT_IDS(&intel_broxton_info),
 415         INTEL_KBL_GT1_IDS(&intel_kabylake_info),
 416         INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 417         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 418         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 419         {0, 0, 0}
 420 };
 421
 422 MODULE_DEVICE_TABLE(pci, pciidlist);
 423
 424 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 425 {
 426         enum intel_pch ret = PCH_NOP;
 427
 428         /*
 429          * In a virtualized passthrough environment we can be in a
 430          * setup where the ISA bridge is not able to be passed through.
 431          * In this case, a south bridge can be emulated and we have to
 432          * make an educated guess as to which PCH is really there.
 433          */
 434
 435         if (IS_GEN5(dev)) {
 436                 ret = PCH_IBX;
 437                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 438         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 439                 ret = PCH_CPT;
 440                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 441         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 442                 ret = PCH_LPT;
 443                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 444         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 445                 ret = PCH_SPT;
 446                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 447         }
 448
 449         return ret;
 450 }
 451
 452 void intel_detect_pch(struct drm_device *dev)
 453 {
 454         struct drm_i915_private *dev_priv = dev->dev_private;
 455         struct pci_dev *pch = NULL;
 456
 457         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 458          * (which really amounts to a PCH but no South Display).
 459          */
 460         if (INTEL_INFO(dev)->num_pipes == 0) {
 461                 dev_priv->pch_type = PCH_NOP;
 462                 return;
 463         }
 464
 465         /*
 466          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 467          * make graphics device passthrough work easy for VMM, that only
 468          * need to expose ISA bridge to let driver know the real hardware
 469          * underneath. This is a requirement from virtualization team.
 470          *
 471          * In some virtualized environments (e.g. XEN), there is irrelevant
 472          * ISA bridge in the system. To work reliably, we should scan trhough
 473          * all the ISA bridge devices and check for the first match, instead
 474          * of only checking the first one.
 475          */
 476         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 477                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 478                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 479                         dev_priv->pch_id = id;
 480
 481                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 482                                 dev_priv->pch_type = PCH_IBX;
 483                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 484                                 WARN_ON(!IS_GEN5(dev));
 485                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 486                                 dev_priv->pch_type = PCH_CPT;
 487                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 488                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 489                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 490                                 /* PantherPoint is CPT compatible */
 491                                 dev_priv->pch_type = PCH_CPT;
 492                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 493                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 494                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 495                                 dev_priv->pch_type = PCH_LPT;
 496                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 497                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 498                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 499                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 500                                 dev_priv->pch_type = PCH_LPT;
 501                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 502                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 503                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 504                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 505                                 dev_priv->pch_type = PCH_SPT;
 506                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 507                                 WARN_ON(!IS_SKYLAKE(dev) &&
 508                                         !IS_KABYLAKE(dev));
 509                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 510                                 dev_priv->pch_type = PCH_SPT;
 511                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 512                                 WARN_ON(!IS_SKYLAKE(dev) &&
 513                                         !IS_KABYLAKE(dev));
 514                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 515                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 516                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 517                                     pch->subsystem_vendor == 0x1af4 &&
 518                                     pch->subsystem_device == 0x1100)) {
 519                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 520                         } else
 521                                 continue;
 522
 523                         break;
 524                 }
 525         }
 526         if (!pch)
 527                 DRM_DEBUG_KMS("No PCH found.\n");
 528
 529         pci_dev_put(pch);
 530 }
 531
 532 bool i915_semaphore_is_enabled(struct drm_device *dev)
 533 {
 534         if (INTEL_INFO(dev)->gen < 6)
 535                 return false;
 536
 537         if (i915.semaphores >= 0)
 538                 return i915.semaphores;
 539
 540         /* TODO: make semaphores and Execlists play nicely together */
 541         if (i915.enable_execlists)
 542                 return false;
 543
 544         /* Until we get further testing... */
 545         if (IS_GEN8(dev))
 546                 return false;
 547
 548 #ifdef CONFIG_INTEL_IOMMU
 549         /* Enable semaphores on SNB when IO remapping is off */
 550         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 551                 return false;
 552 #endif
 553
 554         return true;
 555 }
 556
 557 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 558 {
 559         struct drm_device *dev = dev_priv->dev;
 560         struct intel_encoder *encoder;
 561
 562         drm_modeset_lock_all(dev);
 563         for_each_intel_encoder(dev, encoder)
 564                 if (encoder->suspend)
 565                         encoder->suspend(encoder);
 566         drm_modeset_unlock_all(dev);
 567 }
 568
 569 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 570 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 571                               bool rpm_resume);
 572 static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
 573
 574 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
 575 {
 576 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 577         if (acpi_target_system_state() < ACPI_STATE_S3)
 578                 return true;
 579 #endif
 580         return false;
 581 }
 582
 583 static int i915_drm_suspend(struct drm_device *dev)
 584 {
 585         struct drm_i915_private *dev_priv = dev->dev_private;
 586         pci_power_t opregion_target_state;
 587         int error;
 588
 589         /* ignore lid events during suspend */
 590         mutex_lock(&dev_priv->modeset_restore_lock);
 591         dev_priv->modeset_restore = MODESET_SUSPENDED;
 592         mutex_unlock(&dev_priv->modeset_restore_lock);
 593
 594         disable_rpm_wakeref_asserts(dev_priv);
 595
 596         /* We do a lot of poking in a lot of registers, make sure they work
 597          * properly. */
 598         intel_display_set_init_power(dev_priv, true);
 599
 600         drm_kms_helper_poll_disable(dev);
 601
 602         pci_save_state(dev->pdev);
 603
 604         error = i915_gem_suspend(dev);
 605         if (error) {
 606                 dev_err(&dev->pdev->dev,
 607                         "GEM idle failed, resume might fail\n");
 608                 goto out;
 609         }
 610
 611         intel_guc_suspend(dev);
 612
 613         intel_suspend_gt_powersave(dev);
 614
 615         intel_display_suspend(dev);
 616
 617         intel_dp_mst_suspend(dev);
 618
 619         intel_runtime_pm_disable_interrupts(dev_priv);
 620         intel_hpd_cancel_work(dev_priv);
 621
 622         intel_suspend_encoders(dev_priv);
 623
 624         intel_suspend_hw(dev);
 625
 626         i915_gem_suspend_gtt_mappings(dev);
 627
 628         i915_save_state(dev);
 629
 630         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
 631         intel_opregion_notify_adapter(dev, opregion_target_state);
 632
 633         intel_uncore_forcewake_reset(dev, false);
 634         intel_opregion_fini(dev);
 635
 636         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 637
 638         dev_priv->suspend_count++;
 639
 640         intel_display_set_init_power(dev_priv, false);
 641
 642         if (HAS_CSR(dev_priv))
 643                 flush_work(&dev_priv->csr.work);
 644
 645 out:
 646         enable_rpm_wakeref_asserts(dev_priv);
 647
 648         return error;
 649 }
 650
 651 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 652 {
 653         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 654         bool fw_csr;
 655         int ret;
 656
 657         disable_rpm_wakeref_asserts(dev_priv);
 658
 659         fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
 660         /*
 661          * In case of firmware assisted context save/restore don't manually
 662          * deinit the power domains. This also means the CSR/DMC firmware will
 663          * stay active, it will power down any HW resources as required and
 664          * also enable deeper system power states that would be blocked if the
 665          * firmware was inactive.
 666          */
 667         if (!fw_csr)
 668                 intel_power_domains_suspend(dev_priv);
 669
 670         ret = intel_suspend_complete(dev_priv);
 671
 672         if (ret) {
 673                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 674                 if (!fw_csr)
 675                         intel_power_domains_init_hw(dev_priv, true);
 676
 677                 goto out;
 678         }
 679
 680         pci_disable_device(drm_dev->pdev);
 681         /*
 682          * During hibernation on some platforms the BIOS may try to access
 683          * the device even though it's already in D3 and hang the machine. So
 684          * leave the device in D0 on those platforms and hope the BIOS will
 685          * power down the device properly. The issue was seen on multiple old
 686          * GENs with different BIOS vendors, so having an explicit blacklist
 687          * is inpractical; apply the workaround on everything pre GEN6. The
 688          * platforms where the issue was seen:
 689          * Lenovo Thinkpad X301, X61s, X60, T60, X41
 690          * Fujitsu FSC S7110
 691          * Acer Aspire 1830T
 692          */
 693         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
 694                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 695
 696         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
 697
 698 out:
 699         enable_rpm_wakeref_asserts(dev_priv);
 700
 701         return ret;
 702 }
 703
 704 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
 705 {
 706         int error;
 707
 708         if (!dev || !dev->dev_private) {
 709                 DRM_ERROR("dev: %p\n", dev);
 710                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 711                 return -ENODEV;
 712         }
 713
 714         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 715                          state.event != PM_EVENT_FREEZE))
 716                 return -EINVAL;
 717
 718         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 719                 return 0;
 720
 721         error = i915_drm_suspend(dev);
 722         if (error)
 723                 return error;
 724
 725         return i915_drm_suspend_late(dev, false);
 726 }
 727
 728 static int i915_drm_resume(struct drm_device *dev)
 729 {
 730         struct drm_i915_private *dev_priv = dev->dev_private;
 731
 732         disable_rpm_wakeref_asserts(dev_priv);
 733
 734         mutex_lock(&dev->struct_mutex);
 735         i915_gem_restore_gtt_mappings(dev);
 736         mutex_unlock(&dev->struct_mutex);
 737
 738         i915_restore_state(dev);
 739         intel_opregion_setup(dev);
 740
 741         intel_init_pch_refclk(dev);
 742         drm_mode_config_reset(dev);
 743
 744         /*
 745          * Interrupts have to be enabled before any batches are run. If not the
 746          * GPU will hang. i915_gem_init_hw() will initiate batches to
 747          * update/restore the context.
 748          *
 749          * Modeset enabling in intel_modeset_init_hw() also needs working
 750          * interrupts.
 751          */
 752         intel_runtime_pm_enable_interrupts(dev_priv);
 753
 754         mutex_lock(&dev->struct_mutex);
 755         if (i915_gem_init_hw(dev)) {
 756                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 757                         atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 758         }
 759         mutex_unlock(&dev->struct_mutex);
 760
 761         intel_guc_resume(dev);
 762
 763         intel_modeset_init_hw(dev);
 764
 765         spin_lock_irq(&dev_priv->irq_lock);
 766         if (dev_priv->display.hpd_irq_setup)
 767                 dev_priv->display.hpd_irq_setup(dev);
 768         spin_unlock_irq(&dev_priv->irq_lock);
 769
 770         intel_display_resume(dev);
 771
 772         intel_dp_mst_resume(dev);
 773
 774         /*
 775          * ... but also need to make sure that hotplug processing
 776          * doesn't cause havoc. Like in the driver load code we don't
 777          * bother with the tiny race here where we might loose hotplug
 778          * notifications.
 779          * */
 780         intel_hpd_init(dev_priv);
 781         /* Config may have changed between suspend and resume */
 782         drm_helper_hpd_irq_event(dev);
 783
 784         intel_opregion_init(dev);
 785
 786         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 787
 788         mutex_lock(&dev_priv->modeset_restore_lock);
 789         dev_priv->modeset_restore = MODESET_DONE;
 790         mutex_unlock(&dev_priv->modeset_restore_lock);
 791
 792         intel_opregion_notify_adapter(dev, PCI_D0);
 793
 794         drm_kms_helper_poll_enable(dev);
 795
 796         enable_rpm_wakeref_asserts(dev_priv);
 797
 798         return 0;
 799 }
 800
 801 static int i915_drm_resume_early(struct drm_device *dev)
 802 {
 803         struct drm_i915_private *dev_priv = dev->dev_private;
 804         int ret = 0;
 805
 806         /*
 807          * We have a resume ordering issue with the snd-hda driver also
 808          * requiring our device to be power up. Due to the lack of a
 809          * parent/child relationship we currently solve this with an early
 810          * resume hook.
 811          *
 812          * FIXME: This should be solved with a special hdmi sink device or
 813          * similar so that power domains can be employed.
 814          */
 815         if (pci_enable_device(dev->pdev)) {
 816                 ret = -EIO;
 817                 goto out;
 818         }
 819
 820         pci_set_master(dev->pdev);
 821
 822         disable_rpm_wakeref_asserts(dev_priv);
 823
 824         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 825                 ret = vlv_resume_prepare(dev_priv, false);
 826         if (ret)
 827                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 828                           ret);
 829
 830         intel_uncore_early_sanitize(dev, true);
 831
 832         if (IS_BROXTON(dev))
 833                 ret = bxt_resume_prepare(dev_priv);
 834         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 835                 hsw_disable_pc8(dev_priv);
 836
 837         intel_uncore_sanitize(dev);
 838
 839         if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
 840                 intel_power_domains_init_hw(dev_priv, true);
 841
 842 out:
 843         dev_priv->suspended_to_idle = false;
 844
 845         enable_rpm_wakeref_asserts(dev_priv);
 846
 847         return ret;
 848 }
 849
 850 int i915_resume_switcheroo(struct drm_device *dev)
 851 {
 852         int ret;
 853
 854         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 855                 return 0;
 856
 857         ret = i915_drm_resume_early(dev);
 858         if (ret)
 859                 return ret;
 860
 861         return i915_drm_resume(dev);
 862 }
 863
 864 /**
 865  * i915_reset - reset chip after a hang
 866  * @dev: drm device to reset
 867  *
 868  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 869  * reset or otherwise an error code.
 870  *
 871  * Procedure is fairly simple:
 872  *   - reset the chip using the reset reg
 873  *   - re-init context state
 874  *   - re-init hardware status page
 875  *   - re-init ring buffer
 876  *   - re-init interrupt state
 877  *   - re-init display
 878  */
 879 int i915_reset(struct drm_device *dev)
 880 {
 881         struct drm_i915_private *dev_priv = dev->dev_private;
 882         bool simulated;
 883         int ret;
 884
 885         intel_reset_gt_powersave(dev);
 886
 887         mutex_lock(&dev->struct_mutex);
 888
 889         i915_gem_reset(dev);
 890
 891         simulated = dev_priv->gpu_error.stop_rings != 0;
 892
 893         ret = intel_gpu_reset(dev, ALL_ENGINES);
 894
 895         /* Also reset the gpu hangman. */
 896         if (simulated) {
 897                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 898                 dev_priv->gpu_error.stop_rings = 0;
 899                 if (ret == -ENODEV) {
 900                         DRM_INFO("Reset not implemented, but ignoring "
 901                                  "error for simulated gpu hangs\n");
 902                         ret = 0;
 903                 }
 904         }
 905
 906         if (i915_stop_ring_allow_warn(dev_priv))
 907                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 908
 909         if (ret) {
 910                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 911                 mutex_unlock(&dev->struct_mutex);
 912                 return ret;
 913         }
 914
 915         intel_overlay_reset(dev_priv);
 916
 917         /* Ok, now get things going again... */
 918
 919         /*
 920          * Everything depends on having the GTT running, so we need to start
 921          * there.  Fortunately we don't need to do this unless we reset the
 922          * chip at a PCI level.
 923          *
 924          * Next we need to restore the context, but we don't use those
 925          * yet either...
 926          *
 927          * Ring buffer needs to be re-initialized in the KMS case, or if X
 928          * was running at the time of the reset (i.e. we weren't VT
 929          * switched away).
 930          */
 931
 932         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 933         dev_priv->gpu_error.reload_in_reset = true;
 934
 935         ret = i915_gem_init_hw(dev);
 936
 937         dev_priv->gpu_error.reload_in_reset = false;
 938
 939         mutex_unlock(&dev->struct_mutex);
 940         if (ret) {
 941                 DRM_ERROR("Failed hw init on reset %d\n", ret);
 942                 return ret;
 943         }
 944
 945         /*
 946          * rps/rc6 re-init is necessary to restore state lost after the
 947          * reset and the re-install of gt irqs. Skip for ironlake per
 948          * previous concerns that it doesn't respond well to some forms
 949          * of re-init after reset.
 950          */
 951         if (INTEL_INFO(dev)->gen > 5)
 952                 intel_enable_gt_powersave(dev);
 953
 954         return 0;
 955 }
 956
 957 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 958 {
 959         struct intel_device_info *intel_info =
 960                 (struct intel_device_info *) ent->driver_data;
 961
 962         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 963                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 964                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 965                 return -ENODEV;
 966         }
 967
 968         /* Only bind to function 0 of the device. Early generations
 969          * used function 1 as a placeholder for multi-head. This causes
 970          * us confusion instead, especially on the systems where both
 971          * functions have the same PCI-ID!
 972          */
 973         if (PCI_FUNC(pdev->devfn))
 974                 return -ENODEV;
 975
 976         /*
 977          * apple-gmux is needed on dual GPU MacBook Pro
 978          * to probe the panel if we're the inactive GPU.
 979          */
 980         if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
 981             apple_gmux_present() && pdev != vga_default_device() &&
 982             !vga_switcheroo_handler_flags())
 983                 return -EPROBE_DEFER;
 984
 985         return drm_get_pci_dev(pdev, ent, &driver);
 986 }
 987
 988 static void
 989 i915_pci_remove(struct pci_dev *pdev)
 990 {
 991         struct drm_device *dev = pci_get_drvdata(pdev);
 992
 993         drm_put_dev(dev);
 994 }
 995
 996 static int i915_pm_suspend(struct device *dev)
 997 {
 998         struct pci_dev *pdev = to_pci_dev(dev);
 999         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1000
1001         if (!drm_dev || !drm_dev->dev_private) {
1002                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1003                 return -ENODEV;
1004         }
1005
1006         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1007                 return 0;
1008
1009         return i915_drm_suspend(drm_dev);
1010 }
1011
1012 static int i915_pm_suspend_late(struct device *dev)
1013 {
1014         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1015
1016         /*
1017          * We have a suspend ordering issue with the snd-hda driver also
1018          * requiring our device to be power up. Due to the lack of a
1019          * parent/child relationship we currently solve this with an late
1020          * suspend hook.
1021          *
1022          * FIXME: This should be solved with a special hdmi sink device or
1023          * similar so that power domains can be employed.
1024          */
1025         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1026                 return 0;
1027
1028         return i915_drm_suspend_late(drm_dev, false);
1029 }
1030
1031 static int i915_pm_poweroff_late(struct device *dev)
1032 {
1033         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1034
1035         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1036                 return 0;
1037
1038         return i915_drm_suspend_late(drm_dev, true);
1039 }
1040
1041 static int i915_pm_resume_early(struct device *dev)
1042 {
1043         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1044
1045         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1046                 return 0;
1047
1048         return i915_drm_resume_early(drm_dev);
1049 }
1050
1051 static int i915_pm_resume(struct device *dev)
1052 {
1053         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1054
1055         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1056                 return 0;
1057
1058         return i915_drm_resume(drm_dev);
1059 }
1060
1061 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1062 {
1063         hsw_enable_pc8(dev_priv);
1064
1065         return 0;
1066 }
1067
1068 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1069 {
1070         struct drm_device *dev = dev_priv->dev;
1071
1072         /* TODO: when DC5 support is added disable DC5 here. */
1073
1074         broxton_ddi_phy_uninit(dev);
1075         broxton_uninit_cdclk(dev);
1076         bxt_enable_dc9(dev_priv);
1077
1078         return 0;
1079 }
1080
1081 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1082 {
1083         struct drm_device *dev = dev_priv->dev;
1084
1085         /* TODO: when CSR FW support is added make sure the FW is loaded */
1086
1087         bxt_disable_dc9(dev_priv);
1088
1089         /*
1090          * TODO: when DC5 support is added enable DC5 here if the CSR FW
1091          * is available.
1092          */
1093         broxton_init_cdclk(dev);
1094         broxton_ddi_phy_init(dev);
1095
1096         return 0;
1097 }
1098
1099 /*
1100  * Save all Gunit registers that may be lost after a D3 and a subsequent
1101  * S0i[R123] transition. The list of registers needing a save/restore is
1102  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1103  * registers in the following way:
1104  * - Driver: saved/restored by the driver
1105  * - Punit : saved/restored by the Punit firmware
1106  * - No, w/o marking: no need to save/restore, since the register is R/O or
1107  *                    used internally by the HW in a way that doesn't depend
1108  *                    keeping the content across a suspend/resume.
1109  * - Debug : used for debugging
1110  *
1111  * We save/restore all registers marked with 'Driver', with the following
1112  * exceptions:
1113  * - Registers out of use, including also registers marked with 'Debug'.
1114  *   These have no effect on the driver's operation, so we don't save/restore
1115  *   them to reduce the overhead.
1116  * - Registers that are fully setup by an initialization function called from
1117  *   the resume path. For example many clock gating and RPS/RC6 registers.
1118  * - Registers that provide the right functionality with their reset defaults.
1119  *
1120  * TODO: Except for registers that based on the above 3 criteria can be safely
1121  * ignored, we save/restore all others, practically treating the HW context as
1122  * a black-box for the driver. Further investigation is needed to reduce the
1123  * saved/restored registers even further, by following the same 3 criteria.
1124  */
1125 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1126 {
1127         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1128         int i;
1129
1130         /* GAM 0x4000-0x4770 */
1131         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1132         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1133         s->arb_mode             = I915_READ(ARB_MODE);
1134         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1135         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1136
1137         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1138                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1139
1140         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1141         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1142
1143         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1144         s->ecochk               = I915_READ(GAM_ECOCHK);
1145         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1146         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1147
1148         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1149
1150         /* MBC 0x9024-0x91D0, 0x8500 */
1151         s->g3dctl               = I915_READ(VLV_G3DCTL);
1152         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1153         s->mbctl                = I915_READ(GEN6_MBCTL);
1154
1155         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1156         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1157         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1158         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1159         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1160         s->rstctl               = I915_READ(GEN6_RSTCTL);
1161         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1162
1163         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1164         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1165         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1166         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1167         s->ecobus               = I915_READ(ECOBUS);
1168         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1169         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1170         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1171         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1172         s->rcedata              = I915_READ(VLV_RCEDATA);
1173         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1174
1175         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1176         s->gt_imr               = I915_READ(GTIMR);
1177         s->gt_ier               = I915_READ(GTIER);
1178         s->pm_imr               = I915_READ(GEN6_PMIMR);
1179         s->pm_ier               = I915_READ(GEN6_PMIER);
1180
1181         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1182                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1183
1184         /* GT SA CZ domain, 0x100000-0x138124 */
1185         s->tilectl              = I915_READ(TILECTL);
1186         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1187         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1188         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1189         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1190
1191         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1192         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1193         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1194         s->pcbr                 = I915_READ(VLV_PCBR);
1195         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1196
1197         /*
1198          * Not saving any of:
1199          * DFT,         0x9800-0x9EC0
1200          * SARB,        0xB000-0xB1FC
1201          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1202          * PCI CFG
1203          */
1204 }
1205
1206 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1207 {
1208         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1209         u32 val;
1210         int i;
1211
1212         /* GAM 0x4000-0x4770 */
1213         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1214         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1215         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1216         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1217         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1218
1219         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1220                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1221
1222         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1223         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1224
1225         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1226         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1227         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1228         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1229
1230         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1231
1232         /* MBC 0x9024-0x91D0, 0x8500 */
1233         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1234         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1235         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1236
1237         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1238         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1239         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1240         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1241         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1242         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1243         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1244
1245         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1246         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1247         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1248         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1249         I915_WRITE(ECOBUS,              s->ecobus);
1250         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1251         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1252         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1253         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1254         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1255         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1256
1257         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1258         I915_WRITE(GTIMR,               s->gt_imr);
1259         I915_WRITE(GTIER,               s->gt_ier);
1260         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1261         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1262
1263         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1264                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1265
1266         /* GT SA CZ domain, 0x100000-0x138124 */
1267         I915_WRITE(TILECTL,                     s->tilectl);
1268         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1269         /*
1270          * Preserve the GT allow wake and GFX force clock bit, they are not
1271          * be restored, as they are used to control the s0ix suspend/resume
1272          * sequence by the caller.
1273          */
1274         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1275         val &= VLV_GTLC_ALLOWWAKEREQ;
1276         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1277         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1278
1279         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1280         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1281         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1282         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1283
1284         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1285
1286         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1287         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1288         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1289         I915_WRITE(VLV_PCBR,                    s->pcbr);
1290         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1291 }
1292
1293 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1294 {
1295         u32 val;
1296         int err;
1297
1298 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1299
1300         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1301         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1302         if (force_on)
1303                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1304         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1305
1306         if (!force_on)
1307                 return 0;
1308
1309         err = wait_for(COND, 20);
1310         if (err)
1311                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1312                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1313
1314         return err;
1315 #undef COND
1316 }
1317
1318 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1319 {
1320         u32 val;
1321         int err = 0;
1322
1323         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1324         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1325         if (allow)
1326                 val |= VLV_GTLC_ALLOWWAKEREQ;
1327         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1328         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1329
1330 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1331               allow)
1332         err = wait_for(COND, 1);
1333         if (err)
1334                 DRM_ERROR("timeout disabling GT waking\n");
1335         return err;
1336 #undef COND
1337 }
1338
1339 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1340                                  bool wait_for_on)
1341 {
1342         u32 mask;
1343         u32 val;
1344         int err;
1345
1346         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1347         val = wait_for_on ? mask : 0;
1348 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1349         if (COND)
1350                 return 0;
1351
1352         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1353                       onoff(wait_for_on),
1354                       I915_READ(VLV_GTLC_PW_STATUS));
1355
1356         /*
1357          * RC6 transitioning can be delayed up to 2 msec (see
1358          * valleyview_enable_rps), use 3 msec for safety.
1359          */
1360         err = wait_for(COND, 3);
1361         if (err)
1362                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1363                           onoff(wait_for_on));
1364
1365         return err;
1366 #undef COND
1367 }
1368
1369 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1370 {
1371         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1372                 return;
1373
1374         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1375         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1376 }
1377
1378 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1379 {
1380         u32 mask;
1381         int err;
1382
1383         /*
1384          * Bspec defines the following GT well on flags as debug only, so
1385          * don't treat them as hard failures.
1386          */
1387         (void)vlv_wait_for_gt_wells(dev_priv, false);
1388
1389         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1390         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1391
1392         vlv_check_no_gt_access(dev_priv);
1393
1394         err = vlv_force_gfx_clock(dev_priv, true);
1395         if (err)
1396                 goto err1;
1397
1398         err = vlv_allow_gt_wake(dev_priv, false);
1399         if (err)
1400                 goto err2;
1401
1402         if (!IS_CHERRYVIEW(dev_priv->dev))
1403                 vlv_save_gunit_s0ix_state(dev_priv);
1404
1405         err = vlv_force_gfx_clock(dev_priv, false);
1406         if (err)
1407                 goto err2;
1408
1409         return 0;
1410
1411 err2:
1412         /* For safety always re-enable waking and disable gfx clock forcing */
1413         vlv_allow_gt_wake(dev_priv, true);
1414 err1:
1415         vlv_force_gfx_clock(dev_priv, false);
1416
1417         return err;
1418 }
1419
1420 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1421                                 bool rpm_resume)
1422 {
1423         struct drm_device *dev = dev_priv->dev;
1424         int err;
1425         int ret;
1426
1427         /*
1428          * If any of the steps fail just try to continue, that's the best we
1429          * can do at this point. Return the first error code (which will also
1430          * leave RPM permanently disabled).
1431          */
1432         ret = vlv_force_gfx_clock(dev_priv, true);
1433
1434         if (!IS_CHERRYVIEW(dev_priv->dev))
1435                 vlv_restore_gunit_s0ix_state(dev_priv);
1436
1437         err = vlv_allow_gt_wake(dev_priv, true);
1438         if (!ret)
1439                 ret = err;
1440
1441         err = vlv_force_gfx_clock(dev_priv, false);
1442         if (!ret)
1443                 ret = err;
1444
1445         vlv_check_no_gt_access(dev_priv);
1446
1447         if (rpm_resume) {
1448                 intel_init_clock_gating(dev);
1449                 i915_gem_restore_fences(dev);
1450         }
1451
1452         return ret;
1453 }
1454
1455 static int intel_runtime_suspend(struct device *device)
1456 {
1457         struct pci_dev *pdev = to_pci_dev(device);
1458         struct drm_device *dev = pci_get_drvdata(pdev);
1459         struct drm_i915_private *dev_priv = dev->dev_private;
1460         int ret;
1461
1462         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1463                 return -ENODEV;
1464
1465         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1466                 return -ENODEV;
1467
1468         DRM_DEBUG_KMS("Suspending device\n");
1469
1470         /*
1471          * We could deadlock here in case another thread holding struct_mutex
1472          * calls RPM suspend concurrently, since the RPM suspend will wait
1473          * first for this RPM suspend to finish. In this case the concurrent
1474          * RPM resume will be followed by its RPM suspend counterpart. Still
1475          * for consistency return -EAGAIN, which will reschedule this suspend.
1476          */
1477         if (!mutex_trylock(&dev->struct_mutex)) {
1478                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1479                 /*
1480                  * Bump the expiration timestamp, otherwise the suspend won't
1481                  * be rescheduled.
1482                  */
1483                 pm_runtime_mark_last_busy(device);
1484
1485                 return -EAGAIN;
1486         }
1487
1488         disable_rpm_wakeref_asserts(dev_priv);
1489
1490         /*
1491          * We are safe here against re-faults, since the fault handler takes
1492          * an RPM reference.
1493          */
1494         i915_gem_release_all_mmaps(dev_priv);
1495         mutex_unlock(&dev->struct_mutex);
1496
1497         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1498
1499         intel_guc_suspend(dev);
1500
1501         intel_suspend_gt_powersave(dev);
1502         intel_runtime_pm_disable_interrupts(dev_priv);
1503
1504         ret = intel_suspend_complete(dev_priv);
1505         if (ret) {
1506                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1507                 intel_runtime_pm_enable_interrupts(dev_priv);
1508
1509                 enable_rpm_wakeref_asserts(dev_priv);
1510
1511                 return ret;
1512         }
1513
1514         intel_uncore_forcewake_reset(dev, false);
1515
1516         enable_rpm_wakeref_asserts(dev_priv);
1517         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1518
1519         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1520                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1521
1522         dev_priv->pm.suspended = true;
1523
1524         /*
1525          * FIXME: We really should find a document that references the arguments
1526          * used below!
1527          */
1528         if (IS_BROADWELL(dev)) {
1529                 /*
1530                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1531                  * being detected, and the call we do at intel_runtime_resume()
1532                  * won't be able to restore them. Since PCI_D3hot matches the
1533                  * actual specification and appears to be working, use it.
1534                  */
1535                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1536         } else {
1537                 /*
1538                  * current versions of firmware which depend on this opregion
1539                  * notification have repurposed the D1 definition to mean
1540                  * "runtime suspended" vs. what you would normally expect (D3)
1541                  * to distinguish it from notifications that might be sent via
1542                  * the suspend path.
1543                  */
1544                 intel_opregion_notify_adapter(dev, PCI_D1);
1545         }
1546
1547         assert_forcewakes_inactive(dev_priv);
1548
1549         DRM_DEBUG_KMS("Device suspended\n");
1550         return 0;
1551 }
1552
1553 static int intel_runtime_resume(struct device *device)
1554 {
1555         struct pci_dev *pdev = to_pci_dev(device);
1556         struct drm_device *dev = pci_get_drvdata(pdev);
1557         struct drm_i915_private *dev_priv = dev->dev_private;
1558         int ret = 0;
1559
1560         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1561                 return -ENODEV;
1562
1563         DRM_DEBUG_KMS("Resuming device\n");
1564
1565         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1566         disable_rpm_wakeref_asserts(dev_priv);
1567
1568         intel_opregion_notify_adapter(dev, PCI_D0);
1569         dev_priv->pm.suspended = false;
1570         if (intel_uncore_unclaimed_mmio(dev_priv))
1571                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1572
1573         intel_guc_resume(dev);
1574
1575         if (IS_GEN6(dev_priv))
1576                 intel_init_pch_refclk(dev);
1577
1578         if (IS_BROXTON(dev))
1579                 ret = bxt_resume_prepare(dev_priv);
1580         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1581                 hsw_disable_pc8(dev_priv);
1582         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1583                 ret = vlv_resume_prepare(dev_priv, true);
1584
1585         /*
1586          * No point of rolling back things in case of an error, as the best
1587          * we can do is to hope that things will still work (and disable RPM).
1588          */
1589         i915_gem_init_swizzling(dev);
1590         gen6_update_ring_freq(dev);
1591
1592         intel_runtime_pm_enable_interrupts(dev_priv);
1593
1594         /*
1595          * On VLV/CHV display interrupts are part of the display
1596          * power well, so hpd is reinitialized from there. For
1597          * everyone else do it here.
1598          */
1599         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1600                 intel_hpd_init(dev_priv);
1601
1602         intel_enable_gt_powersave(dev);
1603
1604         enable_rpm_wakeref_asserts(dev_priv);
1605
1606         if (ret)
1607                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1608         else
1609                 DRM_DEBUG_KMS("Device resumed\n");
1610
1611         return ret;
1612 }
1613
1614 /*
1615  * This function implements common functionality of runtime and system
1616  * suspend sequence.
1617  */
1618 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1619 {
1620         int ret;
1621
1622         if (IS_BROXTON(dev_priv))
1623                 ret = bxt_suspend_complete(dev_priv);
1624         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1625                 ret = hsw_suspend_complete(dev_priv);
1626         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1627                 ret = vlv_suspend_complete(dev_priv);
1628         else
1629                 ret = 0;
1630
1631         return ret;
1632 }
1633
1634 static const struct dev_pm_ops i915_pm_ops = {
1635         /*
1636          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1637          * PMSG_RESUME]
1638          */
1639         .suspend = i915_pm_suspend,
1640         .suspend_late = i915_pm_suspend_late,
1641         .resume_early = i915_pm_resume_early,
1642         .resume = i915_pm_resume,
1643
1644         /*
1645          * S4 event handlers
1646          * @freeze, @freeze_late    : called (1) before creating the
1647          *                            hibernation image [PMSG_FREEZE] and
1648          *                            (2) after rebooting, before restoring
1649          *                            the image [PMSG_QUIESCE]
1650          * @thaw, @thaw_early       : called (1) after creating the hibernation
1651          *                            image, before writing it [PMSG_THAW]
1652          *                            and (2) after failing to create or
1653          *                            restore the image [PMSG_RECOVER]
1654          * @poweroff, @poweroff_late: called after writing the hibernation
1655          *                            image, before rebooting [PMSG_HIBERNATE]
1656          * @restore, @restore_early : called after rebooting and restoring the
1657          *                            hibernation image [PMSG_RESTORE]
1658          */
1659         .freeze = i915_pm_suspend,
1660         .freeze_late = i915_pm_suspend_late,
1661         .thaw_early = i915_pm_resume_early,
1662         .thaw = i915_pm_resume,
1663         .poweroff = i915_pm_suspend,
1664         .poweroff_late = i915_pm_poweroff_late,
1665         .restore_early = i915_pm_resume_early,
1666         .restore = i915_pm_resume,
1667
1668         /* S0ix (via runtime suspend) event handlers */
1669         .runtime_suspend = intel_runtime_suspend,
1670         .runtime_resume = intel_runtime_resume,
1671 };
1672
1673 static const struct vm_operations_struct i915_gem_vm_ops = {
1674         .fault = i915_gem_fault,
1675         .open = drm_gem_vm_open,
1676         .close = drm_gem_vm_close,
1677 };
1678
1679 static const struct file_operations i915_driver_fops = {
1680         .owner = THIS_MODULE,
1681         .open = drm_open,
1682         .release = drm_release,
1683         .unlocked_ioctl = drm_ioctl,
1684         .mmap = drm_gem_mmap,
1685         .poll = drm_poll,
1686         .read = drm_read,
1687 #ifdef CONFIG_COMPAT
1688         .compat_ioctl = i915_compat_ioctl,
1689 #endif
1690         .llseek = noop_llseek,
1691 };
1692
1693 static struct drm_driver driver = {
1694         /* Don't use MTRRs here; the Xserver or userspace app should
1695          * deal with them for Intel hardware.
1696          */
1697         .driver_features =
1698             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1699             DRIVER_RENDER | DRIVER_MODESET,
1700         .load = i915_driver_load,
1701         .unload = i915_driver_unload,
1702         .open = i915_driver_open,
1703         .lastclose = i915_driver_lastclose,
1704         .preclose = i915_driver_preclose,
1705         .postclose = i915_driver_postclose,
1706         .set_busid = drm_pci_set_busid,
1707
1708 #if defined(CONFIG_DEBUG_FS)
1709         .debugfs_init = i915_debugfs_init,
1710         .debugfs_cleanup = i915_debugfs_cleanup,
1711 #endif
1712         .gem_free_object = i915_gem_free_object,
1713         .gem_vm_ops = &i915_gem_vm_ops,
1714
1715         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1716         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1717         .gem_prime_export = i915_gem_prime_export,
1718         .gem_prime_import = i915_gem_prime_import,
1719
1720         .dumb_create = i915_gem_dumb_create,
1721         .dumb_map_offset = i915_gem_mmap_gtt,
1722         .dumb_destroy = drm_gem_dumb_destroy,
1723         .ioctls = i915_ioctls,
1724         .fops = &i915_driver_fops,
1725         .name = DRIVER_NAME,
1726         .desc = DRIVER_DESC,
1727         .date = DRIVER_DATE,
1728         .major = DRIVER_MAJOR,
1729         .minor = DRIVER_MINOR,
1730         .patchlevel = DRIVER_PATCHLEVEL,
1731 };
1732
1733 static struct pci_driver i915_pci_driver = {
1734         .name = DRIVER_NAME,
1735         .id_table = pciidlist,
1736         .probe = i915_pci_probe,
1737         .remove = i915_pci_remove,
1738         .driver.pm = &i915_pm_ops,
1739 };
1740
1741 static int __init i915_init(void)
1742 {
1743         driver.num_ioctls = i915_max_ioctl;
1744
1745         /*
1746          * Enable KMS by default, unless explicitly overriden by
1747          * either the i915.modeset prarameter or by the
1748          * vga_text_mode_force boot option.
1749          */
1750
1751         if (i915.modeset == 0)
1752                 driver.driver_features &= ~DRIVER_MODESET;
1753
1754 #ifdef CONFIG_VGA_CONSOLE
1755         if (vgacon_text_force() && i915.modeset == -1)
1756                 driver.driver_features &= ~DRIVER_MODESET;
1757 #endif
1758
1759         if (!(driver.driver_features & DRIVER_MODESET)) {
1760                 /* Silently fail loading to not upset userspace. */
1761                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1762                 return 0;
1763         }
1764
1765         if (i915.nuclear_pageflip)
1766                 driver.driver_features |= DRIVER_ATOMIC;
1767
1768         return drm_pci_init(&driver, &i915_pci_driver);
1769 }
1770
1771 static void __exit i915_exit(void)
1772 {
1773         if (!(driver.driver_features & DRIVER_MODESET))
1774                 return; /* Never loaded a driver. */
1775
1776         drm_pci_exit(&driver, &i915_pci_driver);
1777 }
1778
1779 module_init(i915_init);
1780 module_exit(i915_exit);
1781
1782 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1783 MODULE_AUTHOR("Intel Corporation");
1784
1785 MODULE_DESCRIPTION(DRIVER_DESC);
1786 MODULE_LICENSE("GPL and additional rights");