1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
50 int i915_panel_ignore_lid __read_mostly = 1;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123 MODULE_PARM_DESC(preliminary_hw_support,
124 "Enable preliminary hardware support. (default: false)");
126 int i915_disable_power_well __read_mostly = 0;
127 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
128 MODULE_PARM_DESC(disable_power_well,
129 "Disable the power well when possible (default: false)");
131 static struct drm_driver driver;
132 extern int intel_agp_enabled;
134 #define INTEL_VGA_DEVICE(id, info) { \
135 .class = PCI_BASE_CLASS_DISPLAY << 16, \
136 .class_mask = 0xff0000, \
139 .subvendor = PCI_ANY_ID, \
140 .subdevice = PCI_ANY_ID, \
141 .driver_data = (unsigned long) info }
143 #define INTEL_QUANTA_VGA_DEVICE(info) { \
144 .class = PCI_BASE_CLASS_DISPLAY << 16, \
145 .class_mask = 0xff0000, \
148 .subvendor = 0x152d, \
149 .subdevice = 0x8990, \
150 .driver_data = (unsigned long) info }
153 static const struct intel_device_info intel_i830_info = {
154 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
155 .has_overlay = 1, .overlay_needs_physical = 1,
158 static const struct intel_device_info intel_845g_info = {
159 .gen = 2, .num_pipes = 1,
160 .has_overlay = 1, .overlay_needs_physical = 1,
163 static const struct intel_device_info intel_i85x_info = {
164 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
165 .cursor_needs_physical = 1,
166 .has_overlay = 1, .overlay_needs_physical = 1,
169 static const struct intel_device_info intel_i865g_info = {
170 .gen = 2, .num_pipes = 1,
171 .has_overlay = 1, .overlay_needs_physical = 1,
174 static const struct intel_device_info intel_i915g_info = {
175 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
176 .has_overlay = 1, .overlay_needs_physical = 1,
178 static const struct intel_device_info intel_i915gm_info = {
179 .gen = 3, .is_mobile = 1, .num_pipes = 2,
180 .cursor_needs_physical = 1,
181 .has_overlay = 1, .overlay_needs_physical = 1,
184 static const struct intel_device_info intel_i945g_info = {
185 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
186 .has_overlay = 1, .overlay_needs_physical = 1,
188 static const struct intel_device_info intel_i945gm_info = {
189 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
190 .has_hotplug = 1, .cursor_needs_physical = 1,
191 .has_overlay = 1, .overlay_needs_physical = 1,
195 static const struct intel_device_info intel_i965g_info = {
196 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
201 static const struct intel_device_info intel_i965gm_info = {
202 .gen = 4, .is_crestline = 1, .num_pipes = 2,
203 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
208 static const struct intel_device_info intel_g33_info = {
209 .gen = 3, .is_g33 = 1, .num_pipes = 2,
210 .need_gfx_hws = 1, .has_hotplug = 1,
214 static const struct intel_device_info intel_g45_info = {
215 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
216 .has_pipe_cxsr = 1, .has_hotplug = 1,
220 static const struct intel_device_info intel_gm45_info = {
221 .gen = 4, .is_g4x = 1, .num_pipes = 2,
222 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
223 .has_pipe_cxsr = 1, .has_hotplug = 1,
228 static const struct intel_device_info intel_pineview_info = {
229 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
230 .need_gfx_hws = 1, .has_hotplug = 1,
234 static const struct intel_device_info intel_ironlake_d_info = {
235 .gen = 5, .num_pipes = 2,
236 .need_gfx_hws = 1, .has_hotplug = 1,
240 static const struct intel_device_info intel_ironlake_m_info = {
241 .gen = 5, .is_mobile = 1, .num_pipes = 2,
242 .need_gfx_hws = 1, .has_hotplug = 1,
247 static const struct intel_device_info intel_sandybridge_d_info = {
248 .gen = 6, .num_pipes = 2,
249 .need_gfx_hws = 1, .has_hotplug = 1,
256 static const struct intel_device_info intel_sandybridge_m_info = {
257 .gen = 6, .is_mobile = 1, .num_pipes = 2,
258 .need_gfx_hws = 1, .has_hotplug = 1,
266 #define GEN7_FEATURES \
267 .gen = 7, .num_pipes = 3, \
268 .need_gfx_hws = 1, .has_hotplug = 1, \
274 static const struct intel_device_info intel_ivybridge_d_info = {
279 static const struct intel_device_info intel_ivybridge_m_info = {
285 static const struct intel_device_info intel_ivybridge_q_info = {
288 .num_pipes = 0, /* legal, last one wins */
291 static const struct intel_device_info intel_valleyview_m_info = {
296 .display_mmio_offset = VLV_DISPLAY_BASE,
297 .has_llc = 0, /* legal, last one wins */
300 static const struct intel_device_info intel_valleyview_d_info = {
304 .display_mmio_offset = VLV_DISPLAY_BASE,
305 .has_llc = 0, /* legal, last one wins */
308 static const struct intel_device_info intel_haswell_d_info = {
313 static const struct intel_device_info intel_haswell_m_info = {
319 static const struct pci_device_id pciidlist[] = { /* aka */
320 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
321 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
322 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
323 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
324 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
325 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
326 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
327 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
328 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
329 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
330 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
331 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
332 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
333 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
334 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
335 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
336 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
337 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
338 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
339 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
340 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
341 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
342 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
343 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
344 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
345 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
346 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
347 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
348 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
349 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
350 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
351 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
352 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
353 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
354 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
355 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
356 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
357 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
358 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
359 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
360 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
361 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
362 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
363 INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
364 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
365 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
366 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
367 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
368 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
369 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
370 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
371 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
372 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
373 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
374 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
375 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
376 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
377 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
378 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
379 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
380 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
381 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
382 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
383 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
384 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
385 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
386 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
387 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
388 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
389 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
390 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
391 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
392 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
393 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
394 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
395 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
396 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
397 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
398 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
399 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
400 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
401 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
402 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
403 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
404 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
405 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
406 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
410 #if defined(CONFIG_DRM_I915_KMS)
411 MODULE_DEVICE_TABLE(pci, pciidlist);
414 void intel_detect_pch(struct drm_device *dev)
416 struct drm_i915_private *dev_priv = dev->dev_private;
419 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
420 * (which really amounts to a PCH but no South Display).
422 if (INTEL_INFO(dev)->num_pipes == 0) {
423 dev_priv->pch_type = PCH_NOP;
424 dev_priv->num_pch_pll = 0;
429 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
430 * make graphics device passthrough work easy for VMM, that only
431 * need to expose ISA bridge to let driver know the real hardware
432 * underneath. This is a requirement from virtualization team.
434 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
436 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
438 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
439 dev_priv->pch_id = id;
441 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
442 dev_priv->pch_type = PCH_IBX;
443 dev_priv->num_pch_pll = 2;
444 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
445 WARN_ON(!IS_GEN5(dev));
446 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
447 dev_priv->pch_type = PCH_CPT;
448 dev_priv->num_pch_pll = 2;
449 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
450 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
451 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
452 /* PantherPoint is CPT compatible */
453 dev_priv->pch_type = PCH_CPT;
454 dev_priv->num_pch_pll = 2;
455 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
456 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
457 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
458 dev_priv->pch_type = PCH_LPT;
459 dev_priv->num_pch_pll = 0;
460 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
461 WARN_ON(!IS_HASWELL(dev));
462 WARN_ON(IS_ULT(dev));
463 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
464 dev_priv->pch_type = PCH_LPT;
465 dev_priv->num_pch_pll = 0;
466 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
467 WARN_ON(!IS_HASWELL(dev));
468 WARN_ON(!IS_ULT(dev));
470 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
476 bool i915_semaphore_is_enabled(struct drm_device *dev)
478 if (INTEL_INFO(dev)->gen < 6)
481 if (i915_semaphores >= 0)
482 return i915_semaphores;
484 #ifdef CONFIG_INTEL_IOMMU
485 /* Enable semaphores on SNB when IO remapping is off */
486 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
493 static int i915_drm_freeze(struct drm_device *dev)
495 struct drm_i915_private *dev_priv = dev->dev_private;
496 struct drm_crtc *crtc;
498 /* ignore lid events during suspend */
499 mutex_lock(&dev_priv->modeset_restore_lock);
500 dev_priv->modeset_restore = MODESET_SUSPENDED;
501 mutex_unlock(&dev_priv->modeset_restore_lock);
503 intel_set_power_well(dev, true);
505 drm_kms_helper_poll_disable(dev);
507 pci_save_state(dev->pdev);
509 /* If KMS is active, we do the leavevt stuff here */
510 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
511 int error = i915_gem_idle(dev);
513 dev_err(&dev->pdev->dev,
514 "GEM idle failed, resume might fail\n");
518 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
520 drm_irq_uninstall(dev);
521 dev_priv->enable_hotplug_processing = false;
523 * Disable CRTCs directly since we want to preserve sw state
526 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
527 dev_priv->display.crtc_disable(crtc);
530 i915_save_state(dev);
532 intel_opregion_fini(dev);
535 intel_fbdev_set_suspend(dev, 1);
541 int i915_suspend(struct drm_device *dev, pm_message_t state)
545 if (!dev || !dev->dev_private) {
546 DRM_ERROR("dev: %p\n", dev);
547 DRM_ERROR("DRM not initialized, aborting suspend.\n");
551 if (state.event == PM_EVENT_PRETHAW)
555 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
558 error = i915_drm_freeze(dev);
562 if (state.event == PM_EVENT_SUSPEND) {
563 /* Shut down the device */
564 pci_disable_device(dev->pdev);
565 pci_set_power_state(dev->pdev, PCI_D3hot);
571 void intel_console_resume(struct work_struct *work)
573 struct drm_i915_private *dev_priv =
574 container_of(work, struct drm_i915_private,
575 console_resume_work);
576 struct drm_device *dev = dev_priv->dev;
579 intel_fbdev_set_suspend(dev, 0);
583 static void intel_resume_hotplug(struct drm_device *dev)
585 struct drm_mode_config *mode_config = &dev->mode_config;
586 struct intel_encoder *encoder;
588 mutex_lock(&mode_config->mutex);
589 DRM_DEBUG_KMS("running encoder hotplug functions\n");
591 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
592 if (encoder->hot_plug)
593 encoder->hot_plug(encoder);
595 mutex_unlock(&mode_config->mutex);
597 /* Just fire off a uevent and let userspace tell us what to do */
598 drm_helper_hpd_irq_event(dev);
601 static int __i915_drm_thaw(struct drm_device *dev)
603 struct drm_i915_private *dev_priv = dev->dev_private;
606 i915_restore_state(dev);
607 intel_opregion_setup(dev);
609 /* KMS EnterVT equivalent */
610 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
611 intel_init_pch_refclk(dev);
613 mutex_lock(&dev->struct_mutex);
614 dev_priv->mm.suspended = 0;
616 error = i915_gem_init_hw(dev);
617 mutex_unlock(&dev->struct_mutex);
619 /* We need working interrupts for modeset enabling ... */
620 drm_irq_install(dev);
622 intel_modeset_init_hw(dev);
624 drm_modeset_lock_all(dev);
625 intel_modeset_setup_hw_state(dev, true);
626 drm_modeset_unlock_all(dev);
629 * ... but also need to make sure that hotplug processing
630 * doesn't cause havoc. Like in the driver load code we don't
631 * bother with the tiny race here where we might loose hotplug
635 dev_priv->enable_hotplug_processing = true;
636 /* Config may have changed between suspend and resume */
637 intel_resume_hotplug(dev);
640 intel_opregion_init(dev);
643 * The console lock can be pretty contented on resume due
644 * to all the printk activity. Try to keep it out of the hot
645 * path of resume if possible.
647 if (console_trylock()) {
648 intel_fbdev_set_suspend(dev, 0);
651 schedule_work(&dev_priv->console_resume_work);
654 mutex_lock(&dev_priv->modeset_restore_lock);
655 dev_priv->modeset_restore = MODESET_DONE;
656 mutex_unlock(&dev_priv->modeset_restore_lock);
660 static int i915_drm_thaw(struct drm_device *dev)
666 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
667 mutex_lock(&dev->struct_mutex);
668 i915_gem_restore_gtt_mappings(dev);
669 mutex_unlock(&dev->struct_mutex);
672 __i915_drm_thaw(dev);
677 int i915_resume(struct drm_device *dev)
679 struct drm_i915_private *dev_priv = dev->dev_private;
682 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
685 if (pci_enable_device(dev->pdev))
688 pci_set_master(dev->pdev);
693 * Platforms with opregion should have sane BIOS, older ones (gen3 and
694 * earlier) need this since the BIOS might clear all our scratch PTEs.
696 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
697 !dev_priv->opregion.header) {
698 mutex_lock(&dev->struct_mutex);
699 i915_gem_restore_gtt_mappings(dev);
700 mutex_unlock(&dev->struct_mutex);
703 ret = __i915_drm_thaw(dev);
707 drm_kms_helper_poll_enable(dev);
711 static int i8xx_do_reset(struct drm_device *dev)
713 struct drm_i915_private *dev_priv = dev->dev_private;
718 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
719 POSTING_READ(D_STATE);
721 if (IS_I830(dev) || IS_845G(dev)) {
722 I915_WRITE(DEBUG_RESET_I830,
723 DEBUG_RESET_DISPLAY |
726 POSTING_READ(DEBUG_RESET_I830);
729 I915_WRITE(DEBUG_RESET_I830, 0);
730 POSTING_READ(DEBUG_RESET_I830);
735 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
736 POSTING_READ(D_STATE);
741 static int i965_reset_complete(struct drm_device *dev)
744 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
745 return (gdrst & GRDOM_RESET_ENABLE) == 0;
748 static int i965_do_reset(struct drm_device *dev)
754 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
755 * well as the reset bit (GR/bit 0). Setting the GR bit
756 * triggers the reset; when done, the hardware will clear it.
758 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
759 pci_write_config_byte(dev->pdev, I965_GDRST,
760 gdrst | GRDOM_RENDER |
762 ret = wait_for(i965_reset_complete(dev), 500);
766 /* We can't reset render&media without also resetting display ... */
767 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
768 pci_write_config_byte(dev->pdev, I965_GDRST,
769 gdrst | GRDOM_MEDIA |
772 return wait_for(i965_reset_complete(dev), 500);
775 static int ironlake_do_reset(struct drm_device *dev)
777 struct drm_i915_private *dev_priv = dev->dev_private;
781 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
782 gdrst &= ~GRDOM_MASK;
783 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
784 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
785 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
789 /* We can't reset render&media without also resetting display ... */
790 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
791 gdrst &= ~GRDOM_MASK;
792 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
793 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
794 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
797 static int gen6_do_reset(struct drm_device *dev)
799 struct drm_i915_private *dev_priv = dev->dev_private;
801 unsigned long irqflags;
803 /* Hold gt_lock across reset to prevent any register access
804 * with forcewake not set correctly
806 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
810 /* GEN6_GDRST is not in the gt power well, no need to check
811 * for fifo space for the write or forcewake the chip for
814 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
816 /* Spin waiting for the device to ack the reset request */
817 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
819 /* If reset with a user forcewake, try to restore, otherwise turn it off */
820 if (dev_priv->forcewake_count)
821 dev_priv->gt.force_wake_get(dev_priv);
823 dev_priv->gt.force_wake_put(dev_priv);
825 /* Restore fifo count */
826 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
828 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
832 int intel_gpu_reset(struct drm_device *dev)
834 struct drm_i915_private *dev_priv = dev->dev_private;
837 switch (INTEL_INFO(dev)->gen) {
840 ret = gen6_do_reset(dev);
843 ret = ironlake_do_reset(dev);
846 ret = i965_do_reset(dev);
849 ret = i8xx_do_reset(dev);
853 /* Also reset the gpu hangman. */
854 if (dev_priv->gpu_error.stop_rings) {
855 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
856 dev_priv->gpu_error.stop_rings = 0;
857 if (ret == -ENODEV) {
858 DRM_ERROR("Reset not implemented, but ignoring "
859 "error for simulated gpu hangs\n");
868 * i915_reset - reset chip after a hang
869 * @dev: drm device to reset
871 * Reset the chip. Useful if a hang is detected. Returns zero on successful
872 * reset or otherwise an error code.
874 * Procedure is fairly simple:
875 * - reset the chip using the reset reg
876 * - re-init context state
877 * - re-init hardware status page
878 * - re-init ring buffer
879 * - re-init interrupt state
882 int i915_reset(struct drm_device *dev)
884 drm_i915_private_t *dev_priv = dev->dev_private;
890 mutex_lock(&dev->struct_mutex);
895 if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
896 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
898 ret = intel_gpu_reset(dev);
900 dev_priv->gpu_error.last_reset = get_seconds();
902 DRM_ERROR("Failed to reset chip.\n");
903 mutex_unlock(&dev->struct_mutex);
907 /* Ok, now get things going again... */
910 * Everything depends on having the GTT running, so we need to start
911 * there. Fortunately we don't need to do this unless we reset the
912 * chip at a PCI level.
914 * Next we need to restore the context, but we don't use those
917 * Ring buffer needs to be re-initialized in the KMS case, or if X
918 * was running at the time of the reset (i.e. we weren't VT
921 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
922 !dev_priv->mm.suspended) {
923 struct intel_ring_buffer *ring;
926 dev_priv->mm.suspended = 0;
928 i915_gem_init_swizzling(dev);
930 for_each_ring(ring, dev_priv, i)
933 i915_gem_context_init(dev);
934 if (dev_priv->mm.aliasing_ppgtt) {
935 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
937 i915_gem_cleanup_aliasing_ppgtt(dev);
941 * It would make sense to re-init all the other hw state, at
942 * least the rps/rc6/emon init done within modeset_init_hw. For
943 * some unknown reason, this blows up my ilk, so don't.
946 mutex_unlock(&dev->struct_mutex);
948 drm_irq_uninstall(dev);
949 drm_irq_install(dev);
952 mutex_unlock(&dev->struct_mutex);
958 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
960 struct intel_device_info *intel_info =
961 (struct intel_device_info *) ent->driver_data;
963 if (intel_info->is_valleyview)
964 if(!i915_preliminary_hw_support) {
965 DRM_ERROR("Preliminary hardware support disabled\n");
969 /* Only bind to function 0 of the device. Early generations
970 * used function 1 as a placeholder for multi-head. This causes
971 * us confusion instead, especially on the systems where both
972 * functions have the same PCI-ID!
974 if (PCI_FUNC(pdev->devfn))
977 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
978 * implementation for gen3 (and only gen3) that used legacy drm maps
979 * (gasp!) to share buffers between X and the client. Hence we need to
980 * keep around the fake agp stuff for gen3, even when kms is enabled. */
981 if (intel_info->gen != 3) {
982 driver.driver_features &=
983 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
984 } else if (!intel_agp_enabled) {
985 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
989 return drm_get_pci_dev(pdev, ent, &driver);
993 i915_pci_remove(struct pci_dev *pdev)
995 struct drm_device *dev = pci_get_drvdata(pdev);
1000 static int i915_pm_suspend(struct device *dev)
1002 struct pci_dev *pdev = to_pci_dev(dev);
1003 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1006 if (!drm_dev || !drm_dev->dev_private) {
1007 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1011 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1014 error = i915_drm_freeze(drm_dev);
1018 pci_disable_device(pdev);
1019 pci_set_power_state(pdev, PCI_D3hot);
1024 static int i915_pm_resume(struct device *dev)
1026 struct pci_dev *pdev = to_pci_dev(dev);
1027 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1029 return i915_resume(drm_dev);
1032 static int i915_pm_freeze(struct device *dev)
1034 struct pci_dev *pdev = to_pci_dev(dev);
1035 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1037 if (!drm_dev || !drm_dev->dev_private) {
1038 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1042 return i915_drm_freeze(drm_dev);
1045 static int i915_pm_thaw(struct device *dev)
1047 struct pci_dev *pdev = to_pci_dev(dev);
1048 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1050 return i915_drm_thaw(drm_dev);
1053 static int i915_pm_poweroff(struct device *dev)
1055 struct pci_dev *pdev = to_pci_dev(dev);
1056 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1058 return i915_drm_freeze(drm_dev);
1061 static const struct dev_pm_ops i915_pm_ops = {
1062 .suspend = i915_pm_suspend,
1063 .resume = i915_pm_resume,
1064 .freeze = i915_pm_freeze,
1065 .thaw = i915_pm_thaw,
1066 .poweroff = i915_pm_poweroff,
1067 .restore = i915_pm_resume,
1070 static const struct vm_operations_struct i915_gem_vm_ops = {
1071 .fault = i915_gem_fault,
1072 .open = drm_gem_vm_open,
1073 .close = drm_gem_vm_close,
1076 static const struct file_operations i915_driver_fops = {
1077 .owner = THIS_MODULE,
1079 .release = drm_release,
1080 .unlocked_ioctl = drm_ioctl,
1081 .mmap = drm_gem_mmap,
1083 .fasync = drm_fasync,
1085 #ifdef CONFIG_COMPAT
1086 .compat_ioctl = i915_compat_ioctl,
1088 .llseek = noop_llseek,
1091 static struct drm_driver driver = {
1092 /* Don't use MTRRs here; the Xserver or userspace app should
1093 * deal with them for Intel hardware.
1096 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1097 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1098 .load = i915_driver_load,
1099 .unload = i915_driver_unload,
1100 .open = i915_driver_open,
1101 .lastclose = i915_driver_lastclose,
1102 .preclose = i915_driver_preclose,
1103 .postclose = i915_driver_postclose,
1105 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1106 .suspend = i915_suspend,
1107 .resume = i915_resume,
1109 .device_is_agp = i915_driver_device_is_agp,
1110 .master_create = i915_master_create,
1111 .master_destroy = i915_master_destroy,
1112 #if defined(CONFIG_DEBUG_FS)
1113 .debugfs_init = i915_debugfs_init,
1114 .debugfs_cleanup = i915_debugfs_cleanup,
1116 .gem_init_object = i915_gem_init_object,
1117 .gem_free_object = i915_gem_free_object,
1118 .gem_vm_ops = &i915_gem_vm_ops,
1120 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1121 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1122 .gem_prime_export = i915_gem_prime_export,
1123 .gem_prime_import = i915_gem_prime_import,
1125 .dumb_create = i915_gem_dumb_create,
1126 .dumb_map_offset = i915_gem_mmap_gtt,
1127 .dumb_destroy = i915_gem_dumb_destroy,
1128 .ioctls = i915_ioctls,
1129 .fops = &i915_driver_fops,
1130 .name = DRIVER_NAME,
1131 .desc = DRIVER_DESC,
1132 .date = DRIVER_DATE,
1133 .major = DRIVER_MAJOR,
1134 .minor = DRIVER_MINOR,
1135 .patchlevel = DRIVER_PATCHLEVEL,
1138 static struct pci_driver i915_pci_driver = {
1139 .name = DRIVER_NAME,
1140 .id_table = pciidlist,
1141 .probe = i915_pci_probe,
1142 .remove = i915_pci_remove,
1143 .driver.pm = &i915_pm_ops,
1146 static int __init i915_init(void)
1148 driver.num_ioctls = i915_max_ioctl;
1151 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1152 * explicitly disabled with the module pararmeter.
1154 * Otherwise, just follow the parameter (defaulting to off).
1156 * Allow optional vga_text_mode_force boot option to override
1157 * the default behavior.
1159 #if defined(CONFIG_DRM_I915_KMS)
1160 if (i915_modeset != 0)
1161 driver.driver_features |= DRIVER_MODESET;
1163 if (i915_modeset == 1)
1164 driver.driver_features |= DRIVER_MODESET;
1166 #ifdef CONFIG_VGA_CONSOLE
1167 if (vgacon_text_force() && i915_modeset == -1)
1168 driver.driver_features &= ~DRIVER_MODESET;
1171 if (!(driver.driver_features & DRIVER_MODESET))
1172 driver.get_vblank_timestamp = NULL;
1174 return drm_pci_init(&driver, &i915_pci_driver);
1177 static void __exit i915_exit(void)
1179 drm_pci_exit(&driver, &i915_pci_driver);
1182 module_init(i915_init);
1183 module_exit(i915_exit);
1185 MODULE_AUTHOR(DRIVER_AUTHOR);
1186 MODULE_DESCRIPTION(DRIVER_DESC);
1187 MODULE_LICENSE("GPL and additional rights");
1189 /* We give fast paths for the really cool registers */
1190 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1191 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1192 ((reg) < 0x40000) && \
1193 ((reg) != FORCEWAKE))
1195 ilk_dummy_write(struct drm_i915_private *dev_priv)
1197 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1198 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1199 * harmless to write 0 into. */
1200 I915_WRITE_NOTRACE(MI_MODE, 0);
1204 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1206 if (IS_HASWELL(dev_priv->dev) &&
1207 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1208 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1210 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1215 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1217 if (IS_HASWELL(dev_priv->dev) &&
1218 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1219 DRM_ERROR("Unclaimed write to %x\n", reg);
1220 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1224 #define __i915_read(x, y) \
1225 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1227 if (IS_GEN5(dev_priv->dev)) \
1228 ilk_dummy_write(dev_priv); \
1229 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1230 unsigned long irqflags; \
1231 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1232 if (dev_priv->forcewake_count == 0) \
1233 dev_priv->gt.force_wake_get(dev_priv); \
1234 val = read##y(dev_priv->regs + reg); \
1235 if (dev_priv->forcewake_count == 0) \
1236 dev_priv->gt.force_wake_put(dev_priv); \
1237 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1239 val = read##y(dev_priv->regs + reg); \
1241 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1251 #define __i915_write(x, y) \
1252 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1253 u32 __fifo_ret = 0; \
1254 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1255 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1256 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1258 if (IS_GEN5(dev_priv->dev)) \
1259 ilk_dummy_write(dev_priv); \
1260 hsw_unclaimed_reg_clear(dev_priv, reg); \
1261 write##y(val, dev_priv->regs + reg); \
1262 if (unlikely(__fifo_ret)) { \
1263 gen6_gt_check_fifodbg(dev_priv); \
1265 hsw_unclaimed_reg_check(dev_priv, reg); \
1273 static const struct register_whitelist {
1276 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1278 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1281 int i915_reg_read_ioctl(struct drm_device *dev,
1282 void *data, struct drm_file *file)
1284 struct drm_i915_private *dev_priv = dev->dev_private;
1285 struct drm_i915_reg_read *reg = data;
1286 struct register_whitelist const *entry = whitelist;
1289 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1290 if (entry->offset == reg->offset &&
1291 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1295 if (i == ARRAY_SIZE(whitelist))
1298 switch (entry->size) {
1300 reg->val = I915_READ64(reg->offset);
1303 reg->val = I915_READ(reg->offset);
1306 reg->val = I915_READ16(reg->offset);
1309 reg->val = I915_READ8(reg->offset);