1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vga_switcheroo.h>
41 #include <acpi/video.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_irq.h>
46 #include <drm/drm_probe_helper.h>
47 #include <drm/i915_drm.h>
49 #include "display/intel_acpi.h"
50 #include "display/intel_audio.h"
51 #include "display/intel_bw.h"
52 #include "display/intel_cdclk.h"
53 #include "display/intel_csr.h"
54 #include "display/intel_display_debugfs.h"
55 #include "display/intel_display_types.h"
56 #include "display/intel_dp.h"
57 #include "display/intel_fbdev.h"
58 #include "display/intel_hotplug.h"
59 #include "display/intel_overlay.h"
60 #include "display/intel_pipe_crc.h"
61 #include "display/intel_psr.h"
62 #include "display/intel_sprite.h"
63 #include "display/intel_vga.h"
65 #include "gem/i915_gem_context.h"
66 #include "gem/i915_gem_ioctls.h"
67 #include "gem/i915_gem_mman.h"
68 #include "gt/intel_gt.h"
69 #include "gt/intel_gt_pm.h"
70 #include "gt/intel_rc6.h"
72 #include "i915_debugfs.h"
75 #include "i915_memcpy.h"
76 #include "i915_perf.h"
77 #include "i915_query.h"
78 #include "i915_suspend.h"
79 #include "i915_switcheroo.h"
80 #include "i915_sysfs.h"
81 #include "i915_trace.h"
82 #include "i915_vgpu.h"
83 #include "intel_memory_region.h"
85 #include "vlv_suspend.h"
87 static struct drm_driver driver;
89 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
91 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
93 dev_priv->bridge_dev =
94 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
95 if (!dev_priv->bridge_dev) {
96 drm_err(&dev_priv->drm, "bridge device not found\n");
102 /* Allocate space for the MCH regs if needed, return nonzero on error */
104 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
106 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
107 u32 temp_lo, temp_hi = 0;
111 if (INTEL_GEN(dev_priv) >= 4)
112 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
113 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
114 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
116 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
119 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
123 /* Get some space for it */
124 dev_priv->mch_res.name = "i915 MCHBAR";
125 dev_priv->mch_res.flags = IORESOURCE_MEM;
126 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
128 MCHBAR_SIZE, MCHBAR_SIZE,
130 0, pcibios_align_resource,
131 dev_priv->bridge_dev);
133 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
134 dev_priv->mch_res.start = 0;
138 if (INTEL_GEN(dev_priv) >= 4)
139 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
140 upper_32_bits(dev_priv->mch_res.start));
142 pci_write_config_dword(dev_priv->bridge_dev, reg,
143 lower_32_bits(dev_priv->mch_res.start));
147 /* Setup MCHBAR if possible, return true if we should disable it again */
149 intel_setup_mchbar(struct drm_i915_private *dev_priv)
151 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
155 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
158 dev_priv->mchbar_need_disable = false;
160 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
161 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
162 enabled = !!(temp & DEVEN_MCHBAR_EN);
164 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
168 /* If it's already enabled, don't have to do anything */
172 if (intel_alloc_mchbar_resource(dev_priv))
175 dev_priv->mchbar_need_disable = true;
177 /* Space is allocated or reserved, so enable it. */
178 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
179 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
180 temp | DEVEN_MCHBAR_EN);
182 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
183 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
188 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
190 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
192 if (dev_priv->mchbar_need_disable) {
193 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
196 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
198 deven_val &= ~DEVEN_MCHBAR_EN;
199 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
204 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
207 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
212 if (dev_priv->mch_res.start)
213 release_resource(&dev_priv->mch_res);
216 /* part #1: call before irq install */
217 static int i915_driver_modeset_probe_noirq(struct drm_i915_private *i915)
221 if (i915_inject_probe_failure(i915))
224 if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
225 ret = drm_vblank_init(&i915->drm,
226 INTEL_NUM_PIPES(i915));
231 intel_bios_init(i915);
233 ret = intel_vga_register(i915);
237 intel_power_domains_init_hw(i915, false);
239 intel_csr_ucode_init(i915);
247 /* part #2: call after irq install */
248 static int i915_driver_modeset_probe(struct drm_i915_private *i915)
252 /* Important: The output setup functions called by modeset_init need
253 * working irqs for e.g. gmbus and dp aux transfers. */
254 ret = intel_modeset_init(i915);
258 ret = i915_gem_init(i915);
260 goto cleanup_modeset;
262 intel_overlay_setup(i915);
264 if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915))
267 ret = intel_fbdev_init(&i915->drm);
271 /* Only enable hotplug handling once the fbdev is fully set up. */
272 intel_hpd_init(i915);
274 intel_init_ipc(i915);
276 intel_psr_set_force_mode_changed(i915->psr.dp);
281 i915_gem_suspend(i915);
282 i915_gem_driver_remove(i915);
283 i915_gem_driver_release(i915);
286 intel_modeset_driver_remove(i915);
287 intel_irq_uninstall(i915);
288 intel_modeset_driver_remove_noirq(i915);
293 /* part #1: call before irq uninstall */
294 static void i915_driver_modeset_remove(struct drm_i915_private *i915)
296 intel_modeset_driver_remove(i915);
299 /* part #2: call after irq uninstall */
300 static void i915_driver_modeset_remove_noirq(struct drm_i915_private *i915)
302 intel_modeset_driver_remove_noirq(i915);
304 intel_bios_driver_remove(i915);
306 intel_vga_unregister(i915);
308 intel_csr_ucode_fini(i915);
311 static void intel_init_dpio(struct drm_i915_private *dev_priv)
314 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
315 * CHV x1 PHY (DP/HDMI D)
316 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
318 if (IS_CHERRYVIEW(dev_priv)) {
319 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
320 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
321 } else if (IS_VALLEYVIEW(dev_priv)) {
322 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
326 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
329 * The i915 workqueue is primarily used for batched retirement of
330 * requests (and thus managing bo) once the task has been completed
331 * by the GPU. i915_retire_requests() is called directly when we
332 * need high-priority retirement, such as waiting for an explicit
335 * It is also used for periodic low-priority events, such as
336 * idle-timers and recording error state.
338 * All tasks on the workqueue are expected to acquire the dev mutex
339 * so there is no point in running more than one instance of the
340 * workqueue at any time. Use an ordered one.
342 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
343 if (dev_priv->wq == NULL)
346 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
347 if (dev_priv->hotplug.dp_wq == NULL)
353 destroy_workqueue(dev_priv->wq);
355 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
360 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
362 destroy_workqueue(dev_priv->hotplug.dp_wq);
363 destroy_workqueue(dev_priv->wq);
367 * We don't keep the workarounds for pre-production hardware, so we expect our
368 * driver to fail on these machines in one way or another. A little warning on
369 * dmesg may help both the user and the bug triagers.
371 * Our policy for removing pre-production workarounds is to keep the
372 * current gen workarounds as a guide to the bring-up of the next gen
373 * (workarounds have a habit of persisting!). Anything older than that
374 * should be removed along with the complications they introduce.
376 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
380 pre |= IS_HSW_EARLY_SDV(dev_priv);
381 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
382 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
383 pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
386 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
387 "It may not be fully functional.\n");
388 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
392 static void sanitize_gpu(struct drm_i915_private *i915)
394 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
395 __intel_gt_reset(&i915->gt, ALL_ENGINES);
399 * i915_driver_early_probe - setup state not requiring device access
400 * @dev_priv: device private
402 * Initialize everything that is a "SW-only" state, that is state not
403 * requiring accessing the device or exposing the driver via kernel internal
404 * or userspace interfaces. Example steps belonging here: lock initialization,
405 * system memory allocation, setting up device specific attributes and
406 * function hooks not requiring accessing the device.
408 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
412 if (i915_inject_probe_failure(dev_priv))
415 intel_device_info_subplatform_init(dev_priv);
417 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
418 intel_uncore_init_early(&dev_priv->uncore, dev_priv);
420 spin_lock_init(&dev_priv->irq_lock);
421 spin_lock_init(&dev_priv->gpu_error.lock);
422 mutex_init(&dev_priv->backlight_lock);
424 mutex_init(&dev_priv->sb_lock);
425 pm_qos_add_request(&dev_priv->sb_qos,
426 PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
428 mutex_init(&dev_priv->av_mutex);
429 mutex_init(&dev_priv->wm.wm_mutex);
430 mutex_init(&dev_priv->pps_mutex);
431 mutex_init(&dev_priv->hdcp_comp_mutex);
433 i915_memcpy_init_early(dev_priv);
434 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
436 ret = i915_workqueues_init(dev_priv);
440 ret = vlv_suspend_init(dev_priv);
444 intel_wopcm_init_early(&dev_priv->wopcm);
446 intel_gt_init_early(&dev_priv->gt, dev_priv);
448 i915_gem_init_early(dev_priv);
450 /* This must be called before any calls to HAS_PCH_* */
451 intel_detect_pch(dev_priv);
453 intel_pm_setup(dev_priv);
454 intel_init_dpio(dev_priv);
455 ret = intel_power_domains_init(dev_priv);
458 intel_irq_init(dev_priv);
459 intel_init_display_hooks(dev_priv);
460 intel_init_clock_gating_hooks(dev_priv);
461 intel_init_audio_hooks(dev_priv);
462 intel_display_crc_init(dev_priv);
464 intel_detect_preproduction_hw(dev_priv);
469 i915_gem_cleanup_early(dev_priv);
470 intel_gt_driver_late_release(&dev_priv->gt);
471 vlv_suspend_cleanup(dev_priv);
473 i915_workqueues_cleanup(dev_priv);
478 * i915_driver_late_release - cleanup the setup done in
479 * i915_driver_early_probe()
480 * @dev_priv: device private
482 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
484 intel_irq_fini(dev_priv);
485 intel_power_domains_cleanup(dev_priv);
486 i915_gem_cleanup_early(dev_priv);
487 intel_gt_driver_late_release(&dev_priv->gt);
488 vlv_suspend_cleanup(dev_priv);
489 i915_workqueues_cleanup(dev_priv);
491 pm_qos_remove_request(&dev_priv->sb_qos);
492 mutex_destroy(&dev_priv->sb_lock);
496 * i915_driver_mmio_probe - setup device MMIO
497 * @dev_priv: device private
499 * Setup minimal device state necessary for MMIO accesses later in the
500 * initialization sequence. The setup here should avoid any other device-wide
501 * side effects or exposing the driver via kernel internal or user space
504 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
508 if (i915_inject_probe_failure(dev_priv))
511 if (i915_get_bridge_dev(dev_priv))
514 ret = intel_uncore_init_mmio(&dev_priv->uncore);
518 /* Try to make sure MCHBAR is enabled before poking at it */
519 intel_setup_mchbar(dev_priv);
521 intel_device_info_init_mmio(dev_priv);
523 intel_uncore_prune_mmio_domains(&dev_priv->uncore);
525 intel_uc_init_mmio(&dev_priv->gt.uc);
527 ret = intel_engines_init_mmio(&dev_priv->gt);
531 /* As early as possible, scrub existing GPU state before clobbering */
532 sanitize_gpu(dev_priv);
537 intel_teardown_mchbar(dev_priv);
538 intel_uncore_fini_mmio(&dev_priv->uncore);
540 pci_dev_put(dev_priv->bridge_dev);
546 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
547 * @dev_priv: device private
549 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
551 intel_teardown_mchbar(dev_priv);
552 intel_uncore_fini_mmio(&dev_priv->uncore);
553 pci_dev_put(dev_priv->bridge_dev);
556 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
558 intel_gvt_sanitize_options(dev_priv);
561 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
563 static const char *intel_dram_type_str(enum intel_dram_type type)
565 static const char * const str[] = {
566 DRAM_TYPE_STR(UNKNOWN),
569 DRAM_TYPE_STR(LPDDR3),
570 DRAM_TYPE_STR(LPDDR4),
573 if (type >= ARRAY_SIZE(str))
574 type = INTEL_DRAM_UNKNOWN;
581 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
583 return dimm->ranks * 64 / (dimm->width ?: 1);
586 /* Returns total GB for the whole DIMM */
587 static int skl_get_dimm_size(u16 val)
589 return val & SKL_DRAM_SIZE_MASK;
592 static int skl_get_dimm_width(u16 val)
594 if (skl_get_dimm_size(val) == 0)
597 switch (val & SKL_DRAM_WIDTH_MASK) {
598 case SKL_DRAM_WIDTH_X8:
599 case SKL_DRAM_WIDTH_X16:
600 case SKL_DRAM_WIDTH_X32:
601 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
609 static int skl_get_dimm_ranks(u16 val)
611 if (skl_get_dimm_size(val) == 0)
614 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
619 /* Returns total GB for the whole DIMM */
620 static int cnl_get_dimm_size(u16 val)
622 return (val & CNL_DRAM_SIZE_MASK) / 2;
625 static int cnl_get_dimm_width(u16 val)
627 if (cnl_get_dimm_size(val) == 0)
630 switch (val & CNL_DRAM_WIDTH_MASK) {
631 case CNL_DRAM_WIDTH_X8:
632 case CNL_DRAM_WIDTH_X16:
633 case CNL_DRAM_WIDTH_X32:
634 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
642 static int cnl_get_dimm_ranks(u16 val)
644 if (cnl_get_dimm_size(val) == 0)
647 val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
653 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
655 /* Convert total GB to Gb per DRAM device */
656 return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
660 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
661 struct dram_dimm_info *dimm,
662 int channel, char dimm_name, u16 val)
664 if (INTEL_GEN(dev_priv) >= 10) {
665 dimm->size = cnl_get_dimm_size(val);
666 dimm->width = cnl_get_dimm_width(val);
667 dimm->ranks = cnl_get_dimm_ranks(val);
669 dimm->size = skl_get_dimm_size(val);
670 dimm->width = skl_get_dimm_width(val);
671 dimm->ranks = skl_get_dimm_ranks(val);
674 drm_dbg_kms(&dev_priv->drm,
675 "CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
676 channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
677 yesno(skl_is_16gb_dimm(dimm)));
681 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
682 struct dram_channel_info *ch,
683 int channel, u32 val)
685 skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
686 channel, 'L', val & 0xffff);
687 skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
688 channel, 'S', val >> 16);
690 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
691 drm_dbg_kms(&dev_priv->drm, "CH%u not populated\n", channel);
695 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
697 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
703 skl_is_16gb_dimm(&ch->dimm_l) ||
704 skl_is_16gb_dimm(&ch->dimm_s);
706 drm_dbg_kms(&dev_priv->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
707 channel, ch->ranks, yesno(ch->is_16gb_dimm));
713 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
714 const struct dram_channel_info *ch1)
716 return !memcmp(ch0, ch1, sizeof(*ch0)) &&
717 (ch0->dimm_s.size == 0 ||
718 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
722 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
724 struct dram_info *dram_info = &dev_priv->dram_info;
725 struct dram_channel_info ch0 = {}, ch1 = {};
729 val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
730 ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
732 dram_info->num_channels++;
734 val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
735 ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
737 dram_info->num_channels++;
739 if (dram_info->num_channels == 0) {
740 drm_info(&dev_priv->drm,
741 "Number of memory channels is zero\n");
746 * If any of the channel is single rank channel, worst case output
747 * will be same as if single rank memory, so consider single rank
750 if (ch0.ranks == 1 || ch1.ranks == 1)
751 dram_info->ranks = 1;
753 dram_info->ranks = max(ch0.ranks, ch1.ranks);
755 if (dram_info->ranks == 0) {
756 drm_info(&dev_priv->drm,
757 "couldn't get memory rank information\n");
761 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
763 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
765 drm_dbg_kms(&dev_priv->drm, "Memory configuration is symmetric? %s\n",
766 yesno(dram_info->symmetric_memory));
770 static enum intel_dram_type
771 skl_get_dram_type(struct drm_i915_private *dev_priv)
775 val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
777 switch (val & SKL_DRAM_DDR_TYPE_MASK) {
778 case SKL_DRAM_DDR_TYPE_DDR3:
779 return INTEL_DRAM_DDR3;
780 case SKL_DRAM_DDR_TYPE_DDR4:
781 return INTEL_DRAM_DDR4;
782 case SKL_DRAM_DDR_TYPE_LPDDR3:
783 return INTEL_DRAM_LPDDR3;
784 case SKL_DRAM_DDR_TYPE_LPDDR4:
785 return INTEL_DRAM_LPDDR4;
788 return INTEL_DRAM_UNKNOWN;
793 skl_get_dram_info(struct drm_i915_private *dev_priv)
795 struct dram_info *dram_info = &dev_priv->dram_info;
796 u32 mem_freq_khz, val;
799 dram_info->type = skl_get_dram_type(dev_priv);
800 drm_dbg_kms(&dev_priv->drm, "DRAM type: %s\n",
801 intel_dram_type_str(dram_info->type));
803 ret = skl_dram_get_channels_info(dev_priv);
807 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
808 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
809 SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
811 dram_info->bandwidth_kbps = dram_info->num_channels *
814 if (dram_info->bandwidth_kbps == 0) {
815 drm_info(&dev_priv->drm,
816 "Couldn't get system memory bandwidth\n");
820 dram_info->valid = true;
824 /* Returns Gb per DRAM device */
825 static int bxt_get_dimm_size(u32 val)
827 switch (val & BXT_DRAM_SIZE_MASK) {
828 case BXT_DRAM_SIZE_4GBIT:
830 case BXT_DRAM_SIZE_6GBIT:
832 case BXT_DRAM_SIZE_8GBIT:
834 case BXT_DRAM_SIZE_12GBIT:
836 case BXT_DRAM_SIZE_16GBIT:
844 static int bxt_get_dimm_width(u32 val)
846 if (!bxt_get_dimm_size(val))
849 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
854 static int bxt_get_dimm_ranks(u32 val)
856 if (!bxt_get_dimm_size(val))
859 switch (val & BXT_DRAM_RANK_MASK) {
860 case BXT_DRAM_RANK_SINGLE:
862 case BXT_DRAM_RANK_DUAL:
870 static enum intel_dram_type bxt_get_dimm_type(u32 val)
872 if (!bxt_get_dimm_size(val))
873 return INTEL_DRAM_UNKNOWN;
875 switch (val & BXT_DRAM_TYPE_MASK) {
876 case BXT_DRAM_TYPE_DDR3:
877 return INTEL_DRAM_DDR3;
878 case BXT_DRAM_TYPE_LPDDR3:
879 return INTEL_DRAM_LPDDR3;
880 case BXT_DRAM_TYPE_DDR4:
881 return INTEL_DRAM_DDR4;
882 case BXT_DRAM_TYPE_LPDDR4:
883 return INTEL_DRAM_LPDDR4;
886 return INTEL_DRAM_UNKNOWN;
890 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
893 dimm->width = bxt_get_dimm_width(val);
894 dimm->ranks = bxt_get_dimm_ranks(val);
897 * Size in register is Gb per DRAM device. Convert to total
898 * GB to match the way we report this for non-LP platforms.
900 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
904 bxt_get_dram_info(struct drm_i915_private *dev_priv)
906 struct dram_info *dram_info = &dev_priv->dram_info;
908 u32 mem_freq_khz, val;
909 u8 num_active_channels;
912 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
913 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
914 BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
916 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
917 num_active_channels = hweight32(dram_channels);
919 /* Each active bit represents 4-byte channel */
920 dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
922 if (dram_info->bandwidth_kbps == 0) {
923 drm_info(&dev_priv->drm,
924 "Couldn't get system memory bandwidth\n");
929 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
931 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
932 struct dram_dimm_info dimm;
933 enum intel_dram_type type;
935 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
936 if (val == 0xFFFFFFFF)
939 dram_info->num_channels++;
941 bxt_get_dimm_info(&dimm, val);
942 type = bxt_get_dimm_type(val);
944 drm_WARN_ON(&dev_priv->drm, type != INTEL_DRAM_UNKNOWN &&
945 dram_info->type != INTEL_DRAM_UNKNOWN &&
946 dram_info->type != type);
948 drm_dbg_kms(&dev_priv->drm,
949 "CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
950 i - BXT_D_CR_DRP0_DUNIT_START,
951 dimm.size, dimm.width, dimm.ranks,
952 intel_dram_type_str(type));
955 * If any of the channel is single rank channel,
956 * worst case output will be same as if single rank
957 * memory, so consider single rank memory.
959 if (dram_info->ranks == 0)
960 dram_info->ranks = dimm.ranks;
961 else if (dimm.ranks == 1)
962 dram_info->ranks = 1;
964 if (type != INTEL_DRAM_UNKNOWN)
965 dram_info->type = type;
968 if (dram_info->type == INTEL_DRAM_UNKNOWN ||
969 dram_info->ranks == 0) {
970 drm_info(&dev_priv->drm, "couldn't get memory information\n");
974 dram_info->valid = true;
979 intel_get_dram_info(struct drm_i915_private *dev_priv)
981 struct dram_info *dram_info = &dev_priv->dram_info;
985 * Assume 16Gb DIMMs are present until proven otherwise.
986 * This is only used for the level 0 watermark latency
987 * w/a which does not apply to bxt/glk.
989 dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
991 if (INTEL_GEN(dev_priv) < 9 || !HAS_DISPLAY(dev_priv))
994 if (IS_GEN9_LP(dev_priv))
995 ret = bxt_get_dram_info(dev_priv);
997 ret = skl_get_dram_info(dev_priv);
1001 drm_dbg_kms(&dev_priv->drm, "DRAM bandwidth: %u kBps, channels: %u\n",
1002 dram_info->bandwidth_kbps,
1003 dram_info->num_channels);
1005 drm_dbg_kms(&dev_priv->drm, "DRAM ranks: %u, 16Gb DIMMs: %s\n",
1006 dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1009 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1011 static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1012 static const u8 sets[4] = { 1, 1, 2, 2 };
1014 return EDRAM_NUM_BANKS(cap) *
1015 ways[EDRAM_WAYS_IDX(cap)] *
1016 sets[EDRAM_SETS_IDX(cap)];
1019 static void edram_detect(struct drm_i915_private *dev_priv)
1023 if (!(IS_HASWELL(dev_priv) ||
1024 IS_BROADWELL(dev_priv) ||
1025 INTEL_GEN(dev_priv) >= 9))
1028 edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1030 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1032 if (!(edram_cap & EDRAM_ENABLED))
1036 * The needed capability bits for size calculation are not there with
1037 * pre gen9 so return 128MB always.
1039 if (INTEL_GEN(dev_priv) < 9)
1040 dev_priv->edram_size_mb = 128;
1042 dev_priv->edram_size_mb =
1043 gen9_edram_size_mb(dev_priv, edram_cap);
1045 dev_info(dev_priv->drm.dev,
1046 "Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1050 * i915_driver_hw_probe - setup state requiring device access
1051 * @dev_priv: device private
1053 * Setup state that requires accessing the device, but doesn't require
1054 * exposing the driver via kernel internal or userspace interfaces.
1056 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
1058 struct pci_dev *pdev = dev_priv->drm.pdev;
1061 if (i915_inject_probe_failure(dev_priv))
1064 intel_device_info_runtime_init(dev_priv);
1066 if (HAS_PPGTT(dev_priv)) {
1067 if (intel_vgpu_active(dev_priv) &&
1068 !intel_vgpu_has_full_ppgtt(dev_priv)) {
1069 i915_report_error(dev_priv,
1070 "incompatible vGPU found, support for isolated ppGTT required\n");
1075 if (HAS_EXECLISTS(dev_priv)) {
1077 * Older GVT emulation depends upon intercepting CSB mmio,
1078 * which we no longer use, preferring to use the HWSP cache
1081 if (intel_vgpu_active(dev_priv) &&
1082 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1083 i915_report_error(dev_priv,
1084 "old vGPU host found, support for HWSP emulation required\n");
1089 intel_sanitize_options(dev_priv);
1091 /* needs to be done before ggtt probe */
1092 edram_detect(dev_priv);
1094 i915_perf_init(dev_priv);
1096 ret = i915_ggtt_probe_hw(dev_priv);
1100 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
1104 ret = i915_ggtt_init_hw(dev_priv);
1108 ret = intel_memory_regions_hw_probe(dev_priv);
1112 intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
1114 ret = i915_ggtt_enable_hw(dev_priv);
1116 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
1117 goto err_mem_regions;
1120 pci_set_master(pdev);
1123 * We don't have a max segment size, so set it to the max so sg's
1124 * debugging layer doesn't complain
1126 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1128 /* overlay on gen2 is broken and can't address above 1G */
1129 if (IS_GEN(dev_priv, 2)) {
1130 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1132 drm_err(&dev_priv->drm, "failed to set DMA mask\n");
1134 goto err_mem_regions;
1138 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1139 * using 32bit addressing, overwriting memory if HWS is located
1142 * The documentation also mentions an issue with undefined
1143 * behaviour if any general state is accessed within a page above 4GB,
1144 * which also needs to be handled carefully.
1146 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1147 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1150 drm_err(&dev_priv->drm, "failed to set DMA mask\n");
1152 goto err_mem_regions;
1156 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1157 PM_QOS_DEFAULT_VALUE);
1159 intel_gt_init_workarounds(dev_priv);
1161 /* On the 945G/GM, the chipset reports the MSI capability on the
1162 * integrated graphics even though the support isn't actually there
1163 * according to the published specs. It doesn't appear to function
1164 * correctly in testing on 945G.
1165 * This may be a side effect of MSI having been made available for PEG
1166 * and the registers being closely associated.
1168 * According to chipset errata, on the 965GM, MSI interrupts may
1169 * be lost or delayed, and was defeatured. MSI interrupts seem to
1170 * get lost on g4x as well, and interrupt delivery seems to stay
1171 * properly dead afterwards. So we'll just disable them for all
1172 * pre-gen5 chipsets.
1174 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1175 * interrupts even when in MSI mode. This results in spurious
1176 * interrupt warnings if the legacy irq no. is shared with another
1177 * device. The kernel then disables that interrupt source and so
1178 * prevents the other device from working properly.
1180 if (INTEL_GEN(dev_priv) >= 5) {
1181 if (pci_enable_msi(pdev) < 0)
1182 drm_dbg(&dev_priv->drm, "can't enable MSI");
1185 ret = intel_gvt_init(dev_priv);
1189 intel_opregion_setup(dev_priv);
1191 * Fill the dram structure to get the system raw bandwidth and
1192 * dram info. This will be used for memory latency calculation.
1194 intel_get_dram_info(dev_priv);
1196 intel_bw_init_hw(dev_priv);
1201 if (pdev->msi_enabled)
1202 pci_disable_msi(pdev);
1203 pm_qos_remove_request(&dev_priv->pm_qos);
1205 intel_memory_regions_driver_release(dev_priv);
1207 i915_ggtt_driver_release(dev_priv);
1209 i915_perf_fini(dev_priv);
1214 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
1215 * @dev_priv: device private
1217 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
1219 struct pci_dev *pdev = dev_priv->drm.pdev;
1221 i915_perf_fini(dev_priv);
1223 if (pdev->msi_enabled)
1224 pci_disable_msi(pdev);
1226 pm_qos_remove_request(&dev_priv->pm_qos);
1230 * i915_driver_register - register the driver with the rest of the system
1231 * @dev_priv: device private
1233 * Perform any steps necessary to make the driver available via kernel
1234 * internal or userspace interfaces.
1236 static void i915_driver_register(struct drm_i915_private *dev_priv)
1238 struct drm_device *dev = &dev_priv->drm;
1240 i915_gem_driver_register(dev_priv);
1241 i915_pmu_register(dev_priv);
1244 * Notify a valid surface after modesetting,
1245 * when running inside a VM.
1247 if (intel_vgpu_active(dev_priv))
1248 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1250 /* Reveal our presence to userspace */
1251 if (drm_dev_register(dev, 0) == 0) {
1252 i915_debugfs_register(dev_priv);
1253 intel_display_debugfs_register(dev_priv);
1254 i915_setup_sysfs(dev_priv);
1256 /* Depends on sysfs having been initialized */
1257 i915_perf_register(dev_priv);
1259 drm_err(&dev_priv->drm,
1260 "Failed to register driver for userspace access!\n");
1262 if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
1263 /* Must be done after probing outputs */
1264 intel_opregion_register(dev_priv);
1265 acpi_video_register();
1268 intel_gt_driver_register(&dev_priv->gt);
1270 intel_audio_init(dev_priv);
1273 * Some ports require correctly set-up hpd registers for detection to
1274 * work properly (leading to ghost connected connector status), e.g. VGA
1275 * on gm45. Hence we can only set up the initial fbdev config after hpd
1276 * irqs are fully enabled. We do it last so that the async config
1277 * cannot run before the connectors are registered.
1279 intel_fbdev_initial_config_async(dev);
1282 * We need to coordinate the hotplugs with the asynchronous fbdev
1283 * configuration, for which we use the fbdev->async_cookie.
1285 if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv))
1286 drm_kms_helper_poll_init(dev);
1288 intel_power_domains_enable(dev_priv);
1289 intel_runtime_pm_enable(&dev_priv->runtime_pm);
1291 intel_register_dsm_handler();
1293 if (i915_switcheroo_register(dev_priv))
1294 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
1298 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1299 * @dev_priv: device private
1301 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1303 i915_switcheroo_unregister(dev_priv);
1305 intel_unregister_dsm_handler();
1307 intel_runtime_pm_disable(&dev_priv->runtime_pm);
1308 intel_power_domains_disable(dev_priv);
1310 intel_fbdev_unregister(dev_priv);
1311 intel_audio_deinit(dev_priv);
1314 * After flushing the fbdev (incl. a late async config which will
1315 * have delayed queuing of a hotplug event), then flush the hotplug
1318 drm_kms_helper_poll_fini(&dev_priv->drm);
1320 intel_gt_driver_unregister(&dev_priv->gt);
1321 acpi_video_unregister();
1322 intel_opregion_unregister(dev_priv);
1324 i915_perf_unregister(dev_priv);
1325 i915_pmu_unregister(dev_priv);
1327 i915_teardown_sysfs(dev_priv);
1328 drm_dev_unplug(&dev_priv->drm);
1330 i915_gem_driver_unregister(dev_priv);
1333 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1335 if (drm_debug_enabled(DRM_UT_DRIVER)) {
1336 struct drm_printer p = drm_debug_printer("i915 device info:");
1338 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1339 INTEL_DEVID(dev_priv),
1340 INTEL_REVID(dev_priv),
1341 intel_platform_name(INTEL_INFO(dev_priv)->platform),
1342 intel_subplatform(RUNTIME_INFO(dev_priv),
1343 INTEL_INFO(dev_priv)->platform),
1344 INTEL_GEN(dev_priv));
1346 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
1347 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
1350 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1351 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
1352 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1353 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
1354 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1355 drm_info(&dev_priv->drm,
1356 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1359 static struct drm_i915_private *
1360 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1362 const struct intel_device_info *match_info =
1363 (struct intel_device_info *)ent->driver_data;
1364 struct intel_device_info *device_info;
1365 struct drm_i915_private *i915;
1368 i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1370 return ERR_PTR(-ENOMEM);
1372 err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1375 return ERR_PTR(err);
1378 i915->drm.dev_private = i915;
1380 i915->drm.pdev = pdev;
1381 pci_set_drvdata(pdev, i915);
1383 /* Setup the write-once "constant" device info */
1384 device_info = mkwrite_device_info(i915);
1385 memcpy(device_info, match_info, sizeof(*device_info));
1386 RUNTIME_INFO(i915)->device_id = pdev->device;
1388 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1393 static void i915_driver_destroy(struct drm_i915_private *i915)
1395 struct pci_dev *pdev = i915->drm.pdev;
1397 drm_dev_fini(&i915->drm);
1400 /* And make sure we never chase our dangling pointer from pci_dev */
1401 pci_set_drvdata(pdev, NULL);
1405 * i915_driver_probe - setup chip and create an initial config
1407 * @ent: matching PCI ID entry
1409 * The driver probe routine has to do several things:
1410 * - drive output discovery via intel_modeset_init()
1411 * - initialize the memory manager
1412 * - allocate initial config memory
1413 * - setup the DRM framebuffer with the allocated memory
1415 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1417 const struct intel_device_info *match_info =
1418 (struct intel_device_info *)ent->driver_data;
1419 struct drm_i915_private *i915;
1422 i915 = i915_driver_create(pdev, ent);
1424 return PTR_ERR(i915);
1426 /* Disable nuclear pageflip by default on pre-ILK */
1427 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1428 i915->drm.driver_features &= ~DRIVER_ATOMIC;
1431 * Check if we support fake LMEM -- for now we only unleash this for
1432 * the live selftests(test-and-exit).
1434 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1435 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
1436 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
1437 i915_modparams.fake_lmem_start) {
1438 mkwrite_device_info(i915)->memory_regions =
1439 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
1440 mkwrite_device_info(i915)->is_dgfx = true;
1441 GEM_BUG_ON(!HAS_LMEM(i915));
1442 GEM_BUG_ON(!IS_DGFX(i915));
1447 ret = pci_enable_device(pdev);
1451 ret = i915_driver_early_probe(i915);
1453 goto out_pci_disable;
1455 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1457 i915_detect_vgpu(i915);
1459 ret = i915_driver_mmio_probe(i915);
1461 goto out_runtime_pm_put;
1463 ret = i915_driver_hw_probe(i915);
1465 goto out_cleanup_mmio;
1467 ret = i915_driver_modeset_probe_noirq(i915);
1469 goto out_cleanup_hw;
1471 ret = intel_irq_install(i915);
1473 goto out_cleanup_modeset;
1475 ret = i915_driver_modeset_probe(i915);
1477 goto out_cleanup_irq;
1479 i915_driver_register(i915);
1481 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1483 i915_welcome_messages(i915);
1488 intel_irq_uninstall(i915);
1489 out_cleanup_modeset:
1492 i915_driver_hw_remove(i915);
1493 intel_memory_regions_driver_release(i915);
1494 i915_ggtt_driver_release(i915);
1496 i915_driver_mmio_release(i915);
1498 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1499 i915_driver_late_release(i915);
1501 pci_disable_device(pdev);
1503 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
1504 i915_driver_destroy(i915);
1508 void i915_driver_remove(struct drm_i915_private *i915)
1510 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1512 i915_driver_unregister(i915);
1514 /* Flush any external code that still may be under the RCU lock */
1517 i915_gem_suspend(i915);
1519 drm_atomic_helper_shutdown(&i915->drm);
1521 intel_gvt_driver_remove(i915);
1523 i915_driver_modeset_remove(i915);
1525 intel_irq_uninstall(i915);
1527 i915_driver_modeset_remove_noirq(i915);
1529 i915_reset_error_state(i915);
1530 i915_gem_driver_remove(i915);
1532 intel_power_domains_driver_remove(i915);
1534 i915_driver_hw_remove(i915);
1536 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1539 static void i915_driver_release(struct drm_device *dev)
1541 struct drm_i915_private *dev_priv = to_i915(dev);
1542 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1544 disable_rpm_wakeref_asserts(rpm);
1546 i915_gem_driver_release(dev_priv);
1548 intel_memory_regions_driver_release(dev_priv);
1549 i915_ggtt_driver_release(dev_priv);
1551 i915_driver_mmio_release(dev_priv);
1553 enable_rpm_wakeref_asserts(rpm);
1554 intel_runtime_pm_driver_release(rpm);
1556 i915_driver_late_release(dev_priv);
1557 i915_driver_destroy(dev_priv);
1560 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1562 struct drm_i915_private *i915 = to_i915(dev);
1565 ret = i915_gem_open(i915, file);
1573 * i915_driver_lastclose - clean up after all DRM clients have exited
1576 * Take care of cleaning up after all DRM clients have exited. In the
1577 * mode setting case, we want to restore the kernel's initial mode (just
1578 * in case the last client left us in a bad state).
1580 * Additionally, in the non-mode setting case, we'll tear down the GTT
1581 * and DMA structures, since the kernel won't be using them, and clea
1584 static void i915_driver_lastclose(struct drm_device *dev)
1586 intel_fbdev_restore_mode(dev);
1587 vga_switcheroo_process_delayed_switch();
1590 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1592 struct drm_i915_file_private *file_priv = file->driver_priv;
1594 i915_gem_context_close(file);
1595 i915_gem_release(dev, file);
1597 kfree_rcu(file_priv, rcu);
1599 /* Catch up with all the deferred frees from "this" client */
1600 i915_gem_flush_free_objects(to_i915(dev));
1603 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1605 struct drm_device *dev = &dev_priv->drm;
1606 struct intel_encoder *encoder;
1608 drm_modeset_lock_all(dev);
1609 for_each_intel_encoder(dev, encoder)
1610 if (encoder->suspend)
1611 encoder->suspend(encoder);
1612 drm_modeset_unlock_all(dev);
1615 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1617 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1618 if (acpi_target_system_state() < ACPI_STATE_S3)
1624 static int i915_drm_prepare(struct drm_device *dev)
1626 struct drm_i915_private *i915 = to_i915(dev);
1629 * NB intel_display_suspend() may issue new requests after we've
1630 * ostensibly marked the GPU as ready-to-sleep here. We need to
1631 * split out that work and pull it forward so that after point,
1632 * the GPU is not woken again.
1634 i915_gem_suspend(i915);
1639 static int i915_drm_suspend(struct drm_device *dev)
1641 struct drm_i915_private *dev_priv = to_i915(dev);
1642 struct pci_dev *pdev = dev_priv->drm.pdev;
1643 pci_power_t opregion_target_state;
1645 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1647 /* We do a lot of poking in a lot of registers, make sure they work
1649 intel_power_domains_disable(dev_priv);
1651 drm_kms_helper_poll_disable(dev);
1653 pci_save_state(pdev);
1655 intel_display_suspend(dev);
1657 intel_dp_mst_suspend(dev_priv);
1659 intel_runtime_pm_disable_interrupts(dev_priv);
1660 intel_hpd_cancel_work(dev_priv);
1662 intel_suspend_encoders(dev_priv);
1664 intel_suspend_hw(dev_priv);
1666 i915_ggtt_suspend(&dev_priv->ggtt);
1668 i915_save_state(dev_priv);
1670 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1671 intel_opregion_suspend(dev_priv, opregion_target_state);
1673 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1675 dev_priv->suspend_count++;
1677 intel_csr_ucode_suspend(dev_priv);
1679 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1684 static enum i915_drm_suspend_mode
1685 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1688 return I915_DRM_SUSPEND_HIBERNATE;
1690 if (suspend_to_idle(dev_priv))
1691 return I915_DRM_SUSPEND_IDLE;
1693 return I915_DRM_SUSPEND_MEM;
1696 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1698 struct drm_i915_private *dev_priv = to_i915(dev);
1699 struct pci_dev *pdev = dev_priv->drm.pdev;
1700 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1703 disable_rpm_wakeref_asserts(rpm);
1705 i915_gem_suspend_late(dev_priv);
1707 intel_uncore_suspend(&dev_priv->uncore);
1709 intel_power_domains_suspend(dev_priv,
1710 get_suspend_mode(dev_priv, hibernation));
1712 intel_display_power_suspend_late(dev_priv);
1714 ret = vlv_suspend_complete(dev_priv);
1716 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1717 intel_power_domains_resume(dev_priv);
1722 pci_disable_device(pdev);
1724 * During hibernation on some platforms the BIOS may try to access
1725 * the device even though it's already in D3 and hang the machine. So
1726 * leave the device in D0 on those platforms and hope the BIOS will
1727 * power down the device properly. The issue was seen on multiple old
1728 * GENs with different BIOS vendors, so having an explicit blacklist
1729 * is inpractical; apply the workaround on everything pre GEN6. The
1730 * platforms where the issue was seen:
1731 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1735 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1736 pci_set_power_state(pdev, PCI_D3hot);
1739 enable_rpm_wakeref_asserts(rpm);
1740 if (!dev_priv->uncore.user_forcewake_count)
1741 intel_runtime_pm_driver_release(rpm);
1746 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1750 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1751 state.event != PM_EVENT_FREEZE))
1754 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1757 error = i915_drm_suspend(&i915->drm);
1761 return i915_drm_suspend_late(&i915->drm, false);
1764 static int i915_drm_resume(struct drm_device *dev)
1766 struct drm_i915_private *dev_priv = to_i915(dev);
1769 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1771 sanitize_gpu(dev_priv);
1773 ret = i915_ggtt_enable_hw(dev_priv);
1775 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1777 i915_ggtt_resume(&dev_priv->ggtt);
1778 i915_gem_restore_fences(&dev_priv->ggtt);
1780 intel_csr_ucode_resume(dev_priv);
1782 i915_restore_state(dev_priv);
1783 intel_pps_unlock_regs_wa(dev_priv);
1785 intel_init_pch_refclk(dev_priv);
1788 * Interrupts have to be enabled before any batches are run. If not the
1789 * GPU will hang. i915_gem_init_hw() will initiate batches to
1790 * update/restore the context.
1792 * drm_mode_config_reset() needs AUX interrupts.
1794 * Modeset enabling in intel_modeset_init_hw() also needs working
1797 intel_runtime_pm_enable_interrupts(dev_priv);
1799 drm_mode_config_reset(dev);
1801 i915_gem_resume(dev_priv);
1803 intel_modeset_init_hw(dev_priv);
1804 intel_init_clock_gating(dev_priv);
1806 spin_lock_irq(&dev_priv->irq_lock);
1807 if (dev_priv->display.hpd_irq_setup)
1808 dev_priv->display.hpd_irq_setup(dev_priv);
1809 spin_unlock_irq(&dev_priv->irq_lock);
1811 intel_dp_mst_resume(dev_priv);
1813 intel_display_resume(dev);
1815 drm_kms_helper_poll_enable(dev);
1818 * ... but also need to make sure that hotplug processing
1819 * doesn't cause havoc. Like in the driver load code we don't
1820 * bother with the tiny race here where we might lose hotplug
1823 intel_hpd_init(dev_priv);
1825 intel_opregion_resume(dev_priv);
1827 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1829 intel_power_domains_enable(dev_priv);
1831 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1836 static int i915_drm_resume_early(struct drm_device *dev)
1838 struct drm_i915_private *dev_priv = to_i915(dev);
1839 struct pci_dev *pdev = dev_priv->drm.pdev;
1843 * We have a resume ordering issue with the snd-hda driver also
1844 * requiring our device to be power up. Due to the lack of a
1845 * parent/child relationship we currently solve this with an early
1848 * FIXME: This should be solved with a special hdmi sink device or
1849 * similar so that power domains can be employed.
1853 * Note that we need to set the power state explicitly, since we
1854 * powered off the device during freeze and the PCI core won't power
1855 * it back up for us during thaw. Powering off the device during
1856 * freeze is not a hard requirement though, and during the
1857 * suspend/resume phases the PCI core makes sure we get here with the
1858 * device powered on. So in case we change our freeze logic and keep
1859 * the device powered we can also remove the following set power state
1862 ret = pci_set_power_state(pdev, PCI_D0);
1864 drm_err(&dev_priv->drm,
1865 "failed to set PCI D0 power state (%d)\n", ret);
1870 * Note that pci_enable_device() first enables any parent bridge
1871 * device and only then sets the power state for this device. The
1872 * bridge enabling is a nop though, since bridge devices are resumed
1873 * first. The order of enabling power and enabling the device is
1874 * imposed by the PCI core as described above, so here we preserve the
1875 * same order for the freeze/thaw phases.
1877 * TODO: eventually we should remove pci_disable_device() /
1878 * pci_enable_enable_device() from suspend/resume. Due to how they
1879 * depend on the device enable refcount we can't anyway depend on them
1880 * disabling/enabling the device.
1882 if (pci_enable_device(pdev))
1885 pci_set_master(pdev);
1887 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1889 ret = vlv_resume_prepare(dev_priv, false);
1891 drm_err(&dev_priv->drm,
1892 "Resume prepare failed: %d, continuing anyway\n", ret);
1894 intel_uncore_resume_early(&dev_priv->uncore);
1896 intel_gt_check_and_clear_faults(&dev_priv->gt);
1898 intel_display_power_resume_early(dev_priv);
1900 intel_power_domains_resume(dev_priv);
1902 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1907 int i915_resume_switcheroo(struct drm_i915_private *i915)
1911 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1914 ret = i915_drm_resume_early(&i915->drm);
1918 return i915_drm_resume(&i915->drm);
1921 static int i915_pm_prepare(struct device *kdev)
1923 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1926 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1930 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1933 return i915_drm_prepare(&i915->drm);
1936 static int i915_pm_suspend(struct device *kdev)
1938 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1941 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1945 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1948 return i915_drm_suspend(&i915->drm);
1951 static int i915_pm_suspend_late(struct device *kdev)
1953 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1956 * We have a suspend ordering issue with the snd-hda driver also
1957 * requiring our device to be power up. Due to the lack of a
1958 * parent/child relationship we currently solve this with an late
1961 * FIXME: This should be solved with a special hdmi sink device or
1962 * similar so that power domains can be employed.
1964 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1967 return i915_drm_suspend_late(&i915->drm, false);
1970 static int i915_pm_poweroff_late(struct device *kdev)
1972 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1974 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1977 return i915_drm_suspend_late(&i915->drm, true);
1980 static int i915_pm_resume_early(struct device *kdev)
1982 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1984 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1987 return i915_drm_resume_early(&i915->drm);
1990 static int i915_pm_resume(struct device *kdev)
1992 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1994 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1997 return i915_drm_resume(&i915->drm);
2000 /* freeze: before creating the hibernation_image */
2001 static int i915_pm_freeze(struct device *kdev)
2003 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2006 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2007 ret = i915_drm_suspend(&i915->drm);
2012 ret = i915_gem_freeze(i915);
2019 static int i915_pm_freeze_late(struct device *kdev)
2021 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2024 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2025 ret = i915_drm_suspend_late(&i915->drm, true);
2030 ret = i915_gem_freeze_late(i915);
2037 /* thaw: called after creating the hibernation image, but before turning off. */
2038 static int i915_pm_thaw_early(struct device *kdev)
2040 return i915_pm_resume_early(kdev);
2043 static int i915_pm_thaw(struct device *kdev)
2045 return i915_pm_resume(kdev);
2048 /* restore: called after loading the hibernation image. */
2049 static int i915_pm_restore_early(struct device *kdev)
2051 return i915_pm_resume_early(kdev);
2054 static int i915_pm_restore(struct device *kdev)
2056 return i915_pm_resume(kdev);
2059 static int intel_runtime_suspend(struct device *kdev)
2061 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2062 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2065 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
2068 drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
2070 disable_rpm_wakeref_asserts(rpm);
2073 * We are safe here against re-faults, since the fault handler takes
2076 i915_gem_runtime_suspend(dev_priv);
2078 intel_gt_runtime_suspend(&dev_priv->gt);
2080 intel_runtime_pm_disable_interrupts(dev_priv);
2082 intel_uncore_suspend(&dev_priv->uncore);
2084 intel_display_power_suspend(dev_priv);
2086 ret = vlv_suspend_complete(dev_priv);
2088 drm_err(&dev_priv->drm,
2089 "Runtime suspend failed, disabling it (%d)\n", ret);
2090 intel_uncore_runtime_resume(&dev_priv->uncore);
2092 intel_runtime_pm_enable_interrupts(dev_priv);
2094 intel_gt_runtime_resume(&dev_priv->gt);
2096 i915_gem_restore_fences(&dev_priv->ggtt);
2098 enable_rpm_wakeref_asserts(rpm);
2103 enable_rpm_wakeref_asserts(rpm);
2104 intel_runtime_pm_driver_release(rpm);
2106 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2107 drm_err(&dev_priv->drm,
2108 "Unclaimed access detected prior to suspending\n");
2110 rpm->suspended = true;
2113 * FIXME: We really should find a document that references the arguments
2116 if (IS_BROADWELL(dev_priv)) {
2118 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2119 * being detected, and the call we do at intel_runtime_resume()
2120 * won't be able to restore them. Since PCI_D3hot matches the
2121 * actual specification and appears to be working, use it.
2123 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2126 * current versions of firmware which depend on this opregion
2127 * notification have repurposed the D1 definition to mean
2128 * "runtime suspended" vs. what you would normally expect (D3)
2129 * to distinguish it from notifications that might be sent via
2132 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2135 assert_forcewakes_inactive(&dev_priv->uncore);
2137 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2138 intel_hpd_poll_init(dev_priv);
2140 drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
2144 static int intel_runtime_resume(struct device *kdev)
2146 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2147 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2150 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
2153 drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
2155 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
2156 disable_rpm_wakeref_asserts(rpm);
2158 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2159 rpm->suspended = false;
2160 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2161 drm_dbg(&dev_priv->drm,
2162 "Unclaimed access during suspend, bios?\n");
2164 intel_display_power_resume(dev_priv);
2166 ret = vlv_resume_prepare(dev_priv, true);
2168 intel_uncore_runtime_resume(&dev_priv->uncore);
2170 intel_runtime_pm_enable_interrupts(dev_priv);
2173 * No point of rolling back things in case of an error, as the best
2174 * we can do is to hope that things will still work (and disable RPM).
2176 intel_gt_runtime_resume(&dev_priv->gt);
2177 i915_gem_restore_fences(&dev_priv->ggtt);
2180 * On VLV/CHV display interrupts are part of the display
2181 * power well, so hpd is reinitialized from there. For
2182 * everyone else do it here.
2184 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2185 intel_hpd_init(dev_priv);
2187 intel_enable_ipc(dev_priv);
2189 enable_rpm_wakeref_asserts(rpm);
2192 drm_err(&dev_priv->drm,
2193 "Runtime resume failed, disabling it (%d)\n", ret);
2195 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
2200 const struct dev_pm_ops i915_pm_ops = {
2202 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2205 .prepare = i915_pm_prepare,
2206 .suspend = i915_pm_suspend,
2207 .suspend_late = i915_pm_suspend_late,
2208 .resume_early = i915_pm_resume_early,
2209 .resume = i915_pm_resume,
2213 * @freeze, @freeze_late : called (1) before creating the
2214 * hibernation image [PMSG_FREEZE] and
2215 * (2) after rebooting, before restoring
2216 * the image [PMSG_QUIESCE]
2217 * @thaw, @thaw_early : called (1) after creating the hibernation
2218 * image, before writing it [PMSG_THAW]
2219 * and (2) after failing to create or
2220 * restore the image [PMSG_RECOVER]
2221 * @poweroff, @poweroff_late: called after writing the hibernation
2222 * image, before rebooting [PMSG_HIBERNATE]
2223 * @restore, @restore_early : called after rebooting and restoring the
2224 * hibernation image [PMSG_RESTORE]
2226 .freeze = i915_pm_freeze,
2227 .freeze_late = i915_pm_freeze_late,
2228 .thaw_early = i915_pm_thaw_early,
2229 .thaw = i915_pm_thaw,
2230 .poweroff = i915_pm_suspend,
2231 .poweroff_late = i915_pm_poweroff_late,
2232 .restore_early = i915_pm_restore_early,
2233 .restore = i915_pm_restore,
2235 /* S0ix (via runtime suspend) event handlers */
2236 .runtime_suspend = intel_runtime_suspend,
2237 .runtime_resume = intel_runtime_resume,
2240 static const struct file_operations i915_driver_fops = {
2241 .owner = THIS_MODULE,
2243 .release = drm_release_noglobal,
2244 .unlocked_ioctl = drm_ioctl,
2245 .mmap = i915_gem_mmap,
2248 .compat_ioctl = i915_compat_ioctl,
2249 .llseek = noop_llseek,
2253 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2254 struct drm_file *file)
2259 static const struct drm_ioctl_desc i915_ioctls[] = {
2260 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2261 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2262 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2263 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2264 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2265 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2266 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
2267 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2268 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2269 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2270 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2271 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2272 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2273 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2274 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2275 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2276 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2277 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2278 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2279 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
2280 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2281 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2282 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
2283 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2284 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2285 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
2286 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2287 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2288 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2289 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2290 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2291 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2292 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
2293 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2294 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2295 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2296 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2297 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2298 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2299 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2300 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2301 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2302 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2303 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2304 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
2305 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2306 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2307 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2308 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2309 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2310 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2311 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2312 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2313 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
2314 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
2315 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
2316 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
2317 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
2320 static struct drm_driver driver = {
2321 /* Don't use MTRRs here; the Xserver or userspace app should
2322 * deal with them for Intel hardware.
2326 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2327 .release = i915_driver_release,
2328 .open = i915_driver_open,
2329 .lastclose = i915_driver_lastclose,
2330 .postclose = i915_driver_postclose,
2332 .gem_close_object = i915_gem_close_object,
2333 .gem_free_object_unlocked = i915_gem_free_object,
2335 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2336 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2337 .gem_prime_export = i915_gem_prime_export,
2338 .gem_prime_import = i915_gem_prime_import,
2340 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
2341 .get_scanout_position = i915_get_crtc_scanoutpos,
2343 .dumb_create = i915_gem_dumb_create,
2344 .dumb_map_offset = i915_gem_dumb_mmap_offset,
2346 .ioctls = i915_ioctls,
2347 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2348 .fops = &i915_driver_fops,
2349 .name = DRIVER_NAME,
2350 .desc = DRIVER_DESC,
2351 .date = DRIVER_DATE,
2352 .major = DRIVER_MAJOR,
2353 .minor = DRIVER_MINOR,
2354 .patchlevel = DRIVER_PATCHLEVEL,