drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915.inject_load_failure &&
 110                i915_load_fail_count == i915.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 139         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 140                 ret = PCH_SPT;
 141                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 142         }
 143
 144         return ret;
 145 }
 146
 147 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 148 {
 149         struct pci_dev *pch = NULL;
 150
 151         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 152          * (which really amounts to a PCH but no South Display).
 153          */
 154         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 155                 dev_priv->pch_type = PCH_NOP;
 156                 return;
 157         }
 158
 159         /*
 160          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 161          * make graphics device passthrough work easy for VMM, that only
 162          * need to expose ISA bridge to let driver know the real hardware
 163          * underneath. This is a requirement from virtualization team.
 164          *
 165          * In some virtualized environments (e.g. XEN), there is irrelevant
 166          * ISA bridge in the system. To work reliably, we should scan trhough
 167          * all the ISA bridge devices and check for the first match, instead
 168          * of only checking the first one.
 169          */
 170         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 171                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 172                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 173                         dev_priv->pch_id = id;
 174
 175                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 176                                 dev_priv->pch_type = PCH_IBX;
 177                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 178                                 WARN_ON(!IS_GEN5(dev_priv));
 179                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 180                                 dev_priv->pch_type = PCH_CPT;
 181                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 182                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 183                                         IS_IVYBRIDGE(dev_priv)));
 184                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 185                                 /* PantherPoint is CPT compatible */
 186                                 dev_priv->pch_type = PCH_CPT;
 187                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 188                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 189                                         IS_IVYBRIDGE(dev_priv)));
 190                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 191                                 dev_priv->pch_type = PCH_LPT;
 192                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 193                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 194                                         !IS_BROADWELL(dev_priv));
 195                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 196                                         IS_BDW_ULT(dev_priv));
 197                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_LPT;
 199                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 200                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 201                                         !IS_BROADWELL(dev_priv));
 202                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 203                                         !IS_BDW_ULT(dev_priv));
 204                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 205                                 dev_priv->pch_type = PCH_SPT;
 206                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 207                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 208                                         !IS_KABYLAKE(dev_priv));
 209                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 210                                 dev_priv->pch_type = PCH_SPT;
 211                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 212                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 213                                         !IS_KABYLAKE(dev_priv));
 214                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 215                                 dev_priv->pch_type = PCH_KBP;
 216                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 217                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 218                                         !IS_KABYLAKE(dev_priv));
 219                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 220                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 221                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 222                                     pch->subsystem_vendor ==
 223                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 224                                     pch->subsystem_device ==
 225                                             PCI_SUBDEVICE_ID_QEMU)) {
 226                                 dev_priv->pch_type =
 227                                         intel_virt_detect_pch(dev_priv);
 228                         } else
 229                                 continue;
 230
 231                         break;
 232                 }
 233         }
 234         if (!pch)
 235                 DRM_DEBUG_KMS("No PCH found.\n");
 236
 237         pci_dev_put(pch);
 238 }
 239
 240 static int i915_getparam(struct drm_device *dev, void *data,
 241                          struct drm_file *file_priv)
 242 {
 243         struct drm_i915_private *dev_priv = to_i915(dev);
 244         struct pci_dev *pdev = dev_priv->drm.pdev;
 245         drm_i915_getparam_t *param = data;
 246         int value;
 247
 248         switch (param->param) {
 249         case I915_PARAM_IRQ_ACTIVE:
 250         case I915_PARAM_ALLOW_BATCHBUFFER:
 251         case I915_PARAM_LAST_DISPATCH:
 252                 /* Reject all old ums/dri params. */
 253                 return -ENODEV;
 254         case I915_PARAM_CHIPSET_ID:
 255                 value = pdev->device;
 256                 break;
 257         case I915_PARAM_REVISION:
 258                 value = pdev->revision;
 259                 break;
 260         case I915_PARAM_NUM_FENCES_AVAIL:
 261                 value = dev_priv->num_fence_regs;
 262                 break;
 263         case I915_PARAM_HAS_OVERLAY:
 264                 value = dev_priv->overlay ? 1 : 0;
 265                 break;
 266         case I915_PARAM_HAS_BSD:
 267                 value = !!dev_priv->engine[VCS];
 268                 break;
 269         case I915_PARAM_HAS_BLT:
 270                 value = !!dev_priv->engine[BCS];
 271                 break;
 272         case I915_PARAM_HAS_VEBOX:
 273                 value = !!dev_priv->engine[VECS];
 274                 break;
 275         case I915_PARAM_HAS_BSD2:
 276                 value = !!dev_priv->engine[VCS2];
 277                 break;
 278         case I915_PARAM_HAS_EXEC_CONSTANTS:
 279                 value = INTEL_GEN(dev_priv) >= 4;
 280                 break;
 281         case I915_PARAM_HAS_LLC:
 282                 value = HAS_LLC(dev_priv);
 283                 break;
 284         case I915_PARAM_HAS_WT:
 285                 value = HAS_WT(dev_priv);
 286                 break;
 287         case I915_PARAM_HAS_ALIASING_PPGTT:
 288                 value = USES_PPGTT(dev_priv);
 289                 break;
 290         case I915_PARAM_HAS_SEMAPHORES:
 291                 value = i915.semaphores;
 292                 break;
 293         case I915_PARAM_HAS_SECURE_BATCHES:
 294                 value = capable(CAP_SYS_ADMIN);
 295                 break;
 296         case I915_PARAM_CMD_PARSER_VERSION:
 297                 value = i915_cmd_parser_get_version(dev_priv);
 298                 break;
 299         case I915_PARAM_SUBSLICE_TOTAL:
 300                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 301                 if (!value)
 302                         return -ENODEV;
 303                 break;
 304         case I915_PARAM_EU_TOTAL:
 305                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 306                 if (!value)
 307                         return -ENODEV;
 308                 break;
 309         case I915_PARAM_HAS_GPU_RESET:
 310                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 311                 break;
 312         case I915_PARAM_HAS_RESOURCE_STREAMER:
 313                 value = HAS_RESOURCE_STREAMER(dev_priv);
 314                 break;
 315         case I915_PARAM_HAS_POOLED_EU:
 316                 value = HAS_POOLED_EU(dev_priv);
 317                 break;
 318         case I915_PARAM_MIN_EU_IN_POOL:
 319                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 320                 break;
 321         case I915_PARAM_HUC_STATUS:
 322                 /* The register is already force-woken. We dont need
 323                  * any rpm here
 324                  */
 325                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 326                 break;
 327         case I915_PARAM_MMAP_GTT_VERSION:
 328                 /* Though we've started our numbering from 1, and so class all
 329                  * earlier versions as 0, in effect their value is undefined as
 330                  * the ioctl will report EINVAL for the unknown param!
 331                  */
 332                 value = i915_gem_mmap_gtt_version();
 333                 break;
 334         case I915_PARAM_HAS_SCHEDULER:
 335                 value = dev_priv->engine[RCS] &&
 336                         dev_priv->engine[RCS]->schedule;
 337                 break;
 338         case I915_PARAM_MMAP_VERSION:
 339                 /* Remember to bump this if the version changes! */
 340         case I915_PARAM_HAS_GEM:
 341         case I915_PARAM_HAS_PAGEFLIPPING:
 342         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 343         case I915_PARAM_HAS_RELAXED_FENCING:
 344         case I915_PARAM_HAS_COHERENT_RINGS:
 345         case I915_PARAM_HAS_RELAXED_DELTA:
 346         case I915_PARAM_HAS_GEN7_SOL_RESET:
 347         case I915_PARAM_HAS_WAIT_TIMEOUT:
 348         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 349         case I915_PARAM_HAS_PINNED_BATCHES:
 350         case I915_PARAM_HAS_EXEC_NO_RELOC:
 351         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 352         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 353         case I915_PARAM_HAS_EXEC_SOFTPIN:
 354         case I915_PARAM_HAS_EXEC_ASYNC:
 355         case I915_PARAM_HAS_EXEC_FENCE:
 356                 /* For the time being all of these are always true;
 357                  * if some supported hardware does not have one of these
 358                  * features this value needs to be provided from
 359                  * INTEL_INFO(), a feature macro, or similar.
 360                  */
 361                 value = 1;
 362                 break;
 363         default:
 364                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 365                 return -EINVAL;
 366         }
 367
 368         if (put_user(value, param->value))
 369                 return -EFAULT;
 370
 371         return 0;
 372 }
 373
 374 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 375 {
 376         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 377         if (!dev_priv->bridge_dev) {
 378                 DRM_ERROR("bridge device not found\n");
 379                 return -1;
 380         }
 381         return 0;
 382 }
 383
 384 /* Allocate space for the MCH regs if needed, return nonzero on error */
 385 static int
 386 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 387 {
 388         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 389         u32 temp_lo, temp_hi = 0;
 390         u64 mchbar_addr;
 391         int ret;
 392
 393         if (INTEL_GEN(dev_priv) >= 4)
 394                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 395         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 396         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 397
 398         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 399 #ifdef CONFIG_PNP
 400         if (mchbar_addr &&
 401             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 402                 return 0;
 403 #endif
 404
 405         /* Get some space for it */
 406         dev_priv->mch_res.name = "i915 MCHBAR";
 407         dev_priv->mch_res.flags = IORESOURCE_MEM;
 408         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 409                                      &dev_priv->mch_res,
 410                                      MCHBAR_SIZE, MCHBAR_SIZE,
 411                                      PCIBIOS_MIN_MEM,
 412                                      0, pcibios_align_resource,
 413                                      dev_priv->bridge_dev);
 414         if (ret) {
 415                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 416                 dev_priv->mch_res.start = 0;
 417                 return ret;
 418         }
 419
 420         if (INTEL_GEN(dev_priv) >= 4)
 421                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 422                                        upper_32_bits(dev_priv->mch_res.start));
 423
 424         pci_write_config_dword(dev_priv->bridge_dev, reg,
 425                                lower_32_bits(dev_priv->mch_res.start));
 426         return 0;
 427 }
 428
 429 /* Setup MCHBAR if possible, return true if we should disable it again */
 430 static void
 431 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 432 {
 433         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 434         u32 temp;
 435         bool enabled;
 436
 437         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 438                 return;
 439
 440         dev_priv->mchbar_need_disable = false;
 441
 442         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 443                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 444                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 445         } else {
 446                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 447                 enabled = temp & 1;
 448         }
 449
 450         /* If it's already enabled, don't have to do anything */
 451         if (enabled)
 452                 return;
 453
 454         if (intel_alloc_mchbar_resource(dev_priv))
 455                 return;
 456
 457         dev_priv->mchbar_need_disable = true;
 458
 459         /* Space is allocated or reserved, so enable it. */
 460         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 461                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 462                                        temp | DEVEN_MCHBAR_EN);
 463         } else {
 464                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 465                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 466         }
 467 }
 468
 469 static void
 470 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 471 {
 472         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 473
 474         if (dev_priv->mchbar_need_disable) {
 475                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 476                         u32 deven_val;
 477
 478                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 479                                               &deven_val);
 480                         deven_val &= ~DEVEN_MCHBAR_EN;
 481                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 482                                                deven_val);
 483                 } else {
 484                         u32 mchbar_val;
 485
 486                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 487                                               &mchbar_val);
 488                         mchbar_val &= ~1;
 489                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 490                                                mchbar_val);
 491                 }
 492         }
 493
 494         if (dev_priv->mch_res.start)
 495                 release_resource(&dev_priv->mch_res);
 496 }
 497
 498 /* true = enable decode, false = disable decoder */
 499 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 500 {
 501         struct drm_i915_private *dev_priv = cookie;
 502
 503         intel_modeset_vga_set_state(dev_priv, state);
 504         if (state)
 505                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 506                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 507         else
 508                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 509 }
 510
 511 static int i915_resume_switcheroo(struct drm_device *dev);
 512 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 513
 514 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 515 {
 516         struct drm_device *dev = pci_get_drvdata(pdev);
 517         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 518
 519         if (state == VGA_SWITCHEROO_ON) {
 520                 pr_info("switched on\n");
 521                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 522                 /* i915 resume handler doesn't set to D0 */
 523                 pci_set_power_state(pdev, PCI_D0);
 524                 i915_resume_switcheroo(dev);
 525                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 526         } else {
 527                 pr_info("switched off\n");
 528                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 529                 i915_suspend_switcheroo(dev, pmm);
 530                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 531         }
 532 }
 533
 534 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 535 {
 536         struct drm_device *dev = pci_get_drvdata(pdev);
 537
 538         /*
 539          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 540          * locking inversion with the driver load path. And the access here is
 541          * completely racy anyway. So don't bother with locking for now.
 542          */
 543         return dev->open_count == 0;
 544 }
 545
 546 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 547         .set_gpu_state = i915_switcheroo_set_state,
 548         .reprobe = NULL,
 549         .can_switch = i915_switcheroo_can_switch,
 550 };
 551
 552 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 553 {
 554         mutex_lock(&dev_priv->drm.struct_mutex);
 555         i915_gem_cleanup_engines(dev_priv);
 556         i915_gem_context_fini(dev_priv);
 557         mutex_unlock(&dev_priv->drm.struct_mutex);
 558
 559         i915_gem_drain_freed_objects(dev_priv);
 560
 561         WARN_ON(!list_empty(&dev_priv->context_list));
 562 }
 563
 564 static int i915_load_modeset_init(struct drm_device *dev)
 565 {
 566         struct drm_i915_private *dev_priv = to_i915(dev);
 567         struct pci_dev *pdev = dev_priv->drm.pdev;
 568         int ret;
 569
 570         if (i915_inject_load_failure())
 571                 return -ENODEV;
 572
 573         ret = intel_bios_init(dev_priv);
 574         if (ret)
 575                 DRM_INFO("failed to find VBIOS tables\n");
 576
 577         /* If we have > 1 VGA cards, then we need to arbitrate access
 578          * to the common VGA resources.
 579          *
 580          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 581          * then we do not take part in VGA arbitration and the
 582          * vga_client_register() fails with -ENODEV.
 583          */
 584         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 585         if (ret && ret != -ENODEV)
 586                 goto out;
 587
 588         intel_register_dsm_handler();
 589
 590         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 591         if (ret)
 592                 goto cleanup_vga_client;
 593
 594         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 595         intel_update_rawclk(dev_priv);
 596
 597         intel_power_domains_init_hw(dev_priv, false);
 598
 599         intel_csr_ucode_init(dev_priv);
 600
 601         ret = intel_irq_install(dev_priv);
 602         if (ret)
 603                 goto cleanup_csr;
 604
 605         intel_setup_gmbus(dev_priv);
 606
 607         /* Important: The output setup functions called by modeset_init need
 608          * working irqs for e.g. gmbus and dp aux transfers. */
 609         ret = intel_modeset_init(dev);
 610         if (ret)
 611                 goto cleanup_irq;
 612
 613         intel_huc_init(dev_priv);
 614         intel_guc_init(dev_priv);
 615
 616         ret = i915_gem_init(dev_priv);
 617         if (ret)
 618                 goto cleanup_irq;
 619
 620         intel_modeset_gem_init(dev);
 621
 622         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 623                 return 0;
 624
 625         ret = intel_fbdev_init(dev);
 626         if (ret)
 627                 goto cleanup_gem;
 628
 629         /* Only enable hotplug handling once the fbdev is fully set up. */
 630         intel_hpd_init(dev_priv);
 631
 632         drm_kms_helper_poll_init(dev);
 633
 634         return 0;
 635
 636 cleanup_gem:
 637         if (i915_gem_suspend(dev_priv))
 638                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 639         i915_gem_fini(dev_priv);
 640 cleanup_irq:
 641         intel_guc_fini(dev_priv);
 642         intel_huc_fini(dev_priv);
 643         drm_irq_uninstall(dev);
 644         intel_teardown_gmbus(dev_priv);
 645 cleanup_csr:
 646         intel_csr_ucode_fini(dev_priv);
 647         intel_power_domains_fini(dev_priv);
 648         vga_switcheroo_unregister_client(pdev);
 649 cleanup_vga_client:
 650         vga_client_register(pdev, NULL, NULL, NULL);
 651 out:
 652         return ret;
 653 }
 654
 655 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 656 {
 657         struct apertures_struct *ap;
 658         struct pci_dev *pdev = dev_priv->drm.pdev;
 659         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 660         bool primary;
 661         int ret;
 662
 663         ap = alloc_apertures(1);
 664         if (!ap)
 665                 return -ENOMEM;
 666
 667         ap->ranges[0].base = ggtt->mappable_base;
 668         ap->ranges[0].size = ggtt->mappable_end;
 669
 670         primary =
 671                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 672
 673         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 674
 675         kfree(ap);
 676
 677         return ret;
 678 }
 679
 680 #if !defined(CONFIG_VGA_CONSOLE)
 681 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 682 {
 683         return 0;
 684 }
 685 #elif !defined(CONFIG_DUMMY_CONSOLE)
 686 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 687 {
 688         return -ENODEV;
 689 }
 690 #else
 691 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 692 {
 693         int ret = 0;
 694
 695         DRM_INFO("Replacing VGA console driver\n");
 696
 697         console_lock();
 698         if (con_is_bound(&vga_con))
 699                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 700         if (ret == 0) {
 701                 ret = do_unregister_con_driver(&vga_con);
 702
 703                 /* Ignore "already unregistered". */
 704                 if (ret == -ENODEV)
 705                         ret = 0;
 706         }
 707         console_unlock();
 708
 709         return ret;
 710 }
 711 #endif
 712
 713 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 714 {
 715         /*
 716          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 717          * CHV x1 PHY (DP/HDMI D)
 718          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 719          */
 720         if (IS_CHERRYVIEW(dev_priv)) {
 721                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 722                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 723         } else if (IS_VALLEYVIEW(dev_priv)) {
 724                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 725         }
 726 }
 727
 728 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 729 {
 730         /*
 731          * The i915 workqueue is primarily used for batched retirement of
 732          * requests (and thus managing bo) once the task has been completed
 733          * by the GPU. i915_gem_retire_requests() is called directly when we
 734          * need high-priority retirement, such as waiting for an explicit
 735          * bo.
 736          *
 737          * It is also used for periodic low-priority events, such as
 738          * idle-timers and recording error state.
 739          *
 740          * All tasks on the workqueue are expected to acquire the dev mutex
 741          * so there is no point in running more than one instance of the
 742          * workqueue at any time.  Use an ordered one.
 743          */
 744         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 745         if (dev_priv->wq == NULL)
 746                 goto out_err;
 747
 748         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 749         if (dev_priv->hotplug.dp_wq == NULL)
 750                 goto out_free_wq;
 751
 752         return 0;
 753
 754 out_free_wq:
 755         destroy_workqueue(dev_priv->wq);
 756 out_err:
 757         DRM_ERROR("Failed to allocate workqueues.\n");
 758
 759         return -ENOMEM;
 760 }
 761
 762 static void i915_engines_cleanup(struct drm_i915_private *i915)
 763 {
 764         struct intel_engine_cs *engine;
 765         enum intel_engine_id id;
 766
 767         for_each_engine(engine, i915, id)
 768                 kfree(engine);
 769 }
 770
 771 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 772 {
 773         destroy_workqueue(dev_priv->hotplug.dp_wq);
 774         destroy_workqueue(dev_priv->wq);
 775 }
 776
 777 /*
 778  * We don't keep the workarounds for pre-production hardware, so we expect our
 779  * driver to fail on these machines in one way or another. A little warning on
 780  * dmesg may help both the user and the bug triagers.
 781  */
 782 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 783 {
 784         bool pre = false;
 785
 786         pre |= IS_HSW_EARLY_SDV(dev_priv);
 787         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 788         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 789
 790         if (pre) {
 791                 DRM_ERROR("This is a pre-production stepping. "
 792                           "It may not be fully functional.\n");
 793                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 794         }
 795 }
 796
 797 /**
 798  * i915_driver_init_early - setup state not requiring device access
 799  * @dev_priv: device private
 800  *
 801  * Initialize everything that is a "SW-only" state, that is state not
 802  * requiring accessing the device or exposing the driver via kernel internal
 803  * or userspace interfaces. Example steps belonging here: lock initialization,
 804  * system memory allocation, setting up device specific attributes and
 805  * function hooks not requiring accessing the device.
 806  */
 807 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 808                                   const struct pci_device_id *ent)
 809 {
 810         const struct intel_device_info *match_info =
 811                 (struct intel_device_info *)ent->driver_data;
 812         struct intel_device_info *device_info;
 813         int ret = 0;
 814
 815         if (i915_inject_load_failure())
 816                 return -ENODEV;
 817
 818         /* Setup the write-once "constant" device info */
 819         device_info = mkwrite_device_info(dev_priv);
 820         memcpy(device_info, match_info, sizeof(*device_info));
 821         device_info->device_id = dev_priv->drm.pdev->device;
 822
 823         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 824         device_info->gen_mask = BIT(device_info->gen - 1);
 825
 826         spin_lock_init(&dev_priv->irq_lock);
 827         spin_lock_init(&dev_priv->gpu_error.lock);
 828         mutex_init(&dev_priv->backlight_lock);
 829         spin_lock_init(&dev_priv->uncore.lock);
 830         spin_lock_init(&dev_priv->mm.object_stat_lock);
 831         spin_lock_init(&dev_priv->mmio_flip_lock);
 832         spin_lock_init(&dev_priv->wm.dsparb_lock);
 833         mutex_init(&dev_priv->sb_lock);
 834         mutex_init(&dev_priv->modeset_restore_lock);
 835         mutex_init(&dev_priv->av_mutex);
 836         mutex_init(&dev_priv->wm.wm_mutex);
 837         mutex_init(&dev_priv->pps_mutex);
 838
 839         intel_uc_init_early(dev_priv);
 840         i915_memcpy_init_early(dev_priv);
 841
 842         ret = intel_engines_init_early(dev_priv);
 843         if (ret)
 844                 return ret;
 845
 846         ret = i915_workqueues_init(dev_priv);
 847         if (ret < 0)
 848                 goto err_engines;
 849
 850         ret = intel_gvt_init(dev_priv);
 851         if (ret < 0)
 852                 goto err_workqueues;
 853
 854         /* This must be called before any calls to HAS_PCH_* */
 855         intel_detect_pch(dev_priv);
 856
 857         intel_pm_setup(dev_priv);
 858         intel_init_dpio(dev_priv);
 859         intel_power_domains_init(dev_priv);
 860         intel_irq_init(dev_priv);
 861         intel_hangcheck_init(dev_priv);
 862         intel_init_display_hooks(dev_priv);
 863         intel_init_clock_gating_hooks(dev_priv);
 864         intel_init_audio_hooks(dev_priv);
 865         ret = i915_gem_load_init(dev_priv);
 866         if (ret < 0)
 867                 goto err_gvt;
 868
 869         intel_display_crc_init(dev_priv);
 870
 871         intel_device_info_dump(dev_priv);
 872
 873         intel_detect_preproduction_hw(dev_priv);
 874
 875         i915_perf_init(dev_priv);
 876
 877         return 0;
 878
 879 err_gvt:
 880         intel_gvt_cleanup(dev_priv);
 881 err_workqueues:
 882         i915_workqueues_cleanup(dev_priv);
 883 err_engines:
 884         i915_engines_cleanup(dev_priv);
 885         return ret;
 886 }
 887
 888 /**
 889  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 890  * @dev_priv: device private
 891  */
 892 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 893 {
 894         i915_perf_fini(dev_priv);
 895         i915_gem_load_cleanup(dev_priv);
 896         i915_workqueues_cleanup(dev_priv);
 897         i915_engines_cleanup(dev_priv);
 898 }
 899
 900 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 901 {
 902         struct pci_dev *pdev = dev_priv->drm.pdev;
 903         int mmio_bar;
 904         int mmio_size;
 905
 906         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 907         /*
 908          * Before gen4, the registers and the GTT are behind different BARs.
 909          * However, from gen4 onwards, the registers and the GTT are shared
 910          * in the same BAR, so we want to restrict this ioremap from
 911          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 912          * the register BAR remains the same size for all the earlier
 913          * generations up to Ironlake.
 914          */
 915         if (INTEL_GEN(dev_priv) < 5)
 916                 mmio_size = 512 * 1024;
 917         else
 918                 mmio_size = 2 * 1024 * 1024;
 919         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 920         if (dev_priv->regs == NULL) {
 921                 DRM_ERROR("failed to map registers\n");
 922
 923                 return -EIO;
 924         }
 925
 926         /* Try to make sure MCHBAR is enabled before poking at it */
 927         intel_setup_mchbar(dev_priv);
 928
 929         return 0;
 930 }
 931
 932 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 933 {
 934         struct pci_dev *pdev = dev_priv->drm.pdev;
 935
 936         intel_teardown_mchbar(dev_priv);
 937         pci_iounmap(pdev, dev_priv->regs);
 938 }
 939
 940 /**
 941  * i915_driver_init_mmio - setup device MMIO
 942  * @dev_priv: device private
 943  *
 944  * Setup minimal device state necessary for MMIO accesses later in the
 945  * initialization sequence. The setup here should avoid any other device-wide
 946  * side effects or exposing the driver via kernel internal or user space
 947  * interfaces.
 948  */
 949 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 950 {
 951         int ret;
 952
 953         if (i915_inject_load_failure())
 954                 return -ENODEV;
 955
 956         if (i915_get_bridge_dev(dev_priv))
 957                 return -EIO;
 958
 959         ret = i915_mmio_setup(dev_priv);
 960         if (ret < 0)
 961                 goto put_bridge;
 962
 963         intel_uncore_init(dev_priv);
 964         i915_gem_init_mmio(dev_priv);
 965
 966         return 0;
 967
 968 put_bridge:
 969         pci_dev_put(dev_priv->bridge_dev);
 970
 971         return ret;
 972 }
 973
 974 /**
 975  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 976  * @dev_priv: device private
 977  */
 978 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 979 {
 980         intel_uncore_fini(dev_priv);
 981         i915_mmio_cleanup(dev_priv);
 982         pci_dev_put(dev_priv->bridge_dev);
 983 }
 984
 985 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 986 {
 987         i915.enable_execlists =
 988                 intel_sanitize_enable_execlists(dev_priv,
 989                                                 i915.enable_execlists);
 990
 991         /*
 992          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 993          * user's requested state against the hardware/driver capabilities.  We
 994          * do this now so that we can print out any log messages once rather
 995          * than every time we check intel_enable_ppgtt().
 996          */
 997         i915.enable_ppgtt =
 998                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 999         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1000
1001         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
1002         DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
1003 }
1004
1005 /**
1006  * i915_driver_init_hw - setup state requiring device access
1007  * @dev_priv: device private
1008  *
1009  * Setup state that requires accessing the device, but doesn't require
1010  * exposing the driver via kernel internal or userspace interfaces.
1011  */
1012 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1013 {
1014         struct pci_dev *pdev = dev_priv->drm.pdev;
1015         int ret;
1016
1017         if (i915_inject_load_failure())
1018                 return -ENODEV;
1019
1020         intel_device_info_runtime_init(dev_priv);
1021
1022         intel_sanitize_options(dev_priv);
1023
1024         ret = i915_ggtt_probe_hw(dev_priv);
1025         if (ret)
1026                 return ret;
1027
1028         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1029          * otherwise the vga fbdev driver falls over. */
1030         ret = i915_kick_out_firmware_fb(dev_priv);
1031         if (ret) {
1032                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1033                 goto out_ggtt;
1034         }
1035
1036         ret = i915_kick_out_vgacon(dev_priv);
1037         if (ret) {
1038                 DRM_ERROR("failed to remove conflicting VGA console\n");
1039                 goto out_ggtt;
1040         }
1041
1042         ret = i915_ggtt_init_hw(dev_priv);
1043         if (ret)
1044                 return ret;
1045
1046         ret = i915_ggtt_enable_hw(dev_priv);
1047         if (ret) {
1048                 DRM_ERROR("failed to enable GGTT\n");
1049                 goto out_ggtt;
1050         }
1051
1052         pci_set_master(pdev);
1053
1054         /* overlay on gen2 is broken and can't address above 1G */
1055         if (IS_GEN2(dev_priv)) {
1056                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1057                 if (ret) {
1058                         DRM_ERROR("failed to set DMA mask\n");
1059
1060                         goto out_ggtt;
1061                 }
1062         }
1063
1064         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1065          * using 32bit addressing, overwriting memory if HWS is located
1066          * above 4GB.
1067          *
1068          * The documentation also mentions an issue with undefined
1069          * behaviour if any general state is accessed within a page above 4GB,
1070          * which also needs to be handled carefully.
1071          */
1072         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1073                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1074
1075                 if (ret) {
1076                         DRM_ERROR("failed to set DMA mask\n");
1077
1078                         goto out_ggtt;
1079                 }
1080         }
1081
1082         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1083                            PM_QOS_DEFAULT_VALUE);
1084
1085         intel_uncore_sanitize(dev_priv);
1086
1087         intel_opregion_setup(dev_priv);
1088
1089         i915_gem_load_init_fences(dev_priv);
1090
1091         /* On the 945G/GM, the chipset reports the MSI capability on the
1092          * integrated graphics even though the support isn't actually there
1093          * according to the published specs.  It doesn't appear to function
1094          * correctly in testing on 945G.
1095          * This may be a side effect of MSI having been made available for PEG
1096          * and the registers being closely associated.
1097          *
1098          * According to chipset errata, on the 965GM, MSI interrupts may
1099          * be lost or delayed, but we use them anyways to avoid
1100          * stuck interrupts on some machines.
1101          */
1102         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1103                 if (pci_enable_msi(pdev) < 0)
1104                         DRM_DEBUG_DRIVER("can't enable MSI");
1105         }
1106
1107         return 0;
1108
1109 out_ggtt:
1110         i915_ggtt_cleanup_hw(dev_priv);
1111
1112         return ret;
1113 }
1114
1115 /**
1116  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1117  * @dev_priv: device private
1118  */
1119 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1120 {
1121         struct pci_dev *pdev = dev_priv->drm.pdev;
1122
1123         if (pdev->msi_enabled)
1124                 pci_disable_msi(pdev);
1125
1126         pm_qos_remove_request(&dev_priv->pm_qos);
1127         i915_ggtt_cleanup_hw(dev_priv);
1128 }
1129
1130 /**
1131  * i915_driver_register - register the driver with the rest of the system
1132  * @dev_priv: device private
1133  *
1134  * Perform any steps necessary to make the driver available via kernel
1135  * internal or userspace interfaces.
1136  */
1137 static void i915_driver_register(struct drm_i915_private *dev_priv)
1138 {
1139         struct drm_device *dev = &dev_priv->drm;
1140
1141         i915_gem_shrinker_init(dev_priv);
1142
1143         /*
1144          * Notify a valid surface after modesetting,
1145          * when running inside a VM.
1146          */
1147         if (intel_vgpu_active(dev_priv))
1148                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1149
1150         /* Reveal our presence to userspace */
1151         if (drm_dev_register(dev, 0) == 0) {
1152                 i915_debugfs_register(dev_priv);
1153                 i915_guc_log_register(dev_priv);
1154                 i915_setup_sysfs(dev_priv);
1155
1156                 /* Depends on sysfs having been initialized */
1157                 i915_perf_register(dev_priv);
1158         } else
1159                 DRM_ERROR("Failed to register driver for userspace access!\n");
1160
1161         if (INTEL_INFO(dev_priv)->num_pipes) {
1162                 /* Must be done after probing outputs */
1163                 intel_opregion_register(dev_priv);
1164                 acpi_video_register();
1165         }
1166
1167         if (IS_GEN5(dev_priv))
1168                 intel_gpu_ips_init(dev_priv);
1169
1170         i915_audio_component_init(dev_priv);
1171
1172         /*
1173          * Some ports require correctly set-up hpd registers for detection to
1174          * work properly (leading to ghost connected connector status), e.g. VGA
1175          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1176          * irqs are fully enabled. We do it last so that the async config
1177          * cannot run before the connectors are registered.
1178          */
1179         intel_fbdev_initial_config_async(dev);
1180 }
1181
1182 /**
1183  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1184  * @dev_priv: device private
1185  */
1186 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1187 {
1188         i915_audio_component_cleanup(dev_priv);
1189
1190         intel_gpu_ips_teardown();
1191         acpi_video_unregister();
1192         intel_opregion_unregister(dev_priv);
1193
1194         i915_perf_unregister(dev_priv);
1195
1196         i915_teardown_sysfs(dev_priv);
1197         i915_guc_log_unregister(dev_priv);
1198         i915_debugfs_unregister(dev_priv);
1199         drm_dev_unregister(&dev_priv->drm);
1200
1201         i915_gem_shrinker_cleanup(dev_priv);
1202 }
1203
1204 /**
1205  * i915_driver_load - setup chip and create an initial config
1206  * @pdev: PCI device
1207  * @ent: matching PCI ID entry
1208  *
1209  * The driver load routine has to do several things:
1210  *   - drive output discovery via intel_modeset_init()
1211  *   - initialize the memory manager
1212  *   - allocate initial config memory
1213  *   - setup the DRM framebuffer with the allocated memory
1214  */
1215 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1216 {
1217         struct drm_i915_private *dev_priv;
1218         int ret;
1219
1220         if (i915.nuclear_pageflip)
1221                 driver.driver_features |= DRIVER_ATOMIC;
1222
1223         ret = -ENOMEM;
1224         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1225         if (dev_priv)
1226                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1227         if (ret) {
1228                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1229                 kfree(dev_priv);
1230                 return ret;
1231         }
1232
1233         dev_priv->drm.pdev = pdev;
1234         dev_priv->drm.dev_private = dev_priv;
1235
1236         ret = pci_enable_device(pdev);
1237         if (ret)
1238                 goto out_free_priv;
1239
1240         pci_set_drvdata(pdev, &dev_priv->drm);
1241
1242         ret = i915_driver_init_early(dev_priv, ent);
1243         if (ret < 0)
1244                 goto out_pci_disable;
1245
1246         intel_runtime_pm_get(dev_priv);
1247
1248         ret = i915_driver_init_mmio(dev_priv);
1249         if (ret < 0)
1250                 goto out_runtime_pm_put;
1251
1252         ret = i915_driver_init_hw(dev_priv);
1253         if (ret < 0)
1254                 goto out_cleanup_mmio;
1255
1256         /*
1257          * TODO: move the vblank init and parts of modeset init steps into one
1258          * of the i915_driver_init_/i915_driver_register functions according
1259          * to the role/effect of the given init step.
1260          */
1261         if (INTEL_INFO(dev_priv)->num_pipes) {
1262                 ret = drm_vblank_init(&dev_priv->drm,
1263                                       INTEL_INFO(dev_priv)->num_pipes);
1264                 if (ret)
1265                         goto out_cleanup_hw;
1266         }
1267
1268         ret = i915_load_modeset_init(&dev_priv->drm);
1269         if (ret < 0)
1270                 goto out_cleanup_vblank;
1271
1272         i915_driver_register(dev_priv);
1273
1274         intel_runtime_pm_enable(dev_priv);
1275
1276         dev_priv->ipc_enabled = false;
1277
1278         /* Everything is in place, we can now relax! */
1279         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1280                  driver.name, driver.major, driver.minor, driver.patchlevel,
1281                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1282         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1283                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1284         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1285                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1286
1287         intel_runtime_pm_put(dev_priv);
1288
1289         return 0;
1290
1291 out_cleanup_vblank:
1292         drm_vblank_cleanup(&dev_priv->drm);
1293 out_cleanup_hw:
1294         i915_driver_cleanup_hw(dev_priv);
1295 out_cleanup_mmio:
1296         i915_driver_cleanup_mmio(dev_priv);
1297 out_runtime_pm_put:
1298         intel_runtime_pm_put(dev_priv);
1299         i915_driver_cleanup_early(dev_priv);
1300 out_pci_disable:
1301         pci_disable_device(pdev);
1302 out_free_priv:
1303         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1304         drm_dev_unref(&dev_priv->drm);
1305         return ret;
1306 }
1307
1308 void i915_driver_unload(struct drm_device *dev)
1309 {
1310         struct drm_i915_private *dev_priv = to_i915(dev);
1311         struct pci_dev *pdev = dev_priv->drm.pdev;
1312         struct drm_modeset_acquire_ctx ctx;
1313         int ret;
1314
1315         intel_fbdev_fini(dev);
1316
1317         if (i915_gem_suspend(dev_priv))
1318                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1319
1320         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1321
1322         drm_modeset_acquire_init(&ctx, 0);
1323         while (1) {
1324                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
1325                 if (!ret)
1326                         ret = drm_atomic_helper_disable_all(dev, &ctx);
1327
1328                 if (ret != -EDEADLK)
1329                         break;
1330
1331                 drm_modeset_backoff(&ctx);
1332         }
1333
1334         if (ret)
1335                 DRM_ERROR("Disabling all crtc's during unload failed with %i\n", ret);
1336
1337         drm_modeset_drop_locks(&ctx);
1338         drm_modeset_acquire_fini(&ctx);
1339
1340         i915_driver_unregister(dev_priv);
1341
1342         drm_vblank_cleanup(dev);
1343
1344         intel_modeset_cleanup(dev);
1345
1346         /*
1347          * free the memory space allocated for the child device
1348          * config parsed from VBT
1349          */
1350         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1351                 kfree(dev_priv->vbt.child_dev);
1352                 dev_priv->vbt.child_dev = NULL;
1353                 dev_priv->vbt.child_dev_num = 0;
1354         }
1355         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1356         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1357         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1358         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1359
1360         vga_switcheroo_unregister_client(pdev);
1361         vga_client_register(pdev, NULL, NULL, NULL);
1362
1363         intel_csr_ucode_fini(dev_priv);
1364
1365         /* Free error state after interrupts are fully disabled. */
1366         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1367         i915_destroy_error_state(dev_priv);
1368
1369         /* Flush any outstanding unpin_work. */
1370         drain_workqueue(dev_priv->wq);
1371
1372         intel_guc_fini(dev_priv);
1373         intel_huc_fini(dev_priv);
1374         i915_gem_fini(dev_priv);
1375         intel_fbc_cleanup_cfb(dev_priv);
1376
1377         intel_power_domains_fini(dev_priv);
1378
1379         i915_driver_cleanup_hw(dev_priv);
1380         i915_driver_cleanup_mmio(dev_priv);
1381
1382         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1383
1384         i915_driver_cleanup_early(dev_priv);
1385 }
1386
1387 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1388 {
1389         int ret;
1390
1391         ret = i915_gem_open(dev, file);
1392         if (ret)
1393                 return ret;
1394
1395         return 0;
1396 }
1397
1398 /**
1399  * i915_driver_lastclose - clean up after all DRM clients have exited
1400  * @dev: DRM device
1401  *
1402  * Take care of cleaning up after all DRM clients have exited.  In the
1403  * mode setting case, we want to restore the kernel's initial mode (just
1404  * in case the last client left us in a bad state).
1405  *
1406  * Additionally, in the non-mode setting case, we'll tear down the GTT
1407  * and DMA structures, since the kernel won't be using them, and clea
1408  * up any GEM state.
1409  */
1410 static void i915_driver_lastclose(struct drm_device *dev)
1411 {
1412         intel_fbdev_restore_mode(dev);
1413         vga_switcheroo_process_delayed_switch();
1414 }
1415
1416 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1417 {
1418         mutex_lock(&dev->struct_mutex);
1419         i915_gem_context_close(dev, file);
1420         i915_gem_release(dev, file);
1421         mutex_unlock(&dev->struct_mutex);
1422 }
1423
1424 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1425 {
1426         struct drm_i915_file_private *file_priv = file->driver_priv;
1427
1428         kfree(file_priv);
1429 }
1430
1431 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1432 {
1433         struct drm_device *dev = &dev_priv->drm;
1434         struct intel_encoder *encoder;
1435
1436         drm_modeset_lock_all(dev);
1437         for_each_intel_encoder(dev, encoder)
1438                 if (encoder->suspend)
1439                         encoder->suspend(encoder);
1440         drm_modeset_unlock_all(dev);
1441 }
1442
1443 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1444                               bool rpm_resume);
1445 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1446
1447 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1448 {
1449 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1450         if (acpi_target_system_state() < ACPI_STATE_S3)
1451                 return true;
1452 #endif
1453         return false;
1454 }
1455
1456 static int i915_drm_suspend(struct drm_device *dev)
1457 {
1458         struct drm_i915_private *dev_priv = to_i915(dev);
1459         struct pci_dev *pdev = dev_priv->drm.pdev;
1460         pci_power_t opregion_target_state;
1461         int error;
1462
1463         /* ignore lid events during suspend */
1464         mutex_lock(&dev_priv->modeset_restore_lock);
1465         dev_priv->modeset_restore = MODESET_SUSPENDED;
1466         mutex_unlock(&dev_priv->modeset_restore_lock);
1467
1468         disable_rpm_wakeref_asserts(dev_priv);
1469
1470         /* We do a lot of poking in a lot of registers, make sure they work
1471          * properly. */
1472         intel_display_set_init_power(dev_priv, true);
1473
1474         drm_kms_helper_poll_disable(dev);
1475
1476         pci_save_state(pdev);
1477
1478         error = i915_gem_suspend(dev_priv);
1479         if (error) {
1480                 dev_err(&pdev->dev,
1481                         "GEM idle failed, resume might fail\n");
1482                 goto out;
1483         }
1484
1485         intel_guc_suspend(dev_priv);
1486
1487         intel_display_suspend(dev);
1488
1489         intel_dp_mst_suspend(dev);
1490
1491         intel_runtime_pm_disable_interrupts(dev_priv);
1492         intel_hpd_cancel_work(dev_priv);
1493
1494         intel_suspend_encoders(dev_priv);
1495
1496         intel_suspend_hw(dev_priv);
1497
1498         i915_gem_suspend_gtt_mappings(dev_priv);
1499
1500         i915_save_state(dev_priv);
1501
1502         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1503         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1504
1505         intel_uncore_forcewake_reset(dev_priv, false);
1506         intel_opregion_unregister(dev_priv);
1507
1508         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1509
1510         dev_priv->suspend_count++;
1511
1512         intel_csr_ucode_suspend(dev_priv);
1513
1514 out:
1515         enable_rpm_wakeref_asserts(dev_priv);
1516
1517         return error;
1518 }
1519
1520 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1521 {
1522         struct drm_i915_private *dev_priv = to_i915(dev);
1523         struct pci_dev *pdev = dev_priv->drm.pdev;
1524         bool fw_csr;
1525         int ret;
1526
1527         disable_rpm_wakeref_asserts(dev_priv);
1528
1529         intel_display_set_init_power(dev_priv, false);
1530
1531         fw_csr = !IS_GEN9_LP(dev_priv) &&
1532                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1533         /*
1534          * In case of firmware assisted context save/restore don't manually
1535          * deinit the power domains. This also means the CSR/DMC firmware will
1536          * stay active, it will power down any HW resources as required and
1537          * also enable deeper system power states that would be blocked if the
1538          * firmware was inactive.
1539          */
1540         if (!fw_csr)
1541                 intel_power_domains_suspend(dev_priv);
1542
1543         ret = 0;
1544         if (IS_GEN9_LP(dev_priv))
1545                 bxt_enable_dc9(dev_priv);
1546         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1547                 hsw_enable_pc8(dev_priv);
1548         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1549                 ret = vlv_suspend_complete(dev_priv);
1550
1551         if (ret) {
1552                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1553                 if (!fw_csr)
1554                         intel_power_domains_init_hw(dev_priv, true);
1555
1556                 goto out;
1557         }
1558
1559         pci_disable_device(pdev);
1560         /*
1561          * During hibernation on some platforms the BIOS may try to access
1562          * the device even though it's already in D3 and hang the machine. So
1563          * leave the device in D0 on those platforms and hope the BIOS will
1564          * power down the device properly. The issue was seen on multiple old
1565          * GENs with different BIOS vendors, so having an explicit blacklist
1566          * is inpractical; apply the workaround on everything pre GEN6. The
1567          * platforms where the issue was seen:
1568          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1569          * Fujitsu FSC S7110
1570          * Acer Aspire 1830T
1571          */
1572         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1573                 pci_set_power_state(pdev, PCI_D3hot);
1574
1575         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1576
1577 out:
1578         enable_rpm_wakeref_asserts(dev_priv);
1579
1580         return ret;
1581 }
1582
1583 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1584 {
1585         int error;
1586
1587         if (!dev) {
1588                 DRM_ERROR("dev: %p\n", dev);
1589                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1590                 return -ENODEV;
1591         }
1592
1593         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1594                          state.event != PM_EVENT_FREEZE))
1595                 return -EINVAL;
1596
1597         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1598                 return 0;
1599
1600         error = i915_drm_suspend(dev);
1601         if (error)
1602                 return error;
1603
1604         return i915_drm_suspend_late(dev, false);
1605 }
1606
1607 static int i915_drm_resume(struct drm_device *dev)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(dev);
1610         int ret;
1611
1612         disable_rpm_wakeref_asserts(dev_priv);
1613         intel_sanitize_gt_powersave(dev_priv);
1614
1615         ret = i915_ggtt_enable_hw(dev_priv);
1616         if (ret)
1617                 DRM_ERROR("failed to re-enable GGTT\n");
1618
1619         intel_csr_ucode_resume(dev_priv);
1620
1621         i915_gem_resume(dev_priv);
1622
1623         i915_restore_state(dev_priv);
1624         intel_pps_unlock_regs_wa(dev_priv);
1625         intel_opregion_setup(dev_priv);
1626
1627         intel_init_pch_refclk(dev_priv);
1628
1629         /*
1630          * Interrupts have to be enabled before any batches are run. If not the
1631          * GPU will hang. i915_gem_init_hw() will initiate batches to
1632          * update/restore the context.
1633          *
1634          * drm_mode_config_reset() needs AUX interrupts.
1635          *
1636          * Modeset enabling in intel_modeset_init_hw() also needs working
1637          * interrupts.
1638          */
1639         intel_runtime_pm_enable_interrupts(dev_priv);
1640
1641         drm_mode_config_reset(dev);
1642
1643         mutex_lock(&dev->struct_mutex);
1644         if (i915_gem_init_hw(dev_priv)) {
1645                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1646                 i915_gem_set_wedged(dev_priv);
1647         }
1648         mutex_unlock(&dev->struct_mutex);
1649
1650         intel_guc_resume(dev_priv);
1651
1652         intel_modeset_init_hw(dev);
1653
1654         spin_lock_irq(&dev_priv->irq_lock);
1655         if (dev_priv->display.hpd_irq_setup)
1656                 dev_priv->display.hpd_irq_setup(dev_priv);
1657         spin_unlock_irq(&dev_priv->irq_lock);
1658
1659         intel_dp_mst_resume(dev);
1660
1661         intel_display_resume(dev);
1662
1663         drm_kms_helper_poll_enable(dev);
1664
1665         /*
1666          * ... but also need to make sure that hotplug processing
1667          * doesn't cause havoc. Like in the driver load code we don't
1668          * bother with the tiny race here where we might loose hotplug
1669          * notifications.
1670          * */
1671         intel_hpd_init(dev_priv);
1672
1673         intel_opregion_register(dev_priv);
1674
1675         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1676
1677         mutex_lock(&dev_priv->modeset_restore_lock);
1678         dev_priv->modeset_restore = MODESET_DONE;
1679         mutex_unlock(&dev_priv->modeset_restore_lock);
1680
1681         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1682
1683         intel_autoenable_gt_powersave(dev_priv);
1684
1685         enable_rpm_wakeref_asserts(dev_priv);
1686
1687         return 0;
1688 }
1689
1690 static int i915_drm_resume_early(struct drm_device *dev)
1691 {
1692         struct drm_i915_private *dev_priv = to_i915(dev);
1693         struct pci_dev *pdev = dev_priv->drm.pdev;
1694         int ret;
1695
1696         /*
1697          * We have a resume ordering issue with the snd-hda driver also
1698          * requiring our device to be power up. Due to the lack of a
1699          * parent/child relationship we currently solve this with an early
1700          * resume hook.
1701          *
1702          * FIXME: This should be solved with a special hdmi sink device or
1703          * similar so that power domains can be employed.
1704          */
1705
1706         /*
1707          * Note that we need to set the power state explicitly, since we
1708          * powered off the device during freeze and the PCI core won't power
1709          * it back up for us during thaw. Powering off the device during
1710          * freeze is not a hard requirement though, and during the
1711          * suspend/resume phases the PCI core makes sure we get here with the
1712          * device powered on. So in case we change our freeze logic and keep
1713          * the device powered we can also remove the following set power state
1714          * call.
1715          */
1716         ret = pci_set_power_state(pdev, PCI_D0);
1717         if (ret) {
1718                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1719                 goto out;
1720         }
1721
1722         /*
1723          * Note that pci_enable_device() first enables any parent bridge
1724          * device and only then sets the power state for this device. The
1725          * bridge enabling is a nop though, since bridge devices are resumed
1726          * first. The order of enabling power and enabling the device is
1727          * imposed by the PCI core as described above, so here we preserve the
1728          * same order for the freeze/thaw phases.
1729          *
1730          * TODO: eventually we should remove pci_disable_device() /
1731          * pci_enable_enable_device() from suspend/resume. Due to how they
1732          * depend on the device enable refcount we can't anyway depend on them
1733          * disabling/enabling the device.
1734          */
1735         if (pci_enable_device(pdev)) {
1736                 ret = -EIO;
1737                 goto out;
1738         }
1739
1740         pci_set_master(pdev);
1741
1742         disable_rpm_wakeref_asserts(dev_priv);
1743
1744         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1745                 ret = vlv_resume_prepare(dev_priv, false);
1746         if (ret)
1747                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1748                           ret);
1749
1750         intel_uncore_early_sanitize(dev_priv, true);
1751
1752         if (IS_GEN9_LP(dev_priv)) {
1753                 if (!dev_priv->suspended_to_idle)
1754                         gen9_sanitize_dc_state(dev_priv);
1755                 bxt_disable_dc9(dev_priv);
1756         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1757                 hsw_disable_pc8(dev_priv);
1758         }
1759
1760         intel_uncore_sanitize(dev_priv);
1761
1762         if (IS_GEN9_LP(dev_priv) ||
1763             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1764                 intel_power_domains_init_hw(dev_priv, true);
1765
1766         i915_gem_sanitize(dev_priv);
1767
1768         enable_rpm_wakeref_asserts(dev_priv);
1769
1770 out:
1771         dev_priv->suspended_to_idle = false;
1772
1773         return ret;
1774 }
1775
1776 static int i915_resume_switcheroo(struct drm_device *dev)
1777 {
1778         int ret;
1779
1780         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1781                 return 0;
1782
1783         ret = i915_drm_resume_early(dev);
1784         if (ret)
1785                 return ret;
1786
1787         return i915_drm_resume(dev);
1788 }
1789
1790 /**
1791  * i915_reset - reset chip after a hang
1792  * @dev_priv: device private to reset
1793  *
1794  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1795  * on failure.
1796  *
1797  * Caller must hold the struct_mutex.
1798  *
1799  * Procedure is fairly simple:
1800  *   - reset the chip using the reset reg
1801  *   - re-init context state
1802  *   - re-init hardware status page
1803  *   - re-init ring buffer
1804  *   - re-init interrupt state
1805  *   - re-init display
1806  */
1807 void i915_reset(struct drm_i915_private *dev_priv)
1808 {
1809         struct i915_gpu_error *error = &dev_priv->gpu_error;
1810         int ret;
1811
1812         lockdep_assert_held(&dev_priv->drm.struct_mutex);
1813
1814         if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
1815                 return;
1816
1817         /* Clear any previous failed attempts at recovery. Time to try again. */
1818         __clear_bit(I915_WEDGED, &error->flags);
1819         error->reset_count++;
1820
1821         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1822         disable_irq(dev_priv->drm.irq);
1823         ret = i915_gem_reset_prepare(dev_priv);
1824         if (ret) {
1825                 DRM_ERROR("GPU recovery failed\n");
1826                 intel_gpu_reset(dev_priv, ALL_ENGINES);
1827                 goto error;
1828         }
1829
1830         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1831         if (ret) {
1832                 if (ret != -ENODEV)
1833                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1834                 else
1835                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1836                 goto error;
1837         }
1838
1839         i915_gem_reset_finish(dev_priv);
1840         intel_overlay_reset(dev_priv);
1841
1842         /* Ok, now get things going again... */
1843
1844         /*
1845          * Everything depends on having the GTT running, so we need to start
1846          * there.  Fortunately we don't need to do this unless we reset the
1847          * chip at a PCI level.
1848          *
1849          * Next we need to restore the context, but we don't use those
1850          * yet either...
1851          *
1852          * Ring buffer needs to be re-initialized in the KMS case, or if X
1853          * was running at the time of the reset (i.e. we weren't VT
1854          * switched away).
1855          */
1856         ret = i915_gem_init_hw(dev_priv);
1857         if (ret) {
1858                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1859                 goto error;
1860         }
1861
1862         i915_queue_hangcheck(dev_priv);
1863
1864 wakeup:
1865         enable_irq(dev_priv->drm.irq);
1866         wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1867         return;
1868
1869 error:
1870         i915_gem_set_wedged(dev_priv);
1871         goto wakeup;
1872 }
1873
1874 static int i915_pm_suspend(struct device *kdev)
1875 {
1876         struct pci_dev *pdev = to_pci_dev(kdev);
1877         struct drm_device *dev = pci_get_drvdata(pdev);
1878
1879         if (!dev) {
1880                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1881                 return -ENODEV;
1882         }
1883
1884         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1885                 return 0;
1886
1887         return i915_drm_suspend(dev);
1888 }
1889
1890 static int i915_pm_suspend_late(struct device *kdev)
1891 {
1892         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1893
1894         /*
1895          * We have a suspend ordering issue with the snd-hda driver also
1896          * requiring our device to be power up. Due to the lack of a
1897          * parent/child relationship we currently solve this with an late
1898          * suspend hook.
1899          *
1900          * FIXME: This should be solved with a special hdmi sink device or
1901          * similar so that power domains can be employed.
1902          */
1903         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1904                 return 0;
1905
1906         return i915_drm_suspend_late(dev, false);
1907 }
1908
1909 static int i915_pm_poweroff_late(struct device *kdev)
1910 {
1911         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1912
1913         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1914                 return 0;
1915
1916         return i915_drm_suspend_late(dev, true);
1917 }
1918
1919 static int i915_pm_resume_early(struct device *kdev)
1920 {
1921         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1922
1923         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1924                 return 0;
1925
1926         return i915_drm_resume_early(dev);
1927 }
1928
1929 static int i915_pm_resume(struct device *kdev)
1930 {
1931         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1932
1933         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1934                 return 0;
1935
1936         return i915_drm_resume(dev);
1937 }
1938
1939 /* freeze: before creating the hibernation_image */
1940 static int i915_pm_freeze(struct device *kdev)
1941 {
1942         int ret;
1943
1944         ret = i915_pm_suspend(kdev);
1945         if (ret)
1946                 return ret;
1947
1948         ret = i915_gem_freeze(kdev_to_i915(kdev));
1949         if (ret)
1950                 return ret;
1951
1952         return 0;
1953 }
1954
1955 static int i915_pm_freeze_late(struct device *kdev)
1956 {
1957         int ret;
1958
1959         ret = i915_pm_suspend_late(kdev);
1960         if (ret)
1961                 return ret;
1962
1963         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1964         if (ret)
1965                 return ret;
1966
1967         return 0;
1968 }
1969
1970 /* thaw: called after creating the hibernation image, but before turning off. */
1971 static int i915_pm_thaw_early(struct device *kdev)
1972 {
1973         return i915_pm_resume_early(kdev);
1974 }
1975
1976 static int i915_pm_thaw(struct device *kdev)
1977 {
1978         return i915_pm_resume(kdev);
1979 }
1980
1981 /* restore: called after loading the hibernation image. */
1982 static int i915_pm_restore_early(struct device *kdev)
1983 {
1984         return i915_pm_resume_early(kdev);
1985 }
1986
1987 static int i915_pm_restore(struct device *kdev)
1988 {
1989         return i915_pm_resume(kdev);
1990 }
1991
1992 /*
1993  * Save all Gunit registers that may be lost after a D3 and a subsequent
1994  * S0i[R123] transition. The list of registers needing a save/restore is
1995  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1996  * registers in the following way:
1997  * - Driver: saved/restored by the driver
1998  * - Punit : saved/restored by the Punit firmware
1999  * - No, w/o marking: no need to save/restore, since the register is R/O or
2000  *                    used internally by the HW in a way that doesn't depend
2001  *                    keeping the content across a suspend/resume.
2002  * - Debug : used for debugging
2003  *
2004  * We save/restore all registers marked with 'Driver', with the following
2005  * exceptions:
2006  * - Registers out of use, including also registers marked with 'Debug'.
2007  *   These have no effect on the driver's operation, so we don't save/restore
2008  *   them to reduce the overhead.
2009  * - Registers that are fully setup by an initialization function called from
2010  *   the resume path. For example many clock gating and RPS/RC6 registers.
2011  * - Registers that provide the right functionality with their reset defaults.
2012  *
2013  * TODO: Except for registers that based on the above 3 criteria can be safely
2014  * ignored, we save/restore all others, practically treating the HW context as
2015  * a black-box for the driver. Further investigation is needed to reduce the
2016  * saved/restored registers even further, by following the same 3 criteria.
2017  */
2018 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2019 {
2020         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2021         int i;
2022
2023         /* GAM 0x4000-0x4770 */
2024         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2025         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2026         s->arb_mode             = I915_READ(ARB_MODE);
2027         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2028         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2029
2030         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2031                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2032
2033         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2034         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2035
2036         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2037         s->ecochk               = I915_READ(GAM_ECOCHK);
2038         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2039         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2040
2041         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2042
2043         /* MBC 0x9024-0x91D0, 0x8500 */
2044         s->g3dctl               = I915_READ(VLV_G3DCTL);
2045         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2046         s->mbctl                = I915_READ(GEN6_MBCTL);
2047
2048         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2049         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2050         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2051         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2052         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2053         s->rstctl               = I915_READ(GEN6_RSTCTL);
2054         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2055
2056         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2057         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2058         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2059         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2060         s->ecobus               = I915_READ(ECOBUS);
2061         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2062         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2063         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2064         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2065         s->rcedata              = I915_READ(VLV_RCEDATA);
2066         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2067
2068         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2069         s->gt_imr               = I915_READ(GTIMR);
2070         s->gt_ier               = I915_READ(GTIER);
2071         s->pm_imr               = I915_READ(GEN6_PMIMR);
2072         s->pm_ier               = I915_READ(GEN6_PMIER);
2073
2074         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2075                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2076
2077         /* GT SA CZ domain, 0x100000-0x138124 */
2078         s->tilectl              = I915_READ(TILECTL);
2079         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2080         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2081         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2082         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2083
2084         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2085         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2086         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2087         s->pcbr                 = I915_READ(VLV_PCBR);
2088         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2089
2090         /*
2091          * Not saving any of:
2092          * DFT,         0x9800-0x9EC0
2093          * SARB,        0xB000-0xB1FC
2094          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2095          * PCI CFG
2096          */
2097 }
2098
2099 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2100 {
2101         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2102         u32 val;
2103         int i;
2104
2105         /* GAM 0x4000-0x4770 */
2106         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2107         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2108         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2109         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2110         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2111
2112         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2113                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2114
2115         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2116         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2117
2118         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2119         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2120         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2121         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2122
2123         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2124
2125         /* MBC 0x9024-0x91D0, 0x8500 */
2126         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2127         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2128         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2129
2130         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2131         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2132         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2133         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2134         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2135         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2136         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2137
2138         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2139         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2140         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2141         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2142         I915_WRITE(ECOBUS,              s->ecobus);
2143         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2144         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2145         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2146         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2147         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2148         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2149
2150         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2151         I915_WRITE(GTIMR,               s->gt_imr);
2152         I915_WRITE(GTIER,               s->gt_ier);
2153         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2154         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2155
2156         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2157                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2158
2159         /* GT SA CZ domain, 0x100000-0x138124 */
2160         I915_WRITE(TILECTL,                     s->tilectl);
2161         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2162         /*
2163          * Preserve the GT allow wake and GFX force clock bit, they are not
2164          * be restored, as they are used to control the s0ix suspend/resume
2165          * sequence by the caller.
2166          */
2167         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2168         val &= VLV_GTLC_ALLOWWAKEREQ;
2169         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2170         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2171
2172         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2173         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2174         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2175         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2176
2177         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2178
2179         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2180         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2181         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2182         I915_WRITE(VLV_PCBR,                    s->pcbr);
2183         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2184 }
2185
2186 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2187 {
2188         u32 val;
2189         int err;
2190
2191         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2192         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2193         if (force_on)
2194                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2195         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2196
2197         if (!force_on)
2198                 return 0;
2199
2200         err = intel_wait_for_register(dev_priv,
2201                                       VLV_GTLC_SURVIVABILITY_REG,
2202                                       VLV_GFX_CLK_STATUS_BIT,
2203                                       VLV_GFX_CLK_STATUS_BIT,
2204                                       20);
2205         if (err)
2206                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2207                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2208
2209         return err;
2210 }
2211
2212 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2213 {
2214         u32 val;
2215         int err = 0;
2216
2217         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2218         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2219         if (allow)
2220                 val |= VLV_GTLC_ALLOWWAKEREQ;
2221         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2222         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2223
2224         err = intel_wait_for_register(dev_priv,
2225                                       VLV_GTLC_PW_STATUS,
2226                                       VLV_GTLC_ALLOWWAKEACK,
2227                                       allow,
2228                                       1);
2229         if (err)
2230                 DRM_ERROR("timeout disabling GT waking\n");
2231
2232         return err;
2233 }
2234
2235 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2236                                  bool wait_for_on)
2237 {
2238         u32 mask;
2239         u32 val;
2240         int err;
2241
2242         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2243         val = wait_for_on ? mask : 0;
2244         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2245                 return 0;
2246
2247         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2248                       onoff(wait_for_on),
2249                       I915_READ(VLV_GTLC_PW_STATUS));
2250
2251         /*
2252          * RC6 transitioning can be delayed up to 2 msec (see
2253          * valleyview_enable_rps), use 3 msec for safety.
2254          */
2255         err = intel_wait_for_register(dev_priv,
2256                                       VLV_GTLC_PW_STATUS, mask, val,
2257                                       3);
2258         if (err)
2259                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2260                           onoff(wait_for_on));
2261
2262         return err;
2263 }
2264
2265 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2266 {
2267         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2268                 return;
2269
2270         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2271         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2272 }
2273
2274 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2275 {
2276         u32 mask;
2277         int err;
2278
2279         /*
2280          * Bspec defines the following GT well on flags as debug only, so
2281          * don't treat them as hard failures.
2282          */
2283         (void)vlv_wait_for_gt_wells(dev_priv, false);
2284
2285         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2286         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2287
2288         vlv_check_no_gt_access(dev_priv);
2289
2290         err = vlv_force_gfx_clock(dev_priv, true);
2291         if (err)
2292                 goto err1;
2293
2294         err = vlv_allow_gt_wake(dev_priv, false);
2295         if (err)
2296                 goto err2;
2297
2298         if (!IS_CHERRYVIEW(dev_priv))
2299                 vlv_save_gunit_s0ix_state(dev_priv);
2300
2301         err = vlv_force_gfx_clock(dev_priv, false);
2302         if (err)
2303                 goto err2;
2304
2305         return 0;
2306
2307 err2:
2308         /* For safety always re-enable waking and disable gfx clock forcing */
2309         vlv_allow_gt_wake(dev_priv, true);
2310 err1:
2311         vlv_force_gfx_clock(dev_priv, false);
2312
2313         return err;
2314 }
2315
2316 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2317                                 bool rpm_resume)
2318 {
2319         int err;
2320         int ret;
2321
2322         /*
2323          * If any of the steps fail just try to continue, that's the best we
2324          * can do at this point. Return the first error code (which will also
2325          * leave RPM permanently disabled).
2326          */
2327         ret = vlv_force_gfx_clock(dev_priv, true);
2328
2329         if (!IS_CHERRYVIEW(dev_priv))
2330                 vlv_restore_gunit_s0ix_state(dev_priv);
2331
2332         err = vlv_allow_gt_wake(dev_priv, true);
2333         if (!ret)
2334                 ret = err;
2335
2336         err = vlv_force_gfx_clock(dev_priv, false);
2337         if (!ret)
2338                 ret = err;
2339
2340         vlv_check_no_gt_access(dev_priv);
2341
2342         if (rpm_resume)
2343                 intel_init_clock_gating(dev_priv);
2344
2345         return ret;
2346 }
2347
2348 static int intel_runtime_suspend(struct device *kdev)
2349 {
2350         struct pci_dev *pdev = to_pci_dev(kdev);
2351         struct drm_device *dev = pci_get_drvdata(pdev);
2352         struct drm_i915_private *dev_priv = to_i915(dev);
2353         int ret;
2354
2355         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2356                 return -ENODEV;
2357
2358         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2359                 return -ENODEV;
2360
2361         DRM_DEBUG_KMS("Suspending device\n");
2362
2363         disable_rpm_wakeref_asserts(dev_priv);
2364
2365         /*
2366          * We are safe here against re-faults, since the fault handler takes
2367          * an RPM reference.
2368          */
2369         i915_gem_runtime_suspend(dev_priv);
2370
2371         intel_guc_suspend(dev_priv);
2372
2373         intel_runtime_pm_disable_interrupts(dev_priv);
2374
2375         ret = 0;
2376         if (IS_GEN9_LP(dev_priv)) {
2377                 bxt_display_core_uninit(dev_priv);
2378                 bxt_enable_dc9(dev_priv);
2379         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2380                 hsw_enable_pc8(dev_priv);
2381         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2382                 ret = vlv_suspend_complete(dev_priv);
2383         }
2384
2385         if (ret) {
2386                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2387                 intel_runtime_pm_enable_interrupts(dev_priv);
2388
2389                 enable_rpm_wakeref_asserts(dev_priv);
2390
2391                 return ret;
2392         }
2393
2394         intel_uncore_forcewake_reset(dev_priv, false);
2395
2396         enable_rpm_wakeref_asserts(dev_priv);
2397         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2398
2399         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2400                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2401
2402         dev_priv->pm.suspended = true;
2403
2404         /*
2405          * FIXME: We really should find a document that references the arguments
2406          * used below!
2407          */
2408         if (IS_BROADWELL(dev_priv)) {
2409                 /*
2410                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2411                  * being detected, and the call we do at intel_runtime_resume()
2412                  * won't be able to restore them. Since PCI_D3hot matches the
2413                  * actual specification and appears to be working, use it.
2414                  */
2415                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2416         } else {
2417                 /*
2418                  * current versions of firmware which depend on this opregion
2419                  * notification have repurposed the D1 definition to mean
2420                  * "runtime suspended" vs. what you would normally expect (D3)
2421                  * to distinguish it from notifications that might be sent via
2422                  * the suspend path.
2423                  */
2424                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2425         }
2426
2427         assert_forcewakes_inactive(dev_priv);
2428
2429         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2430                 intel_hpd_poll_init(dev_priv);
2431
2432         DRM_DEBUG_KMS("Device suspended\n");
2433         return 0;
2434 }
2435
2436 static int intel_runtime_resume(struct device *kdev)
2437 {
2438         struct pci_dev *pdev = to_pci_dev(kdev);
2439         struct drm_device *dev = pci_get_drvdata(pdev);
2440         struct drm_i915_private *dev_priv = to_i915(dev);
2441         int ret = 0;
2442
2443         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2444                 return -ENODEV;
2445
2446         DRM_DEBUG_KMS("Resuming device\n");
2447
2448         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2449         disable_rpm_wakeref_asserts(dev_priv);
2450
2451         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2452         dev_priv->pm.suspended = false;
2453         if (intel_uncore_unclaimed_mmio(dev_priv))
2454                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2455
2456         intel_guc_resume(dev_priv);
2457
2458         if (IS_GEN6(dev_priv))
2459                 intel_init_pch_refclk(dev_priv);
2460
2461         if (IS_GEN9_LP(dev_priv)) {
2462                 bxt_disable_dc9(dev_priv);
2463                 bxt_display_core_init(dev_priv, true);
2464                 if (dev_priv->csr.dmc_payload &&
2465                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2466                         gen9_enable_dc5(dev_priv);
2467         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2468                 hsw_disable_pc8(dev_priv);
2469         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2470                 ret = vlv_resume_prepare(dev_priv, true);
2471         }
2472
2473         /*
2474          * No point of rolling back things in case of an error, as the best
2475          * we can do is to hope that things will still work (and disable RPM).
2476          */
2477         i915_gem_init_swizzling(dev_priv);
2478         i915_gem_restore_fences(dev_priv);
2479
2480         intel_runtime_pm_enable_interrupts(dev_priv);
2481
2482         /*
2483          * On VLV/CHV display interrupts are part of the display
2484          * power well, so hpd is reinitialized from there. For
2485          * everyone else do it here.
2486          */
2487         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2488                 intel_hpd_init(dev_priv);
2489
2490         enable_rpm_wakeref_asserts(dev_priv);
2491
2492         if (ret)
2493                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2494         else
2495                 DRM_DEBUG_KMS("Device resumed\n");
2496
2497         return ret;
2498 }
2499
2500 const struct dev_pm_ops i915_pm_ops = {
2501         /*
2502          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2503          * PMSG_RESUME]
2504          */
2505         .suspend = i915_pm_suspend,
2506         .suspend_late = i915_pm_suspend_late,
2507         .resume_early = i915_pm_resume_early,
2508         .resume = i915_pm_resume,
2509
2510         /*
2511          * S4 event handlers
2512          * @freeze, @freeze_late    : called (1) before creating the
2513          *                            hibernation image [PMSG_FREEZE] and
2514          *                            (2) after rebooting, before restoring
2515          *                            the image [PMSG_QUIESCE]
2516          * @thaw, @thaw_early       : called (1) after creating the hibernation
2517          *                            image, before writing it [PMSG_THAW]
2518          *                            and (2) after failing to create or
2519          *                            restore the image [PMSG_RECOVER]
2520          * @poweroff, @poweroff_late: called after writing the hibernation
2521          *                            image, before rebooting [PMSG_HIBERNATE]
2522          * @restore, @restore_early : called after rebooting and restoring the
2523          *                            hibernation image [PMSG_RESTORE]
2524          */
2525         .freeze = i915_pm_freeze,
2526         .freeze_late = i915_pm_freeze_late,
2527         .thaw_early = i915_pm_thaw_early,
2528         .thaw = i915_pm_thaw,
2529         .poweroff = i915_pm_suspend,
2530         .poweroff_late = i915_pm_poweroff_late,
2531         .restore_early = i915_pm_restore_early,
2532         .restore = i915_pm_restore,
2533
2534         /* S0ix (via runtime suspend) event handlers */
2535         .runtime_suspend = intel_runtime_suspend,
2536         .runtime_resume = intel_runtime_resume,
2537 };
2538
2539 static const struct vm_operations_struct i915_gem_vm_ops = {
2540         .fault = i915_gem_fault,
2541         .open = drm_gem_vm_open,
2542         .close = drm_gem_vm_close,
2543 };
2544
2545 static const struct file_operations i915_driver_fops = {
2546         .owner = THIS_MODULE,
2547         .open = drm_open,
2548         .release = drm_release,
2549         .unlocked_ioctl = drm_ioctl,
2550         .mmap = drm_gem_mmap,
2551         .poll = drm_poll,
2552         .read = drm_read,
2553         .compat_ioctl = i915_compat_ioctl,
2554         .llseek = noop_llseek,
2555 };
2556
2557 static int
2558 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2559                           struct drm_file *file)
2560 {
2561         return -ENODEV;
2562 }
2563
2564 static const struct drm_ioctl_desc i915_ioctls[] = {
2565         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2566         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2567         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2568         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2569         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2570         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2571         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2572         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2573         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2574         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2575         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2576         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2577         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2578         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2579         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2580         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2581         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2582         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2583         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2584         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2585         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2586         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2587         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2588         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2589         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2590         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2591         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2592         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2593         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2594         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2595         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2596         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2597         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2598         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2599         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2600         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2601         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2602         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2603         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2604         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2605         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2606         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2607         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2608         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2609         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2610         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2611         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2612         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2613         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2614         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2615         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2616         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2617         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2618 };
2619
2620 static struct drm_driver driver = {
2621         /* Don't use MTRRs here; the Xserver or userspace app should
2622          * deal with them for Intel hardware.
2623          */
2624         .driver_features =
2625             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2626             DRIVER_RENDER | DRIVER_MODESET,
2627         .open = i915_driver_open,
2628         .lastclose = i915_driver_lastclose,
2629         .preclose = i915_driver_preclose,
2630         .postclose = i915_driver_postclose,
2631         .set_busid = drm_pci_set_busid,
2632
2633         .gem_close_object = i915_gem_close_object,
2634         .gem_free_object_unlocked = i915_gem_free_object,
2635         .gem_vm_ops = &i915_gem_vm_ops,
2636
2637         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2638         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2639         .gem_prime_export = i915_gem_prime_export,
2640         .gem_prime_import = i915_gem_prime_import,
2641
2642         .dumb_create = i915_gem_dumb_create,
2643         .dumb_map_offset = i915_gem_mmap_gtt,
2644         .dumb_destroy = drm_gem_dumb_destroy,
2645         .ioctls = i915_ioctls,
2646         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2647         .fops = &i915_driver_fops,
2648         .name = DRIVER_NAME,
2649         .desc = DRIVER_DESC,
2650         .date = DRIVER_DATE,
2651         .major = DRIVER_MAJOR,
2652         .minor = DRIVER_MINOR,
2653         .patchlevel = DRIVER_PATCHLEVEL,
2654 };