drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52
  53 static struct drm_driver driver;
  54
  55 static unsigned int i915_load_fail_count;
  56
  57 bool __i915_inject_load_failure(const char *func, int line)
  58 {
  59         if (i915_load_fail_count >= i915.inject_load_failure)
  60                 return false;
  61
  62         if (++i915_load_fail_count == i915.inject_load_failure) {
  63                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64                          i915.inject_load_failure, func, line);
  65                 return true;
  66         }
  67
  68         return false;
  69 }
  70
  71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73                     "providing the dmesg log by booting with drm.debug=0xf"
  74
  75 void
  76 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77               const char *fmt, ...)
  78 {
  79         static bool shown_bug_once;
  80         struct device *dev = dev_priv->drm.dev;
  81         bool is_error = level[1] <= KERN_ERR[1];
  82         bool is_debug = level[1] == KERN_DEBUG[1];
  83         struct va_format vaf;
  84         va_list args;
  85
  86         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87                 return;
  88
  89         va_start(args, fmt);
  90
  91         vaf.fmt = fmt;
  92         vaf.va = &args;
  93
  94         dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
  95                    __builtin_return_address(0), &vaf);
  96
  97         if (is_error && !shown_bug_once) {
  98                 dev_notice(dev, "%s", FDO_BUG_MSG);
  99                 shown_bug_once = true;
 100         }
 101
 102         va_end(args);
 103 }
 104
 105 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106 {
 107         return i915.inject_load_failure &&
 108                i915_load_fail_count == i915.inject_load_failure;
 109 }
 110
 111 #define i915_load_error(dev_priv, fmt, ...)                                  \
 112         __i915_printk(dev_priv,                                              \
 113                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114                       fmt, ##__VA_ARGS__)
 115
 116
 117 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 118 {
 119         enum intel_pch ret = PCH_NOP;
 120
 121         /*
 122          * In a virtualized passthrough environment we can be in a
 123          * setup where the ISA bridge is not able to be passed through.
 124          * In this case, a south bridge can be emulated and we have to
 125          * make an educated guess as to which PCH is really there.
 126          */
 127
 128         if (IS_GEN5(dev)) {
 129                 ret = PCH_IBX;
 130                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 132                 ret = PCH_CPT;
 133                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 135                 ret = PCH_LPT;
 136                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 138                 ret = PCH_SPT;
 139                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140         }
 141
 142         return ret;
 143 }
 144
 145 static void intel_detect_pch(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = to_i915(dev);
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 182                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 183                                 /* PantherPoint is CPT compatible */
 184                                 dev_priv->pch_type = PCH_CPT;
 185                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 186                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 187                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_LPT;
 189                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 190                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 191                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 192                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 193                                 dev_priv->pch_type = PCH_LPT;
 194                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 195                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 196                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 197                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_SPT;
 199                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 200                                 WARN_ON(!IS_SKYLAKE(dev) &&
 201                                         !IS_KABYLAKE(dev));
 202                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 203                                 dev_priv->pch_type = PCH_SPT;
 204                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 205                                 WARN_ON(!IS_SKYLAKE(dev) &&
 206                                         !IS_KABYLAKE(dev));
 207                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 208                                 dev_priv->pch_type = PCH_KBP;
 209                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 210                                 WARN_ON(!IS_KABYLAKE(dev));
 211                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 212                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 213                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 214                                     pch->subsystem_vendor ==
 215                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 216                                     pch->subsystem_device ==
 217                                             PCI_SUBDEVICE_ID_QEMU)) {
 218                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 219                         } else
 220                                 continue;
 221
 222                         break;
 223                 }
 224         }
 225         if (!pch)
 226                 DRM_DEBUG_KMS("No PCH found.\n");
 227
 228         pci_dev_put(pch);
 229 }
 230
 231 static int i915_getparam(struct drm_device *dev, void *data,
 232                          struct drm_file *file_priv)
 233 {
 234         struct drm_i915_private *dev_priv = to_i915(dev);
 235         drm_i915_getparam_t *param = data;
 236         int value;
 237
 238         switch (param->param) {
 239         case I915_PARAM_IRQ_ACTIVE:
 240         case I915_PARAM_ALLOW_BATCHBUFFER:
 241         case I915_PARAM_LAST_DISPATCH:
 242                 /* Reject all old ums/dri params. */
 243                 return -ENODEV;
 244         case I915_PARAM_CHIPSET_ID:
 245                 value = dev->pdev->device;
 246                 break;
 247         case I915_PARAM_REVISION:
 248                 value = dev->pdev->revision;
 249                 break;
 250         case I915_PARAM_HAS_GEM:
 251                 value = 1;
 252                 break;
 253         case I915_PARAM_NUM_FENCES_AVAIL:
 254                 value = dev_priv->num_fence_regs;
 255                 break;
 256         case I915_PARAM_HAS_OVERLAY:
 257                 value = dev_priv->overlay ? 1 : 0;
 258                 break;
 259         case I915_PARAM_HAS_PAGEFLIPPING:
 260                 value = 1;
 261                 break;
 262         case I915_PARAM_HAS_EXECBUF2:
 263                 /* depends on GEM */
 264                 value = 1;
 265                 break;
 266         case I915_PARAM_HAS_BSD:
 267                 value = intel_engine_initialized(&dev_priv->engine[VCS]);
 268                 break;
 269         case I915_PARAM_HAS_BLT:
 270                 value = intel_engine_initialized(&dev_priv->engine[BCS]);
 271                 break;
 272         case I915_PARAM_HAS_VEBOX:
 273                 value = intel_engine_initialized(&dev_priv->engine[VECS]);
 274                 break;
 275         case I915_PARAM_HAS_BSD2:
 276                 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
 277                 break;
 278         case I915_PARAM_HAS_RELAXED_FENCING:
 279                 value = 1;
 280                 break;
 281         case I915_PARAM_HAS_COHERENT_RINGS:
 282                 value = 1;
 283                 break;
 284         case I915_PARAM_HAS_EXEC_CONSTANTS:
 285                 value = INTEL_INFO(dev)->gen >= 4;
 286                 break;
 287         case I915_PARAM_HAS_RELAXED_DELTA:
 288                 value = 1;
 289                 break;
 290         case I915_PARAM_HAS_GEN7_SOL_RESET:
 291                 value = 1;
 292                 break;
 293         case I915_PARAM_HAS_LLC:
 294                 value = HAS_LLC(dev);
 295                 break;
 296         case I915_PARAM_HAS_WT:
 297                 value = HAS_WT(dev);
 298                 break;
 299         case I915_PARAM_HAS_ALIASING_PPGTT:
 300                 value = USES_PPGTT(dev);
 301                 break;
 302         case I915_PARAM_HAS_WAIT_TIMEOUT:
 303                 value = 1;
 304                 break;
 305         case I915_PARAM_HAS_SEMAPHORES:
 306                 value = i915.semaphores;
 307                 break;
 308         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 309                 value = 1;
 310                 break;
 311         case I915_PARAM_HAS_SECURE_BATCHES:
 312                 value = capable(CAP_SYS_ADMIN);
 313                 break;
 314         case I915_PARAM_HAS_PINNED_BATCHES:
 315                 value = 1;
 316                 break;
 317         case I915_PARAM_HAS_EXEC_NO_RELOC:
 318                 value = 1;
 319                 break;
 320         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 321                 value = 1;
 322                 break;
 323         case I915_PARAM_CMD_PARSER_VERSION:
 324                 value = i915_cmd_parser_get_version(dev_priv);
 325                 break;
 326         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 327                 value = 1;
 328                 break;
 329         case I915_PARAM_MMAP_VERSION:
 330                 value = 1;
 331                 break;
 332         case I915_PARAM_SUBSLICE_TOTAL:
 333                 value = INTEL_INFO(dev)->subslice_total;
 334                 if (!value)
 335                         return -ENODEV;
 336                 break;
 337         case I915_PARAM_EU_TOTAL:
 338                 value = INTEL_INFO(dev)->eu_total;
 339                 if (!value)
 340                         return -ENODEV;
 341                 break;
 342         case I915_PARAM_HAS_GPU_RESET:
 343                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 344                 break;
 345         case I915_PARAM_HAS_RESOURCE_STREAMER:
 346                 value = HAS_RESOURCE_STREAMER(dev);
 347                 break;
 348         case I915_PARAM_HAS_EXEC_SOFTPIN:
 349                 value = 1;
 350                 break;
 351         case I915_PARAM_HAS_POOLED_EU:
 352                 value = HAS_POOLED_EU(dev);
 353                 break;
 354         case I915_PARAM_MIN_EU_IN_POOL:
 355                 value = INTEL_INFO(dev)->min_eu_in_pool;
 356                 break;
 357         default:
 358                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 359                 return -EINVAL;
 360         }
 361
 362         if (put_user(value, param->value))
 363                 return -EFAULT;
 364
 365         return 0;
 366 }
 367
 368 static int i915_get_bridge_dev(struct drm_device *dev)
 369 {
 370         struct drm_i915_private *dev_priv = to_i915(dev);
 371
 372         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 373         if (!dev_priv->bridge_dev) {
 374                 DRM_ERROR("bridge device not found\n");
 375                 return -1;
 376         }
 377         return 0;
 378 }
 379
 380 /* Allocate space for the MCH regs if needed, return nonzero on error */
 381 static int
 382 intel_alloc_mchbar_resource(struct drm_device *dev)
 383 {
 384         struct drm_i915_private *dev_priv = to_i915(dev);
 385         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 386         u32 temp_lo, temp_hi = 0;
 387         u64 mchbar_addr;
 388         int ret;
 389
 390         if (INTEL_INFO(dev)->gen >= 4)
 391                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 392         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 393         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 394
 395         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 396 #ifdef CONFIG_PNP
 397         if (mchbar_addr &&
 398             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 399                 return 0;
 400 #endif
 401
 402         /* Get some space for it */
 403         dev_priv->mch_res.name = "i915 MCHBAR";
 404         dev_priv->mch_res.flags = IORESOURCE_MEM;
 405         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 406                                      &dev_priv->mch_res,
 407                                      MCHBAR_SIZE, MCHBAR_SIZE,
 408                                      PCIBIOS_MIN_MEM,
 409                                      0, pcibios_align_resource,
 410                                      dev_priv->bridge_dev);
 411         if (ret) {
 412                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 413                 dev_priv->mch_res.start = 0;
 414                 return ret;
 415         }
 416
 417         if (INTEL_INFO(dev)->gen >= 4)
 418                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 419                                        upper_32_bits(dev_priv->mch_res.start));
 420
 421         pci_write_config_dword(dev_priv->bridge_dev, reg,
 422                                lower_32_bits(dev_priv->mch_res.start));
 423         return 0;
 424 }
 425
 426 /* Setup MCHBAR if possible, return true if we should disable it again */
 427 static void
 428 intel_setup_mchbar(struct drm_device *dev)
 429 {
 430         struct drm_i915_private *dev_priv = to_i915(dev);
 431         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 432         u32 temp;
 433         bool enabled;
 434
 435         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 436                 return;
 437
 438         dev_priv->mchbar_need_disable = false;
 439
 440         if (IS_I915G(dev) || IS_I915GM(dev)) {
 441                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 442                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 443         } else {
 444                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 445                 enabled = temp & 1;
 446         }
 447
 448         /* If it's already enabled, don't have to do anything */
 449         if (enabled)
 450                 return;
 451
 452         if (intel_alloc_mchbar_resource(dev))
 453                 return;
 454
 455         dev_priv->mchbar_need_disable = true;
 456
 457         /* Space is allocated or reserved, so enable it. */
 458         if (IS_I915G(dev) || IS_I915GM(dev)) {
 459                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 460                                        temp | DEVEN_MCHBAR_EN);
 461         } else {
 462                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 463                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 464         }
 465 }
 466
 467 static void
 468 intel_teardown_mchbar(struct drm_device *dev)
 469 {
 470         struct drm_i915_private *dev_priv = to_i915(dev);
 471         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 472
 473         if (dev_priv->mchbar_need_disable) {
 474                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 475                         u32 deven_val;
 476
 477                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 478                                               &deven_val);
 479                         deven_val &= ~DEVEN_MCHBAR_EN;
 480                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 481                                                deven_val);
 482                 } else {
 483                         u32 mchbar_val;
 484
 485                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 486                                               &mchbar_val);
 487                         mchbar_val &= ~1;
 488                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 489                                                mchbar_val);
 490                 }
 491         }
 492
 493         if (dev_priv->mch_res.start)
 494                 release_resource(&dev_priv->mch_res);
 495 }
 496
 497 /* true = enable decode, false = disable decoder */
 498 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 499 {
 500         struct drm_device *dev = cookie;
 501
 502         intel_modeset_vga_set_state(dev, state);
 503         if (state)
 504                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 505                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 506         else
 507                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 508 }
 509
 510 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 511 {
 512         struct drm_device *dev = pci_get_drvdata(pdev);
 513         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 514
 515         if (state == VGA_SWITCHEROO_ON) {
 516                 pr_info("switched on\n");
 517                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 518                 /* i915 resume handler doesn't set to D0 */
 519                 pci_set_power_state(dev->pdev, PCI_D0);
 520                 i915_resume_switcheroo(dev);
 521                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 522         } else {
 523                 pr_info("switched off\n");
 524                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 525                 i915_suspend_switcheroo(dev, pmm);
 526                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 527         }
 528 }
 529
 530 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 531 {
 532         struct drm_device *dev = pci_get_drvdata(pdev);
 533
 534         /*
 535          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 536          * locking inversion with the driver load path. And the access here is
 537          * completely racy anyway. So don't bother with locking for now.
 538          */
 539         return dev->open_count == 0;
 540 }
 541
 542 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 543         .set_gpu_state = i915_switcheroo_set_state,
 544         .reprobe = NULL,
 545         .can_switch = i915_switcheroo_can_switch,
 546 };
 547
 548 static void i915_gem_fini(struct drm_device *dev)
 549 {
 550         struct drm_i915_private *dev_priv = to_i915(dev);
 551
 552         /*
 553          * Neither the BIOS, ourselves or any other kernel
 554          * expects the system to be in execlists mode on startup,
 555          * so we need to reset the GPU back to legacy mode. And the only
 556          * known way to disable logical contexts is through a GPU reset.
 557          *
 558          * So in order to leave the system in a known default configuration,
 559          * always reset the GPU upon unload. Afterwards we then clean up the
 560          * GEM state tracking, flushing off the requests and leaving the
 561          * system in a known idle state.
 562          *
 563          * Note that is of the upmost importance that the GPU is idle and
 564          * all stray writes are flushed *before* we dismantle the backing
 565          * storage for the pinned objects.
 566          *
 567          * However, since we are uncertain that reseting the GPU on older
 568          * machines is a good idea, we don't - just in case it leaves the
 569          * machine in an unusable condition.
 570          */
 571         if (HAS_HW_CONTEXTS(dev)) {
 572                 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
 573                 WARN_ON(reset && reset != -ENODEV);
 574         }
 575
 576         mutex_lock(&dev->struct_mutex);
 577         i915_gem_reset(dev);
 578         i915_gem_cleanup_engines(dev);
 579         i915_gem_context_fini(dev);
 580         mutex_unlock(&dev->struct_mutex);
 581
 582         WARN_ON(!list_empty(&to_i915(dev)->context_list));
 583 }
 584
 585 static int i915_load_modeset_init(struct drm_device *dev)
 586 {
 587         struct drm_i915_private *dev_priv = to_i915(dev);
 588         int ret;
 589
 590         if (i915_inject_load_failure())
 591                 return -ENODEV;
 592
 593         ret = intel_bios_init(dev_priv);
 594         if (ret)
 595                 DRM_INFO("failed to find VBIOS tables\n");
 596
 597         /* If we have > 1 VGA cards, then we need to arbitrate access
 598          * to the common VGA resources.
 599          *
 600          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 601          * then we do not take part in VGA arbitration and the
 602          * vga_client_register() fails with -ENODEV.
 603          */
 604         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 605         if (ret && ret != -ENODEV)
 606                 goto out;
 607
 608         intel_register_dsm_handler();
 609
 610         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 611         if (ret)
 612                 goto cleanup_vga_client;
 613
 614         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 615         intel_update_rawclk(dev_priv);
 616
 617         intel_power_domains_init_hw(dev_priv, false);
 618
 619         intel_csr_ucode_init(dev_priv);
 620
 621         ret = intel_irq_install(dev_priv);
 622         if (ret)
 623                 goto cleanup_csr;
 624
 625         intel_setup_gmbus(dev);
 626
 627         /* Important: The output setup functions called by modeset_init need
 628          * working irqs for e.g. gmbus and dp aux transfers. */
 629         intel_modeset_init(dev);
 630
 631         intel_guc_init(dev);
 632
 633         ret = i915_gem_init(dev);
 634         if (ret)
 635                 goto cleanup_irq;
 636
 637         intel_modeset_gem_init(dev);
 638
 639         if (INTEL_INFO(dev)->num_pipes == 0)
 640                 return 0;
 641
 642         ret = intel_fbdev_init(dev);
 643         if (ret)
 644                 goto cleanup_gem;
 645
 646         /* Only enable hotplug handling once the fbdev is fully set up. */
 647         intel_hpd_init(dev_priv);
 648
 649         drm_kms_helper_poll_init(dev);
 650
 651         return 0;
 652
 653 cleanup_gem:
 654         i915_gem_fini(dev);
 655 cleanup_irq:
 656         intel_guc_fini(dev);
 657         drm_irq_uninstall(dev);
 658         intel_teardown_gmbus(dev);
 659 cleanup_csr:
 660         intel_csr_ucode_fini(dev_priv);
 661         intel_power_domains_fini(dev_priv);
 662         vga_switcheroo_unregister_client(dev->pdev);
 663 cleanup_vga_client:
 664         vga_client_register(dev->pdev, NULL, NULL, NULL);
 665 out:
 666         return ret;
 667 }
 668
 669 #if IS_ENABLED(CONFIG_FB)
 670 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 671 {
 672         struct apertures_struct *ap;
 673         struct pci_dev *pdev = dev_priv->drm.pdev;
 674         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 675         bool primary;
 676         int ret;
 677
 678         ap = alloc_apertures(1);
 679         if (!ap)
 680                 return -ENOMEM;
 681
 682         ap->ranges[0].base = ggtt->mappable_base;
 683         ap->ranges[0].size = ggtt->mappable_end;
 684
 685         primary =
 686                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 687
 688         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 689
 690         kfree(ap);
 691
 692         return ret;
 693 }
 694 #else
 695 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 696 {
 697         return 0;
 698 }
 699 #endif
 700
 701 #if !defined(CONFIG_VGA_CONSOLE)
 702 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 703 {
 704         return 0;
 705 }
 706 #elif !defined(CONFIG_DUMMY_CONSOLE)
 707 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 708 {
 709         return -ENODEV;
 710 }
 711 #else
 712 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 713 {
 714         int ret = 0;
 715
 716         DRM_INFO("Replacing VGA console driver\n");
 717
 718         console_lock();
 719         if (con_is_bound(&vga_con))
 720                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 721         if (ret == 0) {
 722                 ret = do_unregister_con_driver(&vga_con);
 723
 724                 /* Ignore "already unregistered". */
 725                 if (ret == -ENODEV)
 726                         ret = 0;
 727         }
 728         console_unlock();
 729
 730         return ret;
 731 }
 732 #endif
 733
 734 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 735 {
 736         /*
 737          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 738          * CHV x1 PHY (DP/HDMI D)
 739          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 740          */
 741         if (IS_CHERRYVIEW(dev_priv)) {
 742                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 743                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 744         } else if (IS_VALLEYVIEW(dev_priv)) {
 745                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 746         }
 747 }
 748
 749 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 750 {
 751         /*
 752          * The i915 workqueue is primarily used for batched retirement of
 753          * requests (and thus managing bo) once the task has been completed
 754          * by the GPU. i915_gem_retire_requests() is called directly when we
 755          * need high-priority retirement, such as waiting for an explicit
 756          * bo.
 757          *
 758          * It is also used for periodic low-priority events, such as
 759          * idle-timers and recording error state.
 760          *
 761          * All tasks on the workqueue are expected to acquire the dev mutex
 762          * so there is no point in running more than one instance of the
 763          * workqueue at any time.  Use an ordered one.
 764          */
 765         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 766         if (dev_priv->wq == NULL)
 767                 goto out_err;
 768
 769         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 770         if (dev_priv->hotplug.dp_wq == NULL)
 771                 goto out_free_wq;
 772
 773         return 0;
 774
 775 out_free_wq:
 776         destroy_workqueue(dev_priv->wq);
 777 out_err:
 778         DRM_ERROR("Failed to allocate workqueues.\n");
 779
 780         return -ENOMEM;
 781 }
 782
 783 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 784 {
 785         destroy_workqueue(dev_priv->hotplug.dp_wq);
 786         destroy_workqueue(dev_priv->wq);
 787 }
 788
 789 /**
 790  * i915_driver_init_early - setup state not requiring device access
 791  * @dev_priv: device private
 792  *
 793  * Initialize everything that is a "SW-only" state, that is state not
 794  * requiring accessing the device or exposing the driver via kernel internal
 795  * or userspace interfaces. Example steps belonging here: lock initialization,
 796  * system memory allocation, setting up device specific attributes and
 797  * function hooks not requiring accessing the device.
 798  */
 799 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 800                                   const struct pci_device_id *ent)
 801 {
 802         const struct intel_device_info *match_info =
 803                 (struct intel_device_info *)ent->driver_data;
 804         struct intel_device_info *device_info;
 805         int ret = 0;
 806
 807         if (i915_inject_load_failure())
 808                 return -ENODEV;
 809
 810         /* Setup the write-once "constant" device info */
 811         device_info = mkwrite_device_info(dev_priv);
 812         memcpy(device_info, match_info, sizeof(*device_info));
 813         device_info->device_id = dev_priv->drm.pdev->device;
 814
 815         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 816         device_info->gen_mask = BIT(device_info->gen - 1);
 817
 818         spin_lock_init(&dev_priv->irq_lock);
 819         spin_lock_init(&dev_priv->gpu_error.lock);
 820         mutex_init(&dev_priv->backlight_lock);
 821         spin_lock_init(&dev_priv->uncore.lock);
 822         spin_lock_init(&dev_priv->mm.object_stat_lock);
 823         spin_lock_init(&dev_priv->mmio_flip_lock);
 824         mutex_init(&dev_priv->sb_lock);
 825         mutex_init(&dev_priv->modeset_restore_lock);
 826         mutex_init(&dev_priv->av_mutex);
 827         mutex_init(&dev_priv->wm.wm_mutex);
 828         mutex_init(&dev_priv->pps_mutex);
 829
 830         ret = i915_workqueues_init(dev_priv);
 831         if (ret < 0)
 832                 return ret;
 833
 834         ret = intel_gvt_init(dev_priv);
 835         if (ret < 0)
 836                 goto err_workqueues;
 837
 838         /* This must be called before any calls to HAS_PCH_* */
 839         intel_detect_pch(&dev_priv->drm);
 840
 841         intel_pm_setup(&dev_priv->drm);
 842         intel_init_dpio(dev_priv);
 843         intel_power_domains_init(dev_priv);
 844         intel_irq_init(dev_priv);
 845         intel_init_display_hooks(dev_priv);
 846         intel_init_clock_gating_hooks(dev_priv);
 847         intel_init_audio_hooks(dev_priv);
 848         i915_gem_load_init(&dev_priv->drm);
 849
 850         intel_display_crc_init(&dev_priv->drm);
 851
 852         intel_device_info_dump(dev_priv);
 853
 854         /* Not all pre-production machines fall into this category, only the
 855          * very first ones. Almost everything should work, except for maybe
 856          * suspend/resume. And we don't implement workarounds that affect only
 857          * pre-production machines. */
 858         if (IS_HSW_EARLY_SDV(dev_priv))
 859                 DRM_INFO("This is an early pre-production Haswell machine. "
 860                          "It may not be fully functional.\n");
 861
 862         return 0;
 863
 864 err_workqueues:
 865         i915_workqueues_cleanup(dev_priv);
 866         return ret;
 867 }
 868
 869 /**
 870  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 871  * @dev_priv: device private
 872  */
 873 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 874 {
 875         i915_gem_load_cleanup(&dev_priv->drm);
 876         i915_workqueues_cleanup(dev_priv);
 877 }
 878
 879 static int i915_mmio_setup(struct drm_device *dev)
 880 {
 881         struct drm_i915_private *dev_priv = to_i915(dev);
 882         int mmio_bar;
 883         int mmio_size;
 884
 885         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 886         /*
 887          * Before gen4, the registers and the GTT are behind different BARs.
 888          * However, from gen4 onwards, the registers and the GTT are shared
 889          * in the same BAR, so we want to restrict this ioremap from
 890          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 891          * the register BAR remains the same size for all the earlier
 892          * generations up to Ironlake.
 893          */
 894         if (INTEL_INFO(dev)->gen < 5)
 895                 mmio_size = 512 * 1024;
 896         else
 897                 mmio_size = 2 * 1024 * 1024;
 898         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 899         if (dev_priv->regs == NULL) {
 900                 DRM_ERROR("failed to map registers\n");
 901
 902                 return -EIO;
 903         }
 904
 905         /* Try to make sure MCHBAR is enabled before poking at it */
 906         intel_setup_mchbar(dev);
 907
 908         return 0;
 909 }
 910
 911 static void i915_mmio_cleanup(struct drm_device *dev)
 912 {
 913         struct drm_i915_private *dev_priv = to_i915(dev);
 914
 915         intel_teardown_mchbar(dev);
 916         pci_iounmap(dev->pdev, dev_priv->regs);
 917 }
 918
 919 /**
 920  * i915_driver_init_mmio - setup device MMIO
 921  * @dev_priv: device private
 922  *
 923  * Setup minimal device state necessary for MMIO accesses later in the
 924  * initialization sequence. The setup here should avoid any other device-wide
 925  * side effects or exposing the driver via kernel internal or user space
 926  * interfaces.
 927  */
 928 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 929 {
 930         struct drm_device *dev = &dev_priv->drm;
 931         int ret;
 932
 933         if (i915_inject_load_failure())
 934                 return -ENODEV;
 935
 936         if (i915_get_bridge_dev(dev))
 937                 return -EIO;
 938
 939         ret = i915_mmio_setup(dev);
 940         if (ret < 0)
 941                 goto put_bridge;
 942
 943         intel_uncore_init(dev_priv);
 944
 945         return 0;
 946
 947 put_bridge:
 948         pci_dev_put(dev_priv->bridge_dev);
 949
 950         return ret;
 951 }
 952
 953 /**
 954  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 955  * @dev_priv: device private
 956  */
 957 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 958 {
 959         struct drm_device *dev = &dev_priv->drm;
 960
 961         intel_uncore_fini(dev_priv);
 962         i915_mmio_cleanup(dev);
 963         pci_dev_put(dev_priv->bridge_dev);
 964 }
 965
 966 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 967 {
 968         i915.enable_execlists =
 969                 intel_sanitize_enable_execlists(dev_priv,
 970                                                 i915.enable_execlists);
 971
 972         /*
 973          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 974          * user's requested state against the hardware/driver capabilities.  We
 975          * do this now so that we can print out any log messages once rather
 976          * than every time we check intel_enable_ppgtt().
 977          */
 978         i915.enable_ppgtt =
 979                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 980         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 981
 982         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 983         DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
 984 }
 985
 986 /**
 987  * i915_driver_init_hw - setup state requiring device access
 988  * @dev_priv: device private
 989  *
 990  * Setup state that requires accessing the device, but doesn't require
 991  * exposing the driver via kernel internal or userspace interfaces.
 992  */
 993 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 994 {
 995         struct drm_device *dev = &dev_priv->drm;
 996         int ret;
 997
 998         if (i915_inject_load_failure())
 999                 return -ENODEV;
1000
1001         intel_device_info_runtime_init(dev_priv);
1002
1003         intel_sanitize_options(dev_priv);
1004
1005         ret = i915_ggtt_probe_hw(dev_priv);
1006         if (ret)
1007                 return ret;
1008
1009         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1010          * otherwise the vga fbdev driver falls over. */
1011         ret = i915_kick_out_firmware_fb(dev_priv);
1012         if (ret) {
1013                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1014                 goto out_ggtt;
1015         }
1016
1017         ret = i915_kick_out_vgacon(dev_priv);
1018         if (ret) {
1019                 DRM_ERROR("failed to remove conflicting VGA console\n");
1020                 goto out_ggtt;
1021         }
1022
1023         ret = i915_ggtt_init_hw(dev_priv);
1024         if (ret)
1025                 return ret;
1026
1027         ret = i915_ggtt_enable_hw(dev_priv);
1028         if (ret) {
1029                 DRM_ERROR("failed to enable GGTT\n");
1030                 goto out_ggtt;
1031         }
1032
1033         pci_set_master(dev->pdev);
1034
1035         /* overlay on gen2 is broken and can't address above 1G */
1036         if (IS_GEN2(dev)) {
1037                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1038                 if (ret) {
1039                         DRM_ERROR("failed to set DMA mask\n");
1040
1041                         goto out_ggtt;
1042                 }
1043         }
1044
1045         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1046          * using 32bit addressing, overwriting memory if HWS is located
1047          * above 4GB.
1048          *
1049          * The documentation also mentions an issue with undefined
1050          * behaviour if any general state is accessed within a page above 4GB,
1051          * which also needs to be handled carefully.
1052          */
1053         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1054                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1055
1056                 if (ret) {
1057                         DRM_ERROR("failed to set DMA mask\n");
1058
1059                         goto out_ggtt;
1060                 }
1061         }
1062
1063         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1064                            PM_QOS_DEFAULT_VALUE);
1065
1066         intel_uncore_sanitize(dev_priv);
1067
1068         intel_opregion_setup(dev_priv);
1069
1070         i915_gem_load_init_fences(dev_priv);
1071
1072         /* On the 945G/GM, the chipset reports the MSI capability on the
1073          * integrated graphics even though the support isn't actually there
1074          * according to the published specs.  It doesn't appear to function
1075          * correctly in testing on 945G.
1076          * This may be a side effect of MSI having been made available for PEG
1077          * and the registers being closely associated.
1078          *
1079          * According to chipset errata, on the 965GM, MSI interrupts may
1080          * be lost or delayed, but we use them anyways to avoid
1081          * stuck interrupts on some machines.
1082          */
1083         if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1084                 if (pci_enable_msi(dev->pdev) < 0)
1085                         DRM_DEBUG_DRIVER("can't enable MSI");
1086         }
1087
1088         return 0;
1089
1090 out_ggtt:
1091         i915_ggtt_cleanup_hw(dev_priv);
1092
1093         return ret;
1094 }
1095
1096 /**
1097  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1098  * @dev_priv: device private
1099  */
1100 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1101 {
1102         struct drm_device *dev = &dev_priv->drm;
1103
1104         if (dev->pdev->msi_enabled)
1105                 pci_disable_msi(dev->pdev);
1106
1107         pm_qos_remove_request(&dev_priv->pm_qos);
1108         i915_ggtt_cleanup_hw(dev_priv);
1109 }
1110
1111 /**
1112  * i915_driver_register - register the driver with the rest of the system
1113  * @dev_priv: device private
1114  *
1115  * Perform any steps necessary to make the driver available via kernel
1116  * internal or userspace interfaces.
1117  */
1118 static void i915_driver_register(struct drm_i915_private *dev_priv)
1119 {
1120         struct drm_device *dev = &dev_priv->drm;
1121
1122         i915_gem_shrinker_init(dev_priv);
1123
1124         /*
1125          * Notify a valid surface after modesetting,
1126          * when running inside a VM.
1127          */
1128         if (intel_vgpu_active(dev_priv))
1129                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1130
1131         /* Reveal our presence to userspace */
1132         if (drm_dev_register(dev, 0) == 0) {
1133                 i915_debugfs_register(dev_priv);
1134                 i915_setup_sysfs(dev);
1135         } else
1136                 DRM_ERROR("Failed to register driver for userspace access!\n");
1137
1138         if (INTEL_INFO(dev_priv)->num_pipes) {
1139                 /* Must be done after probing outputs */
1140                 intel_opregion_register(dev_priv);
1141                 acpi_video_register();
1142         }
1143
1144         if (IS_GEN5(dev_priv))
1145                 intel_gpu_ips_init(dev_priv);
1146
1147         i915_audio_component_init(dev_priv);
1148
1149         /*
1150          * Some ports require correctly set-up hpd registers for detection to
1151          * work properly (leading to ghost connected connector status), e.g. VGA
1152          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1153          * irqs are fully enabled. We do it last so that the async config
1154          * cannot run before the connectors are registered.
1155          */
1156         intel_fbdev_initial_config_async(dev);
1157 }
1158
1159 /**
1160  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1161  * @dev_priv: device private
1162  */
1163 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1164 {
1165         i915_audio_component_cleanup(dev_priv);
1166
1167         intel_gpu_ips_teardown();
1168         acpi_video_unregister();
1169         intel_opregion_unregister(dev_priv);
1170
1171         i915_teardown_sysfs(&dev_priv->drm);
1172         i915_debugfs_unregister(dev_priv);
1173         drm_dev_unregister(&dev_priv->drm);
1174
1175         i915_gem_shrinker_cleanup(dev_priv);
1176 }
1177
1178 /**
1179  * i915_driver_load - setup chip and create an initial config
1180  * @dev: DRM device
1181  * @flags: startup flags
1182  *
1183  * The driver load routine has to do several things:
1184  *   - drive output discovery via intel_modeset_init()
1185  *   - initialize the memory manager
1186  *   - allocate initial config memory
1187  *   - setup the DRM framebuffer with the allocated memory
1188  */
1189 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1190 {
1191         struct drm_i915_private *dev_priv;
1192         int ret;
1193
1194         if (i915.nuclear_pageflip)
1195                 driver.driver_features |= DRIVER_ATOMIC;
1196
1197         ret = -ENOMEM;
1198         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1199         if (dev_priv)
1200                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1201         if (ret) {
1202                 dev_printk(KERN_ERR, &pdev->dev,
1203                            "[" DRM_NAME ":%s] allocation failed\n", __func__);
1204                 kfree(dev_priv);
1205                 return ret;
1206         }
1207
1208         dev_priv->drm.pdev = pdev;
1209         dev_priv->drm.dev_private = dev_priv;
1210
1211         ret = pci_enable_device(pdev);
1212         if (ret)
1213                 goto out_free_priv;
1214
1215         pci_set_drvdata(pdev, &dev_priv->drm);
1216
1217         ret = i915_driver_init_early(dev_priv, ent);
1218         if (ret < 0)
1219                 goto out_pci_disable;
1220
1221         intel_runtime_pm_get(dev_priv);
1222
1223         ret = i915_driver_init_mmio(dev_priv);
1224         if (ret < 0)
1225                 goto out_runtime_pm_put;
1226
1227         ret = i915_driver_init_hw(dev_priv);
1228         if (ret < 0)
1229                 goto out_cleanup_mmio;
1230
1231         /*
1232          * TODO: move the vblank init and parts of modeset init steps into one
1233          * of the i915_driver_init_/i915_driver_register functions according
1234          * to the role/effect of the given init step.
1235          */
1236         if (INTEL_INFO(dev_priv)->num_pipes) {
1237                 ret = drm_vblank_init(&dev_priv->drm,
1238                                       INTEL_INFO(dev_priv)->num_pipes);
1239                 if (ret)
1240                         goto out_cleanup_hw;
1241         }
1242
1243         ret = i915_load_modeset_init(&dev_priv->drm);
1244         if (ret < 0)
1245                 goto out_cleanup_vblank;
1246
1247         i915_driver_register(dev_priv);
1248
1249         intel_runtime_pm_enable(dev_priv);
1250
1251         intel_runtime_pm_put(dev_priv);
1252
1253         return 0;
1254
1255 out_cleanup_vblank:
1256         drm_vblank_cleanup(&dev_priv->drm);
1257 out_cleanup_hw:
1258         i915_driver_cleanup_hw(dev_priv);
1259 out_cleanup_mmio:
1260         i915_driver_cleanup_mmio(dev_priv);
1261 out_runtime_pm_put:
1262         intel_runtime_pm_put(dev_priv);
1263         i915_driver_cleanup_early(dev_priv);
1264 out_pci_disable:
1265         pci_disable_device(pdev);
1266 out_free_priv:
1267         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1268         drm_dev_unref(&dev_priv->drm);
1269         return ret;
1270 }
1271
1272 void i915_driver_unload(struct drm_device *dev)
1273 {
1274         struct drm_i915_private *dev_priv = to_i915(dev);
1275
1276         intel_fbdev_fini(dev);
1277
1278         if (i915_gem_suspend(dev))
1279                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1280
1281         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1282
1283         i915_driver_unregister(dev_priv);
1284
1285         drm_vblank_cleanup(dev);
1286
1287         intel_modeset_cleanup(dev);
1288
1289         /*
1290          * free the memory space allocated for the child device
1291          * config parsed from VBT
1292          */
1293         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1294                 kfree(dev_priv->vbt.child_dev);
1295                 dev_priv->vbt.child_dev = NULL;
1296                 dev_priv->vbt.child_dev_num = 0;
1297         }
1298         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1299         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1300         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1301         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1302
1303         vga_switcheroo_unregister_client(dev->pdev);
1304         vga_client_register(dev->pdev, NULL, NULL, NULL);
1305
1306         intel_csr_ucode_fini(dev_priv);
1307
1308         /* Free error state after interrupts are fully disabled. */
1309         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1310         i915_destroy_error_state(dev);
1311
1312         /* Flush any outstanding unpin_work. */
1313         drain_workqueue(dev_priv->wq);
1314
1315         intel_guc_fini(dev);
1316         i915_gem_fini(dev);
1317         intel_fbc_cleanup_cfb(dev_priv);
1318
1319         intel_power_domains_fini(dev_priv);
1320
1321         i915_driver_cleanup_hw(dev_priv);
1322         i915_driver_cleanup_mmio(dev_priv);
1323
1324         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1325
1326         i915_driver_cleanup_early(dev_priv);
1327 }
1328
1329 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1330 {
1331         int ret;
1332
1333         ret = i915_gem_open(dev, file);
1334         if (ret)
1335                 return ret;
1336
1337         return 0;
1338 }
1339
1340 /**
1341  * i915_driver_lastclose - clean up after all DRM clients have exited
1342  * @dev: DRM device
1343  *
1344  * Take care of cleaning up after all DRM clients have exited.  In the
1345  * mode setting case, we want to restore the kernel's initial mode (just
1346  * in case the last client left us in a bad state).
1347  *
1348  * Additionally, in the non-mode setting case, we'll tear down the GTT
1349  * and DMA structures, since the kernel won't be using them, and clea
1350  * up any GEM state.
1351  */
1352 static void i915_driver_lastclose(struct drm_device *dev)
1353 {
1354         intel_fbdev_restore_mode(dev);
1355         vga_switcheroo_process_delayed_switch();
1356 }
1357
1358 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1359 {
1360         mutex_lock(&dev->struct_mutex);
1361         i915_gem_context_close(dev, file);
1362         i915_gem_release(dev, file);
1363         mutex_unlock(&dev->struct_mutex);
1364 }
1365
1366 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1367 {
1368         struct drm_i915_file_private *file_priv = file->driver_priv;
1369
1370         kfree(file_priv);
1371 }
1372
1373 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1374 {
1375         struct drm_device *dev = &dev_priv->drm;
1376         struct intel_encoder *encoder;
1377
1378         drm_modeset_lock_all(dev);
1379         for_each_intel_encoder(dev, encoder)
1380                 if (encoder->suspend)
1381                         encoder->suspend(encoder);
1382         drm_modeset_unlock_all(dev);
1383 }
1384
1385 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1386                               bool rpm_resume);
1387 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1388
1389 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1390 {
1391 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1392         if (acpi_target_system_state() < ACPI_STATE_S3)
1393                 return true;
1394 #endif
1395         return false;
1396 }
1397
1398 static int i915_drm_suspend(struct drm_device *dev)
1399 {
1400         struct drm_i915_private *dev_priv = to_i915(dev);
1401         pci_power_t opregion_target_state;
1402         int error;
1403
1404         /* ignore lid events during suspend */
1405         mutex_lock(&dev_priv->modeset_restore_lock);
1406         dev_priv->modeset_restore = MODESET_SUSPENDED;
1407         mutex_unlock(&dev_priv->modeset_restore_lock);
1408
1409         disable_rpm_wakeref_asserts(dev_priv);
1410
1411         /* We do a lot of poking in a lot of registers, make sure they work
1412          * properly. */
1413         intel_display_set_init_power(dev_priv, true);
1414
1415         drm_kms_helper_poll_disable(dev);
1416
1417         pci_save_state(dev->pdev);
1418
1419         error = i915_gem_suspend(dev);
1420         if (error) {
1421                 dev_err(&dev->pdev->dev,
1422                         "GEM idle failed, resume might fail\n");
1423                 goto out;
1424         }
1425
1426         intel_guc_suspend(dev);
1427
1428         intel_display_suspend(dev);
1429
1430         intel_dp_mst_suspend(dev);
1431
1432         intel_runtime_pm_disable_interrupts(dev_priv);
1433         intel_hpd_cancel_work(dev_priv);
1434
1435         intel_suspend_encoders(dev_priv);
1436
1437         intel_suspend_hw(dev);
1438
1439         i915_gem_suspend_gtt_mappings(dev);
1440
1441         i915_save_state(dev);
1442
1443         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1444         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1445
1446         intel_uncore_forcewake_reset(dev_priv, false);
1447         intel_opregion_unregister(dev_priv);
1448
1449         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1450
1451         dev_priv->suspend_count++;
1452
1453         intel_display_set_init_power(dev_priv, false);
1454
1455         intel_csr_ucode_suspend(dev_priv);
1456
1457 out:
1458         enable_rpm_wakeref_asserts(dev_priv);
1459
1460         return error;
1461 }
1462
1463 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
1464 {
1465         struct drm_i915_private *dev_priv = to_i915(drm_dev);
1466         bool fw_csr;
1467         int ret;
1468
1469         disable_rpm_wakeref_asserts(dev_priv);
1470
1471         fw_csr = !IS_BROXTON(dev_priv) &&
1472                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1473         /*
1474          * In case of firmware assisted context save/restore don't manually
1475          * deinit the power domains. This also means the CSR/DMC firmware will
1476          * stay active, it will power down any HW resources as required and
1477          * also enable deeper system power states that would be blocked if the
1478          * firmware was inactive.
1479          */
1480         if (!fw_csr)
1481                 intel_power_domains_suspend(dev_priv);
1482
1483         ret = 0;
1484         if (IS_BROXTON(dev_priv))
1485                 bxt_enable_dc9(dev_priv);
1486         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1487                 hsw_enable_pc8(dev_priv);
1488         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1489                 ret = vlv_suspend_complete(dev_priv);
1490
1491         if (ret) {
1492                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1493                 if (!fw_csr)
1494                         intel_power_domains_init_hw(dev_priv, true);
1495
1496                 goto out;
1497         }
1498
1499         pci_disable_device(drm_dev->pdev);
1500         /*
1501          * During hibernation on some platforms the BIOS may try to access
1502          * the device even though it's already in D3 and hang the machine. So
1503          * leave the device in D0 on those platforms and hope the BIOS will
1504          * power down the device properly. The issue was seen on multiple old
1505          * GENs with different BIOS vendors, so having an explicit blacklist
1506          * is inpractical; apply the workaround on everything pre GEN6. The
1507          * platforms where the issue was seen:
1508          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1509          * Fujitsu FSC S7110
1510          * Acer Aspire 1830T
1511          */
1512         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
1513                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
1514
1515         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1516
1517 out:
1518         enable_rpm_wakeref_asserts(dev_priv);
1519
1520         return ret;
1521 }
1522
1523 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1524 {
1525         int error;
1526
1527         if (!dev) {
1528                 DRM_ERROR("dev: %p\n", dev);
1529                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1530                 return -ENODEV;
1531         }
1532
1533         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1534                          state.event != PM_EVENT_FREEZE))
1535                 return -EINVAL;
1536
1537         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1538                 return 0;
1539
1540         error = i915_drm_suspend(dev);
1541         if (error)
1542                 return error;
1543
1544         return i915_drm_suspend_late(dev, false);
1545 }
1546
1547 static int i915_drm_resume(struct drm_device *dev)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(dev);
1550         int ret;
1551
1552         disable_rpm_wakeref_asserts(dev_priv);
1553
1554         ret = i915_ggtt_enable_hw(dev_priv);
1555         if (ret)
1556                 DRM_ERROR("failed to re-enable GGTT\n");
1557
1558         intel_csr_ucode_resume(dev_priv);
1559
1560         i915_gem_resume(dev);
1561
1562         i915_restore_state(dev);
1563         intel_opregion_setup(dev_priv);
1564
1565         intel_init_pch_refclk(dev);
1566         drm_mode_config_reset(dev);
1567
1568         /*
1569          * Interrupts have to be enabled before any batches are run. If not the
1570          * GPU will hang. i915_gem_init_hw() will initiate batches to
1571          * update/restore the context.
1572          *
1573          * Modeset enabling in intel_modeset_init_hw() also needs working
1574          * interrupts.
1575          */
1576         intel_runtime_pm_enable_interrupts(dev_priv);
1577
1578         mutex_lock(&dev->struct_mutex);
1579         if (i915_gem_init_hw(dev)) {
1580                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1581                 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
1582         }
1583         mutex_unlock(&dev->struct_mutex);
1584
1585         intel_guc_resume(dev);
1586
1587         intel_modeset_init_hw(dev);
1588
1589         spin_lock_irq(&dev_priv->irq_lock);
1590         if (dev_priv->display.hpd_irq_setup)
1591                 dev_priv->display.hpd_irq_setup(dev_priv);
1592         spin_unlock_irq(&dev_priv->irq_lock);
1593
1594         intel_dp_mst_resume(dev);
1595
1596         intel_display_resume(dev);
1597
1598         /*
1599          * ... but also need to make sure that hotplug processing
1600          * doesn't cause havoc. Like in the driver load code we don't
1601          * bother with the tiny race here where we might loose hotplug
1602          * notifications.
1603          * */
1604         intel_hpd_init(dev_priv);
1605         /* Config may have changed between suspend and resume */
1606         drm_helper_hpd_irq_event(dev);
1607
1608         intel_opregion_register(dev_priv);
1609
1610         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1611
1612         mutex_lock(&dev_priv->modeset_restore_lock);
1613         dev_priv->modeset_restore = MODESET_DONE;
1614         mutex_unlock(&dev_priv->modeset_restore_lock);
1615
1616         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1617
1618         intel_autoenable_gt_powersave(dev_priv);
1619         drm_kms_helper_poll_enable(dev);
1620
1621         enable_rpm_wakeref_asserts(dev_priv);
1622
1623         return 0;
1624 }
1625
1626 static int i915_drm_resume_early(struct drm_device *dev)
1627 {
1628         struct drm_i915_private *dev_priv = to_i915(dev);
1629         int ret;
1630
1631         /*
1632          * We have a resume ordering issue with the snd-hda driver also
1633          * requiring our device to be power up. Due to the lack of a
1634          * parent/child relationship we currently solve this with an early
1635          * resume hook.
1636          *
1637          * FIXME: This should be solved with a special hdmi sink device or
1638          * similar so that power domains can be employed.
1639          */
1640
1641         /*
1642          * Note that we need to set the power state explicitly, since we
1643          * powered off the device during freeze and the PCI core won't power
1644          * it back up for us during thaw. Powering off the device during
1645          * freeze is not a hard requirement though, and during the
1646          * suspend/resume phases the PCI core makes sure we get here with the
1647          * device powered on. So in case we change our freeze logic and keep
1648          * the device powered we can also remove the following set power state
1649          * call.
1650          */
1651         ret = pci_set_power_state(dev->pdev, PCI_D0);
1652         if (ret) {
1653                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1654                 goto out;
1655         }
1656
1657         /*
1658          * Note that pci_enable_device() first enables any parent bridge
1659          * device and only then sets the power state for this device. The
1660          * bridge enabling is a nop though, since bridge devices are resumed
1661          * first. The order of enabling power and enabling the device is
1662          * imposed by the PCI core as described above, so here we preserve the
1663          * same order for the freeze/thaw phases.
1664          *
1665          * TODO: eventually we should remove pci_disable_device() /
1666          * pci_enable_enable_device() from suspend/resume. Due to how they
1667          * depend on the device enable refcount we can't anyway depend on them
1668          * disabling/enabling the device.
1669          */
1670         if (pci_enable_device(dev->pdev)) {
1671                 ret = -EIO;
1672                 goto out;
1673         }
1674
1675         pci_set_master(dev->pdev);
1676
1677         disable_rpm_wakeref_asserts(dev_priv);
1678
1679         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1680                 ret = vlv_resume_prepare(dev_priv, false);
1681         if (ret)
1682                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1683                           ret);
1684
1685         intel_uncore_early_sanitize(dev_priv, true);
1686
1687         if (IS_BROXTON(dev_priv)) {
1688                 if (!dev_priv->suspended_to_idle)
1689                         gen9_sanitize_dc_state(dev_priv);
1690                 bxt_disable_dc9(dev_priv);
1691         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1692                 hsw_disable_pc8(dev_priv);
1693         }
1694
1695         intel_uncore_sanitize(dev_priv);
1696
1697         if (IS_BROXTON(dev_priv) ||
1698             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1699                 intel_power_domains_init_hw(dev_priv, true);
1700
1701         enable_rpm_wakeref_asserts(dev_priv);
1702
1703 out:
1704         dev_priv->suspended_to_idle = false;
1705
1706         return ret;
1707 }
1708
1709 int i915_resume_switcheroo(struct drm_device *dev)
1710 {
1711         int ret;
1712
1713         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1714                 return 0;
1715
1716         ret = i915_drm_resume_early(dev);
1717         if (ret)
1718                 return ret;
1719
1720         return i915_drm_resume(dev);
1721 }
1722
1723 /**
1724  * i915_reset - reset chip after a hang
1725  * @dev: drm device to reset
1726  *
1727  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
1728  * reset or otherwise an error code.
1729  *
1730  * Procedure is fairly simple:
1731  *   - reset the chip using the reset reg
1732  *   - re-init context state
1733  *   - re-init hardware status page
1734  *   - re-init ring buffer
1735  *   - re-init interrupt state
1736  *   - re-init display
1737  */
1738 int i915_reset(struct drm_i915_private *dev_priv)
1739 {
1740         struct drm_device *dev = &dev_priv->drm;
1741         struct i915_gpu_error *error = &dev_priv->gpu_error;
1742         unsigned reset_counter;
1743         int ret;
1744
1745         mutex_lock(&dev->struct_mutex);
1746
1747         /* Clear any previous failed attempts at recovery. Time to try again. */
1748         atomic_andnot(I915_WEDGED, &error->reset_counter);
1749
1750         /* Clear the reset-in-progress flag and increment the reset epoch. */
1751         reset_counter = atomic_inc_return(&error->reset_counter);
1752         if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
1753                 ret = -EIO;
1754                 goto error;
1755         }
1756
1757         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1758
1759         i915_gem_reset(dev);
1760
1761         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1762         if (ret) {
1763                 if (ret != -ENODEV)
1764                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1765                 else
1766                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1767                 goto error;
1768         }
1769
1770         intel_overlay_reset(dev_priv);
1771
1772         /* Ok, now get things going again... */
1773
1774         /*
1775          * Everything depends on having the GTT running, so we need to start
1776          * there.  Fortunately we don't need to do this unless we reset the
1777          * chip at a PCI level.
1778          *
1779          * Next we need to restore the context, but we don't use those
1780          * yet either...
1781          *
1782          * Ring buffer needs to be re-initialized in the KMS case, or if X
1783          * was running at the time of the reset (i.e. we weren't VT
1784          * switched away).
1785          */
1786         ret = i915_gem_init_hw(dev);
1787         if (ret) {
1788                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1789                 goto error;
1790         }
1791
1792         mutex_unlock(&dev->struct_mutex);
1793
1794         /*
1795          * rps/rc6 re-init is necessary to restore state lost after the
1796          * reset and the re-install of gt irqs. Skip for ironlake per
1797          * previous concerns that it doesn't respond well to some forms
1798          * of re-init after reset.
1799          */
1800         intel_autoenable_gt_powersave(dev_priv);
1801
1802         return 0;
1803
1804 error:
1805         atomic_or(I915_WEDGED, &error->reset_counter);
1806         mutex_unlock(&dev->struct_mutex);
1807         return ret;
1808 }
1809
1810 static int i915_pm_suspend(struct device *dev)
1811 {
1812         struct pci_dev *pdev = to_pci_dev(dev);
1813         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1814
1815         if (!drm_dev) {
1816                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1817                 return -ENODEV;
1818         }
1819
1820         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1821                 return 0;
1822
1823         return i915_drm_suspend(drm_dev);
1824 }
1825
1826 static int i915_pm_suspend_late(struct device *dev)
1827 {
1828         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1829
1830         /*
1831          * We have a suspend ordering issue with the snd-hda driver also
1832          * requiring our device to be power up. Due to the lack of a
1833          * parent/child relationship we currently solve this with an late
1834          * suspend hook.
1835          *
1836          * FIXME: This should be solved with a special hdmi sink device or
1837          * similar so that power domains can be employed.
1838          */
1839         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1840                 return 0;
1841
1842         return i915_drm_suspend_late(drm_dev, false);
1843 }
1844
1845 static int i915_pm_poweroff_late(struct device *dev)
1846 {
1847         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1848
1849         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1850                 return 0;
1851
1852         return i915_drm_suspend_late(drm_dev, true);
1853 }
1854
1855 static int i915_pm_resume_early(struct device *dev)
1856 {
1857         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1858
1859         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1860                 return 0;
1861
1862         return i915_drm_resume_early(drm_dev);
1863 }
1864
1865 static int i915_pm_resume(struct device *dev)
1866 {
1867         struct drm_device *drm_dev = &dev_to_i915(dev)->drm;
1868
1869         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1870                 return 0;
1871
1872         return i915_drm_resume(drm_dev);
1873 }
1874
1875 /* freeze: before creating the hibernation_image */
1876 static int i915_pm_freeze(struct device *dev)
1877 {
1878         return i915_pm_suspend(dev);
1879 }
1880
1881 static int i915_pm_freeze_late(struct device *dev)
1882 {
1883         int ret;
1884
1885         ret = i915_pm_suspend_late(dev);
1886         if (ret)
1887                 return ret;
1888
1889         ret = i915_gem_freeze_late(dev_to_i915(dev));
1890         if (ret)
1891                 return ret;
1892
1893         return 0;
1894 }
1895
1896 /* thaw: called after creating the hibernation image, but before turning off. */
1897 static int i915_pm_thaw_early(struct device *dev)
1898 {
1899         return i915_pm_resume_early(dev);
1900 }
1901
1902 static int i915_pm_thaw(struct device *dev)
1903 {
1904         return i915_pm_resume(dev);
1905 }
1906
1907 /* restore: called after loading the hibernation image. */
1908 static int i915_pm_restore_early(struct device *dev)
1909 {
1910         return i915_pm_resume_early(dev);
1911 }
1912
1913 static int i915_pm_restore(struct device *dev)
1914 {
1915         return i915_pm_resume(dev);
1916 }
1917
1918 /*
1919  * Save all Gunit registers that may be lost after a D3 and a subsequent
1920  * S0i[R123] transition. The list of registers needing a save/restore is
1921  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1922  * registers in the following way:
1923  * - Driver: saved/restored by the driver
1924  * - Punit : saved/restored by the Punit firmware
1925  * - No, w/o marking: no need to save/restore, since the register is R/O or
1926  *                    used internally by the HW in a way that doesn't depend
1927  *                    keeping the content across a suspend/resume.
1928  * - Debug : used for debugging
1929  *
1930  * We save/restore all registers marked with 'Driver', with the following
1931  * exceptions:
1932  * - Registers out of use, including also registers marked with 'Debug'.
1933  *   These have no effect on the driver's operation, so we don't save/restore
1934  *   them to reduce the overhead.
1935  * - Registers that are fully setup by an initialization function called from
1936  *   the resume path. For example many clock gating and RPS/RC6 registers.
1937  * - Registers that provide the right functionality with their reset defaults.
1938  *
1939  * TODO: Except for registers that based on the above 3 criteria can be safely
1940  * ignored, we save/restore all others, practically treating the HW context as
1941  * a black-box for the driver. Further investigation is needed to reduce the
1942  * saved/restored registers even further, by following the same 3 criteria.
1943  */
1944 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1945 {
1946         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1947         int i;
1948
1949         /* GAM 0x4000-0x4770 */
1950         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1951         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1952         s->arb_mode             = I915_READ(ARB_MODE);
1953         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1954         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1955
1956         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1957                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1958
1959         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1960         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1961
1962         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1963         s->ecochk               = I915_READ(GAM_ECOCHK);
1964         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1965         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1966
1967         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1968
1969         /* MBC 0x9024-0x91D0, 0x8500 */
1970         s->g3dctl               = I915_READ(VLV_G3DCTL);
1971         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1972         s->mbctl                = I915_READ(GEN6_MBCTL);
1973
1974         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1975         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1976         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1977         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1978         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1979         s->rstctl               = I915_READ(GEN6_RSTCTL);
1980         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1981
1982         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1983         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1984         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1985         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1986         s->ecobus               = I915_READ(ECOBUS);
1987         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1988         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1989         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1990         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1991         s->rcedata              = I915_READ(VLV_RCEDATA);
1992         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1993
1994         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1995         s->gt_imr               = I915_READ(GTIMR);
1996         s->gt_ier               = I915_READ(GTIER);
1997         s->pm_imr               = I915_READ(GEN6_PMIMR);
1998         s->pm_ier               = I915_READ(GEN6_PMIER);
1999
2000         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2001                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2002
2003         /* GT SA CZ domain, 0x100000-0x138124 */
2004         s->tilectl              = I915_READ(TILECTL);
2005         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2006         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2007         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2008         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2009
2010         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2011         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2012         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2013         s->pcbr                 = I915_READ(VLV_PCBR);
2014         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2015
2016         /*
2017          * Not saving any of:
2018          * DFT,         0x9800-0x9EC0
2019          * SARB,        0xB000-0xB1FC
2020          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2021          * PCI CFG
2022          */
2023 }
2024
2025 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2026 {
2027         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2028         u32 val;
2029         int i;
2030
2031         /* GAM 0x4000-0x4770 */
2032         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2033         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2034         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2035         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2036         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2037
2038         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2039                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2040
2041         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2042         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2043
2044         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2045         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2046         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2047         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2048
2049         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2050
2051         /* MBC 0x9024-0x91D0, 0x8500 */
2052         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2053         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2054         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2055
2056         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2057         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2058         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2059         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2060         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2061         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2062         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2063
2064         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2065         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2066         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2067         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2068         I915_WRITE(ECOBUS,              s->ecobus);
2069         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2070         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2071         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2072         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2073         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2074         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2075
2076         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2077         I915_WRITE(GTIMR,               s->gt_imr);
2078         I915_WRITE(GTIER,               s->gt_ier);
2079         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2080         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2081
2082         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2083                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2084
2085         /* GT SA CZ domain, 0x100000-0x138124 */
2086         I915_WRITE(TILECTL,                     s->tilectl);
2087         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2088         /*
2089          * Preserve the GT allow wake and GFX force clock bit, they are not
2090          * be restored, as they are used to control the s0ix suspend/resume
2091          * sequence by the caller.
2092          */
2093         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2094         val &= VLV_GTLC_ALLOWWAKEREQ;
2095         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2096         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2097
2098         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2099         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2100         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2101         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2102
2103         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2104
2105         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2106         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2107         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2108         I915_WRITE(VLV_PCBR,                    s->pcbr);
2109         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2110 }
2111
2112 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2113 {
2114         u32 val;
2115         int err;
2116
2117         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2118         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2119         if (force_on)
2120                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2121         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2122
2123         if (!force_on)
2124                 return 0;
2125
2126         err = intel_wait_for_register(dev_priv,
2127                                       VLV_GTLC_SURVIVABILITY_REG,
2128                                       VLV_GFX_CLK_STATUS_BIT,
2129                                       VLV_GFX_CLK_STATUS_BIT,
2130                                       20);
2131         if (err)
2132                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2133                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2134
2135         return err;
2136 }
2137
2138 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2139 {
2140         u32 val;
2141         int err = 0;
2142
2143         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2144         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2145         if (allow)
2146                 val |= VLV_GTLC_ALLOWWAKEREQ;
2147         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2148         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2149
2150         err = intel_wait_for_register(dev_priv,
2151                                       VLV_GTLC_PW_STATUS,
2152                                       VLV_GTLC_ALLOWWAKEACK,
2153                                       allow,
2154                                       1);
2155         if (err)
2156                 DRM_ERROR("timeout disabling GT waking\n");
2157
2158         return err;
2159 }
2160
2161 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2162                                  bool wait_for_on)
2163 {
2164         u32 mask;
2165         u32 val;
2166         int err;
2167
2168         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2169         val = wait_for_on ? mask : 0;
2170         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2171                 return 0;
2172
2173         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2174                       onoff(wait_for_on),
2175                       I915_READ(VLV_GTLC_PW_STATUS));
2176
2177         /*
2178          * RC6 transitioning can be delayed up to 2 msec (see
2179          * valleyview_enable_rps), use 3 msec for safety.
2180          */
2181         err = intel_wait_for_register(dev_priv,
2182                                       VLV_GTLC_PW_STATUS, mask, val,
2183                                       3);
2184         if (err)
2185                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2186                           onoff(wait_for_on));
2187
2188         return err;
2189 }
2190
2191 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2192 {
2193         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2194                 return;
2195
2196         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2197         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2198 }
2199
2200 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2201 {
2202         u32 mask;
2203         int err;
2204
2205         /*
2206          * Bspec defines the following GT well on flags as debug only, so
2207          * don't treat them as hard failures.
2208          */
2209         (void)vlv_wait_for_gt_wells(dev_priv, false);
2210
2211         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2212         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2213
2214         vlv_check_no_gt_access(dev_priv);
2215
2216         err = vlv_force_gfx_clock(dev_priv, true);
2217         if (err)
2218                 goto err1;
2219
2220         err = vlv_allow_gt_wake(dev_priv, false);
2221         if (err)
2222                 goto err2;
2223
2224         if (!IS_CHERRYVIEW(dev_priv))
2225                 vlv_save_gunit_s0ix_state(dev_priv);
2226
2227         err = vlv_force_gfx_clock(dev_priv, false);
2228         if (err)
2229                 goto err2;
2230
2231         return 0;
2232
2233 err2:
2234         /* For safety always re-enable waking and disable gfx clock forcing */
2235         vlv_allow_gt_wake(dev_priv, true);
2236 err1:
2237         vlv_force_gfx_clock(dev_priv, false);
2238
2239         return err;
2240 }
2241
2242 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2243                                 bool rpm_resume)
2244 {
2245         struct drm_device *dev = &dev_priv->drm;
2246         int err;
2247         int ret;
2248
2249         /*
2250          * If any of the steps fail just try to continue, that's the best we
2251          * can do at this point. Return the first error code (which will also
2252          * leave RPM permanently disabled).
2253          */
2254         ret = vlv_force_gfx_clock(dev_priv, true);
2255
2256         if (!IS_CHERRYVIEW(dev_priv))
2257                 vlv_restore_gunit_s0ix_state(dev_priv);
2258
2259         err = vlv_allow_gt_wake(dev_priv, true);
2260         if (!ret)
2261                 ret = err;
2262
2263         err = vlv_force_gfx_clock(dev_priv, false);
2264         if (!ret)
2265                 ret = err;
2266
2267         vlv_check_no_gt_access(dev_priv);
2268
2269         if (rpm_resume) {
2270                 intel_init_clock_gating(dev);
2271                 i915_gem_restore_fences(dev);
2272         }
2273
2274         return ret;
2275 }
2276
2277 static int intel_runtime_suspend(struct device *device)
2278 {
2279         struct pci_dev *pdev = to_pci_dev(device);
2280         struct drm_device *dev = pci_get_drvdata(pdev);
2281         struct drm_i915_private *dev_priv = to_i915(dev);
2282         int ret;
2283
2284         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2285                 return -ENODEV;
2286
2287         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2288                 return -ENODEV;
2289
2290         DRM_DEBUG_KMS("Suspending device\n");
2291
2292         /*
2293          * We could deadlock here in case another thread holding struct_mutex
2294          * calls RPM suspend concurrently, since the RPM suspend will wait
2295          * first for this RPM suspend to finish. In this case the concurrent
2296          * RPM resume will be followed by its RPM suspend counterpart. Still
2297          * for consistency return -EAGAIN, which will reschedule this suspend.
2298          */
2299         if (!mutex_trylock(&dev->struct_mutex)) {
2300                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2301                 /*
2302                  * Bump the expiration timestamp, otherwise the suspend won't
2303                  * be rescheduled.
2304                  */
2305                 pm_runtime_mark_last_busy(device);
2306
2307                 return -EAGAIN;
2308         }
2309
2310         disable_rpm_wakeref_asserts(dev_priv);
2311
2312         /*
2313          * We are safe here against re-faults, since the fault handler takes
2314          * an RPM reference.
2315          */
2316         i915_gem_release_all_mmaps(dev_priv);
2317         mutex_unlock(&dev->struct_mutex);
2318
2319         intel_guc_suspend(dev);
2320
2321         intel_runtime_pm_disable_interrupts(dev_priv);
2322
2323         ret = 0;
2324         if (IS_BROXTON(dev_priv)) {
2325                 bxt_display_core_uninit(dev_priv);
2326                 bxt_enable_dc9(dev_priv);
2327         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2328                 hsw_enable_pc8(dev_priv);
2329         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2330                 ret = vlv_suspend_complete(dev_priv);
2331         }
2332
2333         if (ret) {
2334                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2335                 intel_runtime_pm_enable_interrupts(dev_priv);
2336
2337                 enable_rpm_wakeref_asserts(dev_priv);
2338
2339                 return ret;
2340         }
2341
2342         intel_uncore_forcewake_reset(dev_priv, false);
2343
2344         enable_rpm_wakeref_asserts(dev_priv);
2345         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2346
2347         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2348                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2349
2350         dev_priv->pm.suspended = true;
2351
2352         /*
2353          * FIXME: We really should find a document that references the arguments
2354          * used below!
2355          */
2356         if (IS_BROADWELL(dev_priv)) {
2357                 /*
2358                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2359                  * being detected, and the call we do at intel_runtime_resume()
2360                  * won't be able to restore them. Since PCI_D3hot matches the
2361                  * actual specification and appears to be working, use it.
2362                  */
2363                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2364         } else {
2365                 /*
2366                  * current versions of firmware which depend on this opregion
2367                  * notification have repurposed the D1 definition to mean
2368                  * "runtime suspended" vs. what you would normally expect (D3)
2369                  * to distinguish it from notifications that might be sent via
2370                  * the suspend path.
2371                  */
2372                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2373         }
2374
2375         assert_forcewakes_inactive(dev_priv);
2376
2377         if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2378                 intel_hpd_poll_init(dev_priv);
2379
2380         DRM_DEBUG_KMS("Device suspended\n");
2381         return 0;
2382 }
2383
2384 static int intel_runtime_resume(struct device *device)
2385 {
2386         struct pci_dev *pdev = to_pci_dev(device);
2387         struct drm_device *dev = pci_get_drvdata(pdev);
2388         struct drm_i915_private *dev_priv = to_i915(dev);
2389         int ret = 0;
2390
2391         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2392                 return -ENODEV;
2393
2394         DRM_DEBUG_KMS("Resuming device\n");
2395
2396         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2397         disable_rpm_wakeref_asserts(dev_priv);
2398
2399         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2400         dev_priv->pm.suspended = false;
2401         if (intel_uncore_unclaimed_mmio(dev_priv))
2402                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2403
2404         intel_guc_resume(dev);
2405
2406         if (IS_GEN6(dev_priv))
2407                 intel_init_pch_refclk(dev);
2408
2409         if (IS_BROXTON(dev)) {
2410                 bxt_disable_dc9(dev_priv);
2411                 bxt_display_core_init(dev_priv, true);
2412                 if (dev_priv->csr.dmc_payload &&
2413                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2414                         gen9_enable_dc5(dev_priv);
2415         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2416                 hsw_disable_pc8(dev_priv);
2417         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2418                 ret = vlv_resume_prepare(dev_priv, true);
2419         }
2420
2421         /*
2422          * No point of rolling back things in case of an error, as the best
2423          * we can do is to hope that things will still work (and disable RPM).
2424          */
2425         i915_gem_init_swizzling(dev);
2426
2427         intel_runtime_pm_enable_interrupts(dev_priv);
2428
2429         /*
2430          * On VLV/CHV display interrupts are part of the display
2431          * power well, so hpd is reinitialized from there. For
2432          * everyone else do it here.
2433          */
2434         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2435                 intel_hpd_init(dev_priv);
2436
2437         enable_rpm_wakeref_asserts(dev_priv);
2438
2439         if (ret)
2440                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2441         else
2442                 DRM_DEBUG_KMS("Device resumed\n");
2443
2444         return ret;
2445 }
2446
2447 const struct dev_pm_ops i915_pm_ops = {
2448         /*
2449          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2450          * PMSG_RESUME]
2451          */
2452         .suspend = i915_pm_suspend,
2453         .suspend_late = i915_pm_suspend_late,
2454         .resume_early = i915_pm_resume_early,
2455         .resume = i915_pm_resume,
2456
2457         /*
2458          * S4 event handlers
2459          * @freeze, @freeze_late    : called (1) before creating the
2460          *                            hibernation image [PMSG_FREEZE] and
2461          *                            (2) after rebooting, before restoring
2462          *                            the image [PMSG_QUIESCE]
2463          * @thaw, @thaw_early       : called (1) after creating the hibernation
2464          *                            image, before writing it [PMSG_THAW]
2465          *                            and (2) after failing to create or
2466          *                            restore the image [PMSG_RECOVER]
2467          * @poweroff, @poweroff_late: called after writing the hibernation
2468          *                            image, before rebooting [PMSG_HIBERNATE]
2469          * @restore, @restore_early : called after rebooting and restoring the
2470          *                            hibernation image [PMSG_RESTORE]
2471          */
2472         .freeze = i915_pm_freeze,
2473         .freeze_late = i915_pm_freeze_late,
2474         .thaw_early = i915_pm_thaw_early,
2475         .thaw = i915_pm_thaw,
2476         .poweroff = i915_pm_suspend,
2477         .poweroff_late = i915_pm_poweroff_late,
2478         .restore_early = i915_pm_restore_early,
2479         .restore = i915_pm_restore,
2480
2481         /* S0ix (via runtime suspend) event handlers */
2482         .runtime_suspend = intel_runtime_suspend,
2483         .runtime_resume = intel_runtime_resume,
2484 };
2485
2486 static const struct vm_operations_struct i915_gem_vm_ops = {
2487         .fault = i915_gem_fault,
2488         .open = drm_gem_vm_open,
2489         .close = drm_gem_vm_close,
2490 };
2491
2492 static const struct file_operations i915_driver_fops = {
2493         .owner = THIS_MODULE,
2494         .open = drm_open,
2495         .release = drm_release,
2496         .unlocked_ioctl = drm_ioctl,
2497         .mmap = drm_gem_mmap,
2498         .poll = drm_poll,
2499         .read = drm_read,
2500 #ifdef CONFIG_COMPAT
2501         .compat_ioctl = i915_compat_ioctl,
2502 #endif
2503         .llseek = noop_llseek,
2504 };
2505
2506 static int
2507 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2508                           struct drm_file *file)
2509 {
2510         return -ENODEV;
2511 }
2512
2513 static const struct drm_ioctl_desc i915_ioctls[] = {
2514         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2515         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2516         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2517         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2518         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2519         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2520         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2521         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2522         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2523         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2524         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2525         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2526         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2527         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2528         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2529         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2530         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2531         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2532         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2533         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2534         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2535         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2536         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2537         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2538         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2539         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2540         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2541         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2542         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2543         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2544         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2545         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2546         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2547         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2548         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2549         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2550         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2551         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2552         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2553         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2554         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2555         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2556         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2557         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2558         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2559         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2560         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2561         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2562         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2563         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2564         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2565         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2566 };
2567
2568 static struct drm_driver driver = {
2569         /* Don't use MTRRs here; the Xserver or userspace app should
2570          * deal with them for Intel hardware.
2571          */
2572         .driver_features =
2573             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2574             DRIVER_RENDER | DRIVER_MODESET,
2575         .open = i915_driver_open,
2576         .lastclose = i915_driver_lastclose,
2577         .preclose = i915_driver_preclose,
2578         .postclose = i915_driver_postclose,
2579         .set_busid = drm_pci_set_busid,
2580
2581         .gem_close_object = i915_gem_close_object,
2582         .gem_free_object = i915_gem_free_object,
2583         .gem_vm_ops = &i915_gem_vm_ops,
2584
2585         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2586         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2587         .gem_prime_export = i915_gem_prime_export,
2588         .gem_prime_import = i915_gem_prime_import,
2589
2590         .dumb_create = i915_gem_dumb_create,
2591         .dumb_map_offset = i915_gem_mmap_gtt,
2592         .dumb_destroy = drm_gem_dumb_destroy,
2593         .ioctls = i915_ioctls,
2594         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2595         .fops = &i915_driver_fops,
2596         .name = DRIVER_NAME,
2597         .desc = DRIVER_DESC,
2598         .date = DRIVER_DATE,
2599         .major = DRIVER_MAJOR,
2600         .minor = DRIVER_MINOR,
2601         .patchlevel = DRIVER_PATCHLEVEL,
2602 };