drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41 #include <acpi/video.h>
  42
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_irq.h>
  46 #include <drm/drm_managed.h>
  47 #include <drm/drm_probe_helper.h>
  48
  49 #include "display/intel_acpi.h"
  50 #include "display/intel_audio.h"
  51 #include "display/intel_bw.h"
  52 #include "display/intel_cdclk.h"
  53 #include "display/intel_csr.h"
  54 #include "display/intel_display_debugfs.h"
  55 #include "display/intel_display_types.h"
  56 #include "display/intel_dp.h"
  57 #include "display/intel_fbdev.h"
  58 #include "display/intel_hotplug.h"
  59 #include "display/intel_overlay.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_pps.h"
  62 #include "display/intel_sprite.h"
  63 #include "display/intel_vga.h"
  64
  65 #include "gem/i915_gem_context.h"
  66 #include "gem/i915_gem_ioctls.h"
  67 #include "gem/i915_gem_mman.h"
  68 #include "gt/intel_gt.h"
  69 #include "gt/intel_gt_pm.h"
  70 #include "gt/intel_rc6.h"
  71
  72 #include "i915_debugfs.h"
  73 #include "i915_drv.h"
  74 #include "i915_ioc32.h"
  75 #include "i915_irq.h"
  76 #include "i915_memcpy.h"
  77 #include "i915_perf.h"
  78 #include "i915_query.h"
  79 #include "i915_suspend.h"
  80 #include "i915_switcheroo.h"
  81 #include "i915_sysfs.h"
  82 #include "i915_trace.h"
  83 #include "i915_vgpu.h"
  84 #include "intel_dram.h"
  85 #include "intel_gvt.h"
  86 #include "intel_memory_region.h"
  87 #include "intel_pm.h"
  88 #include "intel_sideband.h"
  89 #include "vlv_suspend.h"
  90
  91 static const struct drm_driver driver;
  92
  93 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  94 {
  95         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
  96
  97         dev_priv->bridge_dev =
  98                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
  99         if (!dev_priv->bridge_dev) {
 100                 drm_err(&dev_priv->drm, "bridge device not found\n");
 101                 return -1;
 102         }
 103         return 0;
 104 }
 105
 106 /* Allocate space for the MCH regs if needed, return nonzero on error */
 107 static int
 108 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 109 {
 110         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 111         u32 temp_lo, temp_hi = 0;
 112         u64 mchbar_addr;
 113         int ret;
 114
 115         if (INTEL_GEN(dev_priv) >= 4)
 116                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 117         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 118         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 119
 120         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 121 #ifdef CONFIG_PNP
 122         if (mchbar_addr &&
 123             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 124                 return 0;
 125 #endif
 126
 127         /* Get some space for it */
 128         dev_priv->mch_res.name = "i915 MCHBAR";
 129         dev_priv->mch_res.flags = IORESOURCE_MEM;
 130         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 131                                      &dev_priv->mch_res,
 132                                      MCHBAR_SIZE, MCHBAR_SIZE,
 133                                      PCIBIOS_MIN_MEM,
 134                                      0, pcibios_align_resource,
 135                                      dev_priv->bridge_dev);
 136         if (ret) {
 137                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 138                 dev_priv->mch_res.start = 0;
 139                 return ret;
 140         }
 141
 142         if (INTEL_GEN(dev_priv) >= 4)
 143                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 144                                        upper_32_bits(dev_priv->mch_res.start));
 145
 146         pci_write_config_dword(dev_priv->bridge_dev, reg,
 147                                lower_32_bits(dev_priv->mch_res.start));
 148         return 0;
 149 }
 150
 151 /* Setup MCHBAR if possible, return true if we should disable it again */
 152 static void
 153 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 154 {
 155         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 156         u32 temp;
 157         bool enabled;
 158
 159         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 160                 return;
 161
 162         dev_priv->mchbar_need_disable = false;
 163
 164         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 165                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 166                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 167         } else {
 168                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 169                 enabled = temp & 1;
 170         }
 171
 172         /* If it's already enabled, don't have to do anything */
 173         if (enabled)
 174                 return;
 175
 176         if (intel_alloc_mchbar_resource(dev_priv))
 177                 return;
 178
 179         dev_priv->mchbar_need_disable = true;
 180
 181         /* Space is allocated or reserved, so enable it. */
 182         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 183                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 184                                        temp | DEVEN_MCHBAR_EN);
 185         } else {
 186                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 187                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 188         }
 189 }
 190
 191 static void
 192 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 193 {
 194         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 195
 196         if (dev_priv->mchbar_need_disable) {
 197                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 198                         u32 deven_val;
 199
 200                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 201                                               &deven_val);
 202                         deven_val &= ~DEVEN_MCHBAR_EN;
 203                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 204                                                deven_val);
 205                 } else {
 206                         u32 mchbar_val;
 207
 208                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 209                                               &mchbar_val);
 210                         mchbar_val &= ~1;
 211                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 212                                                mchbar_val);
 213                 }
 214         }
 215
 216         if (dev_priv->mch_res.start)
 217                 release_resource(&dev_priv->mch_res);
 218 }
 219
 220 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 221 {
 222         /*
 223          * The i915 workqueue is primarily used for batched retirement of
 224          * requests (and thus managing bo) once the task has been completed
 225          * by the GPU. i915_retire_requests() is called directly when we
 226          * need high-priority retirement, such as waiting for an explicit
 227          * bo.
 228          *
 229          * It is also used for periodic low-priority events, such as
 230          * idle-timers and recording error state.
 231          *
 232          * All tasks on the workqueue are expected to acquire the dev mutex
 233          * so there is no point in running more than one instance of the
 234          * workqueue at any time.  Use an ordered one.
 235          */
 236         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 237         if (dev_priv->wq == NULL)
 238                 goto out_err;
 239
 240         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 241         if (dev_priv->hotplug.dp_wq == NULL)
 242                 goto out_free_wq;
 243
 244         return 0;
 245
 246 out_free_wq:
 247         destroy_workqueue(dev_priv->wq);
 248 out_err:
 249         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 250
 251         return -ENOMEM;
 252 }
 253
 254 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 255 {
 256         destroy_workqueue(dev_priv->hotplug.dp_wq);
 257         destroy_workqueue(dev_priv->wq);
 258 }
 259
 260 /*
 261  * We don't keep the workarounds for pre-production hardware, so we expect our
 262  * driver to fail on these machines in one way or another. A little warning on
 263  * dmesg may help both the user and the bug triagers.
 264  *
 265  * Our policy for removing pre-production workarounds is to keep the
 266  * current gen workarounds as a guide to the bring-up of the next gen
 267  * (workarounds have a habit of persisting!). Anything older than that
 268  * should be removed along with the complications they introduce.
 269  */
 270 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 271 {
 272         bool pre = false;
 273
 274         pre |= IS_HSW_EARLY_SDV(dev_priv);
 275         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 276         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 277         pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0);
 278         pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
 279
 280         if (pre) {
 281                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 282                           "It may not be fully functional.\n");
 283                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 284         }
 285 }
 286
 287 static void sanitize_gpu(struct drm_i915_private *i915)
 288 {
 289         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 290                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 291 }
 292
 293 /**
 294  * i915_driver_early_probe - setup state not requiring device access
 295  * @dev_priv: device private
 296  *
 297  * Initialize everything that is a "SW-only" state, that is state not
 298  * requiring accessing the device or exposing the driver via kernel internal
 299  * or userspace interfaces. Example steps belonging here: lock initialization,
 300  * system memory allocation, setting up device specific attributes and
 301  * function hooks not requiring accessing the device.
 302  */
 303 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 304 {
 305         int ret = 0;
 306
 307         if (i915_inject_probe_failure(dev_priv))
 308                 return -ENODEV;
 309
 310         intel_device_info_subplatform_init(dev_priv);
 311
 312         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 313         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 314
 315         spin_lock_init(&dev_priv->irq_lock);
 316         spin_lock_init(&dev_priv->gpu_error.lock);
 317         mutex_init(&dev_priv->backlight_lock);
 318
 319         mutex_init(&dev_priv->sb_lock);
 320         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 321
 322         mutex_init(&dev_priv->av_mutex);
 323         mutex_init(&dev_priv->wm.wm_mutex);
 324         mutex_init(&dev_priv->pps_mutex);
 325         mutex_init(&dev_priv->hdcp_comp_mutex);
 326
 327         i915_memcpy_init_early(dev_priv);
 328         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 329
 330         ret = i915_workqueues_init(dev_priv);
 331         if (ret < 0)
 332                 return ret;
 333
 334         ret = vlv_suspend_init(dev_priv);
 335         if (ret < 0)
 336                 goto err_workqueues;
 337
 338         intel_wopcm_init_early(&dev_priv->wopcm);
 339
 340         intel_gt_init_early(&dev_priv->gt, dev_priv);
 341
 342         i915_gem_init_early(dev_priv);
 343
 344         /* This must be called before any calls to HAS_PCH_* */
 345         intel_detect_pch(dev_priv);
 346
 347         intel_pm_setup(dev_priv);
 348         ret = intel_power_domains_init(dev_priv);
 349         if (ret < 0)
 350                 goto err_gem;
 351         intel_irq_init(dev_priv);
 352         intel_init_display_hooks(dev_priv);
 353         intel_init_clock_gating_hooks(dev_priv);
 354         intel_init_audio_hooks(dev_priv);
 355
 356         intel_detect_preproduction_hw(dev_priv);
 357
 358         return 0;
 359
 360 err_gem:
 361         i915_gem_cleanup_early(dev_priv);
 362         intel_gt_driver_late_release(&dev_priv->gt);
 363         vlv_suspend_cleanup(dev_priv);
 364 err_workqueues:
 365         i915_workqueues_cleanup(dev_priv);
 366         return ret;
 367 }
 368
 369 /**
 370  * i915_driver_late_release - cleanup the setup done in
 371  *                             i915_driver_early_probe()
 372  * @dev_priv: device private
 373  */
 374 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 375 {
 376         intel_irq_fini(dev_priv);
 377         intel_power_domains_cleanup(dev_priv);
 378         i915_gem_cleanup_early(dev_priv);
 379         intel_gt_driver_late_release(&dev_priv->gt);
 380         vlv_suspend_cleanup(dev_priv);
 381         i915_workqueues_cleanup(dev_priv);
 382
 383         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 384         mutex_destroy(&dev_priv->sb_lock);
 385
 386         i915_params_free(&dev_priv->params);
 387 }
 388
 389 /**
 390  * i915_driver_mmio_probe - setup device MMIO
 391  * @dev_priv: device private
 392  *
 393  * Setup minimal device state necessary for MMIO accesses later in the
 394  * initialization sequence. The setup here should avoid any other device-wide
 395  * side effects or exposing the driver via kernel internal or user space
 396  * interfaces.
 397  */
 398 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 399 {
 400         int ret;
 401
 402         if (i915_inject_probe_failure(dev_priv))
 403                 return -ENODEV;
 404
 405         if (i915_get_bridge_dev(dev_priv))
 406                 return -EIO;
 407
 408         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 409         if (ret < 0)
 410                 goto err_bridge;
 411
 412         /* Try to make sure MCHBAR is enabled before poking at it */
 413         intel_setup_mchbar(dev_priv);
 414         intel_device_info_runtime_init(dev_priv);
 415
 416         ret = intel_gt_init_mmio(&dev_priv->gt);
 417         if (ret)
 418                 goto err_uncore;
 419
 420         /* As early as possible, scrub existing GPU state before clobbering */
 421         sanitize_gpu(dev_priv);
 422
 423         return 0;
 424
 425 err_uncore:
 426         intel_teardown_mchbar(dev_priv);
 427         intel_uncore_fini_mmio(&dev_priv->uncore);
 428 err_bridge:
 429         pci_dev_put(dev_priv->bridge_dev);
 430
 431         return ret;
 432 }
 433
 434 /**
 435  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 436  * @dev_priv: device private
 437  */
 438 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 439 {
 440         intel_teardown_mchbar(dev_priv);
 441         intel_uncore_fini_mmio(&dev_priv->uncore);
 442         pci_dev_put(dev_priv->bridge_dev);
 443 }
 444
 445 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 446 {
 447         intel_gvt_sanitize_options(dev_priv);
 448 }
 449
 450 /**
 451  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 452  * platform
 453  * @i915: valid i915 instance
 454  *
 455  * Set the dma max segment size, device and coherent masks.  The dma mask set
 456  * needs to occur before i915_ggtt_probe_hw.
 457  *
 458  * A couple of platforms have special needs.  Address them as well.
 459  *
 460  */
 461 static int i915_set_dma_info(struct drm_i915_private *i915)
 462 {
 463         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 464         int ret;
 465
 466         GEM_BUG_ON(!mask_size);
 467
 468         /*
 469          * We don't have a max segment size, so set it to the max so sg's
 470          * debugging layer doesn't complain
 471          */
 472         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 473
 474         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 475         if (ret)
 476                 goto mask_err;
 477
 478         /* overlay on gen2 is broken and can't address above 1G */
 479         if (IS_GEN(i915, 2))
 480                 mask_size = 30;
 481
 482         /*
 483          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 484          * using 32bit addressing, overwriting memory if HWS is located
 485          * above 4GB.
 486          *
 487          * The documentation also mentions an issue with undefined
 488          * behaviour if any general state is accessed within a page above 4GB,
 489          * which also needs to be handled carefully.
 490          */
 491         if (IS_I965G(i915) || IS_I965GM(i915))
 492                 mask_size = 32;
 493
 494         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 495         if (ret)
 496                 goto mask_err;
 497
 498         return 0;
 499
 500 mask_err:
 501         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 502         return ret;
 503 }
 504
 505 /**
 506  * i915_driver_hw_probe - setup state requiring device access
 507  * @dev_priv: device private
 508  *
 509  * Setup state that requires accessing the device, but doesn't require
 510  * exposing the driver via kernel internal or userspace interfaces.
 511  */
 512 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 513 {
 514         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 515         int ret;
 516
 517         if (i915_inject_probe_failure(dev_priv))
 518                 return -ENODEV;
 519
 520         if (HAS_PPGTT(dev_priv)) {
 521                 if (intel_vgpu_active(dev_priv) &&
 522                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 523                         i915_report_error(dev_priv,
 524                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 525                         return -ENXIO;
 526                 }
 527         }
 528
 529         if (HAS_EXECLISTS(dev_priv)) {
 530                 /*
 531                  * Older GVT emulation depends upon intercepting CSB mmio,
 532                  * which we no longer use, preferring to use the HWSP cache
 533                  * instead.
 534                  */
 535                 if (intel_vgpu_active(dev_priv) &&
 536                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 537                         i915_report_error(dev_priv,
 538                                           "old vGPU host found, support for HWSP emulation required\n");
 539                         return -ENXIO;
 540                 }
 541         }
 542
 543         intel_sanitize_options(dev_priv);
 544
 545         /* needs to be done before ggtt probe */
 546         intel_dram_edram_detect(dev_priv);
 547
 548         ret = i915_set_dma_info(dev_priv);
 549         if (ret)
 550                 return ret;
 551
 552         i915_perf_init(dev_priv);
 553
 554         ret = i915_ggtt_probe_hw(dev_priv);
 555         if (ret)
 556                 goto err_perf;
 557
 558         ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
 559         if (ret)
 560                 goto err_ggtt;
 561
 562         ret = i915_ggtt_init_hw(dev_priv);
 563         if (ret)
 564                 goto err_ggtt;
 565
 566         ret = intel_memory_regions_hw_probe(dev_priv);
 567         if (ret)
 568                 goto err_ggtt;
 569
 570         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 571
 572         ret = i915_ggtt_enable_hw(dev_priv);
 573         if (ret) {
 574                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 575                 goto err_mem_regions;
 576         }
 577
 578         pci_set_master(pdev);
 579
 580         intel_gt_init_workarounds(dev_priv);
 581
 582         /* On the 945G/GM, the chipset reports the MSI capability on the
 583          * integrated graphics even though the support isn't actually there
 584          * according to the published specs.  It doesn't appear to function
 585          * correctly in testing on 945G.
 586          * This may be a side effect of MSI having been made available for PEG
 587          * and the registers being closely associated.
 588          *
 589          * According to chipset errata, on the 965GM, MSI interrupts may
 590          * be lost or delayed, and was defeatured. MSI interrupts seem to
 591          * get lost on g4x as well, and interrupt delivery seems to stay
 592          * properly dead afterwards. So we'll just disable them for all
 593          * pre-gen5 chipsets.
 594          *
 595          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 596          * interrupts even when in MSI mode. This results in spurious
 597          * interrupt warnings if the legacy irq no. is shared with another
 598          * device. The kernel then disables that interrupt source and so
 599          * prevents the other device from working properly.
 600          */
 601         if (INTEL_GEN(dev_priv) >= 5) {
 602                 if (pci_enable_msi(pdev) < 0)
 603                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 604         }
 605
 606         ret = intel_gvt_init(dev_priv);
 607         if (ret)
 608                 goto err_msi;
 609
 610         intel_opregion_setup(dev_priv);
 611
 612         intel_pcode_init(dev_priv);
 613
 614         /*
 615          * Fill the dram structure to get the system dram info. This will be
 616          * used for memory latency calculation.
 617          */
 618         intel_dram_detect(dev_priv);
 619
 620         intel_bw_init_hw(dev_priv);
 621
 622         return 0;
 623
 624 err_msi:
 625         if (pdev->msi_enabled)
 626                 pci_disable_msi(pdev);
 627 err_mem_regions:
 628         intel_memory_regions_driver_release(dev_priv);
 629 err_ggtt:
 630         i915_ggtt_driver_release(dev_priv);
 631 err_perf:
 632         i915_perf_fini(dev_priv);
 633         return ret;
 634 }
 635
 636 /**
 637  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 638  * @dev_priv: device private
 639  */
 640 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 641 {
 642         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 643
 644         i915_perf_fini(dev_priv);
 645
 646         if (pdev->msi_enabled)
 647                 pci_disable_msi(pdev);
 648 }
 649
 650 /**
 651  * i915_driver_register - register the driver with the rest of the system
 652  * @dev_priv: device private
 653  *
 654  * Perform any steps necessary to make the driver available via kernel
 655  * internal or userspace interfaces.
 656  */
 657 static void i915_driver_register(struct drm_i915_private *dev_priv)
 658 {
 659         struct drm_device *dev = &dev_priv->drm;
 660
 661         i915_gem_driver_register(dev_priv);
 662         i915_pmu_register(dev_priv);
 663
 664         intel_vgpu_register(dev_priv);
 665
 666         /* Reveal our presence to userspace */
 667         if (drm_dev_register(dev, 0) == 0) {
 668                 i915_debugfs_register(dev_priv);
 669                 if (HAS_DISPLAY(dev_priv))
 670                         intel_display_debugfs_register(dev_priv);
 671                 i915_setup_sysfs(dev_priv);
 672
 673                 /* Depends on sysfs having been initialized */
 674                 i915_perf_register(dev_priv);
 675         } else
 676                 drm_err(&dev_priv->drm,
 677                         "Failed to register driver for userspace access!\n");
 678
 679         if (HAS_DISPLAY(dev_priv)) {
 680                 /* Must be done after probing outputs */
 681                 intel_opregion_register(dev_priv);
 682                 acpi_video_register();
 683         }
 684
 685         intel_gt_driver_register(&dev_priv->gt);
 686
 687         intel_audio_init(dev_priv);
 688
 689         /*
 690          * Some ports require correctly set-up hpd registers for detection to
 691          * work properly (leading to ghost connected connector status), e.g. VGA
 692          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 693          * irqs are fully enabled. We do it last so that the async config
 694          * cannot run before the connectors are registered.
 695          */
 696         intel_fbdev_initial_config_async(dev);
 697
 698         /*
 699          * We need to coordinate the hotplugs with the asynchronous fbdev
 700          * configuration, for which we use the fbdev->async_cookie.
 701          */
 702         if (HAS_DISPLAY(dev_priv))
 703                 drm_kms_helper_poll_init(dev);
 704
 705         intel_power_domains_enable(dev_priv);
 706         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 707
 708         intel_register_dsm_handler();
 709
 710         if (i915_switcheroo_register(dev_priv))
 711                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 712 }
 713
 714 /**
 715  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 716  * @dev_priv: device private
 717  */
 718 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 719 {
 720         i915_switcheroo_unregister(dev_priv);
 721
 722         intel_unregister_dsm_handler();
 723
 724         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 725         intel_power_domains_disable(dev_priv);
 726
 727         intel_fbdev_unregister(dev_priv);
 728         intel_audio_deinit(dev_priv);
 729
 730         /*
 731          * After flushing the fbdev (incl. a late async config which will
 732          * have delayed queuing of a hotplug event), then flush the hotplug
 733          * events.
 734          */
 735         drm_kms_helper_poll_fini(&dev_priv->drm);
 736         drm_atomic_helper_shutdown(&dev_priv->drm);
 737
 738         intel_gt_driver_unregister(&dev_priv->gt);
 739         acpi_video_unregister();
 740         intel_opregion_unregister(dev_priv);
 741
 742         i915_perf_unregister(dev_priv);
 743         i915_pmu_unregister(dev_priv);
 744
 745         i915_teardown_sysfs(dev_priv);
 746         drm_dev_unplug(&dev_priv->drm);
 747
 748         i915_gem_driver_unregister(dev_priv);
 749 }
 750
 751 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 752 {
 753         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 754                 struct drm_printer p = drm_debug_printer("i915 device info:");
 755
 756                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 757                            INTEL_DEVID(dev_priv),
 758                            INTEL_REVID(dev_priv),
 759                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 760                            intel_subplatform(RUNTIME_INFO(dev_priv),
 761                                              INTEL_INFO(dev_priv)->platform),
 762                            INTEL_GEN(dev_priv));
 763
 764                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 765                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 766                 intel_gt_info_print(&dev_priv->gt.info, &p);
 767         }
 768
 769         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 770                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 771         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 772                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 773         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 774                 drm_info(&dev_priv->drm,
 775                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 776 }
 777
 778 static struct drm_i915_private *
 779 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 780 {
 781         const struct intel_device_info *match_info =
 782                 (struct intel_device_info *)ent->driver_data;
 783         struct intel_device_info *device_info;
 784         struct drm_i915_private *i915;
 785
 786         i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
 787                                   struct drm_i915_private, drm);
 788         if (IS_ERR(i915))
 789                 return i915;
 790
 791         i915->drm.pdev = pdev;
 792         pci_set_drvdata(pdev, i915);
 793
 794         /* Device parameters start as a copy of module parameters. */
 795         i915_params_copy(&i915->params, &i915_modparams);
 796
 797         /* Setup the write-once "constant" device info */
 798         device_info = mkwrite_device_info(i915);
 799         memcpy(device_info, match_info, sizeof(*device_info));
 800         RUNTIME_INFO(i915)->device_id = pdev->device;
 801
 802         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
 803
 804         return i915;
 805 }
 806
 807 /**
 808  * i915_driver_probe - setup chip and create an initial config
 809  * @pdev: PCI device
 810  * @ent: matching PCI ID entry
 811  *
 812  * The driver probe routine has to do several things:
 813  *   - drive output discovery via intel_modeset_init()
 814  *   - initialize the memory manager
 815  *   - allocate initial config memory
 816  *   - setup the DRM framebuffer with the allocated memory
 817  */
 818 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 819 {
 820         const struct intel_device_info *match_info =
 821                 (struct intel_device_info *)ent->driver_data;
 822         struct drm_i915_private *i915;
 823         int ret;
 824
 825         i915 = i915_driver_create(pdev, ent);
 826         if (IS_ERR(i915))
 827                 return PTR_ERR(i915);
 828
 829         /* Disable nuclear pageflip by default on pre-ILK */
 830         if (!i915->params.nuclear_pageflip && match_info->gen < 5)
 831                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 832
 833         /*
 834          * Check if we support fake LMEM -- for now we only unleash this for
 835          * the live selftests(test-and-exit).
 836          */
 837 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 838         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 839                 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
 840                     i915->params.fake_lmem_start) {
 841                         mkwrite_device_info(i915)->memory_regions =
 842                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
 843                         GEM_BUG_ON(!HAS_LMEM(i915));
 844                 }
 845         }
 846 #endif
 847
 848         ret = pci_enable_device(pdev);
 849         if (ret)
 850                 goto out_fini;
 851
 852         ret = i915_driver_early_probe(i915);
 853         if (ret < 0)
 854                 goto out_pci_disable;
 855
 856         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 857
 858         intel_vgpu_detect(i915);
 859
 860         ret = i915_driver_mmio_probe(i915);
 861         if (ret < 0)
 862                 goto out_runtime_pm_put;
 863
 864         ret = i915_driver_hw_probe(i915);
 865         if (ret < 0)
 866                 goto out_cleanup_mmio;
 867
 868         ret = intel_modeset_init_noirq(i915);
 869         if (ret < 0)
 870                 goto out_cleanup_hw;
 871
 872         ret = intel_irq_install(i915);
 873         if (ret)
 874                 goto out_cleanup_modeset;
 875
 876         ret = intel_modeset_init_nogem(i915);
 877         if (ret)
 878                 goto out_cleanup_irq;
 879
 880         ret = i915_gem_init(i915);
 881         if (ret)
 882                 goto out_cleanup_modeset2;
 883
 884         ret = intel_modeset_init(i915);
 885         if (ret)
 886                 goto out_cleanup_gem;
 887
 888         i915_driver_register(i915);
 889
 890         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 891
 892         i915_welcome_messages(i915);
 893
 894         i915->do_release = true;
 895
 896         return 0;
 897
 898 out_cleanup_gem:
 899         i915_gem_suspend(i915);
 900         i915_gem_driver_remove(i915);
 901         i915_gem_driver_release(i915);
 902 out_cleanup_modeset2:
 903         /* FIXME clean up the error path */
 904         intel_modeset_driver_remove(i915);
 905         intel_irq_uninstall(i915);
 906         intel_modeset_driver_remove_noirq(i915);
 907         goto out_cleanup_modeset;
 908 out_cleanup_irq:
 909         intel_irq_uninstall(i915);
 910 out_cleanup_modeset:
 911         intel_modeset_driver_remove_nogem(i915);
 912 out_cleanup_hw:
 913         i915_driver_hw_remove(i915);
 914         intel_memory_regions_driver_release(i915);
 915         i915_ggtt_driver_release(i915);
 916 out_cleanup_mmio:
 917         i915_driver_mmio_release(i915);
 918 out_runtime_pm_put:
 919         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 920         i915_driver_late_release(i915);
 921 out_pci_disable:
 922         pci_disable_device(pdev);
 923 out_fini:
 924         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 925         return ret;
 926 }
 927
 928 void i915_driver_remove(struct drm_i915_private *i915)
 929 {
 930         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 931
 932         i915_driver_unregister(i915);
 933
 934         /* Flush any external code that still may be under the RCU lock */
 935         synchronize_rcu();
 936
 937         i915_gem_suspend(i915);
 938
 939         intel_gvt_driver_remove(i915);
 940
 941         intel_modeset_driver_remove(i915);
 942
 943         intel_irq_uninstall(i915);
 944
 945         intel_modeset_driver_remove_noirq(i915);
 946
 947         i915_reset_error_state(i915);
 948         i915_gem_driver_remove(i915);
 949
 950         intel_modeset_driver_remove_nogem(i915);
 951
 952         i915_driver_hw_remove(i915);
 953
 954         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 955 }
 956
 957 static void i915_driver_release(struct drm_device *dev)
 958 {
 959         struct drm_i915_private *dev_priv = to_i915(dev);
 960         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 961
 962         if (!dev_priv->do_release)
 963                 return;
 964
 965         disable_rpm_wakeref_asserts(rpm);
 966
 967         i915_gem_driver_release(dev_priv);
 968
 969         intel_memory_regions_driver_release(dev_priv);
 970         i915_ggtt_driver_release(dev_priv);
 971         i915_gem_drain_freed_objects(dev_priv);
 972
 973         i915_driver_mmio_release(dev_priv);
 974
 975         enable_rpm_wakeref_asserts(rpm);
 976         intel_runtime_pm_driver_release(rpm);
 977
 978         i915_driver_late_release(dev_priv);
 979 }
 980
 981 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 982 {
 983         struct drm_i915_private *i915 = to_i915(dev);
 984         int ret;
 985
 986         ret = i915_gem_open(i915, file);
 987         if (ret)
 988                 return ret;
 989
 990         return 0;
 991 }
 992
 993 /**
 994  * i915_driver_lastclose - clean up after all DRM clients have exited
 995  * @dev: DRM device
 996  *
 997  * Take care of cleaning up after all DRM clients have exited.  In the
 998  * mode setting case, we want to restore the kernel's initial mode (just
 999  * in case the last client left us in a bad state).
1000  *
1001  * Additionally, in the non-mode setting case, we'll tear down the GTT
1002  * and DMA structures, since the kernel won't be using them, and clea
1003  * up any GEM state.
1004  */
1005 static void i915_driver_lastclose(struct drm_device *dev)
1006 {
1007         intel_fbdev_restore_mode(dev);
1008         vga_switcheroo_process_delayed_switch();
1009 }
1010
1011 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1012 {
1013         struct drm_i915_file_private *file_priv = file->driver_priv;
1014
1015         i915_gem_context_close(file);
1016
1017         kfree_rcu(file_priv, rcu);
1018
1019         /* Catch up with all the deferred frees from "this" client */
1020         i915_gem_flush_free_objects(to_i915(dev));
1021 }
1022
1023 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1024 {
1025         struct drm_device *dev = &dev_priv->drm;
1026         struct intel_encoder *encoder;
1027
1028         drm_modeset_lock_all(dev);
1029         for_each_intel_encoder(dev, encoder)
1030                 if (encoder->suspend)
1031                         encoder->suspend(encoder);
1032         drm_modeset_unlock_all(dev);
1033 }
1034
1035 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1036 {
1037         struct drm_device *dev = &dev_priv->drm;
1038         struct intel_encoder *encoder;
1039
1040         drm_modeset_lock_all(dev);
1041         for_each_intel_encoder(dev, encoder)
1042                 if (encoder->shutdown)
1043                         encoder->shutdown(encoder);
1044         drm_modeset_unlock_all(dev);
1045 }
1046
1047 void i915_driver_shutdown(struct drm_i915_private *i915)
1048 {
1049         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1050         intel_runtime_pm_disable(&i915->runtime_pm);
1051         intel_power_domains_disable(i915);
1052
1053         i915_gem_suspend(i915);
1054
1055         drm_kms_helper_poll_disable(&i915->drm);
1056
1057         drm_atomic_helper_shutdown(&i915->drm);
1058
1059         intel_dp_mst_suspend(i915);
1060
1061         intel_runtime_pm_disable_interrupts(i915);
1062         intel_hpd_cancel_work(i915);
1063
1064         intel_suspend_encoders(i915);
1065         intel_shutdown_encoders(i915);
1066
1067         /*
1068          * The only requirement is to reboot with display DC states disabled,
1069          * for now leaving all display power wells in the INIT power domain
1070          * enabled matching the driver reload sequence.
1071          */
1072         intel_power_domains_driver_remove(i915);
1073         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1074
1075         intel_runtime_pm_driver_release(&i915->runtime_pm);
1076 }
1077
1078 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1079 {
1080 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1081         if (acpi_target_system_state() < ACPI_STATE_S3)
1082                 return true;
1083 #endif
1084         return false;
1085 }
1086
1087 static int i915_drm_prepare(struct drm_device *dev)
1088 {
1089         struct drm_i915_private *i915 = to_i915(dev);
1090
1091         /*
1092          * NB intel_display_suspend() may issue new requests after we've
1093          * ostensibly marked the GPU as ready-to-sleep here. We need to
1094          * split out that work and pull it forward so that after point,
1095          * the GPU is not woken again.
1096          */
1097         i915_gem_suspend(i915);
1098
1099         return 0;
1100 }
1101
1102 static int i915_drm_suspend(struct drm_device *dev)
1103 {
1104         struct drm_i915_private *dev_priv = to_i915(dev);
1105         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1106         pci_power_t opregion_target_state;
1107
1108         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1109
1110         /* We do a lot of poking in a lot of registers, make sure they work
1111          * properly. */
1112         intel_power_domains_disable(dev_priv);
1113
1114         drm_kms_helper_poll_disable(dev);
1115
1116         pci_save_state(pdev);
1117
1118         intel_display_suspend(dev);
1119
1120         intel_dp_mst_suspend(dev_priv);
1121
1122         intel_runtime_pm_disable_interrupts(dev_priv);
1123         intel_hpd_cancel_work(dev_priv);
1124
1125         intel_suspend_encoders(dev_priv);
1126
1127         intel_suspend_hw(dev_priv);
1128
1129         i915_ggtt_suspend(&dev_priv->ggtt);
1130
1131         i915_save_display(dev_priv);
1132
1133         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1134         intel_opregion_suspend(dev_priv, opregion_target_state);
1135
1136         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1137
1138         dev_priv->suspend_count++;
1139
1140         intel_csr_ucode_suspend(dev_priv);
1141
1142         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1143
1144         return 0;
1145 }
1146
1147 static enum i915_drm_suspend_mode
1148 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1149 {
1150         if (hibernate)
1151                 return I915_DRM_SUSPEND_HIBERNATE;
1152
1153         if (suspend_to_idle(dev_priv))
1154                 return I915_DRM_SUSPEND_IDLE;
1155
1156         return I915_DRM_SUSPEND_MEM;
1157 }
1158
1159 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1160 {
1161         struct drm_i915_private *dev_priv = to_i915(dev);
1162         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1163         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1164         int ret;
1165
1166         disable_rpm_wakeref_asserts(rpm);
1167
1168         i915_gem_suspend_late(dev_priv);
1169
1170         intel_uncore_suspend(&dev_priv->uncore);
1171
1172         intel_power_domains_suspend(dev_priv,
1173                                     get_suspend_mode(dev_priv, hibernation));
1174
1175         intel_display_power_suspend_late(dev_priv);
1176
1177         ret = vlv_suspend_complete(dev_priv);
1178         if (ret) {
1179                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1180                 intel_power_domains_resume(dev_priv);
1181
1182                 goto out;
1183         }
1184
1185         pci_disable_device(pdev);
1186         /*
1187          * During hibernation on some platforms the BIOS may try to access
1188          * the device even though it's already in D3 and hang the machine. So
1189          * leave the device in D0 on those platforms and hope the BIOS will
1190          * power down the device properly. The issue was seen on multiple old
1191          * GENs with different BIOS vendors, so having an explicit blacklist
1192          * is inpractical; apply the workaround on everything pre GEN6. The
1193          * platforms where the issue was seen:
1194          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1195          * Fujitsu FSC S7110
1196          * Acer Aspire 1830T
1197          */
1198         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1199                 pci_set_power_state(pdev, PCI_D3hot);
1200
1201 out:
1202         enable_rpm_wakeref_asserts(rpm);
1203         if (!dev_priv->uncore.user_forcewake_count)
1204                 intel_runtime_pm_driver_release(rpm);
1205
1206         return ret;
1207 }
1208
1209 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1210 {
1211         int error;
1212
1213         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1214                              state.event != PM_EVENT_FREEZE))
1215                 return -EINVAL;
1216
1217         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1218                 return 0;
1219
1220         error = i915_drm_suspend(&i915->drm);
1221         if (error)
1222                 return error;
1223
1224         return i915_drm_suspend_late(&i915->drm, false);
1225 }
1226
1227 static int i915_drm_resume(struct drm_device *dev)
1228 {
1229         struct drm_i915_private *dev_priv = to_i915(dev);
1230         int ret;
1231
1232         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1233
1234         sanitize_gpu(dev_priv);
1235
1236         ret = i915_ggtt_enable_hw(dev_priv);
1237         if (ret)
1238                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1239
1240         i915_ggtt_resume(&dev_priv->ggtt);
1241
1242         intel_csr_ucode_resume(dev_priv);
1243
1244         i915_restore_display(dev_priv);
1245         intel_pps_unlock_regs_wa(dev_priv);
1246
1247         intel_init_pch_refclk(dev_priv);
1248
1249         /*
1250          * Interrupts have to be enabled before any batches are run. If not the
1251          * GPU will hang. i915_gem_init_hw() will initiate batches to
1252          * update/restore the context.
1253          *
1254          * drm_mode_config_reset() needs AUX interrupts.
1255          *
1256          * Modeset enabling in intel_modeset_init_hw() also needs working
1257          * interrupts.
1258          */
1259         intel_runtime_pm_enable_interrupts(dev_priv);
1260
1261         drm_mode_config_reset(dev);
1262
1263         i915_gem_resume(dev_priv);
1264
1265         intel_modeset_init_hw(dev_priv);
1266         intel_init_clock_gating(dev_priv);
1267         intel_hpd_init(dev_priv);
1268
1269         /* MST sideband requires HPD interrupts enabled */
1270         intel_dp_mst_resume(dev_priv);
1271         intel_display_resume(dev);
1272
1273         intel_hpd_poll_disable(dev_priv);
1274         drm_kms_helper_poll_enable(dev);
1275
1276         intel_opregion_resume(dev_priv);
1277
1278         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1279
1280         intel_power_domains_enable(dev_priv);
1281
1282         intel_gvt_resume(dev_priv);
1283
1284         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1285
1286         return 0;
1287 }
1288
1289 static int i915_drm_resume_early(struct drm_device *dev)
1290 {
1291         struct drm_i915_private *dev_priv = to_i915(dev);
1292         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1293         int ret;
1294
1295         /*
1296          * We have a resume ordering issue with the snd-hda driver also
1297          * requiring our device to be power up. Due to the lack of a
1298          * parent/child relationship we currently solve this with an early
1299          * resume hook.
1300          *
1301          * FIXME: This should be solved with a special hdmi sink device or
1302          * similar so that power domains can be employed.
1303          */
1304
1305         /*
1306          * Note that we need to set the power state explicitly, since we
1307          * powered off the device during freeze and the PCI core won't power
1308          * it back up for us during thaw. Powering off the device during
1309          * freeze is not a hard requirement though, and during the
1310          * suspend/resume phases the PCI core makes sure we get here with the
1311          * device powered on. So in case we change our freeze logic and keep
1312          * the device powered we can also remove the following set power state
1313          * call.
1314          */
1315         ret = pci_set_power_state(pdev, PCI_D0);
1316         if (ret) {
1317                 drm_err(&dev_priv->drm,
1318                         "failed to set PCI D0 power state (%d)\n", ret);
1319                 return ret;
1320         }
1321
1322         /*
1323          * Note that pci_enable_device() first enables any parent bridge
1324          * device and only then sets the power state for this device. The
1325          * bridge enabling is a nop though, since bridge devices are resumed
1326          * first. The order of enabling power and enabling the device is
1327          * imposed by the PCI core as described above, so here we preserve the
1328          * same order for the freeze/thaw phases.
1329          *
1330          * TODO: eventually we should remove pci_disable_device() /
1331          * pci_enable_enable_device() from suspend/resume. Due to how they
1332          * depend on the device enable refcount we can't anyway depend on them
1333          * disabling/enabling the device.
1334          */
1335         if (pci_enable_device(pdev))
1336                 return -EIO;
1337
1338         pci_set_master(pdev);
1339
1340         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1341
1342         ret = vlv_resume_prepare(dev_priv, false);
1343         if (ret)
1344                 drm_err(&dev_priv->drm,
1345                         "Resume prepare failed: %d, continuing anyway\n", ret);
1346
1347         intel_uncore_resume_early(&dev_priv->uncore);
1348
1349         intel_gt_check_and_clear_faults(&dev_priv->gt);
1350
1351         intel_display_power_resume_early(dev_priv);
1352
1353         intel_power_domains_resume(dev_priv);
1354
1355         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1356
1357         return ret;
1358 }
1359
1360 int i915_resume_switcheroo(struct drm_i915_private *i915)
1361 {
1362         int ret;
1363
1364         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1365                 return 0;
1366
1367         ret = i915_drm_resume_early(&i915->drm);
1368         if (ret)
1369                 return ret;
1370
1371         return i915_drm_resume(&i915->drm);
1372 }
1373
1374 static int i915_pm_prepare(struct device *kdev)
1375 {
1376         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1377
1378         if (!i915) {
1379                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1380                 return -ENODEV;
1381         }
1382
1383         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1384                 return 0;
1385
1386         return i915_drm_prepare(&i915->drm);
1387 }
1388
1389 static int i915_pm_suspend(struct device *kdev)
1390 {
1391         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1392
1393         if (!i915) {
1394                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1395                 return -ENODEV;
1396         }
1397
1398         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1399                 return 0;
1400
1401         return i915_drm_suspend(&i915->drm);
1402 }
1403
1404 static int i915_pm_suspend_late(struct device *kdev)
1405 {
1406         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1407
1408         /*
1409          * We have a suspend ordering issue with the snd-hda driver also
1410          * requiring our device to be power up. Due to the lack of a
1411          * parent/child relationship we currently solve this with an late
1412          * suspend hook.
1413          *
1414          * FIXME: This should be solved with a special hdmi sink device or
1415          * similar so that power domains can be employed.
1416          */
1417         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1418                 return 0;
1419
1420         return i915_drm_suspend_late(&i915->drm, false);
1421 }
1422
1423 static int i915_pm_poweroff_late(struct device *kdev)
1424 {
1425         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1426
1427         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1428                 return 0;
1429
1430         return i915_drm_suspend_late(&i915->drm, true);
1431 }
1432
1433 static int i915_pm_resume_early(struct device *kdev)
1434 {
1435         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1436
1437         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1438                 return 0;
1439
1440         return i915_drm_resume_early(&i915->drm);
1441 }
1442
1443 static int i915_pm_resume(struct device *kdev)
1444 {
1445         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1446
1447         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1448                 return 0;
1449
1450         return i915_drm_resume(&i915->drm);
1451 }
1452
1453 /* freeze: before creating the hibernation_image */
1454 static int i915_pm_freeze(struct device *kdev)
1455 {
1456         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1457         int ret;
1458
1459         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1460                 ret = i915_drm_suspend(&i915->drm);
1461                 if (ret)
1462                         return ret;
1463         }
1464
1465         ret = i915_gem_freeze(i915);
1466         if (ret)
1467                 return ret;
1468
1469         return 0;
1470 }
1471
1472 static int i915_pm_freeze_late(struct device *kdev)
1473 {
1474         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1475         int ret;
1476
1477         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1478                 ret = i915_drm_suspend_late(&i915->drm, true);
1479                 if (ret)
1480                         return ret;
1481         }
1482
1483         ret = i915_gem_freeze_late(i915);
1484         if (ret)
1485                 return ret;
1486
1487         return 0;
1488 }
1489
1490 /* thaw: called after creating the hibernation image, but before turning off. */
1491 static int i915_pm_thaw_early(struct device *kdev)
1492 {
1493         return i915_pm_resume_early(kdev);
1494 }
1495
1496 static int i915_pm_thaw(struct device *kdev)
1497 {
1498         return i915_pm_resume(kdev);
1499 }
1500
1501 /* restore: called after loading the hibernation image. */
1502 static int i915_pm_restore_early(struct device *kdev)
1503 {
1504         return i915_pm_resume_early(kdev);
1505 }
1506
1507 static int i915_pm_restore(struct device *kdev)
1508 {
1509         return i915_pm_resume(kdev);
1510 }
1511
1512 static int intel_runtime_suspend(struct device *kdev)
1513 {
1514         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1515         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1516         int ret;
1517
1518         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1519                 return -ENODEV;
1520
1521         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1522
1523         disable_rpm_wakeref_asserts(rpm);
1524
1525         /*
1526          * We are safe here against re-faults, since the fault handler takes
1527          * an RPM reference.
1528          */
1529         i915_gem_runtime_suspend(dev_priv);
1530
1531         intel_gt_runtime_suspend(&dev_priv->gt);
1532
1533         intel_runtime_pm_disable_interrupts(dev_priv);
1534
1535         intel_uncore_suspend(&dev_priv->uncore);
1536
1537         intel_display_power_suspend(dev_priv);
1538
1539         ret = vlv_suspend_complete(dev_priv);
1540         if (ret) {
1541                 drm_err(&dev_priv->drm,
1542                         "Runtime suspend failed, disabling it (%d)\n", ret);
1543                 intel_uncore_runtime_resume(&dev_priv->uncore);
1544
1545                 intel_runtime_pm_enable_interrupts(dev_priv);
1546
1547                 intel_gt_runtime_resume(&dev_priv->gt);
1548
1549                 enable_rpm_wakeref_asserts(rpm);
1550
1551                 return ret;
1552         }
1553
1554         enable_rpm_wakeref_asserts(rpm);
1555         intel_runtime_pm_driver_release(rpm);
1556
1557         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1558                 drm_err(&dev_priv->drm,
1559                         "Unclaimed access detected prior to suspending\n");
1560
1561         rpm->suspended = true;
1562
1563         /*
1564          * FIXME: We really should find a document that references the arguments
1565          * used below!
1566          */
1567         if (IS_BROADWELL(dev_priv)) {
1568                 /*
1569                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1570                  * being detected, and the call we do at intel_runtime_resume()
1571                  * won't be able to restore them. Since PCI_D3hot matches the
1572                  * actual specification and appears to be working, use it.
1573                  */
1574                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1575         } else {
1576                 /*
1577                  * current versions of firmware which depend on this opregion
1578                  * notification have repurposed the D1 definition to mean
1579                  * "runtime suspended" vs. what you would normally expect (D3)
1580                  * to distinguish it from notifications that might be sent via
1581                  * the suspend path.
1582                  */
1583                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1584         }
1585
1586         assert_forcewakes_inactive(&dev_priv->uncore);
1587
1588         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1589                 intel_hpd_poll_enable(dev_priv);
1590
1591         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1592         return 0;
1593 }
1594
1595 static int intel_runtime_resume(struct device *kdev)
1596 {
1597         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1598         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1599         int ret;
1600
1601         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1602                 return -ENODEV;
1603
1604         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1605
1606         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1607         disable_rpm_wakeref_asserts(rpm);
1608
1609         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1610         rpm->suspended = false;
1611         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1612                 drm_dbg(&dev_priv->drm,
1613                         "Unclaimed access during suspend, bios?\n");
1614
1615         intel_display_power_resume(dev_priv);
1616
1617         ret = vlv_resume_prepare(dev_priv, true);
1618
1619         intel_uncore_runtime_resume(&dev_priv->uncore);
1620
1621         intel_runtime_pm_enable_interrupts(dev_priv);
1622
1623         /*
1624          * No point of rolling back things in case of an error, as the best
1625          * we can do is to hope that things will still work (and disable RPM).
1626          */
1627         intel_gt_runtime_resume(&dev_priv->gt);
1628
1629         /*
1630          * On VLV/CHV display interrupts are part of the display
1631          * power well, so hpd is reinitialized from there. For
1632          * everyone else do it here.
1633          */
1634         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1635                 intel_hpd_init(dev_priv);
1636                 intel_hpd_poll_disable(dev_priv);
1637         }
1638
1639         intel_enable_ipc(dev_priv);
1640
1641         enable_rpm_wakeref_asserts(rpm);
1642
1643         if (ret)
1644                 drm_err(&dev_priv->drm,
1645                         "Runtime resume failed, disabling it (%d)\n", ret);
1646         else
1647                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1648
1649         return ret;
1650 }
1651
1652 const struct dev_pm_ops i915_pm_ops = {
1653         /*
1654          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1655          * PMSG_RESUME]
1656          */
1657         .prepare = i915_pm_prepare,
1658         .suspend = i915_pm_suspend,
1659         .suspend_late = i915_pm_suspend_late,
1660         .resume_early = i915_pm_resume_early,
1661         .resume = i915_pm_resume,
1662
1663         /*
1664          * S4 event handlers
1665          * @freeze, @freeze_late    : called (1) before creating the
1666          *                            hibernation image [PMSG_FREEZE] and
1667          *                            (2) after rebooting, before restoring
1668          *                            the image [PMSG_QUIESCE]
1669          * @thaw, @thaw_early       : called (1) after creating the hibernation
1670          *                            image, before writing it [PMSG_THAW]
1671          *                            and (2) after failing to create or
1672          *                            restore the image [PMSG_RECOVER]
1673          * @poweroff, @poweroff_late: called after writing the hibernation
1674          *                            image, before rebooting [PMSG_HIBERNATE]
1675          * @restore, @restore_early : called after rebooting and restoring the
1676          *                            hibernation image [PMSG_RESTORE]
1677          */
1678         .freeze = i915_pm_freeze,
1679         .freeze_late = i915_pm_freeze_late,
1680         .thaw_early = i915_pm_thaw_early,
1681         .thaw = i915_pm_thaw,
1682         .poweroff = i915_pm_suspend,
1683         .poweroff_late = i915_pm_poweroff_late,
1684         .restore_early = i915_pm_restore_early,
1685         .restore = i915_pm_restore,
1686
1687         /* S0ix (via runtime suspend) event handlers */
1688         .runtime_suspend = intel_runtime_suspend,
1689         .runtime_resume = intel_runtime_resume,
1690 };
1691
1692 static const struct file_operations i915_driver_fops = {
1693         .owner = THIS_MODULE,
1694         .open = drm_open,
1695         .release = drm_release_noglobal,
1696         .unlocked_ioctl = drm_ioctl,
1697         .mmap = i915_gem_mmap,
1698         .poll = drm_poll,
1699         .read = drm_read,
1700         .compat_ioctl = i915_ioc32_compat_ioctl,
1701         .llseek = noop_llseek,
1702 };
1703
1704 static int
1705 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1706                           struct drm_file *file)
1707 {
1708         return -ENODEV;
1709 }
1710
1711 static const struct drm_ioctl_desc i915_ioctls[] = {
1712         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1713         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1714         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1715         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1716         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1717         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1718         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1719         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1720         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1721         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1722         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1723         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1724         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1725         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1726         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1727         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1728         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1729         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1730         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
1731         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1732         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1733         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1734         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1735         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1736         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1738         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1739         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1740         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1741         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1742         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1743         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1744         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1745         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1746         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1747         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1748         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1749         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1750         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1751         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1752         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1753         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1754         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1755         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1756         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1757         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1758         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1759         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1760         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1761         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1762         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1763         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1764         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1765         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1766         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1767         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1768         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1769         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1770 };
1771
1772 static const struct drm_driver driver = {
1773         /* Don't use MTRRs here; the Xserver or userspace app should
1774          * deal with them for Intel hardware.
1775          */
1776         .driver_features =
1777             DRIVER_GEM |
1778             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1779             DRIVER_SYNCOBJ_TIMELINE,
1780         .release = i915_driver_release,
1781         .open = i915_driver_open,
1782         .lastclose = i915_driver_lastclose,
1783         .postclose = i915_driver_postclose,
1784
1785         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1786         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1787         .gem_prime_import = i915_gem_prime_import,
1788
1789         .dumb_create = i915_gem_dumb_create,
1790         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1791
1792         .ioctls = i915_ioctls,
1793         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1794         .fops = &i915_driver_fops,
1795         .name = DRIVER_NAME,
1796         .desc = DRIVER_DESC,
1797         .date = DRIVER_DATE,
1798         .major = DRIVER_MAJOR,
1799         .minor = DRIVER_MINOR,
1800         .patchlevel = DRIVER_PATCHLEVEL,
1801 };