1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
52 #include "i915_query.h"
53 #include "i915_vgpu.h"
54 #include "intel_drv.h"
57 static struct drm_driver driver;
59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
60 static unsigned int i915_load_fail_count;
62 bool __i915_inject_load_failure(const char *func, int line)
64 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
67 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
68 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
69 i915_modparams.inject_load_failure, func, line);
77 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
78 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
79 "providing the dmesg log by booting with drm.debug=0xf"
82 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
85 static bool shown_bug_once;
86 struct device *kdev = dev_priv->drm.dev;
87 bool is_error = level[1] <= KERN_ERR[1];
88 bool is_debug = level[1] == KERN_DEBUG[1];
92 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
100 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
101 __builtin_return_address(0), &vaf);
103 if (is_error && !shown_bug_once) {
104 dev_notice(kdev, "%s", FDO_BUG_MSG);
105 shown_bug_once = true;
111 static bool i915_error_injected(struct drm_i915_private *dev_priv)
113 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
114 return i915_modparams.inject_load_failure &&
115 i915_load_fail_count == i915_modparams.inject_load_failure;
121 #define i915_load_error(dev_priv, fmt, ...) \
122 __i915_printk(dev_priv, \
123 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
126 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
127 static enum intel_pch
128 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
131 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
132 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
133 WARN_ON(!IS_GEN5(dev_priv));
135 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
136 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
137 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
139 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
140 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
141 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
142 /* PantherPoint is CPT compatible */
144 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
145 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
146 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
147 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
149 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
150 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
151 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
152 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
154 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
155 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
156 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
157 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
158 /* WildcatPoint is LPT compatible */
160 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
161 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
162 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
163 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
164 /* WildcatPoint is LPT compatible */
166 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
167 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
168 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
170 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
171 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
172 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
174 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
175 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
176 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
177 !IS_COFFEELAKE(dev_priv));
179 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
180 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
181 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
183 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
184 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
185 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
187 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
188 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
189 WARN_ON(!IS_ICELAKE(dev_priv));
196 static bool intel_is_virt_pch(unsigned short id,
197 unsigned short svendor, unsigned short sdevice)
199 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
200 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
201 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
202 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
203 sdevice == PCI_SUBDEVICE_ID_QEMU));
206 static unsigned short
207 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
209 unsigned short id = 0;
212 * In a virtualized passthrough environment we can be in a
213 * setup where the ISA bridge is not able to be passed through.
214 * In this case, a south bridge can be emulated and we have to
215 * make an educated guess as to which PCH is really there.
218 if (IS_GEN5(dev_priv))
219 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
220 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
221 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
222 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
223 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
224 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
225 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
226 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
227 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
228 else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
229 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
232 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
234 DRM_DEBUG_KMS("Assuming no PCH\n");
239 static void intel_detect_pch(struct drm_i915_private *dev_priv)
241 struct pci_dev *pch = NULL;
243 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
244 * (which really amounts to a PCH but no South Display).
246 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
247 dev_priv->pch_type = PCH_NOP;
252 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
253 * make graphics device passthrough work easy for VMM, that only
254 * need to expose ISA bridge to let driver know the real hardware
255 * underneath. This is a requirement from virtualization team.
257 * In some virtualized environments (e.g. XEN), there is irrelevant
258 * ISA bridge in the system. To work reliably, we should scan trhough
259 * all the ISA bridge devices and check for the first match, instead
260 * of only checking the first one.
262 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
264 enum intel_pch pch_type;
266 if (pch->vendor != PCI_VENDOR_ID_INTEL)
269 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
271 pch_type = intel_pch_type(dev_priv, id);
272 if (pch_type != PCH_NONE) {
273 dev_priv->pch_type = pch_type;
274 dev_priv->pch_id = id;
276 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
277 pch->subsystem_device)) {
278 id = intel_virt_detect_pch(dev_priv);
280 pch_type = intel_pch_type(dev_priv, id);
281 if (WARN_ON(pch_type == PCH_NONE))
286 dev_priv->pch_type = pch_type;
287 dev_priv->pch_id = id;
292 DRM_DEBUG_KMS("No PCH found.\n");
297 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
298 struct drm_file *file_priv)
300 struct drm_i915_private *dev_priv = to_i915(dev);
301 struct pci_dev *pdev = dev_priv->drm.pdev;
302 drm_i915_getparam_t *param = data;
305 switch (param->param) {
306 case I915_PARAM_IRQ_ACTIVE:
307 case I915_PARAM_ALLOW_BATCHBUFFER:
308 case I915_PARAM_LAST_DISPATCH:
309 case I915_PARAM_HAS_EXEC_CONSTANTS:
310 /* Reject all old ums/dri params. */
312 case I915_PARAM_CHIPSET_ID:
313 value = pdev->device;
315 case I915_PARAM_REVISION:
316 value = pdev->revision;
318 case I915_PARAM_NUM_FENCES_AVAIL:
319 value = dev_priv->num_fence_regs;
321 case I915_PARAM_HAS_OVERLAY:
322 value = dev_priv->overlay ? 1 : 0;
324 case I915_PARAM_HAS_BSD:
325 value = !!dev_priv->engine[VCS];
327 case I915_PARAM_HAS_BLT:
328 value = !!dev_priv->engine[BCS];
330 case I915_PARAM_HAS_VEBOX:
331 value = !!dev_priv->engine[VECS];
333 case I915_PARAM_HAS_BSD2:
334 value = !!dev_priv->engine[VCS2];
336 case I915_PARAM_HAS_LLC:
337 value = HAS_LLC(dev_priv);
339 case I915_PARAM_HAS_WT:
340 value = HAS_WT(dev_priv);
342 case I915_PARAM_HAS_ALIASING_PPGTT:
343 value = USES_PPGTT(dev_priv);
345 case I915_PARAM_HAS_SEMAPHORES:
346 value = HAS_LEGACY_SEMAPHORES(dev_priv);
348 case I915_PARAM_HAS_SECURE_BATCHES:
349 value = capable(CAP_SYS_ADMIN);
351 case I915_PARAM_CMD_PARSER_VERSION:
352 value = i915_cmd_parser_get_version(dev_priv);
354 case I915_PARAM_SUBSLICE_TOTAL:
355 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
359 case I915_PARAM_EU_TOTAL:
360 value = INTEL_INFO(dev_priv)->sseu.eu_total;
364 case I915_PARAM_HAS_GPU_RESET:
365 value = i915_modparams.enable_hangcheck &&
366 intel_has_gpu_reset(dev_priv);
367 if (value && intel_has_reset_engine(dev_priv))
370 case I915_PARAM_HAS_RESOURCE_STREAMER:
371 value = HAS_RESOURCE_STREAMER(dev_priv);
373 case I915_PARAM_HAS_POOLED_EU:
374 value = HAS_POOLED_EU(dev_priv);
376 case I915_PARAM_MIN_EU_IN_POOL:
377 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
379 case I915_PARAM_HUC_STATUS:
380 intel_runtime_pm_get(dev_priv);
381 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
382 intel_runtime_pm_put(dev_priv);
384 case I915_PARAM_MMAP_GTT_VERSION:
385 /* Though we've started our numbering from 1, and so class all
386 * earlier versions as 0, in effect their value is undefined as
387 * the ioctl will report EINVAL for the unknown param!
389 value = i915_gem_mmap_gtt_version();
391 case I915_PARAM_HAS_SCHEDULER:
392 value = dev_priv->caps.scheduler;
395 case I915_PARAM_MMAP_VERSION:
396 /* Remember to bump this if the version changes! */
397 case I915_PARAM_HAS_GEM:
398 case I915_PARAM_HAS_PAGEFLIPPING:
399 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
400 case I915_PARAM_HAS_RELAXED_FENCING:
401 case I915_PARAM_HAS_COHERENT_RINGS:
402 case I915_PARAM_HAS_RELAXED_DELTA:
403 case I915_PARAM_HAS_GEN7_SOL_RESET:
404 case I915_PARAM_HAS_WAIT_TIMEOUT:
405 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
406 case I915_PARAM_HAS_PINNED_BATCHES:
407 case I915_PARAM_HAS_EXEC_NO_RELOC:
408 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
409 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
410 case I915_PARAM_HAS_EXEC_SOFTPIN:
411 case I915_PARAM_HAS_EXEC_ASYNC:
412 case I915_PARAM_HAS_EXEC_FENCE:
413 case I915_PARAM_HAS_EXEC_CAPTURE:
414 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
415 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
416 /* For the time being all of these are always true;
417 * if some supported hardware does not have one of these
418 * features this value needs to be provided from
419 * INTEL_INFO(), a feature macro, or similar.
423 case I915_PARAM_HAS_CONTEXT_ISOLATION:
424 value = intel_engines_has_context_isolation(dev_priv);
426 case I915_PARAM_SLICE_MASK:
427 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
431 case I915_PARAM_SUBSLICE_MASK:
432 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
436 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
437 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
440 DRM_DEBUG("Unknown parameter %d\n", param->param);
444 if (put_user(value, param->value))
450 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
452 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
453 if (!dev_priv->bridge_dev) {
454 DRM_ERROR("bridge device not found\n");
460 /* Allocate space for the MCH regs if needed, return nonzero on error */
462 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
464 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
465 u32 temp_lo, temp_hi = 0;
469 if (INTEL_GEN(dev_priv) >= 4)
470 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
471 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
472 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
474 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
477 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
481 /* Get some space for it */
482 dev_priv->mch_res.name = "i915 MCHBAR";
483 dev_priv->mch_res.flags = IORESOURCE_MEM;
484 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
486 MCHBAR_SIZE, MCHBAR_SIZE,
488 0, pcibios_align_resource,
489 dev_priv->bridge_dev);
491 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
492 dev_priv->mch_res.start = 0;
496 if (INTEL_GEN(dev_priv) >= 4)
497 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
498 upper_32_bits(dev_priv->mch_res.start));
500 pci_write_config_dword(dev_priv->bridge_dev, reg,
501 lower_32_bits(dev_priv->mch_res.start));
505 /* Setup MCHBAR if possible, return true if we should disable it again */
507 intel_setup_mchbar(struct drm_i915_private *dev_priv)
509 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
513 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
516 dev_priv->mchbar_need_disable = false;
518 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
519 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
520 enabled = !!(temp & DEVEN_MCHBAR_EN);
522 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
526 /* If it's already enabled, don't have to do anything */
530 if (intel_alloc_mchbar_resource(dev_priv))
533 dev_priv->mchbar_need_disable = true;
535 /* Space is allocated or reserved, so enable it. */
536 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
537 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
538 temp | DEVEN_MCHBAR_EN);
540 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
541 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
546 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
548 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
550 if (dev_priv->mchbar_need_disable) {
551 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
554 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
556 deven_val &= ~DEVEN_MCHBAR_EN;
557 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
562 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
565 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
570 if (dev_priv->mch_res.start)
571 release_resource(&dev_priv->mch_res);
574 /* true = enable decode, false = disable decoder */
575 static unsigned int i915_vga_set_decode(void *cookie, bool state)
577 struct drm_i915_private *dev_priv = cookie;
579 intel_modeset_vga_set_state(dev_priv, state);
581 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
582 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
584 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
587 static int i915_resume_switcheroo(struct drm_device *dev);
588 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
590 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
592 struct drm_device *dev = pci_get_drvdata(pdev);
593 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
595 if (state == VGA_SWITCHEROO_ON) {
596 pr_info("switched on\n");
597 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
598 /* i915 resume handler doesn't set to D0 */
599 pci_set_power_state(pdev, PCI_D0);
600 i915_resume_switcheroo(dev);
601 dev->switch_power_state = DRM_SWITCH_POWER_ON;
603 pr_info("switched off\n");
604 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
605 i915_suspend_switcheroo(dev, pmm);
606 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
610 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
612 struct drm_device *dev = pci_get_drvdata(pdev);
615 * FIXME: open_count is protected by drm_global_mutex but that would lead to
616 * locking inversion with the driver load path. And the access here is
617 * completely racy anyway. So don't bother with locking for now.
619 return dev->open_count == 0;
622 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
623 .set_gpu_state = i915_switcheroo_set_state,
625 .can_switch = i915_switcheroo_can_switch,
628 static void i915_gem_fini(struct drm_i915_private *dev_priv)
630 /* Flush any outstanding unpin_work. */
631 i915_gem_drain_workqueue(dev_priv);
633 mutex_lock(&dev_priv->drm.struct_mutex);
634 intel_uc_fini_hw(dev_priv);
635 intel_uc_fini(dev_priv);
636 i915_gem_cleanup_engines(dev_priv);
637 i915_gem_contexts_fini(dev_priv);
638 mutex_unlock(&dev_priv->drm.struct_mutex);
640 intel_uc_fini_misc(dev_priv);
641 i915_gem_cleanup_userptr(dev_priv);
643 i915_gem_drain_freed_objects(dev_priv);
645 WARN_ON(!list_empty(&dev_priv->contexts.list));
648 static int i915_load_modeset_init(struct drm_device *dev)
650 struct drm_i915_private *dev_priv = to_i915(dev);
651 struct pci_dev *pdev = dev_priv->drm.pdev;
654 if (i915_inject_load_failure())
657 intel_bios_init(dev_priv);
659 /* If we have > 1 VGA cards, then we need to arbitrate access
660 * to the common VGA resources.
662 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
663 * then we do not take part in VGA arbitration and the
664 * vga_client_register() fails with -ENODEV.
666 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
667 if (ret && ret != -ENODEV)
670 intel_register_dsm_handler();
672 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
674 goto cleanup_vga_client;
676 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
677 intel_update_rawclk(dev_priv);
679 intel_power_domains_init_hw(dev_priv, false);
681 intel_csr_ucode_init(dev_priv);
683 ret = intel_irq_install(dev_priv);
687 intel_setup_gmbus(dev_priv);
689 /* Important: The output setup functions called by modeset_init need
690 * working irqs for e.g. gmbus and dp aux transfers. */
691 ret = intel_modeset_init(dev);
695 intel_uc_init_fw(dev_priv);
697 ret = i915_gem_init(dev_priv);
701 intel_setup_overlay(dev_priv);
703 if (INTEL_INFO(dev_priv)->num_pipes == 0)
706 ret = intel_fbdev_init(dev);
710 /* Only enable hotplug handling once the fbdev is fully set up. */
711 intel_hpd_init(dev_priv);
716 if (i915_gem_suspend(dev_priv))
717 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
718 i915_gem_fini(dev_priv);
720 intel_uc_fini_fw(dev_priv);
722 drm_irq_uninstall(dev);
723 intel_teardown_gmbus(dev_priv);
725 intel_csr_ucode_fini(dev_priv);
726 intel_power_domains_fini(dev_priv);
727 vga_switcheroo_unregister_client(pdev);
729 vga_client_register(pdev, NULL, NULL, NULL);
734 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
736 struct apertures_struct *ap;
737 struct pci_dev *pdev = dev_priv->drm.pdev;
738 struct i915_ggtt *ggtt = &dev_priv->ggtt;
742 ap = alloc_apertures(1);
746 ap->ranges[0].base = ggtt->gmadr.start;
747 ap->ranges[0].size = ggtt->mappable_end;
750 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
752 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
759 #if !defined(CONFIG_VGA_CONSOLE)
760 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
764 #elif !defined(CONFIG_DUMMY_CONSOLE)
765 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
770 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
774 DRM_INFO("Replacing VGA console driver\n");
777 if (con_is_bound(&vga_con))
778 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
780 ret = do_unregister_con_driver(&vga_con);
782 /* Ignore "already unregistered". */
792 static void intel_init_dpio(struct drm_i915_private *dev_priv)
795 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
796 * CHV x1 PHY (DP/HDMI D)
797 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
799 if (IS_CHERRYVIEW(dev_priv)) {
800 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
801 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
802 } else if (IS_VALLEYVIEW(dev_priv)) {
803 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
807 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
810 * The i915 workqueue is primarily used for batched retirement of
811 * requests (and thus managing bo) once the task has been completed
812 * by the GPU. i915_retire_requests() is called directly when we
813 * need high-priority retirement, such as waiting for an explicit
816 * It is also used for periodic low-priority events, such as
817 * idle-timers and recording error state.
819 * All tasks on the workqueue are expected to acquire the dev mutex
820 * so there is no point in running more than one instance of the
821 * workqueue at any time. Use an ordered one.
823 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
824 if (dev_priv->wq == NULL)
827 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
828 if (dev_priv->hotplug.dp_wq == NULL)
834 destroy_workqueue(dev_priv->wq);
836 DRM_ERROR("Failed to allocate workqueues.\n");
841 static void i915_engines_cleanup(struct drm_i915_private *i915)
843 struct intel_engine_cs *engine;
844 enum intel_engine_id id;
846 for_each_engine(engine, i915, id)
850 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
852 destroy_workqueue(dev_priv->hotplug.dp_wq);
853 destroy_workqueue(dev_priv->wq);
857 * We don't keep the workarounds for pre-production hardware, so we expect our
858 * driver to fail on these machines in one way or another. A little warning on
859 * dmesg may help both the user and the bug triagers.
861 * Our policy for removing pre-production workarounds is to keep the
862 * current gen workarounds as a guide to the bring-up of the next gen
863 * (workarounds have a habit of persisting!). Anything older than that
864 * should be removed along with the complications they introduce.
866 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
870 pre |= IS_HSW_EARLY_SDV(dev_priv);
871 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
872 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
875 DRM_ERROR("This is a pre-production stepping. "
876 "It may not be fully functional.\n");
877 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
882 * i915_driver_init_early - setup state not requiring device access
883 * @dev_priv: device private
884 * @ent: the matching pci_device_id
886 * Initialize everything that is a "SW-only" state, that is state not
887 * requiring accessing the device or exposing the driver via kernel internal
888 * or userspace interfaces. Example steps belonging here: lock initialization,
889 * system memory allocation, setting up device specific attributes and
890 * function hooks not requiring accessing the device.
892 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
893 const struct pci_device_id *ent)
895 const struct intel_device_info *match_info =
896 (struct intel_device_info *)ent->driver_data;
897 struct intel_device_info *device_info;
900 if (i915_inject_load_failure())
903 /* Setup the write-once "constant" device info */
904 device_info = mkwrite_device_info(dev_priv);
905 memcpy(device_info, match_info, sizeof(*device_info));
906 device_info->device_id = dev_priv->drm.pdev->device;
908 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
909 sizeof(device_info->platform_mask) * BITS_PER_BYTE);
910 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
911 spin_lock_init(&dev_priv->irq_lock);
912 spin_lock_init(&dev_priv->gpu_error.lock);
913 mutex_init(&dev_priv->backlight_lock);
914 spin_lock_init(&dev_priv->uncore.lock);
916 mutex_init(&dev_priv->sb_lock);
917 mutex_init(&dev_priv->modeset_restore_lock);
918 mutex_init(&dev_priv->av_mutex);
919 mutex_init(&dev_priv->wm.wm_mutex);
920 mutex_init(&dev_priv->pps_mutex);
922 intel_wopcm_init_early(&dev_priv->wopcm);
923 intel_uc_init_early(dev_priv);
924 i915_memcpy_init_early(dev_priv);
926 ret = i915_workqueues_init(dev_priv);
930 /* This must be called before any calls to HAS_PCH_* */
931 intel_detect_pch(dev_priv);
933 intel_pm_setup(dev_priv);
934 intel_init_dpio(dev_priv);
935 intel_power_domains_init(dev_priv);
936 intel_irq_init(dev_priv);
937 intel_hangcheck_init(dev_priv);
938 intel_init_display_hooks(dev_priv);
939 intel_init_clock_gating_hooks(dev_priv);
940 intel_init_audio_hooks(dev_priv);
941 ret = i915_gem_load_init(dev_priv);
945 intel_display_crc_init(dev_priv);
947 intel_detect_preproduction_hw(dev_priv);
952 intel_irq_fini(dev_priv);
953 i915_workqueues_cleanup(dev_priv);
955 i915_engines_cleanup(dev_priv);
960 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
961 * @dev_priv: device private
963 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
965 i915_gem_load_cleanup(dev_priv);
966 intel_irq_fini(dev_priv);
967 i915_workqueues_cleanup(dev_priv);
968 i915_engines_cleanup(dev_priv);
971 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
973 struct pci_dev *pdev = dev_priv->drm.pdev;
977 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
979 * Before gen4, the registers and the GTT are behind different BARs.
980 * However, from gen4 onwards, the registers and the GTT are shared
981 * in the same BAR, so we want to restrict this ioremap from
982 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
983 * the register BAR remains the same size for all the earlier
984 * generations up to Ironlake.
986 if (INTEL_GEN(dev_priv) < 5)
987 mmio_size = 512 * 1024;
989 mmio_size = 2 * 1024 * 1024;
990 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
991 if (dev_priv->regs == NULL) {
992 DRM_ERROR("failed to map registers\n");
997 /* Try to make sure MCHBAR is enabled before poking at it */
998 intel_setup_mchbar(dev_priv);
1003 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
1005 struct pci_dev *pdev = dev_priv->drm.pdev;
1007 intel_teardown_mchbar(dev_priv);
1008 pci_iounmap(pdev, dev_priv->regs);
1012 * i915_driver_init_mmio - setup device MMIO
1013 * @dev_priv: device private
1015 * Setup minimal device state necessary for MMIO accesses later in the
1016 * initialization sequence. The setup here should avoid any other device-wide
1017 * side effects or exposing the driver via kernel internal or user space
1020 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1024 if (i915_inject_load_failure())
1027 if (i915_get_bridge_dev(dev_priv))
1030 ret = i915_mmio_setup(dev_priv);
1034 intel_uncore_init(dev_priv);
1036 intel_uc_init_mmio(dev_priv);
1038 ret = intel_engines_init_mmio(dev_priv);
1042 i915_gem_init_mmio(dev_priv);
1047 intel_uncore_fini(dev_priv);
1049 pci_dev_put(dev_priv->bridge_dev);
1055 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1056 * @dev_priv: device private
1058 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1060 intel_uncore_fini(dev_priv);
1061 i915_mmio_cleanup(dev_priv);
1062 pci_dev_put(dev_priv->bridge_dev);
1065 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1068 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1069 * user's requested state against the hardware/driver capabilities. We
1070 * do this now so that we can print out any log messages once rather
1071 * than every time we check intel_enable_ppgtt().
1073 i915_modparams.enable_ppgtt =
1074 intel_sanitize_enable_ppgtt(dev_priv,
1075 i915_modparams.enable_ppgtt);
1076 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1078 intel_gvt_sanitize_options(dev_priv);
1082 * i915_driver_init_hw - setup state requiring device access
1083 * @dev_priv: device private
1085 * Setup state that requires accessing the device, but doesn't require
1086 * exposing the driver via kernel internal or userspace interfaces.
1088 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1090 struct pci_dev *pdev = dev_priv->drm.pdev;
1093 if (i915_inject_load_failure())
1096 intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1098 intel_sanitize_options(dev_priv);
1100 i915_perf_init(dev_priv);
1102 ret = i915_ggtt_probe_hw(dev_priv);
1106 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1107 * otherwise the vga fbdev driver falls over. */
1108 ret = i915_kick_out_firmware_fb(dev_priv);
1110 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1114 ret = i915_kick_out_vgacon(dev_priv);
1116 DRM_ERROR("failed to remove conflicting VGA console\n");
1120 ret = i915_ggtt_init_hw(dev_priv);
1124 ret = i915_ggtt_enable_hw(dev_priv);
1126 DRM_ERROR("failed to enable GGTT\n");
1130 pci_set_master(pdev);
1132 /* overlay on gen2 is broken and can't address above 1G */
1133 if (IS_GEN2(dev_priv)) {
1134 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1136 DRM_ERROR("failed to set DMA mask\n");
1142 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1143 * using 32bit addressing, overwriting memory if HWS is located
1146 * The documentation also mentions an issue with undefined
1147 * behaviour if any general state is accessed within a page above 4GB,
1148 * which also needs to be handled carefully.
1150 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1151 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1154 DRM_ERROR("failed to set DMA mask\n");
1160 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1161 PM_QOS_DEFAULT_VALUE);
1163 intel_uncore_sanitize(dev_priv);
1165 intel_opregion_setup(dev_priv);
1167 i915_gem_load_init_fences(dev_priv);
1169 /* On the 945G/GM, the chipset reports the MSI capability on the
1170 * integrated graphics even though the support isn't actually there
1171 * according to the published specs. It doesn't appear to function
1172 * correctly in testing on 945G.
1173 * This may be a side effect of MSI having been made available for PEG
1174 * and the registers being closely associated.
1176 * According to chipset errata, on the 965GM, MSI interrupts may
1177 * be lost or delayed, and was defeatured. MSI interrupts seem to
1178 * get lost on g4x as well, and interrupt delivery seems to stay
1179 * properly dead afterwards. So we'll just disable them for all
1180 * pre-gen5 chipsets.
1182 if (INTEL_GEN(dev_priv) >= 5) {
1183 if (pci_enable_msi(pdev) < 0)
1184 DRM_DEBUG_DRIVER("can't enable MSI");
1187 ret = intel_gvt_init(dev_priv);
1194 i915_ggtt_cleanup_hw(dev_priv);
1200 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1201 * @dev_priv: device private
1203 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1205 struct pci_dev *pdev = dev_priv->drm.pdev;
1207 i915_perf_fini(dev_priv);
1209 if (pdev->msi_enabled)
1210 pci_disable_msi(pdev);
1212 pm_qos_remove_request(&dev_priv->pm_qos);
1213 i915_ggtt_cleanup_hw(dev_priv);
1217 * i915_driver_register - register the driver with the rest of the system
1218 * @dev_priv: device private
1220 * Perform any steps necessary to make the driver available via kernel
1221 * internal or userspace interfaces.
1223 static void i915_driver_register(struct drm_i915_private *dev_priv)
1225 struct drm_device *dev = &dev_priv->drm;
1227 i915_gem_shrinker_register(dev_priv);
1228 i915_pmu_register(dev_priv);
1231 * Notify a valid surface after modesetting,
1232 * when running inside a VM.
1234 if (intel_vgpu_active(dev_priv))
1235 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1237 /* Reveal our presence to userspace */
1238 if (drm_dev_register(dev, 0) == 0) {
1239 i915_debugfs_register(dev_priv);
1240 i915_setup_sysfs(dev_priv);
1242 /* Depends on debugfs having been initialized */
1243 intel_uc_register(dev_priv);
1245 /* Depends on sysfs having been initialized */
1246 i915_perf_register(dev_priv);
1248 DRM_ERROR("Failed to register driver for userspace access!\n");
1250 if (INTEL_INFO(dev_priv)->num_pipes) {
1251 /* Must be done after probing outputs */
1252 intel_opregion_register(dev_priv);
1253 acpi_video_register();
1256 if (IS_GEN5(dev_priv))
1257 intel_gpu_ips_init(dev_priv);
1259 intel_audio_init(dev_priv);
1262 * Some ports require correctly set-up hpd registers for detection to
1263 * work properly (leading to ghost connected connector status), e.g. VGA
1264 * on gm45. Hence we can only set up the initial fbdev config after hpd
1265 * irqs are fully enabled. We do it last so that the async config
1266 * cannot run before the connectors are registered.
1268 intel_fbdev_initial_config_async(dev);
1271 * We need to coordinate the hotplugs with the asynchronous fbdev
1272 * configuration, for which we use the fbdev->async_cookie.
1274 if (INTEL_INFO(dev_priv)->num_pipes)
1275 drm_kms_helper_poll_init(dev);
1279 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1280 * @dev_priv: device private
1282 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1284 intel_fbdev_unregister(dev_priv);
1285 intel_audio_deinit(dev_priv);
1288 * After flushing the fbdev (incl. a late async config which will
1289 * have delayed queuing of a hotplug event), then flush the hotplug
1292 drm_kms_helper_poll_fini(&dev_priv->drm);
1294 intel_gpu_ips_teardown();
1295 acpi_video_unregister();
1296 intel_opregion_unregister(dev_priv);
1298 i915_perf_unregister(dev_priv);
1299 i915_pmu_unregister(dev_priv);
1301 i915_teardown_sysfs(dev_priv);
1302 intel_uc_unregister(dev_priv);
1303 drm_dev_unregister(&dev_priv->drm);
1305 i915_gem_shrinker_unregister(dev_priv);
1308 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1310 if (drm_debug & DRM_UT_DRIVER) {
1311 struct drm_printer p = drm_debug_printer("i915 device info:");
1313 intel_device_info_dump(&dev_priv->info, &p);
1314 intel_device_info_dump_runtime(&dev_priv->info, &p);
1317 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1318 DRM_INFO("DRM_I915_DEBUG enabled\n");
1319 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1320 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1324 * i915_driver_load - setup chip and create an initial config
1326 * @ent: matching PCI ID entry
1328 * The driver load routine has to do several things:
1329 * - drive output discovery via intel_modeset_init()
1330 * - initialize the memory manager
1331 * - allocate initial config memory
1332 * - setup the DRM framebuffer with the allocated memory
1334 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1336 const struct intel_device_info *match_info =
1337 (struct intel_device_info *)ent->driver_data;
1338 struct drm_i915_private *dev_priv;
1341 /* Enable nuclear pageflip on ILK+ */
1342 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1343 driver.driver_features &= ~DRIVER_ATOMIC;
1346 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1348 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1350 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1354 dev_priv->drm.pdev = pdev;
1355 dev_priv->drm.dev_private = dev_priv;
1357 ret = pci_enable_device(pdev);
1361 pci_set_drvdata(pdev, &dev_priv->drm);
1363 * Disable the system suspend direct complete optimization, which can
1364 * leave the device suspended skipping the driver's suspend handlers
1365 * if the device was already runtime suspended. This is needed due to
1366 * the difference in our runtime and system suspend sequence and
1367 * becaue the HDA driver may require us to enable the audio power
1368 * domain during system suspend.
1370 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1372 ret = i915_driver_init_early(dev_priv, ent);
1374 goto out_pci_disable;
1376 intel_runtime_pm_get(dev_priv);
1378 ret = i915_driver_init_mmio(dev_priv);
1380 goto out_runtime_pm_put;
1382 ret = i915_driver_init_hw(dev_priv);
1384 goto out_cleanup_mmio;
1387 * TODO: move the vblank init and parts of modeset init steps into one
1388 * of the i915_driver_init_/i915_driver_register functions according
1389 * to the role/effect of the given init step.
1391 if (INTEL_INFO(dev_priv)->num_pipes) {
1392 ret = drm_vblank_init(&dev_priv->drm,
1393 INTEL_INFO(dev_priv)->num_pipes);
1395 goto out_cleanup_hw;
1398 ret = i915_load_modeset_init(&dev_priv->drm);
1400 goto out_cleanup_hw;
1402 i915_driver_register(dev_priv);
1404 intel_runtime_pm_enable(dev_priv);
1406 intel_init_ipc(dev_priv);
1408 intel_runtime_pm_put(dev_priv);
1410 i915_welcome_messages(dev_priv);
1415 i915_driver_cleanup_hw(dev_priv);
1417 i915_driver_cleanup_mmio(dev_priv);
1419 intel_runtime_pm_put(dev_priv);
1420 i915_driver_cleanup_early(dev_priv);
1422 pci_disable_device(pdev);
1424 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1425 drm_dev_fini(&dev_priv->drm);
1431 void i915_driver_unload(struct drm_device *dev)
1433 struct drm_i915_private *dev_priv = to_i915(dev);
1434 struct pci_dev *pdev = dev_priv->drm.pdev;
1436 i915_driver_unregister(dev_priv);
1438 if (i915_gem_suspend(dev_priv))
1439 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1441 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1443 drm_atomic_helper_shutdown(dev);
1445 intel_gvt_cleanup(dev_priv);
1447 intel_modeset_cleanup(dev);
1449 intel_bios_cleanup(dev_priv);
1451 vga_switcheroo_unregister_client(pdev);
1452 vga_client_register(pdev, NULL, NULL, NULL);
1454 intel_csr_ucode_fini(dev_priv);
1456 /* Free error state after interrupts are fully disabled. */
1457 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1458 i915_reset_error_state(dev_priv);
1460 i915_gem_fini(dev_priv);
1461 intel_uc_fini_fw(dev_priv);
1462 intel_fbc_cleanup_cfb(dev_priv);
1464 intel_power_domains_fini(dev_priv);
1466 i915_driver_cleanup_hw(dev_priv);
1467 i915_driver_cleanup_mmio(dev_priv);
1469 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1472 static void i915_driver_release(struct drm_device *dev)
1474 struct drm_i915_private *dev_priv = to_i915(dev);
1476 i915_driver_cleanup_early(dev_priv);
1477 drm_dev_fini(&dev_priv->drm);
1482 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1484 struct drm_i915_private *i915 = to_i915(dev);
1487 ret = i915_gem_open(i915, file);
1495 * i915_driver_lastclose - clean up after all DRM clients have exited
1498 * Take care of cleaning up after all DRM clients have exited. In the
1499 * mode setting case, we want to restore the kernel's initial mode (just
1500 * in case the last client left us in a bad state).
1502 * Additionally, in the non-mode setting case, we'll tear down the GTT
1503 * and DMA structures, since the kernel won't be using them, and clea
1506 static void i915_driver_lastclose(struct drm_device *dev)
1508 intel_fbdev_restore_mode(dev);
1509 vga_switcheroo_process_delayed_switch();
1512 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1514 struct drm_i915_file_private *file_priv = file->driver_priv;
1516 mutex_lock(&dev->struct_mutex);
1517 i915_gem_context_close(file);
1518 i915_gem_release(dev, file);
1519 mutex_unlock(&dev->struct_mutex);
1524 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1526 struct drm_device *dev = &dev_priv->drm;
1527 struct intel_encoder *encoder;
1529 drm_modeset_lock_all(dev);
1530 for_each_intel_encoder(dev, encoder)
1531 if (encoder->suspend)
1532 encoder->suspend(encoder);
1533 drm_modeset_unlock_all(dev);
1536 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1538 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1540 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1542 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1543 if (acpi_target_system_state() < ACPI_STATE_S3)
1549 static int i915_drm_suspend(struct drm_device *dev)
1551 struct drm_i915_private *dev_priv = to_i915(dev);
1552 struct pci_dev *pdev = dev_priv->drm.pdev;
1553 pci_power_t opregion_target_state;
1556 /* ignore lid events during suspend */
1557 mutex_lock(&dev_priv->modeset_restore_lock);
1558 dev_priv->modeset_restore = MODESET_SUSPENDED;
1559 mutex_unlock(&dev_priv->modeset_restore_lock);
1561 disable_rpm_wakeref_asserts(dev_priv);
1563 /* We do a lot of poking in a lot of registers, make sure they work
1565 intel_display_set_init_power(dev_priv, true);
1567 drm_kms_helper_poll_disable(dev);
1569 pci_save_state(pdev);
1571 error = i915_gem_suspend(dev_priv);
1574 "GEM idle failed, resume might fail\n");
1578 intel_display_suspend(dev);
1580 intel_dp_mst_suspend(dev);
1582 intel_runtime_pm_disable_interrupts(dev_priv);
1583 intel_hpd_cancel_work(dev_priv);
1585 intel_suspend_encoders(dev_priv);
1587 intel_suspend_hw(dev_priv);
1589 i915_gem_suspend_gtt_mappings(dev_priv);
1591 i915_save_state(dev_priv);
1593 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1594 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1596 intel_uncore_suspend(dev_priv);
1597 intel_opregion_unregister(dev_priv);
1599 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1601 dev_priv->suspend_count++;
1603 intel_csr_ucode_suspend(dev_priv);
1606 enable_rpm_wakeref_asserts(dev_priv);
1611 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1613 struct drm_i915_private *dev_priv = to_i915(dev);
1614 struct pci_dev *pdev = dev_priv->drm.pdev;
1618 disable_rpm_wakeref_asserts(dev_priv);
1620 intel_display_set_init_power(dev_priv, false);
1622 fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
1623 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1625 * In case of firmware assisted context save/restore don't manually
1626 * deinit the power domains. This also means the CSR/DMC firmware will
1627 * stay active, it will power down any HW resources as required and
1628 * also enable deeper system power states that would be blocked if the
1629 * firmware was inactive.
1632 intel_power_domains_suspend(dev_priv);
1635 if (IS_GEN9_LP(dev_priv))
1636 bxt_enable_dc9(dev_priv);
1637 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1638 hsw_enable_pc8(dev_priv);
1639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1640 ret = vlv_suspend_complete(dev_priv);
1643 DRM_ERROR("Suspend complete failed: %d\n", ret);
1645 intel_power_domains_init_hw(dev_priv, true);
1650 pci_disable_device(pdev);
1652 * During hibernation on some platforms the BIOS may try to access
1653 * the device even though it's already in D3 and hang the machine. So
1654 * leave the device in D0 on those platforms and hope the BIOS will
1655 * power down the device properly. The issue was seen on multiple old
1656 * GENs with different BIOS vendors, so having an explicit blacklist
1657 * is inpractical; apply the workaround on everything pre GEN6. The
1658 * platforms where the issue was seen:
1659 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1663 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1664 pci_set_power_state(pdev, PCI_D3hot);
1666 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1669 enable_rpm_wakeref_asserts(dev_priv);
1674 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1679 DRM_ERROR("dev: %p\n", dev);
1680 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1684 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1685 state.event != PM_EVENT_FREEZE))
1688 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1691 error = i915_drm_suspend(dev);
1695 return i915_drm_suspend_late(dev, false);
1698 static int i915_drm_resume(struct drm_device *dev)
1700 struct drm_i915_private *dev_priv = to_i915(dev);
1703 disable_rpm_wakeref_asserts(dev_priv);
1704 intel_sanitize_gt_powersave(dev_priv);
1706 ret = i915_ggtt_enable_hw(dev_priv);
1708 DRM_ERROR("failed to re-enable GGTT\n");
1710 intel_csr_ucode_resume(dev_priv);
1712 i915_restore_state(dev_priv);
1713 intel_pps_unlock_regs_wa(dev_priv);
1714 intel_opregion_setup(dev_priv);
1716 intel_init_pch_refclk(dev_priv);
1719 * Interrupts have to be enabled before any batches are run. If not the
1720 * GPU will hang. i915_gem_init_hw() will initiate batches to
1721 * update/restore the context.
1723 * drm_mode_config_reset() needs AUX interrupts.
1725 * Modeset enabling in intel_modeset_init_hw() also needs working
1728 intel_runtime_pm_enable_interrupts(dev_priv);
1730 drm_mode_config_reset(dev);
1732 i915_gem_resume(dev_priv);
1734 intel_modeset_init_hw(dev);
1735 intel_init_clock_gating(dev_priv);
1737 spin_lock_irq(&dev_priv->irq_lock);
1738 if (dev_priv->display.hpd_irq_setup)
1739 dev_priv->display.hpd_irq_setup(dev_priv);
1740 spin_unlock_irq(&dev_priv->irq_lock);
1742 intel_dp_mst_resume(dev);
1744 intel_display_resume(dev);
1746 drm_kms_helper_poll_enable(dev);
1749 * ... but also need to make sure that hotplug processing
1750 * doesn't cause havoc. Like in the driver load code we don't
1751 * bother with the tiny race here where we might loose hotplug
1754 intel_hpd_init(dev_priv);
1756 intel_opregion_register(dev_priv);
1758 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1760 mutex_lock(&dev_priv->modeset_restore_lock);
1761 dev_priv->modeset_restore = MODESET_DONE;
1762 mutex_unlock(&dev_priv->modeset_restore_lock);
1764 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1766 enable_rpm_wakeref_asserts(dev_priv);
1771 static int i915_drm_resume_early(struct drm_device *dev)
1773 struct drm_i915_private *dev_priv = to_i915(dev);
1774 struct pci_dev *pdev = dev_priv->drm.pdev;
1778 * We have a resume ordering issue with the snd-hda driver also
1779 * requiring our device to be power up. Due to the lack of a
1780 * parent/child relationship we currently solve this with an early
1783 * FIXME: This should be solved with a special hdmi sink device or
1784 * similar so that power domains can be employed.
1788 * Note that we need to set the power state explicitly, since we
1789 * powered off the device during freeze and the PCI core won't power
1790 * it back up for us during thaw. Powering off the device during
1791 * freeze is not a hard requirement though, and during the
1792 * suspend/resume phases the PCI core makes sure we get here with the
1793 * device powered on. So in case we change our freeze logic and keep
1794 * the device powered we can also remove the following set power state
1797 ret = pci_set_power_state(pdev, PCI_D0);
1799 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1804 * Note that pci_enable_device() first enables any parent bridge
1805 * device and only then sets the power state for this device. The
1806 * bridge enabling is a nop though, since bridge devices are resumed
1807 * first. The order of enabling power and enabling the device is
1808 * imposed by the PCI core as described above, so here we preserve the
1809 * same order for the freeze/thaw phases.
1811 * TODO: eventually we should remove pci_disable_device() /
1812 * pci_enable_enable_device() from suspend/resume. Due to how they
1813 * depend on the device enable refcount we can't anyway depend on them
1814 * disabling/enabling the device.
1816 if (pci_enable_device(pdev)) {
1821 pci_set_master(pdev);
1823 disable_rpm_wakeref_asserts(dev_priv);
1825 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1826 ret = vlv_resume_prepare(dev_priv, false);
1828 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1831 intel_uncore_resume_early(dev_priv);
1833 if (IS_GEN9_LP(dev_priv)) {
1834 if (!dev_priv->suspended_to_idle)
1835 gen9_sanitize_dc_state(dev_priv);
1836 bxt_disable_dc9(dev_priv);
1837 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1838 hsw_disable_pc8(dev_priv);
1841 intel_uncore_sanitize(dev_priv);
1843 if (IS_GEN9_LP(dev_priv) ||
1844 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1845 intel_power_domains_init_hw(dev_priv, true);
1847 intel_display_set_init_power(dev_priv, true);
1849 i915_gem_sanitize(dev_priv);
1851 enable_rpm_wakeref_asserts(dev_priv);
1854 dev_priv->suspended_to_idle = false;
1859 static int i915_resume_switcheroo(struct drm_device *dev)
1863 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1866 ret = i915_drm_resume_early(dev);
1870 return i915_drm_resume(dev);
1874 * i915_reset - reset chip after a hang
1875 * @i915: #drm_i915_private to reset
1876 * @flags: Instructions
1878 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1881 * Caller must hold the struct_mutex.
1883 * Procedure is fairly simple:
1884 * - reset the chip using the reset reg
1885 * - re-init context state
1886 * - re-init hardware status page
1887 * - re-init ring buffer
1888 * - re-init interrupt state
1891 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1893 struct i915_gpu_error *error = &i915->gpu_error;
1898 lockdep_assert_held(&i915->drm.struct_mutex);
1899 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1901 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1904 /* Clear any previous failed attempts at recovery. Time to try again. */
1905 if (!i915_gem_unset_wedged(i915))
1908 if (!(flags & I915_RESET_QUIET))
1909 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1910 error->reset_count++;
1912 disable_irq(i915->drm.irq);
1913 ret = i915_gem_reset_prepare(i915);
1915 dev_err(i915->drm.dev, "GPU recovery failed\n");
1919 if (!intel_has_gpu_reset(i915)) {
1920 if (i915_modparams.reset)
1921 dev_err(i915->drm.dev, "GPU reset not supported\n");
1923 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1927 for (i = 0; i < 3; i++) {
1928 ret = intel_gpu_reset(i915, ALL_ENGINES);
1935 dev_err(i915->drm.dev, "Failed to reset chip\n");
1939 /* Ok, now get things going again... */
1942 * Everything depends on having the GTT running, so we need to start
1945 ret = i915_ggtt_enable_hw(i915);
1947 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1952 i915_gem_reset(i915);
1953 intel_overlay_reset(i915);
1956 * Next we need to restore the context, but we don't use those
1959 * Ring buffer needs to be re-initialized in the KMS case, or if X
1960 * was running at the time of the reset (i.e. we weren't VT
1963 ret = i915_gem_init_hw(i915);
1965 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1970 i915_queue_hangcheck(i915);
1973 i915_gem_reset_finish(i915);
1974 enable_irq(i915->drm.irq);
1977 clear_bit(I915_RESET_HANDOFF, &error->flags);
1978 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1983 * History tells us that if we cannot reset the GPU now, we
1984 * never will. This then impacts everything that is run
1985 * subsequently. On failing the reset, we mark the driver
1986 * as wedged, preventing further execution on the GPU.
1987 * We also want to go one step further and add a taint to the
1988 * kernel so that any subsequent faults can be traced back to
1989 * this failure. This is important for CI, where if the
1990 * GPU/driver fails we would like to reboot and restart testing
1991 * rather than continue on into oblivion. For everyone else,
1992 * the system should still plod along, but they have been warned!
1994 add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1996 i915_gem_set_wedged(i915);
1997 i915_retire_requests(i915);
2001 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2002 struct intel_engine_cs *engine)
2004 return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2008 * i915_reset_engine - reset GPU engine to recover from a hang
2009 * @engine: engine to reset
2012 * Reset a specific GPU engine. Useful if a hang is detected.
2013 * Returns zero on successful reset or otherwise an error code.
2016 * - identifies the request that caused the hang and it is dropped
2017 * - reset engine (which will force the engine to idle)
2018 * - re-init/configure engine
2020 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
2022 struct i915_gpu_error *error = &engine->i915->gpu_error;
2023 struct i915_request *active_request;
2026 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2028 active_request = i915_gem_reset_prepare_engine(engine);
2029 if (IS_ERR_OR_NULL(active_request)) {
2030 /* Either the previous reset failed, or we pardon the reset. */
2031 ret = PTR_ERR(active_request);
2035 if (!(flags & I915_RESET_QUIET)) {
2036 dev_notice(engine->i915->drm.dev,
2037 "Resetting %s after gpu hang\n", engine->name);
2039 error->reset_engine_count[engine->id]++;
2041 if (!engine->i915->guc.execbuf_client)
2042 ret = intel_gt_reset_engine(engine->i915, engine);
2044 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2046 /* If we fail here, we expect to fallback to a global reset */
2047 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2048 engine->i915->guc.execbuf_client ? "GuC " : "",
2054 * The request that caused the hang is stuck on elsp, we know the
2055 * active request and can drop it, adjust head to skip the offending
2056 * request to resume executing remaining requests in the queue.
2058 i915_gem_reset_engine(engine, active_request);
2061 * The engine and its registers (and workarounds in case of render)
2062 * have been reset to their default values. Follow the init_ring
2063 * process to program RING_MODE, HWSP and re-enable submission.
2065 ret = engine->init_hw(engine);
2070 i915_gem_reset_finish_engine(engine);
2074 static int i915_pm_suspend(struct device *kdev)
2076 struct pci_dev *pdev = to_pci_dev(kdev);
2077 struct drm_device *dev = pci_get_drvdata(pdev);
2080 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2084 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2087 return i915_drm_suspend(dev);
2090 static int i915_pm_suspend_late(struct device *kdev)
2092 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2095 * We have a suspend ordering issue with the snd-hda driver also
2096 * requiring our device to be power up. Due to the lack of a
2097 * parent/child relationship we currently solve this with an late
2100 * FIXME: This should be solved with a special hdmi sink device or
2101 * similar so that power domains can be employed.
2103 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2106 return i915_drm_suspend_late(dev, false);
2109 static int i915_pm_poweroff_late(struct device *kdev)
2111 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2113 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2116 return i915_drm_suspend_late(dev, true);
2119 static int i915_pm_resume_early(struct device *kdev)
2121 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2123 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2126 return i915_drm_resume_early(dev);
2129 static int i915_pm_resume(struct device *kdev)
2131 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2133 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2136 return i915_drm_resume(dev);
2139 /* freeze: before creating the hibernation_image */
2140 static int i915_pm_freeze(struct device *kdev)
2142 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2145 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2146 ret = i915_drm_suspend(dev);
2151 ret = i915_gem_freeze(kdev_to_i915(kdev));
2158 static int i915_pm_freeze_late(struct device *kdev)
2160 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2163 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2164 ret = i915_drm_suspend_late(dev, true);
2169 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2176 /* thaw: called after creating the hibernation image, but before turning off. */
2177 static int i915_pm_thaw_early(struct device *kdev)
2179 return i915_pm_resume_early(kdev);
2182 static int i915_pm_thaw(struct device *kdev)
2184 return i915_pm_resume(kdev);
2187 /* restore: called after loading the hibernation image. */
2188 static int i915_pm_restore_early(struct device *kdev)
2190 return i915_pm_resume_early(kdev);
2193 static int i915_pm_restore(struct device *kdev)
2195 return i915_pm_resume(kdev);
2199 * Save all Gunit registers that may be lost after a D3 and a subsequent
2200 * S0i[R123] transition. The list of registers needing a save/restore is
2201 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2202 * registers in the following way:
2203 * - Driver: saved/restored by the driver
2204 * - Punit : saved/restored by the Punit firmware
2205 * - No, w/o marking: no need to save/restore, since the register is R/O or
2206 * used internally by the HW in a way that doesn't depend
2207 * keeping the content across a suspend/resume.
2208 * - Debug : used for debugging
2210 * We save/restore all registers marked with 'Driver', with the following
2212 * - Registers out of use, including also registers marked with 'Debug'.
2213 * These have no effect on the driver's operation, so we don't save/restore
2214 * them to reduce the overhead.
2215 * - Registers that are fully setup by an initialization function called from
2216 * the resume path. For example many clock gating and RPS/RC6 registers.
2217 * - Registers that provide the right functionality with their reset defaults.
2219 * TODO: Except for registers that based on the above 3 criteria can be safely
2220 * ignored, we save/restore all others, practically treating the HW context as
2221 * a black-box for the driver. Further investigation is needed to reduce the
2222 * saved/restored registers even further, by following the same 3 criteria.
2224 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2226 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2229 /* GAM 0x4000-0x4770 */
2230 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2231 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2232 s->arb_mode = I915_READ(ARB_MODE);
2233 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2234 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2236 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2237 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2239 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2240 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2242 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2243 s->ecochk = I915_READ(GAM_ECOCHK);
2244 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2245 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2247 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2249 /* MBC 0x9024-0x91D0, 0x8500 */
2250 s->g3dctl = I915_READ(VLV_G3DCTL);
2251 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2252 s->mbctl = I915_READ(GEN6_MBCTL);
2254 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2255 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2256 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2257 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2258 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2259 s->rstctl = I915_READ(GEN6_RSTCTL);
2260 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2262 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2263 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2264 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2265 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2266 s->ecobus = I915_READ(ECOBUS);
2267 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2268 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2269 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2270 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2271 s->rcedata = I915_READ(VLV_RCEDATA);
2272 s->spare2gh = I915_READ(VLV_SPAREG2H);
2274 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2275 s->gt_imr = I915_READ(GTIMR);
2276 s->gt_ier = I915_READ(GTIER);
2277 s->pm_imr = I915_READ(GEN6_PMIMR);
2278 s->pm_ier = I915_READ(GEN6_PMIER);
2280 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2281 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2283 /* GT SA CZ domain, 0x100000-0x138124 */
2284 s->tilectl = I915_READ(TILECTL);
2285 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2286 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2287 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2288 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2290 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2291 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2292 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2293 s->pcbr = I915_READ(VLV_PCBR);
2294 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2297 * Not saving any of:
2298 * DFT, 0x9800-0x9EC0
2299 * SARB, 0xB000-0xB1FC
2300 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2305 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2307 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2311 /* GAM 0x4000-0x4770 */
2312 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2313 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2314 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2315 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2316 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2318 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2319 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2321 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2322 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2324 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2325 I915_WRITE(GAM_ECOCHK, s->ecochk);
2326 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2327 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2329 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2331 /* MBC 0x9024-0x91D0, 0x8500 */
2332 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2333 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2334 I915_WRITE(GEN6_MBCTL, s->mbctl);
2336 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2337 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2338 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2339 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2340 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2341 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2342 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2344 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2345 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2346 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2347 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2348 I915_WRITE(ECOBUS, s->ecobus);
2349 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2350 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2351 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2352 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2353 I915_WRITE(VLV_RCEDATA, s->rcedata);
2354 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2356 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2357 I915_WRITE(GTIMR, s->gt_imr);
2358 I915_WRITE(GTIER, s->gt_ier);
2359 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2360 I915_WRITE(GEN6_PMIER, s->pm_ier);
2362 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2363 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2365 /* GT SA CZ domain, 0x100000-0x138124 */
2366 I915_WRITE(TILECTL, s->tilectl);
2367 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2369 * Preserve the GT allow wake and GFX force clock bit, they are not
2370 * be restored, as they are used to control the s0ix suspend/resume
2371 * sequence by the caller.
2373 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2374 val &= VLV_GTLC_ALLOWWAKEREQ;
2375 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2376 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2378 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2379 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2380 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2381 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2383 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2385 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2386 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2387 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2388 I915_WRITE(VLV_PCBR, s->pcbr);
2389 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2392 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2395 /* The HW does not like us polling for PW_STATUS frequently, so
2396 * use the sleeping loop rather than risk the busy spin within
2397 * intel_wait_for_register().
2399 * Transitioning between RC6 states should be at most 2ms (see
2400 * valleyview_enable_rps) so use a 3ms timeout.
2402 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2406 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2411 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2412 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2414 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2415 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2420 err = intel_wait_for_register(dev_priv,
2421 VLV_GTLC_SURVIVABILITY_REG,
2422 VLV_GFX_CLK_STATUS_BIT,
2423 VLV_GFX_CLK_STATUS_BIT,
2426 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2427 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2432 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2438 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2439 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2441 val |= VLV_GTLC_ALLOWWAKEREQ;
2442 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2443 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2445 mask = VLV_GTLC_ALLOWWAKEACK;
2446 val = allow ? mask : 0;
2448 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2450 DRM_ERROR("timeout disabling GT waking\n");
2455 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2461 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2462 val = wait_for_on ? mask : 0;
2465 * RC6 transitioning can be delayed up to 2 msec (see
2466 * valleyview_enable_rps), use 3 msec for safety.
2468 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2469 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2470 onoff(wait_for_on));
2473 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2475 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2478 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2479 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2482 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2488 * Bspec defines the following GT well on flags as debug only, so
2489 * don't treat them as hard failures.
2491 vlv_wait_for_gt_wells(dev_priv, false);
2493 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2494 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2496 vlv_check_no_gt_access(dev_priv);
2498 err = vlv_force_gfx_clock(dev_priv, true);
2502 err = vlv_allow_gt_wake(dev_priv, false);
2506 if (!IS_CHERRYVIEW(dev_priv))
2507 vlv_save_gunit_s0ix_state(dev_priv);
2509 err = vlv_force_gfx_clock(dev_priv, false);
2516 /* For safety always re-enable waking and disable gfx clock forcing */
2517 vlv_allow_gt_wake(dev_priv, true);
2519 vlv_force_gfx_clock(dev_priv, false);
2524 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2531 * If any of the steps fail just try to continue, that's the best we
2532 * can do at this point. Return the first error code (which will also
2533 * leave RPM permanently disabled).
2535 ret = vlv_force_gfx_clock(dev_priv, true);
2537 if (!IS_CHERRYVIEW(dev_priv))
2538 vlv_restore_gunit_s0ix_state(dev_priv);
2540 err = vlv_allow_gt_wake(dev_priv, true);
2544 err = vlv_force_gfx_clock(dev_priv, false);
2548 vlv_check_no_gt_access(dev_priv);
2551 intel_init_clock_gating(dev_priv);
2556 static int intel_runtime_suspend(struct device *kdev)
2558 struct pci_dev *pdev = to_pci_dev(kdev);
2559 struct drm_device *dev = pci_get_drvdata(pdev);
2560 struct drm_i915_private *dev_priv = to_i915(dev);
2563 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2566 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2569 DRM_DEBUG_KMS("Suspending device\n");
2571 disable_rpm_wakeref_asserts(dev_priv);
2574 * We are safe here against re-faults, since the fault handler takes
2577 i915_gem_runtime_suspend(dev_priv);
2579 intel_uc_suspend(dev_priv);
2581 intel_runtime_pm_disable_interrupts(dev_priv);
2583 intel_uncore_suspend(dev_priv);
2586 if (IS_GEN9_LP(dev_priv)) {
2587 bxt_display_core_uninit(dev_priv);
2588 bxt_enable_dc9(dev_priv);
2589 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2590 hsw_enable_pc8(dev_priv);
2591 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2592 ret = vlv_suspend_complete(dev_priv);
2596 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2597 intel_uncore_runtime_resume(dev_priv);
2599 intel_runtime_pm_enable_interrupts(dev_priv);
2601 intel_uc_resume(dev_priv);
2603 i915_gem_init_swizzling(dev_priv);
2604 i915_gem_restore_fences(dev_priv);
2606 enable_rpm_wakeref_asserts(dev_priv);
2611 enable_rpm_wakeref_asserts(dev_priv);
2612 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2614 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2615 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2617 dev_priv->runtime_pm.suspended = true;
2620 * FIXME: We really should find a document that references the arguments
2623 if (IS_BROADWELL(dev_priv)) {
2625 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2626 * being detected, and the call we do at intel_runtime_resume()
2627 * won't be able to restore them. Since PCI_D3hot matches the
2628 * actual specification and appears to be working, use it.
2630 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2633 * current versions of firmware which depend on this opregion
2634 * notification have repurposed the D1 definition to mean
2635 * "runtime suspended" vs. what you would normally expect (D3)
2636 * to distinguish it from notifications that might be sent via
2639 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2642 assert_forcewakes_inactive(dev_priv);
2644 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2645 intel_hpd_poll_init(dev_priv);
2647 DRM_DEBUG_KMS("Device suspended\n");
2651 static int intel_runtime_resume(struct device *kdev)
2653 struct pci_dev *pdev = to_pci_dev(kdev);
2654 struct drm_device *dev = pci_get_drvdata(pdev);
2655 struct drm_i915_private *dev_priv = to_i915(dev);
2658 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2661 DRM_DEBUG_KMS("Resuming device\n");
2663 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2664 disable_rpm_wakeref_asserts(dev_priv);
2666 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2667 dev_priv->runtime_pm.suspended = false;
2668 if (intel_uncore_unclaimed_mmio(dev_priv))
2669 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2671 if (IS_GEN9_LP(dev_priv)) {
2672 bxt_disable_dc9(dev_priv);
2673 bxt_display_core_init(dev_priv, true);
2674 if (dev_priv->csr.dmc_payload &&
2675 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2676 gen9_enable_dc5(dev_priv);
2677 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2678 hsw_disable_pc8(dev_priv);
2679 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2680 ret = vlv_resume_prepare(dev_priv, true);
2683 intel_uncore_runtime_resume(dev_priv);
2685 intel_runtime_pm_enable_interrupts(dev_priv);
2687 intel_uc_resume(dev_priv);
2690 * No point of rolling back things in case of an error, as the best
2691 * we can do is to hope that things will still work (and disable RPM).
2693 i915_gem_init_swizzling(dev_priv);
2694 i915_gem_restore_fences(dev_priv);
2697 * On VLV/CHV display interrupts are part of the display
2698 * power well, so hpd is reinitialized from there. For
2699 * everyone else do it here.
2701 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2702 intel_hpd_init(dev_priv);
2704 intel_enable_ipc(dev_priv);
2706 enable_rpm_wakeref_asserts(dev_priv);
2709 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2711 DRM_DEBUG_KMS("Device resumed\n");
2716 const struct dev_pm_ops i915_pm_ops = {
2718 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2721 .suspend = i915_pm_suspend,
2722 .suspend_late = i915_pm_suspend_late,
2723 .resume_early = i915_pm_resume_early,
2724 .resume = i915_pm_resume,
2728 * @freeze, @freeze_late : called (1) before creating the
2729 * hibernation image [PMSG_FREEZE] and
2730 * (2) after rebooting, before restoring
2731 * the image [PMSG_QUIESCE]
2732 * @thaw, @thaw_early : called (1) after creating the hibernation
2733 * image, before writing it [PMSG_THAW]
2734 * and (2) after failing to create or
2735 * restore the image [PMSG_RECOVER]
2736 * @poweroff, @poweroff_late: called after writing the hibernation
2737 * image, before rebooting [PMSG_HIBERNATE]
2738 * @restore, @restore_early : called after rebooting and restoring the
2739 * hibernation image [PMSG_RESTORE]
2741 .freeze = i915_pm_freeze,
2742 .freeze_late = i915_pm_freeze_late,
2743 .thaw_early = i915_pm_thaw_early,
2744 .thaw = i915_pm_thaw,
2745 .poweroff = i915_pm_suspend,
2746 .poweroff_late = i915_pm_poweroff_late,
2747 .restore_early = i915_pm_restore_early,
2748 .restore = i915_pm_restore,
2750 /* S0ix (via runtime suspend) event handlers */
2751 .runtime_suspend = intel_runtime_suspend,
2752 .runtime_resume = intel_runtime_resume,
2755 static const struct vm_operations_struct i915_gem_vm_ops = {
2756 .fault = i915_gem_fault,
2757 .open = drm_gem_vm_open,
2758 .close = drm_gem_vm_close,
2761 static const struct file_operations i915_driver_fops = {
2762 .owner = THIS_MODULE,
2764 .release = drm_release,
2765 .unlocked_ioctl = drm_ioctl,
2766 .mmap = drm_gem_mmap,
2769 .compat_ioctl = i915_compat_ioctl,
2770 .llseek = noop_llseek,
2774 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2775 struct drm_file *file)
2780 static const struct drm_ioctl_desc i915_ioctls[] = {
2781 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2782 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2783 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2784 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2785 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2786 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2787 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2788 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2789 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2790 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2791 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2792 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2793 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2794 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2795 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2796 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2797 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2798 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2799 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2800 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2801 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2802 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2803 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2804 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2805 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2806 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2807 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2808 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2809 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2810 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2811 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2812 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2813 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2814 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2815 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2816 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2817 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2818 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2819 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2820 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2821 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2822 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2823 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2824 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2825 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2826 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2827 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2828 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2829 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2830 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2831 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2832 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2833 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2834 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2835 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2836 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2839 static struct drm_driver driver = {
2840 /* Don't use MTRRs here; the Xserver or userspace app should
2841 * deal with them for Intel hardware.
2844 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2845 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2846 .release = i915_driver_release,
2847 .open = i915_driver_open,
2848 .lastclose = i915_driver_lastclose,
2849 .postclose = i915_driver_postclose,
2851 .gem_close_object = i915_gem_close_object,
2852 .gem_free_object_unlocked = i915_gem_free_object,
2853 .gem_vm_ops = &i915_gem_vm_ops,
2855 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2856 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2857 .gem_prime_export = i915_gem_prime_export,
2858 .gem_prime_import = i915_gem_prime_import,
2860 .dumb_create = i915_gem_dumb_create,
2861 .dumb_map_offset = i915_gem_mmap_gtt,
2862 .ioctls = i915_ioctls,
2863 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2864 .fops = &i915_driver_fops,
2865 .name = DRIVER_NAME,
2866 .desc = DRIVER_DESC,
2867 .date = DRIVER_DATE,
2868 .major = DRIVER_MAJOR,
2869 .minor = DRIVER_MINOR,
2870 .patchlevel = DRIVER_PATCHLEVEL,
2873 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2874 #include "selftests/mock_drm.c"