drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_irq.h>
  47 #include <drm/drm_probe_helper.h>
  48 #include <drm/i915_drm.h>
  49
  50 #include "i915_drv.h"
  51 #include "i915_pmu.h"
  52 #include "i915_query.h"
  53 #include "i915_reset.h"
  54 #include "i915_trace.h"
  55 #include "i915_vgpu.h"
  56 #include "intel_audio.h"
  57 #include "intel_cdclk.h"
  58 #include "intel_csr.h"
  59 #include "intel_dp.h"
  60 #include "intel_drv.h"
  61 #include "intel_fbdev.h"
  62 #include "intel_pm.h"
  63 #include "intel_sprite.h"
  64 #include "intel_uc.h"
  65 #include "intel_workarounds.h"
  66
  67 static struct drm_driver driver;
  68
  69 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  70 static unsigned int i915_load_fail_count;
  71
  72 bool __i915_inject_load_failure(const char *func, int line)
  73 {
  74         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  75                 return false;
  76
  77         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  78                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  79                          i915_modparams.inject_load_failure, func, line);
  80                 i915_modparams.inject_load_failure = 0;
  81                 return true;
  82         }
  83
  84         return false;
  85 }
  86
  87 bool i915_error_injected(void)
  88 {
  89         return i915_load_fail_count && !i915_modparams.inject_load_failure;
  90 }
  91
  92 #endif
  93
  94 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  95 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  96                     "providing the dmesg log by booting with drm.debug=0xf"
  97
  98 void
  99 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
 100               const char *fmt, ...)
 101 {
 102         static bool shown_bug_once;
 103         struct device *kdev = dev_priv->drm.dev;
 104         bool is_error = level[1] <= KERN_ERR[1];
 105         bool is_debug = level[1] == KERN_DEBUG[1];
 106         struct va_format vaf;
 107         va_list args;
 108
 109         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
 110                 return;
 111
 112         va_start(args, fmt);
 113
 114         vaf.fmt = fmt;
 115         vaf.va = &args;
 116
 117         if (is_error)
 118                 dev_printk(level, kdev, "%pV", &vaf);
 119         else
 120                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 121                            __builtin_return_address(0), &vaf);
 122
 123         va_end(args);
 124
 125         if (is_error && !shown_bug_once) {
 126                 /*
 127                  * Ask the user to file a bug report for the error, except
 128                  * if they may have caused the bug by fiddling with unsafe
 129                  * module parameters.
 130                  */
 131                 if (!test_taint(TAINT_USER))
 132                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 133                 shown_bug_once = true;
 134         }
 135 }
 136
 137 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 138 static enum intel_pch
 139 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 140 {
 141         switch (id) {
 142         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 143                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 144                 WARN_ON(!IS_GEN(dev_priv, 5));
 145                 return PCH_IBX;
 146         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 147                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 148                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
 149                 return PCH_CPT;
 150         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 151                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 152                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
 153                 /* PantherPoint is CPT compatible */
 154                 return PCH_CPT;
 155         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 156                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 157                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 158                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 159                 return PCH_LPT;
 160         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 161                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 162                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 163                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 164                 return PCH_LPT;
 165         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 166                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 167                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 168                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 169                 /* WildcatPoint is LPT compatible */
 170                 return PCH_LPT;
 171         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 172                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 173                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 174                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 175                 /* WildcatPoint is LPT compatible */
 176                 return PCH_LPT;
 177         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 178                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 179                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 180                 return PCH_SPT;
 181         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 182                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 183                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 184                 return PCH_SPT;
 185         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 186                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 187                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 188                         !IS_COFFEELAKE(dev_priv));
 189                 return PCH_KBP;
 190         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 191                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 192                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 193                 return PCH_CNP;
 194         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 195                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 196                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 197                 return PCH_CNP;
 198         case INTEL_PCH_CMP_DEVICE_ID_TYPE:
 199                 DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
 200                 WARN_ON(!IS_COFFEELAKE(dev_priv));
 201                 /* CometPoint is CNP Compatible */
 202                 return PCH_CNP;
 203         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 204                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 205                 WARN_ON(!IS_ICELAKE(dev_priv));
 206                 return PCH_ICP;
 207         default:
 208                 return PCH_NONE;
 209         }
 210 }
 211
 212 static bool intel_is_virt_pch(unsigned short id,
 213                               unsigned short svendor, unsigned short sdevice)
 214 {
 215         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 216                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 217                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 218                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 219                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 220 }
 221
 222 static unsigned short
 223 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 224 {
 225         unsigned short id = 0;
 226
 227         /*
 228          * In a virtualized passthrough environment we can be in a
 229          * setup where the ISA bridge is not able to be passed through.
 230          * In this case, a south bridge can be emulated and we have to
 231          * make an educated guess as to which PCH is really there.
 232          */
 233
 234         if (IS_ICELAKE(dev_priv))
 235                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
 236         else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 237                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 238         else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
 239                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 240         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 241                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 242         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 243                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 244         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
 245                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 246         else if (IS_GEN(dev_priv, 5))
 247                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 248
 249         if (id)
 250                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 251         else
 252                 DRM_DEBUG_KMS("Assuming no PCH\n");
 253
 254         return id;
 255 }
 256
 257 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 258 {
 259         struct pci_dev *pch = NULL;
 260
 261         /*
 262          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 263          * make graphics device passthrough work easy for VMM, that only
 264          * need to expose ISA bridge to let driver know the real hardware
 265          * underneath. This is a requirement from virtualization team.
 266          *
 267          * In some virtualized environments (e.g. XEN), there is irrelevant
 268          * ISA bridge in the system. To work reliably, we should scan trhough
 269          * all the ISA bridge devices and check for the first match, instead
 270          * of only checking the first one.
 271          */
 272         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 273                 unsigned short id;
 274                 enum intel_pch pch_type;
 275
 276                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 277                         continue;
 278
 279                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 280
 281                 pch_type = intel_pch_type(dev_priv, id);
 282                 if (pch_type != PCH_NONE) {
 283                         dev_priv->pch_type = pch_type;
 284                         dev_priv->pch_id = id;
 285                         break;
 286                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 287                                          pch->subsystem_device)) {
 288                         id = intel_virt_detect_pch(dev_priv);
 289                         pch_type = intel_pch_type(dev_priv, id);
 290
 291                         /* Sanity check virtual PCH id */
 292                         if (WARN_ON(id && pch_type == PCH_NONE))
 293                                 id = 0;
 294
 295                         dev_priv->pch_type = pch_type;
 296                         dev_priv->pch_id = id;
 297                         break;
 298                 }
 299         }
 300
 301         /*
 302          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
 303          * display.
 304          */
 305         if (pch && !HAS_DISPLAY(dev_priv)) {
 306                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
 307                 dev_priv->pch_type = PCH_NOP;
 308                 dev_priv->pch_id = 0;
 309         }
 310
 311         if (!pch)
 312                 DRM_DEBUG_KMS("No PCH found.\n");
 313
 314         pci_dev_put(pch);
 315 }
 316
 317 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 318                                struct drm_file *file_priv)
 319 {
 320         struct drm_i915_private *dev_priv = to_i915(dev);
 321         struct pci_dev *pdev = dev_priv->drm.pdev;
 322         drm_i915_getparam_t *param = data;
 323         int value;
 324
 325         switch (param->param) {
 326         case I915_PARAM_IRQ_ACTIVE:
 327         case I915_PARAM_ALLOW_BATCHBUFFER:
 328         case I915_PARAM_LAST_DISPATCH:
 329         case I915_PARAM_HAS_EXEC_CONSTANTS:
 330                 /* Reject all old ums/dri params. */
 331                 return -ENODEV;
 332         case I915_PARAM_CHIPSET_ID:
 333                 value = pdev->device;
 334                 break;
 335         case I915_PARAM_REVISION:
 336                 value = pdev->revision;
 337                 break;
 338         case I915_PARAM_NUM_FENCES_AVAIL:
 339                 value = dev_priv->num_fence_regs;
 340                 break;
 341         case I915_PARAM_HAS_OVERLAY:
 342                 value = dev_priv->overlay ? 1 : 0;
 343                 break;
 344         case I915_PARAM_HAS_BSD:
 345                 value = !!dev_priv->engine[VCS0];
 346                 break;
 347         case I915_PARAM_HAS_BLT:
 348                 value = !!dev_priv->engine[BCS0];
 349                 break;
 350         case I915_PARAM_HAS_VEBOX:
 351                 value = !!dev_priv->engine[VECS0];
 352                 break;
 353         case I915_PARAM_HAS_BSD2:
 354                 value = !!dev_priv->engine[VCS1];
 355                 break;
 356         case I915_PARAM_HAS_LLC:
 357                 value = HAS_LLC(dev_priv);
 358                 break;
 359         case I915_PARAM_HAS_WT:
 360                 value = HAS_WT(dev_priv);
 361                 break;
 362         case I915_PARAM_HAS_ALIASING_PPGTT:
 363                 value = INTEL_PPGTT(dev_priv);
 364                 break;
 365         case I915_PARAM_HAS_SEMAPHORES:
 366                 value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
 367                 break;
 368         case I915_PARAM_HAS_SECURE_BATCHES:
 369                 value = capable(CAP_SYS_ADMIN);
 370                 break;
 371         case I915_PARAM_CMD_PARSER_VERSION:
 372                 value = i915_cmd_parser_get_version(dev_priv);
 373                 break;
 374         case I915_PARAM_SUBSLICE_TOTAL:
 375                 value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
 376                 if (!value)
 377                         return -ENODEV;
 378                 break;
 379         case I915_PARAM_EU_TOTAL:
 380                 value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
 381                 if (!value)
 382                         return -ENODEV;
 383                 break;
 384         case I915_PARAM_HAS_GPU_RESET:
 385                 value = i915_modparams.enable_hangcheck &&
 386                         intel_has_gpu_reset(dev_priv);
 387                 if (value && intel_has_reset_engine(dev_priv))
 388                         value = 2;
 389                 break;
 390         case I915_PARAM_HAS_RESOURCE_STREAMER:
 391                 value = 0;
 392                 break;
 393         case I915_PARAM_HAS_POOLED_EU:
 394                 value = HAS_POOLED_EU(dev_priv);
 395                 break;
 396         case I915_PARAM_MIN_EU_IN_POOL:
 397                 value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
 398                 break;
 399         case I915_PARAM_HUC_STATUS:
 400                 value = intel_huc_check_status(&dev_priv->huc);
 401                 if (value < 0)
 402                         return value;
 403                 break;
 404         case I915_PARAM_MMAP_GTT_VERSION:
 405                 /* Though we've started our numbering from 1, and so class all
 406                  * earlier versions as 0, in effect their value is undefined as
 407                  * the ioctl will report EINVAL for the unknown param!
 408                  */
 409                 value = i915_gem_mmap_gtt_version();
 410                 break;
 411         case I915_PARAM_HAS_SCHEDULER:
 412                 value = dev_priv->caps.scheduler;
 413                 break;
 414
 415         case I915_PARAM_MMAP_VERSION:
 416                 /* Remember to bump this if the version changes! */
 417         case I915_PARAM_HAS_GEM:
 418         case I915_PARAM_HAS_PAGEFLIPPING:
 419         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 420         case I915_PARAM_HAS_RELAXED_FENCING:
 421         case I915_PARAM_HAS_COHERENT_RINGS:
 422         case I915_PARAM_HAS_RELAXED_DELTA:
 423         case I915_PARAM_HAS_GEN7_SOL_RESET:
 424         case I915_PARAM_HAS_WAIT_TIMEOUT:
 425         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 426         case I915_PARAM_HAS_PINNED_BATCHES:
 427         case I915_PARAM_HAS_EXEC_NO_RELOC:
 428         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 429         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 430         case I915_PARAM_HAS_EXEC_SOFTPIN:
 431         case I915_PARAM_HAS_EXEC_ASYNC:
 432         case I915_PARAM_HAS_EXEC_FENCE:
 433         case I915_PARAM_HAS_EXEC_CAPTURE:
 434         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 435         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 436                 /* For the time being all of these are always true;
 437                  * if some supported hardware does not have one of these
 438                  * features this value needs to be provided from
 439                  * INTEL_INFO(), a feature macro, or similar.
 440                  */
 441                 value = 1;
 442                 break;
 443         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 444                 value = intel_engines_has_context_isolation(dev_priv);
 445                 break;
 446         case I915_PARAM_SLICE_MASK:
 447                 value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
 448                 if (!value)
 449                         return -ENODEV;
 450                 break;
 451         case I915_PARAM_SUBSLICE_MASK:
 452                 value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
 453                 if (!value)
 454                         return -ENODEV;
 455                 break;
 456         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 457                 value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
 458                 break;
 459         case I915_PARAM_MMAP_GTT_COHERENT:
 460                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
 461                 break;
 462         default:
 463                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 464                 return -EINVAL;
 465         }
 466
 467         if (put_user(value, param->value))
 468                 return -EFAULT;
 469
 470         return 0;
 471 }
 472
 473 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 474 {
 475         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 476
 477         dev_priv->bridge_dev =
 478                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 479         if (!dev_priv->bridge_dev) {
 480                 DRM_ERROR("bridge device not found\n");
 481                 return -1;
 482         }
 483         return 0;
 484 }
 485
 486 /* Allocate space for the MCH regs if needed, return nonzero on error */
 487 static int
 488 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 489 {
 490         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 491         u32 temp_lo, temp_hi = 0;
 492         u64 mchbar_addr;
 493         int ret;
 494
 495         if (INTEL_GEN(dev_priv) >= 4)
 496                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 497         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 498         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 499
 500         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 501 #ifdef CONFIG_PNP
 502         if (mchbar_addr &&
 503             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 504                 return 0;
 505 #endif
 506
 507         /* Get some space for it */
 508         dev_priv->mch_res.name = "i915 MCHBAR";
 509         dev_priv->mch_res.flags = IORESOURCE_MEM;
 510         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 511                                      &dev_priv->mch_res,
 512                                      MCHBAR_SIZE, MCHBAR_SIZE,
 513                                      PCIBIOS_MIN_MEM,
 514                                      0, pcibios_align_resource,
 515                                      dev_priv->bridge_dev);
 516         if (ret) {
 517                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 518                 dev_priv->mch_res.start = 0;
 519                 return ret;
 520         }
 521
 522         if (INTEL_GEN(dev_priv) >= 4)
 523                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 524                                        upper_32_bits(dev_priv->mch_res.start));
 525
 526         pci_write_config_dword(dev_priv->bridge_dev, reg,
 527                                lower_32_bits(dev_priv->mch_res.start));
 528         return 0;
 529 }
 530
 531 /* Setup MCHBAR if possible, return true if we should disable it again */
 532 static void
 533 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 534 {
 535         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 536         u32 temp;
 537         bool enabled;
 538
 539         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 540                 return;
 541
 542         dev_priv->mchbar_need_disable = false;
 543
 544         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 545                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 546                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 547         } else {
 548                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 549                 enabled = temp & 1;
 550         }
 551
 552         /* If it's already enabled, don't have to do anything */
 553         if (enabled)
 554                 return;
 555
 556         if (intel_alloc_mchbar_resource(dev_priv))
 557                 return;
 558
 559         dev_priv->mchbar_need_disable = true;
 560
 561         /* Space is allocated or reserved, so enable it. */
 562         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 563                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 564                                        temp | DEVEN_MCHBAR_EN);
 565         } else {
 566                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 567                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 568         }
 569 }
 570
 571 static void
 572 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 573 {
 574         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 575
 576         if (dev_priv->mchbar_need_disable) {
 577                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 578                         u32 deven_val;
 579
 580                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 581                                               &deven_val);
 582                         deven_val &= ~DEVEN_MCHBAR_EN;
 583                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 584                                                deven_val);
 585                 } else {
 586                         u32 mchbar_val;
 587
 588                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 589                                               &mchbar_val);
 590                         mchbar_val &= ~1;
 591                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 592                                                mchbar_val);
 593                 }
 594         }
 595
 596         if (dev_priv->mch_res.start)
 597                 release_resource(&dev_priv->mch_res);
 598 }
 599
 600 /* true = enable decode, false = disable decoder */
 601 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 602 {
 603         struct drm_i915_private *dev_priv = cookie;
 604
 605         intel_modeset_vga_set_state(dev_priv, state);
 606         if (state)
 607                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 608                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 609         else
 610                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 611 }
 612
 613 static int i915_resume_switcheroo(struct drm_device *dev);
 614 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 615
 616 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 617 {
 618         struct drm_device *dev = pci_get_drvdata(pdev);
 619         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 620
 621         if (state == VGA_SWITCHEROO_ON) {
 622                 pr_info("switched on\n");
 623                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 624                 /* i915 resume handler doesn't set to D0 */
 625                 pci_set_power_state(pdev, PCI_D0);
 626                 i915_resume_switcheroo(dev);
 627                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 628         } else {
 629                 pr_info("switched off\n");
 630                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 631                 i915_suspend_switcheroo(dev, pmm);
 632                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 633         }
 634 }
 635
 636 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 637 {
 638         struct drm_device *dev = pci_get_drvdata(pdev);
 639
 640         /*
 641          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 642          * locking inversion with the driver load path. And the access here is
 643          * completely racy anyway. So don't bother with locking for now.
 644          */
 645         return dev->open_count == 0;
 646 }
 647
 648 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 649         .set_gpu_state = i915_switcheroo_set_state,
 650         .reprobe = NULL,
 651         .can_switch = i915_switcheroo_can_switch,
 652 };
 653
 654 static int i915_load_modeset_init(struct drm_device *dev)
 655 {
 656         struct drm_i915_private *dev_priv = to_i915(dev);
 657         struct pci_dev *pdev = dev_priv->drm.pdev;
 658         int ret;
 659
 660         if (i915_inject_load_failure())
 661                 return -ENODEV;
 662
 663         if (HAS_DISPLAY(dev_priv)) {
 664                 ret = drm_vblank_init(&dev_priv->drm,
 665                                       INTEL_INFO(dev_priv)->num_pipes);
 666                 if (ret)
 667                         goto out;
 668         }
 669
 670         intel_bios_init(dev_priv);
 671
 672         /* If we have > 1 VGA cards, then we need to arbitrate access
 673          * to the common VGA resources.
 674          *
 675          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 676          * then we do not take part in VGA arbitration and the
 677          * vga_client_register() fails with -ENODEV.
 678          */
 679         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 680         if (ret && ret != -ENODEV)
 681                 goto out;
 682
 683         intel_register_dsm_handler();
 684
 685         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 686         if (ret)
 687                 goto cleanup_vga_client;
 688
 689         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 690         intel_update_rawclk(dev_priv);
 691
 692         intel_power_domains_init_hw(dev_priv, false);
 693
 694         intel_csr_ucode_init(dev_priv);
 695
 696         ret = intel_irq_install(dev_priv);
 697         if (ret)
 698                 goto cleanup_csr;
 699
 700         intel_setup_gmbus(dev_priv);
 701
 702         /* Important: The output setup functions called by modeset_init need
 703          * working irqs for e.g. gmbus and dp aux transfers. */
 704         ret = intel_modeset_init(dev);
 705         if (ret)
 706                 goto cleanup_irq;
 707
 708         ret = i915_gem_init(dev_priv);
 709         if (ret)
 710                 goto cleanup_modeset;
 711
 712         intel_overlay_setup(dev_priv);
 713
 714         if (!HAS_DISPLAY(dev_priv))
 715                 return 0;
 716
 717         ret = intel_fbdev_init(dev);
 718         if (ret)
 719                 goto cleanup_gem;
 720
 721         /* Only enable hotplug handling once the fbdev is fully set up. */
 722         intel_hpd_init(dev_priv);
 723
 724         intel_init_ipc(dev_priv);
 725
 726         return 0;
 727
 728 cleanup_gem:
 729         i915_gem_suspend(dev_priv);
 730         i915_gem_fini(dev_priv);
 731 cleanup_modeset:
 732         intel_modeset_cleanup(dev);
 733 cleanup_irq:
 734         drm_irq_uninstall(dev);
 735         intel_teardown_gmbus(dev_priv);
 736 cleanup_csr:
 737         intel_csr_ucode_fini(dev_priv);
 738         intel_power_domains_fini_hw(dev_priv);
 739         vga_switcheroo_unregister_client(pdev);
 740 cleanup_vga_client:
 741         vga_client_register(pdev, NULL, NULL, NULL);
 742 out:
 743         return ret;
 744 }
 745
 746 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 747 {
 748         struct apertures_struct *ap;
 749         struct pci_dev *pdev = dev_priv->drm.pdev;
 750         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 751         bool primary;
 752         int ret;
 753
 754         ap = alloc_apertures(1);
 755         if (!ap)
 756                 return -ENOMEM;
 757
 758         ap->ranges[0].base = ggtt->gmadr.start;
 759         ap->ranges[0].size = ggtt->mappable_end;
 760
 761         primary =
 762                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 763
 764         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 765
 766         kfree(ap);
 767
 768         return ret;
 769 }
 770
 771 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 772 {
 773         /*
 774          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 775          * CHV x1 PHY (DP/HDMI D)
 776          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 777          */
 778         if (IS_CHERRYVIEW(dev_priv)) {
 779                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 780                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 781         } else if (IS_VALLEYVIEW(dev_priv)) {
 782                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 783         }
 784 }
 785
 786 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 787 {
 788         /*
 789          * The i915 workqueue is primarily used for batched retirement of
 790          * requests (and thus managing bo) once the task has been completed
 791          * by the GPU. i915_retire_requests() is called directly when we
 792          * need high-priority retirement, such as waiting for an explicit
 793          * bo.
 794          *
 795          * It is also used for periodic low-priority events, such as
 796          * idle-timers and recording error state.
 797          *
 798          * All tasks on the workqueue are expected to acquire the dev mutex
 799          * so there is no point in running more than one instance of the
 800          * workqueue at any time.  Use an ordered one.
 801          */
 802         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 803         if (dev_priv->wq == NULL)
 804                 goto out_err;
 805
 806         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 807         if (dev_priv->hotplug.dp_wq == NULL)
 808                 goto out_free_wq;
 809
 810         return 0;
 811
 812 out_free_wq:
 813         destroy_workqueue(dev_priv->wq);
 814 out_err:
 815         DRM_ERROR("Failed to allocate workqueues.\n");
 816
 817         return -ENOMEM;
 818 }
 819
 820 static void i915_engines_cleanup(struct drm_i915_private *i915)
 821 {
 822         struct intel_engine_cs *engine;
 823         enum intel_engine_id id;
 824
 825         for_each_engine(engine, i915, id)
 826                 kfree(engine);
 827 }
 828
 829 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 830 {
 831         destroy_workqueue(dev_priv->hotplug.dp_wq);
 832         destroy_workqueue(dev_priv->wq);
 833 }
 834
 835 /*
 836  * We don't keep the workarounds for pre-production hardware, so we expect our
 837  * driver to fail on these machines in one way or another. A little warning on
 838  * dmesg may help both the user and the bug triagers.
 839  *
 840  * Our policy for removing pre-production workarounds is to keep the
 841  * current gen workarounds as a guide to the bring-up of the next gen
 842  * (workarounds have a habit of persisting!). Anything older than that
 843  * should be removed along with the complications they introduce.
 844  */
 845 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 846 {
 847         bool pre = false;
 848
 849         pre |= IS_HSW_EARLY_SDV(dev_priv);
 850         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 851         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 852         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 853
 854         if (pre) {
 855                 DRM_ERROR("This is a pre-production stepping. "
 856                           "It may not be fully functional.\n");
 857                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 858         }
 859 }
 860
 861 /**
 862  * i915_driver_init_early - setup state not requiring device access
 863  * @dev_priv: device private
 864  *
 865  * Initialize everything that is a "SW-only" state, that is state not
 866  * requiring accessing the device or exposing the driver via kernel internal
 867  * or userspace interfaces. Example steps belonging here: lock initialization,
 868  * system memory allocation, setting up device specific attributes and
 869  * function hooks not requiring accessing the device.
 870  */
 871 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 872 {
 873         int ret = 0;
 874
 875         if (i915_inject_load_failure())
 876                 return -ENODEV;
 877
 878         intel_device_info_subplatform_init(dev_priv);
 879
 880         intel_uncore_init_early(&dev_priv->uncore);
 881
 882         spin_lock_init(&dev_priv->irq_lock);
 883         spin_lock_init(&dev_priv->gpu_error.lock);
 884         mutex_init(&dev_priv->backlight_lock);
 885
 886         mutex_init(&dev_priv->sb_lock);
 887         mutex_init(&dev_priv->av_mutex);
 888         mutex_init(&dev_priv->wm.wm_mutex);
 889         mutex_init(&dev_priv->pps_mutex);
 890         mutex_init(&dev_priv->hdcp_comp_mutex);
 891
 892         i915_memcpy_init_early(dev_priv);
 893         intel_runtime_pm_init_early(dev_priv);
 894
 895         ret = i915_workqueues_init(dev_priv);
 896         if (ret < 0)
 897                 goto err_engines;
 898
 899         ret = i915_gem_init_early(dev_priv);
 900         if (ret < 0)
 901                 goto err_workqueues;
 902
 903         /* This must be called before any calls to HAS_PCH_* */
 904         intel_detect_pch(dev_priv);
 905
 906         intel_wopcm_init_early(&dev_priv->wopcm);
 907         intel_uc_init_early(dev_priv);
 908         intel_pm_setup(dev_priv);
 909         intel_init_dpio(dev_priv);
 910         ret = intel_power_domains_init(dev_priv);
 911         if (ret < 0)
 912                 goto err_uc;
 913         intel_irq_init(dev_priv);
 914         intel_hangcheck_init(dev_priv);
 915         intel_init_display_hooks(dev_priv);
 916         intel_init_clock_gating_hooks(dev_priv);
 917         intel_init_audio_hooks(dev_priv);
 918         intel_display_crc_init(dev_priv);
 919
 920         intel_detect_preproduction_hw(dev_priv);
 921
 922         return 0;
 923
 924 err_uc:
 925         intel_uc_cleanup_early(dev_priv);
 926         i915_gem_cleanup_early(dev_priv);
 927 err_workqueues:
 928         i915_workqueues_cleanup(dev_priv);
 929 err_engines:
 930         i915_engines_cleanup(dev_priv);
 931         return ret;
 932 }
 933
 934 /**
 935  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 936  * @dev_priv: device private
 937  */
 938 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 939 {
 940         intel_irq_fini(dev_priv);
 941         intel_power_domains_cleanup(dev_priv);
 942         intel_uc_cleanup_early(dev_priv);
 943         i915_gem_cleanup_early(dev_priv);
 944         i915_workqueues_cleanup(dev_priv);
 945         i915_engines_cleanup(dev_priv);
 946 }
 947
 948 /**
 949  * i915_driver_init_mmio - setup device MMIO
 950  * @dev_priv: device private
 951  *
 952  * Setup minimal device state necessary for MMIO accesses later in the
 953  * initialization sequence. The setup here should avoid any other device-wide
 954  * side effects or exposing the driver via kernel internal or user space
 955  * interfaces.
 956  */
 957 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 958 {
 959         int ret;
 960
 961         if (i915_inject_load_failure())
 962                 return -ENODEV;
 963
 964         if (i915_get_bridge_dev(dev_priv))
 965                 return -EIO;
 966
 967         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 968         if (ret < 0)
 969                 goto err_bridge;
 970
 971         /* Try to make sure MCHBAR is enabled before poking at it */
 972         intel_setup_mchbar(dev_priv);
 973
 974         intel_device_info_init_mmio(dev_priv);
 975
 976         intel_uncore_prune_mmio_domains(&dev_priv->uncore);
 977
 978         intel_uc_init_mmio(dev_priv);
 979
 980         ret = intel_engines_init_mmio(dev_priv);
 981         if (ret)
 982                 goto err_uncore;
 983
 984         i915_gem_init_mmio(dev_priv);
 985
 986         return 0;
 987
 988 err_uncore:
 989         intel_teardown_mchbar(dev_priv);
 990         intel_uncore_fini_mmio(&dev_priv->uncore);
 991 err_bridge:
 992         pci_dev_put(dev_priv->bridge_dev);
 993
 994         return ret;
 995 }
 996
 997 /**
 998  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 999  * @dev_priv: device private
1000  */
1001 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1002 {
1003         intel_teardown_mchbar(dev_priv);
1004         intel_uncore_fini_mmio(&dev_priv->uncore);
1005         pci_dev_put(dev_priv->bridge_dev);
1006 }
1007
1008 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1009 {
1010         intel_gvt_sanitize_options(dev_priv);
1011 }
1012
1013 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
1014
1015 static const char *intel_dram_type_str(enum intel_dram_type type)
1016 {
1017         static const char * const str[] = {
1018                 DRAM_TYPE_STR(UNKNOWN),
1019                 DRAM_TYPE_STR(DDR3),
1020                 DRAM_TYPE_STR(DDR4),
1021                 DRAM_TYPE_STR(LPDDR3),
1022                 DRAM_TYPE_STR(LPDDR4),
1023         };
1024
1025         if (type >= ARRAY_SIZE(str))
1026                 type = INTEL_DRAM_UNKNOWN;
1027
1028         return str[type];
1029 }
1030
1031 #undef DRAM_TYPE_STR
1032
1033 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
1034 {
1035         return dimm->ranks * 64 / (dimm->width ?: 1);
1036 }
1037
1038 /* Returns total GB for the whole DIMM */
1039 static int skl_get_dimm_size(u16 val)
1040 {
1041         return val & SKL_DRAM_SIZE_MASK;
1042 }
1043
1044 static int skl_get_dimm_width(u16 val)
1045 {
1046         if (skl_get_dimm_size(val) == 0)
1047                 return 0;
1048
1049         switch (val & SKL_DRAM_WIDTH_MASK) {
1050         case SKL_DRAM_WIDTH_X8:
1051         case SKL_DRAM_WIDTH_X16:
1052         case SKL_DRAM_WIDTH_X32:
1053                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1054                 return 8 << val;
1055         default:
1056                 MISSING_CASE(val);
1057                 return 0;
1058         }
1059 }
1060
1061 static int skl_get_dimm_ranks(u16 val)
1062 {
1063         if (skl_get_dimm_size(val) == 0)
1064                 return 0;
1065
1066         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
1067
1068         return val + 1;
1069 }
1070
1071 /* Returns total GB for the whole DIMM */
1072 static int cnl_get_dimm_size(u16 val)
1073 {
1074         return (val & CNL_DRAM_SIZE_MASK) / 2;
1075 }
1076
1077 static int cnl_get_dimm_width(u16 val)
1078 {
1079         if (cnl_get_dimm_size(val) == 0)
1080                 return 0;
1081
1082         switch (val & CNL_DRAM_WIDTH_MASK) {
1083         case CNL_DRAM_WIDTH_X8:
1084         case CNL_DRAM_WIDTH_X16:
1085         case CNL_DRAM_WIDTH_X32:
1086                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
1087                 return 8 << val;
1088         default:
1089                 MISSING_CASE(val);
1090                 return 0;
1091         }
1092 }
1093
1094 static int cnl_get_dimm_ranks(u16 val)
1095 {
1096         if (cnl_get_dimm_size(val) == 0)
1097                 return 0;
1098
1099         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
1100
1101         return val + 1;
1102 }
1103
1104 static bool
1105 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
1106 {
1107         /* Convert total GB to Gb per DRAM device */
1108         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
1109 }
1110
1111 static void
1112 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
1113                        struct dram_dimm_info *dimm,
1114                        int channel, char dimm_name, u16 val)
1115 {
1116         if (INTEL_GEN(dev_priv) >= 10) {
1117                 dimm->size = cnl_get_dimm_size(val);
1118                 dimm->width = cnl_get_dimm_width(val);
1119                 dimm->ranks = cnl_get_dimm_ranks(val);
1120         } else {
1121                 dimm->size = skl_get_dimm_size(val);
1122                 dimm->width = skl_get_dimm_width(val);
1123                 dimm->ranks = skl_get_dimm_ranks(val);
1124         }
1125
1126         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
1127                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
1128                       yesno(skl_is_16gb_dimm(dimm)));
1129 }
1130
1131 static int
1132 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
1133                           struct dram_channel_info *ch,
1134                           int channel, u32 val)
1135 {
1136         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
1137                                channel, 'L', val & 0xffff);
1138         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
1139                                channel, 'S', val >> 16);
1140
1141         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
1142                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
1143                 return -EINVAL;
1144         }
1145
1146         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
1147                 ch->ranks = 2;
1148         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
1149                 ch->ranks = 2;
1150         else
1151                 ch->ranks = 1;
1152
1153         ch->is_16gb_dimm =
1154                 skl_is_16gb_dimm(&ch->dimm_l) ||
1155                 skl_is_16gb_dimm(&ch->dimm_s);
1156
1157         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
1158                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
1159
1160         return 0;
1161 }
1162
1163 static bool
1164 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
1165                         const struct dram_channel_info *ch1)
1166 {
1167         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
1168                 (ch0->dimm_s.size == 0 ||
1169                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
1170 }
1171
1172 static int
1173 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1174 {
1175         struct dram_info *dram_info = &dev_priv->dram_info;
1176         struct dram_channel_info ch0 = {}, ch1 = {};
1177         u32 val;
1178         int ret;
1179
1180         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1181         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
1182         if (ret == 0)
1183                 dram_info->num_channels++;
1184
1185         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1186         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
1187         if (ret == 0)
1188                 dram_info->num_channels++;
1189
1190         if (dram_info->num_channels == 0) {
1191                 DRM_INFO("Number of memory channels is zero\n");
1192                 return -EINVAL;
1193         }
1194
1195         /*
1196          * If any of the channel is single rank channel, worst case output
1197          * will be same as if single rank memory, so consider single rank
1198          * memory.
1199          */
1200         if (ch0.ranks == 1 || ch1.ranks == 1)
1201                 dram_info->ranks = 1;
1202         else
1203                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
1204
1205         if (dram_info->ranks == 0) {
1206                 DRM_INFO("couldn't get memory rank information\n");
1207                 return -EINVAL;
1208         }
1209
1210         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1211
1212         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
1213
1214         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
1215                       yesno(dram_info->symmetric_memory));
1216         return 0;
1217 }
1218
1219 static enum intel_dram_type
1220 skl_get_dram_type(struct drm_i915_private *dev_priv)
1221 {
1222         u32 val;
1223
1224         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
1225
1226         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
1227         case SKL_DRAM_DDR_TYPE_DDR3:
1228                 return INTEL_DRAM_DDR3;
1229         case SKL_DRAM_DDR_TYPE_DDR4:
1230                 return INTEL_DRAM_DDR4;
1231         case SKL_DRAM_DDR_TYPE_LPDDR3:
1232                 return INTEL_DRAM_LPDDR3;
1233         case SKL_DRAM_DDR_TYPE_LPDDR4:
1234                 return INTEL_DRAM_LPDDR4;
1235         default:
1236                 MISSING_CASE(val);
1237                 return INTEL_DRAM_UNKNOWN;
1238         }
1239 }
1240
1241 static int
1242 skl_get_dram_info(struct drm_i915_private *dev_priv)
1243 {
1244         struct dram_info *dram_info = &dev_priv->dram_info;
1245         u32 mem_freq_khz, val;
1246         int ret;
1247
1248         dram_info->type = skl_get_dram_type(dev_priv);
1249         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
1250
1251         ret = skl_dram_get_channels_info(dev_priv);
1252         if (ret)
1253                 return ret;
1254
1255         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1256         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1257                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1258
1259         dram_info->bandwidth_kbps = dram_info->num_channels *
1260                                                         mem_freq_khz * 8;
1261
1262         if (dram_info->bandwidth_kbps == 0) {
1263                 DRM_INFO("Couldn't get system memory bandwidth\n");
1264                 return -EINVAL;
1265         }
1266
1267         dram_info->valid = true;
1268         return 0;
1269 }
1270
1271 /* Returns Gb per DRAM device */
1272 static int bxt_get_dimm_size(u32 val)
1273 {
1274         switch (val & BXT_DRAM_SIZE_MASK) {
1275         case BXT_DRAM_SIZE_4GBIT:
1276                 return 4;
1277         case BXT_DRAM_SIZE_6GBIT:
1278                 return 6;
1279         case BXT_DRAM_SIZE_8GBIT:
1280                 return 8;
1281         case BXT_DRAM_SIZE_12GBIT:
1282                 return 12;
1283         case BXT_DRAM_SIZE_16GBIT:
1284                 return 16;
1285         default:
1286                 MISSING_CASE(val);
1287                 return 0;
1288         }
1289 }
1290
1291 static int bxt_get_dimm_width(u32 val)
1292 {
1293         if (!bxt_get_dimm_size(val))
1294                 return 0;
1295
1296         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1297
1298         return 8 << val;
1299 }
1300
1301 static int bxt_get_dimm_ranks(u32 val)
1302 {
1303         if (!bxt_get_dimm_size(val))
1304                 return 0;
1305
1306         switch (val & BXT_DRAM_RANK_MASK) {
1307         case BXT_DRAM_RANK_SINGLE:
1308                 return 1;
1309         case BXT_DRAM_RANK_DUAL:
1310                 return 2;
1311         default:
1312                 MISSING_CASE(val);
1313                 return 0;
1314         }
1315 }
1316
1317 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1318 {
1319         if (!bxt_get_dimm_size(val))
1320                 return INTEL_DRAM_UNKNOWN;
1321
1322         switch (val & BXT_DRAM_TYPE_MASK) {
1323         case BXT_DRAM_TYPE_DDR3:
1324                 return INTEL_DRAM_DDR3;
1325         case BXT_DRAM_TYPE_LPDDR3:
1326                 return INTEL_DRAM_LPDDR3;
1327         case BXT_DRAM_TYPE_DDR4:
1328                 return INTEL_DRAM_DDR4;
1329         case BXT_DRAM_TYPE_LPDDR4:
1330                 return INTEL_DRAM_LPDDR4;
1331         default:
1332                 MISSING_CASE(val);
1333                 return INTEL_DRAM_UNKNOWN;
1334         }
1335 }
1336
1337 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1338                               u32 val)
1339 {
1340         dimm->width = bxt_get_dimm_width(val);
1341         dimm->ranks = bxt_get_dimm_ranks(val);
1342
1343         /*
1344          * Size in register is Gb per DRAM device. Convert to total
1345          * GB to match the way we report this for non-LP platforms.
1346          */
1347         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1348 }
1349
1350 static int
1351 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1352 {
1353         struct dram_info *dram_info = &dev_priv->dram_info;
1354         u32 dram_channels;
1355         u32 mem_freq_khz, val;
1356         u8 num_active_channels;
1357         int i;
1358
1359         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1360         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1361                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1362
1363         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1364         num_active_channels = hweight32(dram_channels);
1365
1366         /* Each active bit represents 4-byte channel */
1367         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1368
1369         if (dram_info->bandwidth_kbps == 0) {
1370                 DRM_INFO("Couldn't get system memory bandwidth\n");
1371                 return -EINVAL;
1372         }
1373
1374         /*
1375          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1376          */
1377         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1378                 struct dram_dimm_info dimm;
1379                 enum intel_dram_type type;
1380
1381                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1382                 if (val == 0xFFFFFFFF)
1383                         continue;
1384
1385                 dram_info->num_channels++;
1386
1387                 bxt_get_dimm_info(&dimm, val);
1388                 type = bxt_get_dimm_type(val);
1389
1390                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1391                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1392                         dram_info->type != type);
1393
1394                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1395                               i - BXT_D_CR_DRP0_DUNIT_START,
1396                               dimm.size, dimm.width, dimm.ranks,
1397                               intel_dram_type_str(type));
1398
1399                 /*
1400                  * If any of the channel is single rank channel,
1401                  * worst case output will be same as if single rank
1402                  * memory, so consider single rank memory.
1403                  */
1404                 if (dram_info->ranks == 0)
1405                         dram_info->ranks = dimm.ranks;
1406                 else if (dimm.ranks == 1)
1407                         dram_info->ranks = 1;
1408
1409                 if (type != INTEL_DRAM_UNKNOWN)
1410                         dram_info->type = type;
1411         }
1412
1413         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1414             dram_info->ranks == 0) {
1415                 DRM_INFO("couldn't get memory information\n");
1416                 return -EINVAL;
1417         }
1418
1419         dram_info->valid = true;
1420         return 0;
1421 }
1422
1423 static void
1424 intel_get_dram_info(struct drm_i915_private *dev_priv)
1425 {
1426         struct dram_info *dram_info = &dev_priv->dram_info;
1427         int ret;
1428
1429         /*
1430          * Assume 16Gb DIMMs are present until proven otherwise.
1431          * This is only used for the level 0 watermark latency
1432          * w/a which does not apply to bxt/glk.
1433          */
1434         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1435
1436         if (INTEL_GEN(dev_priv) < 9)
1437                 return;
1438
1439         if (IS_GEN9_LP(dev_priv))
1440                 ret = bxt_get_dram_info(dev_priv);
1441         else
1442                 ret = skl_get_dram_info(dev_priv);
1443         if (ret)
1444                 return;
1445
1446         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1447                       dram_info->bandwidth_kbps,
1448                       dram_info->num_channels);
1449
1450         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1451                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1452 }
1453
1454 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1455 {
1456         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1457         const unsigned int sets[4] = { 1, 1, 2, 2 };
1458
1459         return EDRAM_NUM_BANKS(cap) *
1460                 ways[EDRAM_WAYS_IDX(cap)] *
1461                 sets[EDRAM_SETS_IDX(cap)];
1462 }
1463
1464 static void edram_detect(struct drm_i915_private *dev_priv)
1465 {
1466         u32 edram_cap = 0;
1467
1468         if (!(IS_HASWELL(dev_priv) ||
1469               IS_BROADWELL(dev_priv) ||
1470               INTEL_GEN(dev_priv) >= 9))
1471                 return;
1472
1473         edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1474
1475         /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1476
1477         if (!(edram_cap & EDRAM_ENABLED))
1478                 return;
1479
1480         /*
1481          * The needed capability bits for size calculation are not there with
1482          * pre gen9 so return 128MB always.
1483          */
1484         if (INTEL_GEN(dev_priv) < 9)
1485                 dev_priv->edram_size_mb = 128;
1486         else
1487                 dev_priv->edram_size_mb =
1488                         gen9_edram_size_mb(dev_priv, edram_cap);
1489
1490         DRM_INFO("Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1491 }
1492
1493 /**
1494  * i915_driver_init_hw - setup state requiring device access
1495  * @dev_priv: device private
1496  *
1497  * Setup state that requires accessing the device, but doesn't require
1498  * exposing the driver via kernel internal or userspace interfaces.
1499  */
1500 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1501 {
1502         struct pci_dev *pdev = dev_priv->drm.pdev;
1503         int ret;
1504
1505         if (i915_inject_load_failure())
1506                 return -ENODEV;
1507
1508         intel_device_info_runtime_init(dev_priv);
1509
1510         if (HAS_PPGTT(dev_priv)) {
1511                 if (intel_vgpu_active(dev_priv) &&
1512                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1513                         i915_report_error(dev_priv,
1514                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1515                         return -ENXIO;
1516                 }
1517         }
1518
1519         if (HAS_EXECLISTS(dev_priv)) {
1520                 /*
1521                  * Older GVT emulation depends upon intercepting CSB mmio,
1522                  * which we no longer use, preferring to use the HWSP cache
1523                  * instead.
1524                  */
1525                 if (intel_vgpu_active(dev_priv) &&
1526                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1527                         i915_report_error(dev_priv,
1528                                           "old vGPU host found, support for HWSP emulation required\n");
1529                         return -ENXIO;
1530                 }
1531         }
1532
1533         intel_sanitize_options(dev_priv);
1534
1535         /* needs to be done before ggtt probe */
1536         edram_detect(dev_priv);
1537
1538         i915_perf_init(dev_priv);
1539
1540         ret = i915_ggtt_probe_hw(dev_priv);
1541         if (ret)
1542                 goto err_perf;
1543
1544         /*
1545          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1546          * otherwise the vga fbdev driver falls over.
1547          */
1548         ret = i915_kick_out_firmware_fb(dev_priv);
1549         if (ret) {
1550                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1551                 goto err_ggtt;
1552         }
1553
1554         ret = vga_remove_vgacon(pdev);
1555         if (ret) {
1556                 DRM_ERROR("failed to remove conflicting VGA console\n");
1557                 goto err_ggtt;
1558         }
1559
1560         ret = i915_ggtt_init_hw(dev_priv);
1561         if (ret)
1562                 goto err_ggtt;
1563
1564         ret = i915_ggtt_enable_hw(dev_priv);
1565         if (ret) {
1566                 DRM_ERROR("failed to enable GGTT\n");
1567                 goto err_ggtt;
1568         }
1569
1570         pci_set_master(pdev);
1571
1572         /* overlay on gen2 is broken and can't address above 1G */
1573         if (IS_GEN(dev_priv, 2)) {
1574                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1575                 if (ret) {
1576                         DRM_ERROR("failed to set DMA mask\n");
1577
1578                         goto err_ggtt;
1579                 }
1580         }
1581
1582         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1583          * using 32bit addressing, overwriting memory if HWS is located
1584          * above 4GB.
1585          *
1586          * The documentation also mentions an issue with undefined
1587          * behaviour if any general state is accessed within a page above 4GB,
1588          * which also needs to be handled carefully.
1589          */
1590         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1591                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1592
1593                 if (ret) {
1594                         DRM_ERROR("failed to set DMA mask\n");
1595
1596                         goto err_ggtt;
1597                 }
1598         }
1599
1600         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1601                            PM_QOS_DEFAULT_VALUE);
1602
1603         intel_uncore_sanitize(dev_priv);
1604
1605         intel_gt_init_workarounds(dev_priv);
1606         i915_gem_load_init_fences(dev_priv);
1607
1608         /* On the 945G/GM, the chipset reports the MSI capability on the
1609          * integrated graphics even though the support isn't actually there
1610          * according to the published specs.  It doesn't appear to function
1611          * correctly in testing on 945G.
1612          * This may be a side effect of MSI having been made available for PEG
1613          * and the registers being closely associated.
1614          *
1615          * According to chipset errata, on the 965GM, MSI interrupts may
1616          * be lost or delayed, and was defeatured. MSI interrupts seem to
1617          * get lost on g4x as well, and interrupt delivery seems to stay
1618          * properly dead afterwards. So we'll just disable them for all
1619          * pre-gen5 chipsets.
1620          *
1621          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1622          * interrupts even when in MSI mode. This results in spurious
1623          * interrupt warnings if the legacy irq no. is shared with another
1624          * device. The kernel then disables that interrupt source and so
1625          * prevents the other device from working properly.
1626          */
1627         if (INTEL_GEN(dev_priv) >= 5) {
1628                 if (pci_enable_msi(pdev) < 0)
1629                         DRM_DEBUG_DRIVER("can't enable MSI");
1630         }
1631
1632         ret = intel_gvt_init(dev_priv);
1633         if (ret)
1634                 goto err_msi;
1635
1636         intel_opregion_setup(dev_priv);
1637         /*
1638          * Fill the dram structure to get the system raw bandwidth and
1639          * dram info. This will be used for memory latency calculation.
1640          */
1641         intel_get_dram_info(dev_priv);
1642
1643
1644         return 0;
1645
1646 err_msi:
1647         if (pdev->msi_enabled)
1648                 pci_disable_msi(pdev);
1649         pm_qos_remove_request(&dev_priv->pm_qos);
1650 err_ggtt:
1651         i915_ggtt_cleanup_hw(dev_priv);
1652 err_perf:
1653         i915_perf_fini(dev_priv);
1654         return ret;
1655 }
1656
1657 /**
1658  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1659  * @dev_priv: device private
1660  */
1661 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1662 {
1663         struct pci_dev *pdev = dev_priv->drm.pdev;
1664
1665         i915_perf_fini(dev_priv);
1666
1667         if (pdev->msi_enabled)
1668                 pci_disable_msi(pdev);
1669
1670         pm_qos_remove_request(&dev_priv->pm_qos);
1671         i915_ggtt_cleanup_hw(dev_priv);
1672 }
1673
1674 /**
1675  * i915_driver_register - register the driver with the rest of the system
1676  * @dev_priv: device private
1677  *
1678  * Perform any steps necessary to make the driver available via kernel
1679  * internal or userspace interfaces.
1680  */
1681 static void i915_driver_register(struct drm_i915_private *dev_priv)
1682 {
1683         struct drm_device *dev = &dev_priv->drm;
1684
1685         i915_gem_shrinker_register(dev_priv);
1686         i915_pmu_register(dev_priv);
1687
1688         /*
1689          * Notify a valid surface after modesetting,
1690          * when running inside a VM.
1691          */
1692         if (intel_vgpu_active(dev_priv))
1693                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1694
1695         /* Reveal our presence to userspace */
1696         if (drm_dev_register(dev, 0) == 0) {
1697                 i915_debugfs_register(dev_priv);
1698                 i915_setup_sysfs(dev_priv);
1699
1700                 /* Depends on sysfs having been initialized */
1701                 i915_perf_register(dev_priv);
1702         } else
1703                 DRM_ERROR("Failed to register driver for userspace access!\n");
1704
1705         if (HAS_DISPLAY(dev_priv)) {
1706                 /* Must be done after probing outputs */
1707                 intel_opregion_register(dev_priv);
1708                 acpi_video_register();
1709         }
1710
1711         if (IS_GEN(dev_priv, 5))
1712                 intel_gpu_ips_init(dev_priv);
1713
1714         intel_audio_init(dev_priv);
1715
1716         /*
1717          * Some ports require correctly set-up hpd registers for detection to
1718          * work properly (leading to ghost connected connector status), e.g. VGA
1719          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1720          * irqs are fully enabled. We do it last so that the async config
1721          * cannot run before the connectors are registered.
1722          */
1723         intel_fbdev_initial_config_async(dev);
1724
1725         /*
1726          * We need to coordinate the hotplugs with the asynchronous fbdev
1727          * configuration, for which we use the fbdev->async_cookie.
1728          */
1729         if (HAS_DISPLAY(dev_priv))
1730                 drm_kms_helper_poll_init(dev);
1731
1732         intel_power_domains_enable(dev_priv);
1733         intel_runtime_pm_enable(dev_priv);
1734 }
1735
1736 /**
1737  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1738  * @dev_priv: device private
1739  */
1740 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1741 {
1742         intel_runtime_pm_disable(dev_priv);
1743         intel_power_domains_disable(dev_priv);
1744
1745         intel_fbdev_unregister(dev_priv);
1746         intel_audio_deinit(dev_priv);
1747
1748         /*
1749          * After flushing the fbdev (incl. a late async config which will
1750          * have delayed queuing of a hotplug event), then flush the hotplug
1751          * events.
1752          */
1753         drm_kms_helper_poll_fini(&dev_priv->drm);
1754
1755         intel_gpu_ips_teardown();
1756         acpi_video_unregister();
1757         intel_opregion_unregister(dev_priv);
1758
1759         i915_perf_unregister(dev_priv);
1760         i915_pmu_unregister(dev_priv);
1761
1762         i915_teardown_sysfs(dev_priv);
1763         drm_dev_unregister(&dev_priv->drm);
1764
1765         i915_gem_shrinker_unregister(dev_priv);
1766 }
1767
1768 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1769 {
1770         if (drm_debug & DRM_UT_DRIVER) {
1771                 struct drm_printer p = drm_debug_printer("i915 device info:");
1772
1773                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1774                            INTEL_DEVID(dev_priv),
1775                            INTEL_REVID(dev_priv),
1776                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1777                            intel_subplatform(RUNTIME_INFO(dev_priv),
1778                                              INTEL_INFO(dev_priv)->platform),
1779                            INTEL_GEN(dev_priv));
1780
1781                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1782                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1783         }
1784
1785         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1786                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1787         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1788                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1789         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1790                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1791 }
1792
1793 static struct drm_i915_private *
1794 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1795 {
1796         const struct intel_device_info *match_info =
1797                 (struct intel_device_info *)ent->driver_data;
1798         struct intel_device_info *device_info;
1799         struct drm_i915_private *i915;
1800         int err;
1801
1802         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1803         if (!i915)
1804                 return ERR_PTR(-ENOMEM);
1805
1806         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1807         if (err) {
1808                 kfree(i915);
1809                 return ERR_PTR(err);
1810         }
1811
1812         i915->drm.pdev = pdev;
1813         i915->drm.dev_private = i915;
1814         pci_set_drvdata(pdev, &i915->drm);
1815
1816         /* Setup the write-once "constant" device info */
1817         device_info = mkwrite_device_info(i915);
1818         memcpy(device_info, match_info, sizeof(*device_info));
1819         RUNTIME_INFO(i915)->device_id = pdev->device;
1820
1821         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1822
1823         return i915;
1824 }
1825
1826 static void i915_driver_destroy(struct drm_i915_private *i915)
1827 {
1828         struct pci_dev *pdev = i915->drm.pdev;
1829
1830         drm_dev_fini(&i915->drm);
1831         kfree(i915);
1832
1833         /* And make sure we never chase our dangling pointer from pci_dev */
1834         pci_set_drvdata(pdev, NULL);
1835 }
1836
1837 /**
1838  * i915_driver_load - setup chip and create an initial config
1839  * @pdev: PCI device
1840  * @ent: matching PCI ID entry
1841  *
1842  * The driver load routine has to do several things:
1843  *   - drive output discovery via intel_modeset_init()
1844  *   - initialize the memory manager
1845  *   - allocate initial config memory
1846  *   - setup the DRM framebuffer with the allocated memory
1847  */
1848 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1849 {
1850         const struct intel_device_info *match_info =
1851                 (struct intel_device_info *)ent->driver_data;
1852         struct drm_i915_private *dev_priv;
1853         int ret;
1854
1855         dev_priv = i915_driver_create(pdev, ent);
1856         if (IS_ERR(dev_priv))
1857                 return PTR_ERR(dev_priv);
1858
1859         /* Disable nuclear pageflip by default on pre-ILK */
1860         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1861                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1862
1863         ret = pci_enable_device(pdev);
1864         if (ret)
1865                 goto out_fini;
1866
1867         ret = i915_driver_init_early(dev_priv);
1868         if (ret < 0)
1869                 goto out_pci_disable;
1870
1871         disable_rpm_wakeref_asserts(dev_priv);
1872
1873         ret = i915_driver_init_mmio(dev_priv);
1874         if (ret < 0)
1875                 goto out_runtime_pm_put;
1876
1877         ret = i915_driver_init_hw(dev_priv);
1878         if (ret < 0)
1879                 goto out_cleanup_mmio;
1880
1881         ret = i915_load_modeset_init(&dev_priv->drm);
1882         if (ret < 0)
1883                 goto out_cleanup_hw;
1884
1885         i915_driver_register(dev_priv);
1886
1887         enable_rpm_wakeref_asserts(dev_priv);
1888
1889         i915_welcome_messages(dev_priv);
1890
1891         return 0;
1892
1893 out_cleanup_hw:
1894         i915_driver_cleanup_hw(dev_priv);
1895 out_cleanup_mmio:
1896         i915_driver_cleanup_mmio(dev_priv);
1897 out_runtime_pm_put:
1898         enable_rpm_wakeref_asserts(dev_priv);
1899         i915_driver_cleanup_early(dev_priv);
1900 out_pci_disable:
1901         pci_disable_device(pdev);
1902 out_fini:
1903         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1904         i915_driver_destroy(dev_priv);
1905         return ret;
1906 }
1907
1908 void i915_driver_unload(struct drm_device *dev)
1909 {
1910         struct drm_i915_private *dev_priv = to_i915(dev);
1911         struct pci_dev *pdev = dev_priv->drm.pdev;
1912
1913         disable_rpm_wakeref_asserts(dev_priv);
1914
1915         i915_driver_unregister(dev_priv);
1916
1917         /*
1918          * After unregistering the device to prevent any new users, cancel
1919          * all in-flight requests so that we can quickly unbind the active
1920          * resources.
1921          */
1922         i915_gem_set_wedged(dev_priv);
1923
1924         /* Flush any external code that still may be under the RCU lock */
1925         synchronize_rcu();
1926
1927         i915_gem_suspend(dev_priv);
1928
1929         drm_atomic_helper_shutdown(dev);
1930
1931         intel_gvt_cleanup(dev_priv);
1932
1933         intel_modeset_cleanup(dev);
1934
1935         intel_bios_cleanup(dev_priv);
1936
1937         vga_switcheroo_unregister_client(pdev);
1938         vga_client_register(pdev, NULL, NULL, NULL);
1939
1940         intel_csr_ucode_fini(dev_priv);
1941
1942         /* Free error state after interrupts are fully disabled. */
1943         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1944         i915_reset_error_state(dev_priv);
1945
1946         i915_gem_fini(dev_priv);
1947
1948         intel_power_domains_fini_hw(dev_priv);
1949
1950         i915_driver_cleanup_hw(dev_priv);
1951         i915_driver_cleanup_mmio(dev_priv);
1952
1953         enable_rpm_wakeref_asserts(dev_priv);
1954         intel_runtime_pm_cleanup(dev_priv);
1955 }
1956
1957 static void i915_driver_release(struct drm_device *dev)
1958 {
1959         struct drm_i915_private *dev_priv = to_i915(dev);
1960
1961         i915_driver_cleanup_early(dev_priv);
1962         i915_driver_destroy(dev_priv);
1963 }
1964
1965 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1966 {
1967         struct drm_i915_private *i915 = to_i915(dev);
1968         int ret;
1969
1970         ret = i915_gem_open(i915, file);
1971         if (ret)
1972                 return ret;
1973
1974         return 0;
1975 }
1976
1977 /**
1978  * i915_driver_lastclose - clean up after all DRM clients have exited
1979  * @dev: DRM device
1980  *
1981  * Take care of cleaning up after all DRM clients have exited.  In the
1982  * mode setting case, we want to restore the kernel's initial mode (just
1983  * in case the last client left us in a bad state).
1984  *
1985  * Additionally, in the non-mode setting case, we'll tear down the GTT
1986  * and DMA structures, since the kernel won't be using them, and clea
1987  * up any GEM state.
1988  */
1989 static void i915_driver_lastclose(struct drm_device *dev)
1990 {
1991         intel_fbdev_restore_mode(dev);
1992         vga_switcheroo_process_delayed_switch();
1993 }
1994
1995 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1996 {
1997         struct drm_i915_file_private *file_priv = file->driver_priv;
1998
1999         mutex_lock(&dev->struct_mutex);
2000         i915_gem_context_close(file);
2001         i915_gem_release(dev, file);
2002         mutex_unlock(&dev->struct_mutex);
2003
2004         kfree(file_priv);
2005 }
2006
2007 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
2008 {
2009         struct drm_device *dev = &dev_priv->drm;
2010         struct intel_encoder *encoder;
2011
2012         drm_modeset_lock_all(dev);
2013         for_each_intel_encoder(dev, encoder)
2014                 if (encoder->suspend)
2015                         encoder->suspend(encoder);
2016         drm_modeset_unlock_all(dev);
2017 }
2018
2019 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2020                               bool rpm_resume);
2021 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
2022
2023 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
2024 {
2025 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
2026         if (acpi_target_system_state() < ACPI_STATE_S3)
2027                 return true;
2028 #endif
2029         return false;
2030 }
2031
2032 static int i915_drm_prepare(struct drm_device *dev)
2033 {
2034         struct drm_i915_private *i915 = to_i915(dev);
2035
2036         /*
2037          * NB intel_display_suspend() may issue new requests after we've
2038          * ostensibly marked the GPU as ready-to-sleep here. We need to
2039          * split out that work and pull it forward so that after point,
2040          * the GPU is not woken again.
2041          */
2042         i915_gem_suspend(i915);
2043
2044         return 0;
2045 }
2046
2047 static int i915_drm_suspend(struct drm_device *dev)
2048 {
2049         struct drm_i915_private *dev_priv = to_i915(dev);
2050         struct pci_dev *pdev = dev_priv->drm.pdev;
2051         pci_power_t opregion_target_state;
2052
2053         disable_rpm_wakeref_asserts(dev_priv);
2054
2055         /* We do a lot of poking in a lot of registers, make sure they work
2056          * properly. */
2057         intel_power_domains_disable(dev_priv);
2058
2059         drm_kms_helper_poll_disable(dev);
2060
2061         pci_save_state(pdev);
2062
2063         intel_display_suspend(dev);
2064
2065         intel_dp_mst_suspend(dev_priv);
2066
2067         intel_runtime_pm_disable_interrupts(dev_priv);
2068         intel_hpd_cancel_work(dev_priv);
2069
2070         intel_suspend_encoders(dev_priv);
2071
2072         intel_suspend_hw(dev_priv);
2073
2074         i915_gem_suspend_gtt_mappings(dev_priv);
2075
2076         i915_save_state(dev_priv);
2077
2078         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
2079         intel_opregion_suspend(dev_priv, opregion_target_state);
2080
2081         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
2082
2083         dev_priv->suspend_count++;
2084
2085         intel_csr_ucode_suspend(dev_priv);
2086
2087         enable_rpm_wakeref_asserts(dev_priv);
2088
2089         return 0;
2090 }
2091
2092 static enum i915_drm_suspend_mode
2093 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
2094 {
2095         if (hibernate)
2096                 return I915_DRM_SUSPEND_HIBERNATE;
2097
2098         if (suspend_to_idle(dev_priv))
2099                 return I915_DRM_SUSPEND_IDLE;
2100
2101         return I915_DRM_SUSPEND_MEM;
2102 }
2103
2104 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
2105 {
2106         struct drm_i915_private *dev_priv = to_i915(dev);
2107         struct pci_dev *pdev = dev_priv->drm.pdev;
2108         int ret;
2109
2110         disable_rpm_wakeref_asserts(dev_priv);
2111
2112         i915_gem_suspend_late(dev_priv);
2113
2114         intel_uncore_suspend(&dev_priv->uncore);
2115
2116         intel_power_domains_suspend(dev_priv,
2117                                     get_suspend_mode(dev_priv, hibernation));
2118
2119         ret = 0;
2120         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
2121                 bxt_enable_dc9(dev_priv);
2122         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2123                 hsw_enable_pc8(dev_priv);
2124         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2125                 ret = vlv_suspend_complete(dev_priv);
2126
2127         if (ret) {
2128                 DRM_ERROR("Suspend complete failed: %d\n", ret);
2129                 intel_power_domains_resume(dev_priv);
2130
2131                 goto out;
2132         }
2133
2134         pci_disable_device(pdev);
2135         /*
2136          * During hibernation on some platforms the BIOS may try to access
2137          * the device even though it's already in D3 and hang the machine. So
2138          * leave the device in D0 on those platforms and hope the BIOS will
2139          * power down the device properly. The issue was seen on multiple old
2140          * GENs with different BIOS vendors, so having an explicit blacklist
2141          * is inpractical; apply the workaround on everything pre GEN6. The
2142          * platforms where the issue was seen:
2143          * Lenovo Thinkpad X301, X61s, X60, T60, X41
2144          * Fujitsu FSC S7110
2145          * Acer Aspire 1830T
2146          */
2147         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
2148                 pci_set_power_state(pdev, PCI_D3hot);
2149
2150 out:
2151         enable_rpm_wakeref_asserts(dev_priv);
2152         if (!dev_priv->uncore.user_forcewake.count)
2153                 intel_runtime_pm_cleanup(dev_priv);
2154
2155         return ret;
2156 }
2157
2158 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
2159 {
2160         int error;
2161
2162         if (!dev) {
2163                 DRM_ERROR("dev: %p\n", dev);
2164                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2165                 return -ENODEV;
2166         }
2167
2168         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2169                          state.event != PM_EVENT_FREEZE))
2170                 return -EINVAL;
2171
2172         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2173                 return 0;
2174
2175         error = i915_drm_suspend(dev);
2176         if (error)
2177                 return error;
2178
2179         return i915_drm_suspend_late(dev, false);
2180 }
2181
2182 static int i915_drm_resume(struct drm_device *dev)
2183 {
2184         struct drm_i915_private *dev_priv = to_i915(dev);
2185         int ret;
2186
2187         disable_rpm_wakeref_asserts(dev_priv);
2188         intel_sanitize_gt_powersave(dev_priv);
2189
2190         i915_gem_sanitize(dev_priv);
2191
2192         ret = i915_ggtt_enable_hw(dev_priv);
2193         if (ret)
2194                 DRM_ERROR("failed to re-enable GGTT\n");
2195
2196         intel_csr_ucode_resume(dev_priv);
2197
2198         i915_restore_state(dev_priv);
2199         intel_pps_unlock_regs_wa(dev_priv);
2200
2201         intel_init_pch_refclk(dev_priv);
2202
2203         /*
2204          * Interrupts have to be enabled before any batches are run. If not the
2205          * GPU will hang. i915_gem_init_hw() will initiate batches to
2206          * update/restore the context.
2207          *
2208          * drm_mode_config_reset() needs AUX interrupts.
2209          *
2210          * Modeset enabling in intel_modeset_init_hw() also needs working
2211          * interrupts.
2212          */
2213         intel_runtime_pm_enable_interrupts(dev_priv);
2214
2215         drm_mode_config_reset(dev);
2216
2217         i915_gem_resume(dev_priv);
2218
2219         intel_modeset_init_hw(dev);
2220         intel_init_clock_gating(dev_priv);
2221
2222         spin_lock_irq(&dev_priv->irq_lock);
2223         if (dev_priv->display.hpd_irq_setup)
2224                 dev_priv->display.hpd_irq_setup(dev_priv);
2225         spin_unlock_irq(&dev_priv->irq_lock);
2226
2227         intel_dp_mst_resume(dev_priv);
2228
2229         intel_display_resume(dev);
2230
2231         drm_kms_helper_poll_enable(dev);
2232
2233         /*
2234          * ... but also need to make sure that hotplug processing
2235          * doesn't cause havoc. Like in the driver load code we don't
2236          * bother with the tiny race here where we might lose hotplug
2237          * notifications.
2238          * */
2239         intel_hpd_init(dev_priv);
2240
2241         intel_opregion_resume(dev_priv);
2242
2243         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2244
2245         intel_power_domains_enable(dev_priv);
2246
2247         enable_rpm_wakeref_asserts(dev_priv);
2248
2249         return 0;
2250 }
2251
2252 static int i915_drm_resume_early(struct drm_device *dev)
2253 {
2254         struct drm_i915_private *dev_priv = to_i915(dev);
2255         struct pci_dev *pdev = dev_priv->drm.pdev;
2256         int ret;
2257
2258         /*
2259          * We have a resume ordering issue with the snd-hda driver also
2260          * requiring our device to be power up. Due to the lack of a
2261          * parent/child relationship we currently solve this with an early
2262          * resume hook.
2263          *
2264          * FIXME: This should be solved with a special hdmi sink device or
2265          * similar so that power domains can be employed.
2266          */
2267
2268         /*
2269          * Note that we need to set the power state explicitly, since we
2270          * powered off the device during freeze and the PCI core won't power
2271          * it back up for us during thaw. Powering off the device during
2272          * freeze is not a hard requirement though, and during the
2273          * suspend/resume phases the PCI core makes sure we get here with the
2274          * device powered on. So in case we change our freeze logic and keep
2275          * the device powered we can also remove the following set power state
2276          * call.
2277          */
2278         ret = pci_set_power_state(pdev, PCI_D0);
2279         if (ret) {
2280                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2281                 return ret;
2282         }
2283
2284         /*
2285          * Note that pci_enable_device() first enables any parent bridge
2286          * device and only then sets the power state for this device. The
2287          * bridge enabling is a nop though, since bridge devices are resumed
2288          * first. The order of enabling power and enabling the device is
2289          * imposed by the PCI core as described above, so here we preserve the
2290          * same order for the freeze/thaw phases.
2291          *
2292          * TODO: eventually we should remove pci_disable_device() /
2293          * pci_enable_enable_device() from suspend/resume. Due to how they
2294          * depend on the device enable refcount we can't anyway depend on them
2295          * disabling/enabling the device.
2296          */
2297         if (pci_enable_device(pdev))
2298                 return -EIO;
2299
2300         pci_set_master(pdev);
2301
2302         disable_rpm_wakeref_asserts(dev_priv);
2303
2304         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2305                 ret = vlv_resume_prepare(dev_priv, false);
2306         if (ret)
2307                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2308                           ret);
2309
2310         intel_uncore_resume_early(&dev_priv->uncore);
2311
2312         i915_check_and_clear_faults(dev_priv);
2313
2314         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2315                 gen9_sanitize_dc_state(dev_priv);
2316                 bxt_disable_dc9(dev_priv);
2317         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2318                 hsw_disable_pc8(dev_priv);
2319         }
2320
2321         intel_uncore_sanitize(dev_priv);
2322
2323         intel_power_domains_resume(dev_priv);
2324
2325         intel_engines_sanitize(dev_priv, true);
2326
2327         enable_rpm_wakeref_asserts(dev_priv);
2328
2329         return ret;
2330 }
2331
2332 static int i915_resume_switcheroo(struct drm_device *dev)
2333 {
2334         int ret;
2335
2336         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2337                 return 0;
2338
2339         ret = i915_drm_resume_early(dev);
2340         if (ret)
2341                 return ret;
2342
2343         return i915_drm_resume(dev);
2344 }
2345
2346 static int i915_pm_prepare(struct device *kdev)
2347 {
2348         struct pci_dev *pdev = to_pci_dev(kdev);
2349         struct drm_device *dev = pci_get_drvdata(pdev);
2350
2351         if (!dev) {
2352                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2353                 return -ENODEV;
2354         }
2355
2356         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2357                 return 0;
2358
2359         return i915_drm_prepare(dev);
2360 }
2361
2362 static int i915_pm_suspend(struct device *kdev)
2363 {
2364         struct pci_dev *pdev = to_pci_dev(kdev);
2365         struct drm_device *dev = pci_get_drvdata(pdev);
2366
2367         if (!dev) {
2368                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2369                 return -ENODEV;
2370         }
2371
2372         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2373                 return 0;
2374
2375         return i915_drm_suspend(dev);
2376 }
2377
2378 static int i915_pm_suspend_late(struct device *kdev)
2379 {
2380         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2381
2382         /*
2383          * We have a suspend ordering issue with the snd-hda driver also
2384          * requiring our device to be power up. Due to the lack of a
2385          * parent/child relationship we currently solve this with an late
2386          * suspend hook.
2387          *
2388          * FIXME: This should be solved with a special hdmi sink device or
2389          * similar so that power domains can be employed.
2390          */
2391         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2392                 return 0;
2393
2394         return i915_drm_suspend_late(dev, false);
2395 }
2396
2397 static int i915_pm_poweroff_late(struct device *kdev)
2398 {
2399         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2400
2401         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2402                 return 0;
2403
2404         return i915_drm_suspend_late(dev, true);
2405 }
2406
2407 static int i915_pm_resume_early(struct device *kdev)
2408 {
2409         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2410
2411         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2412                 return 0;
2413
2414         return i915_drm_resume_early(dev);
2415 }
2416
2417 static int i915_pm_resume(struct device *kdev)
2418 {
2419         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2420
2421         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2422                 return 0;
2423
2424         return i915_drm_resume(dev);
2425 }
2426
2427 /* freeze: before creating the hibernation_image */
2428 static int i915_pm_freeze(struct device *kdev)
2429 {
2430         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2431         int ret;
2432
2433         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2434                 ret = i915_drm_suspend(dev);
2435                 if (ret)
2436                         return ret;
2437         }
2438
2439         ret = i915_gem_freeze(kdev_to_i915(kdev));
2440         if (ret)
2441                 return ret;
2442
2443         return 0;
2444 }
2445
2446 static int i915_pm_freeze_late(struct device *kdev)
2447 {
2448         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2449         int ret;
2450
2451         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2452                 ret = i915_drm_suspend_late(dev, true);
2453                 if (ret)
2454                         return ret;
2455         }
2456
2457         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2458         if (ret)
2459                 return ret;
2460
2461         return 0;
2462 }
2463
2464 /* thaw: called after creating the hibernation image, but before turning off. */
2465 static int i915_pm_thaw_early(struct device *kdev)
2466 {
2467         return i915_pm_resume_early(kdev);
2468 }
2469
2470 static int i915_pm_thaw(struct device *kdev)
2471 {
2472         return i915_pm_resume(kdev);
2473 }
2474
2475 /* restore: called after loading the hibernation image. */
2476 static int i915_pm_restore_early(struct device *kdev)
2477 {
2478         return i915_pm_resume_early(kdev);
2479 }
2480
2481 static int i915_pm_restore(struct device *kdev)
2482 {
2483         return i915_pm_resume(kdev);
2484 }
2485
2486 /*
2487  * Save all Gunit registers that may be lost after a D3 and a subsequent
2488  * S0i[R123] transition. The list of registers needing a save/restore is
2489  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2490  * registers in the following way:
2491  * - Driver: saved/restored by the driver
2492  * - Punit : saved/restored by the Punit firmware
2493  * - No, w/o marking: no need to save/restore, since the register is R/O or
2494  *                    used internally by the HW in a way that doesn't depend
2495  *                    keeping the content across a suspend/resume.
2496  * - Debug : used for debugging
2497  *
2498  * We save/restore all registers marked with 'Driver', with the following
2499  * exceptions:
2500  * - Registers out of use, including also registers marked with 'Debug'.
2501  *   These have no effect on the driver's operation, so we don't save/restore
2502  *   them to reduce the overhead.
2503  * - Registers that are fully setup by an initialization function called from
2504  *   the resume path. For example many clock gating and RPS/RC6 registers.
2505  * - Registers that provide the right functionality with their reset defaults.
2506  *
2507  * TODO: Except for registers that based on the above 3 criteria can be safely
2508  * ignored, we save/restore all others, practically treating the HW context as
2509  * a black-box for the driver. Further investigation is needed to reduce the
2510  * saved/restored registers even further, by following the same 3 criteria.
2511  */
2512 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2513 {
2514         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2515         int i;
2516
2517         /* GAM 0x4000-0x4770 */
2518         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2519         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2520         s->arb_mode             = I915_READ(ARB_MODE);
2521         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2522         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2523
2524         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2525                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2526
2527         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2528         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2529
2530         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2531         s->ecochk               = I915_READ(GAM_ECOCHK);
2532         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2533         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2534
2535         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2536
2537         /* MBC 0x9024-0x91D0, 0x8500 */
2538         s->g3dctl               = I915_READ(VLV_G3DCTL);
2539         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2540         s->mbctl                = I915_READ(GEN6_MBCTL);
2541
2542         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2543         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2544         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2545         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2546         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2547         s->rstctl               = I915_READ(GEN6_RSTCTL);
2548         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2549
2550         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2551         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2552         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2553         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2554         s->ecobus               = I915_READ(ECOBUS);
2555         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2556         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2557         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2558         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2559         s->rcedata              = I915_READ(VLV_RCEDATA);
2560         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2561
2562         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2563         s->gt_imr               = I915_READ(GTIMR);
2564         s->gt_ier               = I915_READ(GTIER);
2565         s->pm_imr               = I915_READ(GEN6_PMIMR);
2566         s->pm_ier               = I915_READ(GEN6_PMIER);
2567
2568         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2569                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2570
2571         /* GT SA CZ domain, 0x100000-0x138124 */
2572         s->tilectl              = I915_READ(TILECTL);
2573         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2574         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2575         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2576         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2577
2578         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2579         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2580         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2581         s->pcbr                 = I915_READ(VLV_PCBR);
2582         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2583
2584         /*
2585          * Not saving any of:
2586          * DFT,         0x9800-0x9EC0
2587          * SARB,        0xB000-0xB1FC
2588          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2589          * PCI CFG
2590          */
2591 }
2592
2593 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2594 {
2595         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2596         u32 val;
2597         int i;
2598
2599         /* GAM 0x4000-0x4770 */
2600         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2601         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2602         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2603         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2604         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2605
2606         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2607                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2608
2609         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2610         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2611
2612         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2613         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2614         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2615         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2616
2617         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2618
2619         /* MBC 0x9024-0x91D0, 0x8500 */
2620         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2621         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2622         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2623
2624         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2625         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2626         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2627         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2628         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2629         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2630         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2631
2632         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2633         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2634         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2635         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2636         I915_WRITE(ECOBUS,              s->ecobus);
2637         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2638         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2639         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2640         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2641         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2642         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2643
2644         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2645         I915_WRITE(GTIMR,               s->gt_imr);
2646         I915_WRITE(GTIER,               s->gt_ier);
2647         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2648         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2649
2650         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2651                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2652
2653         /* GT SA CZ domain, 0x100000-0x138124 */
2654         I915_WRITE(TILECTL,                     s->tilectl);
2655         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2656         /*
2657          * Preserve the GT allow wake and GFX force clock bit, they are not
2658          * be restored, as they are used to control the s0ix suspend/resume
2659          * sequence by the caller.
2660          */
2661         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2662         val &= VLV_GTLC_ALLOWWAKEREQ;
2663         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2664         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2665
2666         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2667         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2668         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2669         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2670
2671         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2672
2673         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2674         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2675         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2676         I915_WRITE(VLV_PCBR,                    s->pcbr);
2677         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2678 }
2679
2680 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2681                                   u32 mask, u32 val)
2682 {
2683         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2684         u32 reg_value;
2685         int ret;
2686
2687         /* The HW does not like us polling for PW_STATUS frequently, so
2688          * use the sleeping loop rather than risk the busy spin within
2689          * intel_wait_for_register().
2690          *
2691          * Transitioning between RC6 states should be at most 2ms (see
2692          * valleyview_enable_rps) so use a 3ms timeout.
2693          */
2694         ret = wait_for(((reg_value = I915_READ_NOTRACE(reg)) & mask) == val, 3);
2695
2696         /* just trace the final value */
2697         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2698
2699         return ret;
2700 }
2701
2702 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2703 {
2704         u32 val;
2705         int err;
2706
2707         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2708         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2709         if (force_on)
2710                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2711         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2712
2713         if (!force_on)
2714                 return 0;
2715
2716         err = intel_wait_for_register(&dev_priv->uncore,
2717                                       VLV_GTLC_SURVIVABILITY_REG,
2718                                       VLV_GFX_CLK_STATUS_BIT,
2719                                       VLV_GFX_CLK_STATUS_BIT,
2720                                       20);
2721         if (err)
2722                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2723                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2724
2725         return err;
2726 }
2727
2728 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2729 {
2730         u32 mask;
2731         u32 val;
2732         int err;
2733
2734         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2735         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2736         if (allow)
2737                 val |= VLV_GTLC_ALLOWWAKEREQ;
2738         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2739         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2740
2741         mask = VLV_GTLC_ALLOWWAKEACK;
2742         val = allow ? mask : 0;
2743
2744         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2745         if (err)
2746                 DRM_ERROR("timeout disabling GT waking\n");
2747
2748         return err;
2749 }
2750
2751 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2752                                   bool wait_for_on)
2753 {
2754         u32 mask;
2755         u32 val;
2756
2757         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2758         val = wait_for_on ? mask : 0;
2759
2760         /*
2761          * RC6 transitioning can be delayed up to 2 msec (see
2762          * valleyview_enable_rps), use 3 msec for safety.
2763          *
2764          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2765          * reset and we are trying to force the machine to sleep.
2766          */
2767         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2768                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2769                                  onoff(wait_for_on));
2770 }
2771
2772 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2773 {
2774         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2775                 return;
2776
2777         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2778         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2779 }
2780
2781 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2782 {
2783         u32 mask;
2784         int err;
2785
2786         /*
2787          * Bspec defines the following GT well on flags as debug only, so
2788          * don't treat them as hard failures.
2789          */
2790         vlv_wait_for_gt_wells(dev_priv, false);
2791
2792         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2793         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2794
2795         vlv_check_no_gt_access(dev_priv);
2796
2797         err = vlv_force_gfx_clock(dev_priv, true);
2798         if (err)
2799                 goto err1;
2800
2801         err = vlv_allow_gt_wake(dev_priv, false);
2802         if (err)
2803                 goto err2;
2804
2805         if (!IS_CHERRYVIEW(dev_priv))
2806                 vlv_save_gunit_s0ix_state(dev_priv);
2807
2808         err = vlv_force_gfx_clock(dev_priv, false);
2809         if (err)
2810                 goto err2;
2811
2812         return 0;
2813
2814 err2:
2815         /* For safety always re-enable waking and disable gfx clock forcing */
2816         vlv_allow_gt_wake(dev_priv, true);
2817 err1:
2818         vlv_force_gfx_clock(dev_priv, false);
2819
2820         return err;
2821 }
2822
2823 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2824                                 bool rpm_resume)
2825 {
2826         int err;
2827         int ret;
2828
2829         /*
2830          * If any of the steps fail just try to continue, that's the best we
2831          * can do at this point. Return the first error code (which will also
2832          * leave RPM permanently disabled).
2833          */
2834         ret = vlv_force_gfx_clock(dev_priv, true);
2835
2836         if (!IS_CHERRYVIEW(dev_priv))
2837                 vlv_restore_gunit_s0ix_state(dev_priv);
2838
2839         err = vlv_allow_gt_wake(dev_priv, true);
2840         if (!ret)
2841                 ret = err;
2842
2843         err = vlv_force_gfx_clock(dev_priv, false);
2844         if (!ret)
2845                 ret = err;
2846
2847         vlv_check_no_gt_access(dev_priv);
2848
2849         if (rpm_resume)
2850                 intel_init_clock_gating(dev_priv);
2851
2852         return ret;
2853 }
2854
2855 static int intel_runtime_suspend(struct device *kdev)
2856 {
2857         struct pci_dev *pdev = to_pci_dev(kdev);
2858         struct drm_device *dev = pci_get_drvdata(pdev);
2859         struct drm_i915_private *dev_priv = to_i915(dev);
2860         int ret;
2861
2862         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2863                 return -ENODEV;
2864
2865         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2866                 return -ENODEV;
2867
2868         DRM_DEBUG_KMS("Suspending device\n");
2869
2870         disable_rpm_wakeref_asserts(dev_priv);
2871
2872         /*
2873          * We are safe here against re-faults, since the fault handler takes
2874          * an RPM reference.
2875          */
2876         i915_gem_runtime_suspend(dev_priv);
2877
2878         intel_uc_suspend(dev_priv);
2879
2880         intel_runtime_pm_disable_interrupts(dev_priv);
2881
2882         intel_uncore_suspend(&dev_priv->uncore);
2883
2884         ret = 0;
2885         if (INTEL_GEN(dev_priv) >= 11) {
2886                 icl_display_core_uninit(dev_priv);
2887                 bxt_enable_dc9(dev_priv);
2888         } else if (IS_GEN9_LP(dev_priv)) {
2889                 bxt_display_core_uninit(dev_priv);
2890                 bxt_enable_dc9(dev_priv);
2891         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2892                 hsw_enable_pc8(dev_priv);
2893         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2894                 ret = vlv_suspend_complete(dev_priv);
2895         }
2896
2897         if (ret) {
2898                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2899                 intel_uncore_runtime_resume(&dev_priv->uncore);
2900
2901                 intel_runtime_pm_enable_interrupts(dev_priv);
2902
2903                 intel_uc_resume(dev_priv);
2904
2905                 i915_gem_init_swizzling(dev_priv);
2906                 i915_gem_restore_fences(dev_priv);
2907
2908                 enable_rpm_wakeref_asserts(dev_priv);
2909
2910                 return ret;
2911         }
2912
2913         enable_rpm_wakeref_asserts(dev_priv);
2914         intel_runtime_pm_cleanup(dev_priv);
2915
2916         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2917                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2918
2919         dev_priv->runtime_pm.suspended = true;
2920
2921         /*
2922          * FIXME: We really should find a document that references the arguments
2923          * used below!
2924          */
2925         if (IS_BROADWELL(dev_priv)) {
2926                 /*
2927                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2928                  * being detected, and the call we do at intel_runtime_resume()
2929                  * won't be able to restore them. Since PCI_D3hot matches the
2930                  * actual specification and appears to be working, use it.
2931                  */
2932                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2933         } else {
2934                 /*
2935                  * current versions of firmware which depend on this opregion
2936                  * notification have repurposed the D1 definition to mean
2937                  * "runtime suspended" vs. what you would normally expect (D3)
2938                  * to distinguish it from notifications that might be sent via
2939                  * the suspend path.
2940                  */
2941                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2942         }
2943
2944         assert_forcewakes_inactive(&dev_priv->uncore);
2945
2946         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2947                 intel_hpd_poll_init(dev_priv);
2948
2949         DRM_DEBUG_KMS("Device suspended\n");
2950         return 0;
2951 }
2952
2953 static int intel_runtime_resume(struct device *kdev)
2954 {
2955         struct pci_dev *pdev = to_pci_dev(kdev);
2956         struct drm_device *dev = pci_get_drvdata(pdev);
2957         struct drm_i915_private *dev_priv = to_i915(dev);
2958         int ret = 0;
2959
2960         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2961                 return -ENODEV;
2962
2963         DRM_DEBUG_KMS("Resuming device\n");
2964
2965         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2966         disable_rpm_wakeref_asserts(dev_priv);
2967
2968         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2969         dev_priv->runtime_pm.suspended = false;
2970         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2971                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2972
2973         if (INTEL_GEN(dev_priv) >= 11) {
2974                 bxt_disable_dc9(dev_priv);
2975                 icl_display_core_init(dev_priv, true);
2976                 if (dev_priv->csr.dmc_payload) {
2977                         if (dev_priv->csr.allowed_dc_mask &
2978                             DC_STATE_EN_UPTO_DC6)
2979                                 skl_enable_dc6(dev_priv);
2980                         else if (dev_priv->csr.allowed_dc_mask &
2981                                  DC_STATE_EN_UPTO_DC5)
2982                                 gen9_enable_dc5(dev_priv);
2983                 }
2984         } else if (IS_GEN9_LP(dev_priv)) {
2985                 bxt_disable_dc9(dev_priv);
2986                 bxt_display_core_init(dev_priv, true);
2987                 if (dev_priv->csr.dmc_payload &&
2988                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2989                         gen9_enable_dc5(dev_priv);
2990         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2991                 hsw_disable_pc8(dev_priv);
2992         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2993                 ret = vlv_resume_prepare(dev_priv, true);
2994         }
2995
2996         intel_uncore_runtime_resume(&dev_priv->uncore);
2997
2998         intel_runtime_pm_enable_interrupts(dev_priv);
2999
3000         intel_uc_resume(dev_priv);
3001
3002         /*
3003          * No point of rolling back things in case of an error, as the best
3004          * we can do is to hope that things will still work (and disable RPM).
3005          */
3006         i915_gem_init_swizzling(dev_priv);
3007         i915_gem_restore_fences(dev_priv);
3008
3009         /*
3010          * On VLV/CHV display interrupts are part of the display
3011          * power well, so hpd is reinitialized from there. For
3012          * everyone else do it here.
3013          */
3014         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
3015                 intel_hpd_init(dev_priv);
3016
3017         intel_enable_ipc(dev_priv);
3018
3019         enable_rpm_wakeref_asserts(dev_priv);
3020
3021         if (ret)
3022                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
3023         else
3024                 DRM_DEBUG_KMS("Device resumed\n");
3025
3026         return ret;
3027 }
3028
3029 const struct dev_pm_ops i915_pm_ops = {
3030         /*
3031          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
3032          * PMSG_RESUME]
3033          */
3034         .prepare = i915_pm_prepare,
3035         .suspend = i915_pm_suspend,
3036         .suspend_late = i915_pm_suspend_late,
3037         .resume_early = i915_pm_resume_early,
3038         .resume = i915_pm_resume,
3039
3040         /*
3041          * S4 event handlers
3042          * @freeze, @freeze_late    : called (1) before creating the
3043          *                            hibernation image [PMSG_FREEZE] and
3044          *                            (2) after rebooting, before restoring
3045          *                            the image [PMSG_QUIESCE]
3046          * @thaw, @thaw_early       : called (1) after creating the hibernation
3047          *                            image, before writing it [PMSG_THAW]
3048          *                            and (2) after failing to create or
3049          *                            restore the image [PMSG_RECOVER]
3050          * @poweroff, @poweroff_late: called after writing the hibernation
3051          *                            image, before rebooting [PMSG_HIBERNATE]
3052          * @restore, @restore_early : called after rebooting and restoring the
3053          *                            hibernation image [PMSG_RESTORE]
3054          */
3055         .freeze = i915_pm_freeze,
3056         .freeze_late = i915_pm_freeze_late,
3057         .thaw_early = i915_pm_thaw_early,
3058         .thaw = i915_pm_thaw,
3059         .poweroff = i915_pm_suspend,
3060         .poweroff_late = i915_pm_poweroff_late,
3061         .restore_early = i915_pm_restore_early,
3062         .restore = i915_pm_restore,
3063
3064         /* S0ix (via runtime suspend) event handlers */
3065         .runtime_suspend = intel_runtime_suspend,
3066         .runtime_resume = intel_runtime_resume,
3067 };
3068
3069 static const struct vm_operations_struct i915_gem_vm_ops = {
3070         .fault = i915_gem_fault,
3071         .open = drm_gem_vm_open,
3072         .close = drm_gem_vm_close,
3073 };
3074
3075 static const struct file_operations i915_driver_fops = {
3076         .owner = THIS_MODULE,
3077         .open = drm_open,
3078         .release = drm_release,
3079         .unlocked_ioctl = drm_ioctl,
3080         .mmap = drm_gem_mmap,
3081         .poll = drm_poll,
3082         .read = drm_read,
3083         .compat_ioctl = i915_compat_ioctl,
3084         .llseek = noop_llseek,
3085 };
3086
3087 static int
3088 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
3089                           struct drm_file *file)
3090 {
3091         return -ENODEV;
3092 }
3093
3094 static const struct drm_ioctl_desc i915_ioctls[] = {
3095         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3096         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
3097         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
3098         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
3099         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
3100         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
3101         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3102         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3103         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
3104         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
3105         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3106         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
3107         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3108         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3109         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
3110         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
3111         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3112         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3113         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
3114         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3115         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3116         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3117         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3118         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
3119         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
3120         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3121         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3122         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3123         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
3124         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
3125         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
3126         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
3127         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
3128         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
3129         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
3130         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
3131         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
3132         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
3133         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
3134         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3135         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3136         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3137         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3138         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3139         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3140         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3141         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3142         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3143         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3144         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3145         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3146         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3147         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3148         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3149         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3150         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3151 };
3152
3153 static struct drm_driver driver = {
3154         /* Don't use MTRRs here; the Xserver or userspace app should
3155          * deal with them for Intel hardware.
3156          */
3157         .driver_features =
3158             DRIVER_GEM | DRIVER_PRIME |
3159             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3160         .release = i915_driver_release,
3161         .open = i915_driver_open,
3162         .lastclose = i915_driver_lastclose,
3163         .postclose = i915_driver_postclose,
3164
3165         .gem_close_object = i915_gem_close_object,
3166         .gem_free_object_unlocked = i915_gem_free_object,
3167         .gem_vm_ops = &i915_gem_vm_ops,
3168
3169         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3170         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3171         .gem_prime_export = i915_gem_prime_export,
3172         .gem_prime_import = i915_gem_prime_import,
3173
3174         .dumb_create = i915_gem_dumb_create,
3175         .dumb_map_offset = i915_gem_mmap_gtt,
3176         .ioctls = i915_ioctls,
3177         .num_ioctls = ARRAY_SIZE(i915_ioctls),
3178         .fops = &i915_driver_fops,
3179         .name = DRIVER_NAME,
3180         .desc = DRIVER_DESC,
3181         .date = DRIVER_DATE,
3182         .major = DRIVER_MAJOR,
3183         .minor = DRIVER_MINOR,
3184         .patchlevel = DRIVER_PATCHLEVEL,
3185 };
3186
3187 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3188 #include "selftests/mock_drm.c"
3189 #endif