drivers/gpu/drm/i915/i915_driver.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/module.h>
  33 #include <linux/oom.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/slab.h>
  38 #include <linux/string_helpers.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_aperture.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_managed.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_bw.h"
  50 #include "display/intel_cdclk.h"
  51 #include "display/intel_display_types.h"
  52 #include "display/intel_dmc.h"
  53 #include "display/intel_dp.h"
  54 #include "display/intel_dpt.h"
  55 #include "display/intel_fbdev.h"
  56 #include "display/intel_hotplug.h"
  57 #include "display/intel_overlay.h"
  58 #include "display/intel_pch_refclk.h"
  59 #include "display/intel_pipe_crc.h"
  60 #include "display/intel_pps.h"
  61 #include "display/intel_sprite.h"
  62 #include "display/intel_vga.h"
  63 #include "display/skl_watermark.h"
  64
  65 #include "gem/i915_gem_context.h"
  66 #include "gem/i915_gem_create.h"
  67 #include "gem/i915_gem_dmabuf.h"
  68 #include "gem/i915_gem_ioctls.h"
  69 #include "gem/i915_gem_mman.h"
  70 #include "gem/i915_gem_pm.h"
  71 #include "gt/intel_gt.h"
  72 #include "gt/intel_gt_pm.h"
  73 #include "gt/intel_rc6.h"
  74
  75 #include "pxp/intel_pxp.h"
  76 #include "pxp/intel_pxp_debugfs.h"
  77 #include "pxp/intel_pxp_pm.h"
  78
  79 #include "soc/intel_dram.h"
  80 #include "soc/intel_gmch.h"
  81
  82 #include "i915_file_private.h"
  83 #include "i915_debugfs.h"
  84 #include "i915_driver.h"
  85 #include "i915_drm_client.h"
  86 #include "i915_drv.h"
  87 #include "i915_getparam.h"
  88 #include "i915_hwmon.h"
  89 #include "i915_ioc32.h"
  90 #include "i915_ioctl.h"
  91 #include "i915_irq.h"
  92 #include "i915_memcpy.h"
  93 #include "i915_perf.h"
  94 #include "i915_query.h"
  95 #include "i915_suspend.h"
  96 #include "i915_switcheroo.h"
  97 #include "i915_sysfs.h"
  98 #include "i915_utils.h"
  99 #include "i915_vgpu.h"
 100 #include "intel_gvt.h"
 101 #include "intel_memory_region.h"
 102 #include "intel_pci_config.h"
 103 #include "intel_pcode.h"
 104 #include "intel_pm.h"
 105 #include "intel_region_ttm.h"
 106 #include "vlv_suspend.h"
 107
 108 static const struct drm_driver i915_drm_driver;
 109
 110 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 111 {
 112         /*
 113          * The i915 workqueue is primarily used for batched retirement of
 114          * requests (and thus managing bo) once the task has been completed
 115          * by the GPU. i915_retire_requests() is called directly when we
 116          * need high-priority retirement, such as waiting for an explicit
 117          * bo.
 118          *
 119          * It is also used for periodic low-priority events, such as
 120          * idle-timers and recording error state.
 121          *
 122          * All tasks on the workqueue are expected to acquire the dev mutex
 123          * so there is no point in running more than one instance of the
 124          * workqueue at any time.  Use an ordered one.
 125          */
 126         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 127         if (dev_priv->wq == NULL)
 128                 goto out_err;
 129
 130         dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 131         if (dev_priv->display.hotplug.dp_wq == NULL)
 132                 goto out_free_wq;
 133
 134         return 0;
 135
 136 out_free_wq:
 137         destroy_workqueue(dev_priv->wq);
 138 out_err:
 139         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 140
 141         return -ENOMEM;
 142 }
 143
 144 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 145 {
 146         destroy_workqueue(dev_priv->display.hotplug.dp_wq);
 147         destroy_workqueue(dev_priv->wq);
 148 }
 149
 150 /*
 151  * We don't keep the workarounds for pre-production hardware, so we expect our
 152  * driver to fail on these machines in one way or another. A little warning on
 153  * dmesg may help both the user and the bug triagers.
 154  *
 155  * Our policy for removing pre-production workarounds is to keep the
 156  * current gen workarounds as a guide to the bring-up of the next gen
 157  * (workarounds have a habit of persisting!). Anything older than that
 158  * should be removed along with the complications they introduce.
 159  */
 160 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 161 {
 162         bool pre = false;
 163
 164         pre |= IS_HSW_EARLY_SDV(dev_priv);
 165         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 166         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 167         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 168         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 169         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 170         pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 171         pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 172
 173         if (pre) {
 174                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 175                           "It may not be fully functional.\n");
 176                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 177         }
 178 }
 179
 180 static void sanitize_gpu(struct drm_i915_private *i915)
 181 {
 182         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
 183                 struct intel_gt *gt;
 184                 unsigned int i;
 185
 186                 for_each_gt(gt, i915, i)
 187                         __intel_gt_reset(gt, ALL_ENGINES);
 188         }
 189 }
 190
 191 /**
 192  * i915_driver_early_probe - setup state not requiring device access
 193  * @dev_priv: device private
 194  *
 195  * Initialize everything that is a "SW-only" state, that is state not
 196  * requiring accessing the device or exposing the driver via kernel internal
 197  * or userspace interfaces. Example steps belonging here: lock initialization,
 198  * system memory allocation, setting up device specific attributes and
 199  * function hooks not requiring accessing the device.
 200  */
 201 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 202 {
 203         int ret = 0;
 204
 205         if (i915_inject_probe_failure(dev_priv))
 206                 return -ENODEV;
 207
 208         intel_device_info_runtime_init_early(dev_priv);
 209
 210         intel_step_init(dev_priv);
 211
 212         intel_uncore_mmio_debug_init_early(dev_priv);
 213
 214         spin_lock_init(&dev_priv->irq_lock);
 215         spin_lock_init(&dev_priv->gpu_error.lock);
 216         mutex_init(&dev_priv->display.backlight.lock);
 217
 218         mutex_init(&dev_priv->sb_lock);
 219         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 220
 221         mutex_init(&dev_priv->display.audio.mutex);
 222         mutex_init(&dev_priv->display.wm.wm_mutex);
 223         mutex_init(&dev_priv->display.pps.mutex);
 224         mutex_init(&dev_priv->display.hdcp.comp_mutex);
 225         spin_lock_init(&dev_priv->display.dkl.phy_lock);
 226
 227         i915_memcpy_init_early(dev_priv);
 228         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 229
 230         ret = i915_workqueues_init(dev_priv);
 231         if (ret < 0)
 232                 return ret;
 233
 234         ret = vlv_suspend_init(dev_priv);
 235         if (ret < 0)
 236                 goto err_workqueues;
 237
 238         ret = intel_region_ttm_device_init(dev_priv);
 239         if (ret)
 240                 goto err_ttm;
 241
 242         ret = intel_root_gt_init_early(dev_priv);
 243         if (ret < 0)
 244                 goto err_rootgt;
 245
 246         i915_drm_clients_init(&dev_priv->clients, dev_priv);
 247
 248         i915_gem_init_early(dev_priv);
 249
 250         /* This must be called before any calls to HAS_PCH_* */
 251         intel_detect_pch(dev_priv);
 252
 253         intel_irq_init(dev_priv);
 254         intel_init_display_hooks(dev_priv);
 255         intel_init_clock_gating_hooks(dev_priv);
 256
 257         intel_detect_preproduction_hw(dev_priv);
 258
 259         return 0;
 260
 261 err_rootgt:
 262         intel_region_ttm_device_fini(dev_priv);
 263 err_ttm:
 264         vlv_suspend_cleanup(dev_priv);
 265 err_workqueues:
 266         i915_workqueues_cleanup(dev_priv);
 267         return ret;
 268 }
 269
 270 /**
 271  * i915_driver_late_release - cleanup the setup done in
 272  *                             i915_driver_early_probe()
 273  * @dev_priv: device private
 274  */
 275 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 276 {
 277         intel_irq_fini(dev_priv);
 278         intel_power_domains_cleanup(dev_priv);
 279         i915_gem_cleanup_early(dev_priv);
 280         intel_gt_driver_late_release_all(dev_priv);
 281         i915_drm_clients_fini(&dev_priv->clients);
 282         intel_region_ttm_device_fini(dev_priv);
 283         vlv_suspend_cleanup(dev_priv);
 284         i915_workqueues_cleanup(dev_priv);
 285
 286         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 287         mutex_destroy(&dev_priv->sb_lock);
 288
 289         i915_params_free(&dev_priv->params);
 290 }
 291
 292 /**
 293  * i915_driver_mmio_probe - setup device MMIO
 294  * @dev_priv: device private
 295  *
 296  * Setup minimal device state necessary for MMIO accesses later in the
 297  * initialization sequence. The setup here should avoid any other device-wide
 298  * side effects or exposing the driver via kernel internal or user space
 299  * interfaces.
 300  */
 301 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 302 {
 303         struct intel_gt *gt;
 304         int ret, i;
 305
 306         if (i915_inject_probe_failure(dev_priv))
 307                 return -ENODEV;
 308
 309         ret = intel_gmch_bridge_setup(dev_priv);
 310         if (ret < 0)
 311                 return ret;
 312
 313         for_each_gt(gt, dev_priv, i) {
 314                 ret = intel_uncore_init_mmio(gt->uncore);
 315                 if (ret)
 316                         return ret;
 317
 318                 ret = drmm_add_action_or_reset(&dev_priv->drm,
 319                                                intel_uncore_fini_mmio,
 320                                                gt->uncore);
 321                 if (ret)
 322                         return ret;
 323         }
 324
 325         /* Try to make sure MCHBAR is enabled before poking at it */
 326         intel_gmch_bar_setup(dev_priv);
 327         intel_device_info_runtime_init(dev_priv);
 328
 329         for_each_gt(gt, dev_priv, i) {
 330                 ret = intel_gt_init_mmio(gt);
 331                 if (ret)
 332                         goto err_uncore;
 333         }
 334
 335         /* As early as possible, scrub existing GPU state before clobbering */
 336         sanitize_gpu(dev_priv);
 337
 338         return 0;
 339
 340 err_uncore:
 341         intel_gmch_bar_teardown(dev_priv);
 342
 343         return ret;
 344 }
 345
 346 /**
 347  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 348  * @dev_priv: device private
 349  */
 350 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 351 {
 352         intel_gmch_bar_teardown(dev_priv);
 353 }
 354
 355 /**
 356  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 357  * platform
 358  * @i915: valid i915 instance
 359  *
 360  * Set the dma max segment size, device and coherent masks.  The dma mask set
 361  * needs to occur before i915_ggtt_probe_hw.
 362  *
 363  * A couple of platforms have special needs.  Address them as well.
 364  *
 365  */
 366 static int i915_set_dma_info(struct drm_i915_private *i915)
 367 {
 368         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 369         int ret;
 370
 371         GEM_BUG_ON(!mask_size);
 372
 373         /*
 374          * We don't have a max segment size, so set it to the max so sg's
 375          * debugging layer doesn't complain
 376          */
 377         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 378
 379         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 380         if (ret)
 381                 goto mask_err;
 382
 383         /* overlay on gen2 is broken and can't address above 1G */
 384         if (GRAPHICS_VER(i915) == 2)
 385                 mask_size = 30;
 386
 387         /*
 388          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 389          * using 32bit addressing, overwriting memory if HWS is located
 390          * above 4GB.
 391          *
 392          * The documentation also mentions an issue with undefined
 393          * behaviour if any general state is accessed within a page above 4GB,
 394          * which also needs to be handled carefully.
 395          */
 396         if (IS_I965G(i915) || IS_I965GM(i915))
 397                 mask_size = 32;
 398
 399         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 400         if (ret)
 401                 goto mask_err;
 402
 403         return 0;
 404
 405 mask_err:
 406         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 407         return ret;
 408 }
 409
 410 static int i915_pcode_init(struct drm_i915_private *i915)
 411 {
 412         struct intel_gt *gt;
 413         int id, ret;
 414
 415         for_each_gt(gt, i915, id) {
 416                 ret = intel_pcode_init(gt->uncore);
 417                 if (ret) {
 418                         drm_err(&gt->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
 419                         return ret;
 420                 }
 421         }
 422
 423         return 0;
 424 }
 425
 426 /**
 427  * i915_driver_hw_probe - setup state requiring device access
 428  * @dev_priv: device private
 429  *
 430  * Setup state that requires accessing the device, but doesn't require
 431  * exposing the driver via kernel internal or userspace interfaces.
 432  */
 433 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 434 {
 435         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 436         struct pci_dev *root_pdev;
 437         int ret;
 438
 439         if (i915_inject_probe_failure(dev_priv))
 440                 return -ENODEV;
 441
 442         if (HAS_PPGTT(dev_priv)) {
 443                 if (intel_vgpu_active(dev_priv) &&
 444                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 445                         i915_report_error(dev_priv,
 446                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 447                         return -ENXIO;
 448                 }
 449         }
 450
 451         if (HAS_EXECLISTS(dev_priv)) {
 452                 /*
 453                  * Older GVT emulation depends upon intercepting CSB mmio,
 454                  * which we no longer use, preferring to use the HWSP cache
 455                  * instead.
 456                  */
 457                 if (intel_vgpu_active(dev_priv) &&
 458                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 459                         i915_report_error(dev_priv,
 460                                           "old vGPU host found, support for HWSP emulation required\n");
 461                         return -ENXIO;
 462                 }
 463         }
 464
 465         /* needs to be done before ggtt probe */
 466         intel_dram_edram_detect(dev_priv);
 467
 468         ret = i915_set_dma_info(dev_priv);
 469         if (ret)
 470                 return ret;
 471
 472         i915_perf_init(dev_priv);
 473
 474         ret = i915_ggtt_probe_hw(dev_priv);
 475         if (ret)
 476                 goto err_perf;
 477
 478         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 479         if (ret)
 480                 goto err_ggtt;
 481
 482         ret = i915_ggtt_init_hw(dev_priv);
 483         if (ret)
 484                 goto err_ggtt;
 485
 486         ret = intel_memory_regions_hw_probe(dev_priv);
 487         if (ret)
 488                 goto err_ggtt;
 489
 490         ret = intel_gt_tiles_init(dev_priv);
 491         if (ret)
 492                 goto err_mem_regions;
 493
 494         ret = i915_ggtt_enable_hw(dev_priv);
 495         if (ret) {
 496                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 497                 goto err_mem_regions;
 498         }
 499
 500         pci_set_master(pdev);
 501
 502         /* On the 945G/GM, the chipset reports the MSI capability on the
 503          * integrated graphics even though the support isn't actually there
 504          * according to the published specs.  It doesn't appear to function
 505          * correctly in testing on 945G.
 506          * This may be a side effect of MSI having been made available for PEG
 507          * and the registers being closely associated.
 508          *
 509          * According to chipset errata, on the 965GM, MSI interrupts may
 510          * be lost or delayed, and was defeatured. MSI interrupts seem to
 511          * get lost on g4x as well, and interrupt delivery seems to stay
 512          * properly dead afterwards. So we'll just disable them for all
 513          * pre-gen5 chipsets.
 514          *
 515          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 516          * interrupts even when in MSI mode. This results in spurious
 517          * interrupt warnings if the legacy irq no. is shared with another
 518          * device. The kernel then disables that interrupt source and so
 519          * prevents the other device from working properly.
 520          */
 521         if (GRAPHICS_VER(dev_priv) >= 5) {
 522                 if (pci_enable_msi(pdev) < 0)
 523                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 524         }
 525
 526         ret = intel_gvt_init(dev_priv);
 527         if (ret)
 528                 goto err_msi;
 529
 530         intel_opregion_setup(dev_priv);
 531
 532         ret = i915_pcode_init(dev_priv);
 533         if (ret)
 534                 goto err_msi;
 535
 536         /*
 537          * Fill the dram structure to get the system dram info. This will be
 538          * used for memory latency calculation.
 539          */
 540         intel_dram_detect(dev_priv);
 541
 542         intel_bw_init_hw(dev_priv);
 543
 544         /*
 545          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
 546          * This should be totally removed when we handle the pci states properly
 547          * on runtime PM and on s2idle cases.
 548          */
 549         root_pdev = pcie_find_root_port(pdev);
 550         if (root_pdev)
 551                 pci_d3cold_disable(root_pdev);
 552
 553         return 0;
 554
 555 err_msi:
 556         if (pdev->msi_enabled)
 557                 pci_disable_msi(pdev);
 558 err_mem_regions:
 559         intel_memory_regions_driver_release(dev_priv);
 560 err_ggtt:
 561         i915_ggtt_driver_release(dev_priv);
 562         i915_gem_drain_freed_objects(dev_priv);
 563         i915_ggtt_driver_late_release(dev_priv);
 564 err_perf:
 565         i915_perf_fini(dev_priv);
 566         return ret;
 567 }
 568
 569 /**
 570  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 571  * @dev_priv: device private
 572  */
 573 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 574 {
 575         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 576         struct pci_dev *root_pdev;
 577
 578         i915_perf_fini(dev_priv);
 579
 580         if (pdev->msi_enabled)
 581                 pci_disable_msi(pdev);
 582
 583         root_pdev = pcie_find_root_port(pdev);
 584         if (root_pdev)
 585                 pci_d3cold_enable(root_pdev);
 586 }
 587
 588 /**
 589  * i915_driver_register - register the driver with the rest of the system
 590  * @dev_priv: device private
 591  *
 592  * Perform any steps necessary to make the driver available via kernel
 593  * internal or userspace interfaces.
 594  */
 595 static void i915_driver_register(struct drm_i915_private *dev_priv)
 596 {
 597         struct intel_gt *gt;
 598         unsigned int i;
 599
 600         i915_gem_driver_register(dev_priv);
 601         i915_pmu_register(dev_priv);
 602
 603         intel_vgpu_register(dev_priv);
 604
 605         /* Reveal our presence to userspace */
 606         if (drm_dev_register(&dev_priv->drm, 0)) {
 607                 drm_err(&dev_priv->drm,
 608                         "Failed to register driver for userspace access!\n");
 609                 return;
 610         }
 611
 612         i915_debugfs_register(dev_priv);
 613         i915_setup_sysfs(dev_priv);
 614
 615         /* Depends on sysfs having been initialized */
 616         i915_perf_register(dev_priv);
 617
 618         for_each_gt(gt, dev_priv, i)
 619                 intel_gt_driver_register(gt);
 620
 621         intel_pxp_debugfs_register(dev_priv->pxp);
 622
 623         i915_hwmon_register(dev_priv);
 624
 625         intel_display_driver_register(dev_priv);
 626
 627         intel_power_domains_enable(dev_priv);
 628         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 629
 630         intel_register_dsm_handler();
 631
 632         if (i915_switcheroo_register(dev_priv))
 633                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 634 }
 635
 636 /**
 637  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 638  * @dev_priv: device private
 639  */
 640 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 641 {
 642         struct intel_gt *gt;
 643         unsigned int i;
 644
 645         i915_switcheroo_unregister(dev_priv);
 646
 647         intel_unregister_dsm_handler();
 648
 649         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 650         intel_power_domains_disable(dev_priv);
 651
 652         intel_display_driver_unregister(dev_priv);
 653
 654         intel_pxp_fini(dev_priv);
 655
 656         for_each_gt(gt, dev_priv, i)
 657                 intel_gt_driver_unregister(gt);
 658
 659         i915_hwmon_unregister(dev_priv);
 660
 661         i915_perf_unregister(dev_priv);
 662         i915_pmu_unregister(dev_priv);
 663
 664         i915_teardown_sysfs(dev_priv);
 665         drm_dev_unplug(&dev_priv->drm);
 666
 667         i915_gem_driver_unregister(dev_priv);
 668 }
 669
 670 void
 671 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
 672 {
 673         drm_printf(p, "iommu: %s\n",
 674                    str_enabled_disabled(i915_vtd_active(i915)));
 675 }
 676
 677 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 678 {
 679         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 680                 struct drm_printer p = drm_debug_printer("i915 device info:");
 681                 struct intel_gt *gt;
 682                 unsigned int i;
 683
 684                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 685                            INTEL_DEVID(dev_priv),
 686                            INTEL_REVID(dev_priv),
 687                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 688                            intel_subplatform(RUNTIME_INFO(dev_priv),
 689                                              INTEL_INFO(dev_priv)->platform),
 690                            GRAPHICS_VER(dev_priv));
 691
 692                 intel_device_info_print(INTEL_INFO(dev_priv),
 693                                         RUNTIME_INFO(dev_priv), &p);
 694                 i915_print_iommu_status(dev_priv, &p);
 695                 for_each_gt(gt, dev_priv, i)
 696                         intel_gt_info_print(&gt->info, &p);
 697         }
 698
 699         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 700                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 701         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 702                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 703         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 704                 drm_info(&dev_priv->drm,
 705                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 706 }
 707
 708 static struct drm_i915_private *
 709 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 710 {
 711         const struct intel_device_info *match_info =
 712                 (struct intel_device_info *)ent->driver_data;
 713         struct intel_device_info *device_info;
 714         struct intel_runtime_info *runtime;
 715         struct drm_i915_private *i915;
 716
 717         i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
 718                                   struct drm_i915_private, drm);
 719         if (IS_ERR(i915))
 720                 return i915;
 721
 722         pci_set_drvdata(pdev, i915);
 723
 724         /* Device parameters start as a copy of module parameters. */
 725         i915_params_copy(&i915->params, &i915_modparams);
 726
 727         /* Setup the write-once "constant" device info */
 728         device_info = mkwrite_device_info(i915);
 729         memcpy(device_info, match_info, sizeof(*device_info));
 730
 731         /* Initialize initial runtime info from static const data and pdev. */
 732         runtime = RUNTIME_INFO(i915);
 733         memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
 734         runtime->device_id = pdev->device;
 735
 736         return i915;
 737 }
 738
 739 /**
 740  * i915_driver_probe - setup chip and create an initial config
 741  * @pdev: PCI device
 742  * @ent: matching PCI ID entry
 743  *
 744  * The driver probe routine has to do several things:
 745  *   - drive output discovery via intel_modeset_init()
 746  *   - initialize the memory manager
 747  *   - allocate initial config memory
 748  *   - setup the DRM framebuffer with the allocated memory
 749  */
 750 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 751 {
 752         struct drm_i915_private *i915;
 753         int ret;
 754
 755         i915 = i915_driver_create(pdev, ent);
 756         if (IS_ERR(i915))
 757                 return PTR_ERR(i915);
 758
 759         ret = pci_enable_device(pdev);
 760         if (ret)
 761                 goto out_fini;
 762
 763         ret = i915_driver_early_probe(i915);
 764         if (ret < 0)
 765                 goto out_pci_disable;
 766
 767         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 768
 769         intel_vgpu_detect(i915);
 770
 771         ret = intel_gt_probe_all(i915);
 772         if (ret < 0)
 773                 goto out_runtime_pm_put;
 774
 775         ret = i915_driver_mmio_probe(i915);
 776         if (ret < 0)
 777                 goto out_tiles_cleanup;
 778
 779         ret = i915_driver_hw_probe(i915);
 780         if (ret < 0)
 781                 goto out_cleanup_mmio;
 782
 783         ret = intel_modeset_init_noirq(i915);
 784         if (ret < 0)
 785                 goto out_cleanup_hw;
 786
 787         ret = intel_irq_install(i915);
 788         if (ret)
 789                 goto out_cleanup_modeset;
 790
 791         ret = intel_modeset_init_nogem(i915);
 792         if (ret)
 793                 goto out_cleanup_irq;
 794
 795         ret = i915_gem_init(i915);
 796         if (ret)
 797                 goto out_cleanup_modeset2;
 798
 799         intel_pxp_init(i915);
 800
 801         ret = intel_modeset_init(i915);
 802         if (ret)
 803                 goto out_cleanup_gem;
 804
 805         i915_driver_register(i915);
 806
 807         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 808
 809         i915_welcome_messages(i915);
 810
 811         i915->do_release = true;
 812
 813         return 0;
 814
 815 out_cleanup_gem:
 816         i915_gem_suspend(i915);
 817         i915_gem_driver_remove(i915);
 818         i915_gem_driver_release(i915);
 819 out_cleanup_modeset2:
 820         /* FIXME clean up the error path */
 821         intel_modeset_driver_remove(i915);
 822         intel_irq_uninstall(i915);
 823         intel_modeset_driver_remove_noirq(i915);
 824         goto out_cleanup_modeset;
 825 out_cleanup_irq:
 826         intel_irq_uninstall(i915);
 827 out_cleanup_modeset:
 828         intel_modeset_driver_remove_nogem(i915);
 829 out_cleanup_hw:
 830         i915_driver_hw_remove(i915);
 831         intel_memory_regions_driver_release(i915);
 832         i915_ggtt_driver_release(i915);
 833         i915_gem_drain_freed_objects(i915);
 834         i915_ggtt_driver_late_release(i915);
 835 out_cleanup_mmio:
 836         i915_driver_mmio_release(i915);
 837 out_tiles_cleanup:
 838         intel_gt_release_all(i915);
 839 out_runtime_pm_put:
 840         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 841         i915_driver_late_release(i915);
 842 out_pci_disable:
 843         pci_disable_device(pdev);
 844 out_fini:
 845         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 846         return ret;
 847 }
 848
 849 void i915_driver_remove(struct drm_i915_private *i915)
 850 {
 851         intel_wakeref_t wakeref;
 852
 853         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 854
 855         i915_driver_unregister(i915);
 856
 857         /* Flush any external code that still may be under the RCU lock */
 858         synchronize_rcu();
 859
 860         i915_gem_suspend(i915);
 861
 862         intel_gvt_driver_remove(i915);
 863
 864         intel_modeset_driver_remove(i915);
 865
 866         intel_irq_uninstall(i915);
 867
 868         intel_modeset_driver_remove_noirq(i915);
 869
 870         i915_reset_error_state(i915);
 871         i915_gem_driver_remove(i915);
 872
 873         intel_modeset_driver_remove_nogem(i915);
 874
 875         i915_driver_hw_remove(i915);
 876
 877         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 878 }
 879
 880 static void i915_driver_release(struct drm_device *dev)
 881 {
 882         struct drm_i915_private *dev_priv = to_i915(dev);
 883         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 884         intel_wakeref_t wakeref;
 885
 886         if (!dev_priv->do_release)
 887                 return;
 888
 889         wakeref = intel_runtime_pm_get(rpm);
 890
 891         i915_gem_driver_release(dev_priv);
 892
 893         intel_memory_regions_driver_release(dev_priv);
 894         i915_ggtt_driver_release(dev_priv);
 895         i915_gem_drain_freed_objects(dev_priv);
 896         i915_ggtt_driver_late_release(dev_priv);
 897
 898         i915_driver_mmio_release(dev_priv);
 899
 900         intel_runtime_pm_put(rpm, wakeref);
 901
 902         intel_runtime_pm_driver_release(rpm);
 903
 904         i915_driver_late_release(dev_priv);
 905 }
 906
 907 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 908 {
 909         struct drm_i915_private *i915 = to_i915(dev);
 910         int ret;
 911
 912         ret = i915_gem_open(i915, file);
 913         if (ret)
 914                 return ret;
 915
 916         return 0;
 917 }
 918
 919 /**
 920  * i915_driver_lastclose - clean up after all DRM clients have exited
 921  * @dev: DRM device
 922  *
 923  * Take care of cleaning up after all DRM clients have exited.  In the
 924  * mode setting case, we want to restore the kernel's initial mode (just
 925  * in case the last client left us in a bad state).
 926  *
 927  * Additionally, in the non-mode setting case, we'll tear down the GTT
 928  * and DMA structures, since the kernel won't be using them, and clea
 929  * up any GEM state.
 930  */
 931 static void i915_driver_lastclose(struct drm_device *dev)
 932 {
 933         struct drm_i915_private *i915 = to_i915(dev);
 934
 935         intel_fbdev_restore_mode(i915);
 936
 937         vga_switcheroo_process_delayed_switch();
 938 }
 939
 940 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
 941 {
 942         struct drm_i915_file_private *file_priv = file->driver_priv;
 943
 944         i915_gem_context_close(file);
 945         i915_drm_client_put(file_priv->client);
 946
 947         kfree_rcu(file_priv, rcu);
 948
 949         /* Catch up with all the deferred frees from "this" client */
 950         i915_gem_flush_free_objects(to_i915(dev));
 951 }
 952
 953 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 954 {
 955         struct intel_encoder *encoder;
 956
 957         if (!HAS_DISPLAY(dev_priv))
 958                 return;
 959
 960         drm_modeset_lock_all(&dev_priv->drm);
 961         for_each_intel_encoder(&dev_priv->drm, encoder)
 962                 if (encoder->suspend)
 963                         encoder->suspend(encoder);
 964         drm_modeset_unlock_all(&dev_priv->drm);
 965 }
 966
 967 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
 968 {
 969         struct intel_encoder *encoder;
 970
 971         if (!HAS_DISPLAY(dev_priv))
 972                 return;
 973
 974         drm_modeset_lock_all(&dev_priv->drm);
 975         for_each_intel_encoder(&dev_priv->drm, encoder)
 976                 if (encoder->shutdown)
 977                         encoder->shutdown(encoder);
 978         drm_modeset_unlock_all(&dev_priv->drm);
 979 }
 980
 981 void i915_driver_shutdown(struct drm_i915_private *i915)
 982 {
 983         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 984         intel_runtime_pm_disable(&i915->runtime_pm);
 985         intel_power_domains_disable(i915);
 986
 987         if (HAS_DISPLAY(i915)) {
 988                 drm_kms_helper_poll_disable(&i915->drm);
 989
 990                 drm_atomic_helper_shutdown(&i915->drm);
 991         }
 992
 993         intel_dp_mst_suspend(i915);
 994
 995         intel_runtime_pm_disable_interrupts(i915);
 996         intel_hpd_cancel_work(i915);
 997
 998         intel_suspend_encoders(i915);
 999         intel_shutdown_encoders(i915);
1000
1001         intel_dmc_suspend(i915);
1002
1003         i915_gem_suspend(i915);
1004
1005         /*
1006          * The only requirement is to reboot with display DC states disabled,
1007          * for now leaving all display power wells in the INIT power domain
1008          * enabled.
1009          *
1010          * TODO:
1011          * - unify the pci_driver::shutdown sequence here with the
1012          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1013          * - unify the driver remove and system/runtime suspend sequences with
1014          *   the above unified shutdown/poweroff sequence.
1015          */
1016         intel_power_domains_driver_remove(i915);
1017         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1018
1019         intel_runtime_pm_driver_release(&i915->runtime_pm);
1020 }
1021
1022 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1023 {
1024 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1025         if (acpi_target_system_state() < ACPI_STATE_S3)
1026                 return true;
1027 #endif
1028         return false;
1029 }
1030
1031 static void i915_drm_complete(struct drm_device *dev)
1032 {
1033         struct drm_i915_private *i915 = to_i915(dev);
1034
1035         intel_pxp_resume_complete(i915->pxp);
1036 }
1037
1038 static int i915_drm_prepare(struct drm_device *dev)
1039 {
1040         struct drm_i915_private *i915 = to_i915(dev);
1041
1042         intel_pxp_suspend_prepare(i915->pxp);
1043
1044         /*
1045          * NB intel_display_suspend() may issue new requests after we've
1046          * ostensibly marked the GPU as ready-to-sleep here. We need to
1047          * split out that work and pull it forward so that after point,
1048          * the GPU is not woken again.
1049          */
1050         return i915_gem_backup_suspend(i915);
1051 }
1052
1053 static int i915_drm_suspend(struct drm_device *dev)
1054 {
1055         struct drm_i915_private *dev_priv = to_i915(dev);
1056         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1057         pci_power_t opregion_target_state;
1058
1059         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1060
1061         /* We do a lot of poking in a lot of registers, make sure they work
1062          * properly. */
1063         intel_power_domains_disable(dev_priv);
1064         if (HAS_DISPLAY(dev_priv))
1065                 drm_kms_helper_poll_disable(dev);
1066
1067         pci_save_state(pdev);
1068
1069         intel_display_suspend(dev);
1070
1071         intel_dp_mst_suspend(dev_priv);
1072
1073         intel_runtime_pm_disable_interrupts(dev_priv);
1074         intel_hpd_cancel_work(dev_priv);
1075
1076         intel_suspend_encoders(dev_priv);
1077
1078         /* Must be called before GGTT is suspended. */
1079         intel_dpt_suspend(dev_priv);
1080         i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1081
1082         i915_save_display(dev_priv);
1083
1084         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1085         intel_opregion_suspend(dev_priv, opregion_target_state);
1086
1087         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1088
1089         dev_priv->suspend_count++;
1090
1091         intel_dmc_suspend(dev_priv);
1092
1093         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1094
1095         i915_gem_drain_freed_objects(dev_priv);
1096
1097         return 0;
1098 }
1099
1100 static enum i915_drm_suspend_mode
1101 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1102 {
1103         if (hibernate)
1104                 return I915_DRM_SUSPEND_HIBERNATE;
1105
1106         if (suspend_to_idle(dev_priv))
1107                 return I915_DRM_SUSPEND_IDLE;
1108
1109         return I915_DRM_SUSPEND_MEM;
1110 }
1111
1112 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1113 {
1114         struct drm_i915_private *dev_priv = to_i915(dev);
1115         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1116         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1117         struct intel_gt *gt;
1118         int ret, i;
1119
1120         disable_rpm_wakeref_asserts(rpm);
1121
1122         intel_pxp_suspend(dev_priv->pxp);
1123
1124         i915_gem_suspend_late(dev_priv);
1125
1126         for_each_gt(gt, dev_priv, i)
1127                 intel_uncore_suspend(gt->uncore);
1128
1129         intel_power_domains_suspend(dev_priv,
1130                                     get_suspend_mode(dev_priv, hibernation));
1131
1132         intel_display_power_suspend_late(dev_priv);
1133
1134         ret = vlv_suspend_complete(dev_priv);
1135         if (ret) {
1136                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1137                 intel_power_domains_resume(dev_priv);
1138
1139                 goto out;
1140         }
1141
1142         pci_disable_device(pdev);
1143         /*
1144          * During hibernation on some platforms the BIOS may try to access
1145          * the device even though it's already in D3 and hang the machine. So
1146          * leave the device in D0 on those platforms and hope the BIOS will
1147          * power down the device properly. The issue was seen on multiple old
1148          * GENs with different BIOS vendors, so having an explicit blacklist
1149          * is inpractical; apply the workaround on everything pre GEN6. The
1150          * platforms where the issue was seen:
1151          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1152          * Fujitsu FSC S7110
1153          * Acer Aspire 1830T
1154          */
1155         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1156                 pci_set_power_state(pdev, PCI_D3hot);
1157
1158 out:
1159         enable_rpm_wakeref_asserts(rpm);
1160         if (!dev_priv->uncore.user_forcewake_count)
1161                 intel_runtime_pm_driver_release(rpm);
1162
1163         return ret;
1164 }
1165
1166 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1167                                    pm_message_t state)
1168 {
1169         int error;
1170
1171         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1172                              state.event != PM_EVENT_FREEZE))
1173                 return -EINVAL;
1174
1175         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1176                 return 0;
1177
1178         error = i915_drm_suspend(&i915->drm);
1179         if (error)
1180                 return error;
1181
1182         return i915_drm_suspend_late(&i915->drm, false);
1183 }
1184
1185 static int i915_drm_resume(struct drm_device *dev)
1186 {
1187         struct drm_i915_private *dev_priv = to_i915(dev);
1188         struct intel_gt *gt;
1189         int ret, i;
1190
1191         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1192
1193         ret = i915_pcode_init(dev_priv);
1194         if (ret)
1195                 return ret;
1196
1197         sanitize_gpu(dev_priv);
1198
1199         ret = i915_ggtt_enable_hw(dev_priv);
1200         if (ret)
1201                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1202
1203         i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1204
1205         for_each_gt(gt, dev_priv, i)
1206                 if (GRAPHICS_VER(gt->i915) >= 8)
1207                         setup_private_pat(gt);
1208
1209         /* Must be called after GGTT is resumed. */
1210         intel_dpt_resume(dev_priv);
1211
1212         intel_dmc_resume(dev_priv);
1213
1214         i915_restore_display(dev_priv);
1215         intel_pps_unlock_regs_wa(dev_priv);
1216
1217         intel_init_pch_refclk(dev_priv);
1218
1219         /*
1220          * Interrupts have to be enabled before any batches are run. If not the
1221          * GPU will hang. i915_gem_init_hw() will initiate batches to
1222          * update/restore the context.
1223          *
1224          * drm_mode_config_reset() needs AUX interrupts.
1225          *
1226          * Modeset enabling in intel_modeset_init_hw() also needs working
1227          * interrupts.
1228          */
1229         intel_runtime_pm_enable_interrupts(dev_priv);
1230
1231         if (HAS_DISPLAY(dev_priv))
1232                 drm_mode_config_reset(dev);
1233
1234         i915_gem_resume(dev_priv);
1235
1236         intel_modeset_init_hw(dev_priv);
1237         intel_init_clock_gating(dev_priv);
1238         intel_hpd_init(dev_priv);
1239
1240         /* MST sideband requires HPD interrupts enabled */
1241         intel_dp_mst_resume(dev_priv);
1242         intel_display_resume(dev);
1243
1244         intel_hpd_poll_disable(dev_priv);
1245         if (HAS_DISPLAY(dev_priv))
1246                 drm_kms_helper_poll_enable(dev);
1247
1248         intel_opregion_resume(dev_priv);
1249
1250         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1251
1252         intel_power_domains_enable(dev_priv);
1253
1254         intel_gvt_resume(dev_priv);
1255
1256         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1257
1258         return 0;
1259 }
1260
1261 static int i915_drm_resume_early(struct drm_device *dev)
1262 {
1263         struct drm_i915_private *dev_priv = to_i915(dev);
1264         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1265         struct intel_gt *gt;
1266         int ret, i;
1267
1268         /*
1269          * We have a resume ordering issue with the snd-hda driver also
1270          * requiring our device to be power up. Due to the lack of a
1271          * parent/child relationship we currently solve this with an early
1272          * resume hook.
1273          *
1274          * FIXME: This should be solved with a special hdmi sink device or
1275          * similar so that power domains can be employed.
1276          */
1277
1278         /*
1279          * Note that we need to set the power state explicitly, since we
1280          * powered off the device during freeze and the PCI core won't power
1281          * it back up for us during thaw. Powering off the device during
1282          * freeze is not a hard requirement though, and during the
1283          * suspend/resume phases the PCI core makes sure we get here with the
1284          * device powered on. So in case we change our freeze logic and keep
1285          * the device powered we can also remove the following set power state
1286          * call.
1287          */
1288         ret = pci_set_power_state(pdev, PCI_D0);
1289         if (ret) {
1290                 drm_err(&dev_priv->drm,
1291                         "failed to set PCI D0 power state (%d)\n", ret);
1292                 return ret;
1293         }
1294
1295         /*
1296          * Note that pci_enable_device() first enables any parent bridge
1297          * device and only then sets the power state for this device. The
1298          * bridge enabling is a nop though, since bridge devices are resumed
1299          * first. The order of enabling power and enabling the device is
1300          * imposed by the PCI core as described above, so here we preserve the
1301          * same order for the freeze/thaw phases.
1302          *
1303          * TODO: eventually we should remove pci_disable_device() /
1304          * pci_enable_enable_device() from suspend/resume. Due to how they
1305          * depend on the device enable refcount we can't anyway depend on them
1306          * disabling/enabling the device.
1307          */
1308         if (pci_enable_device(pdev))
1309                 return -EIO;
1310
1311         pci_set_master(pdev);
1312
1313         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1314
1315         ret = vlv_resume_prepare(dev_priv, false);
1316         if (ret)
1317                 drm_err(&dev_priv->drm,
1318                         "Resume prepare failed: %d, continuing anyway\n", ret);
1319
1320         for_each_gt(gt, dev_priv, i) {
1321                 intel_uncore_resume_early(gt->uncore);
1322                 intel_gt_check_and_clear_faults(gt);
1323         }
1324
1325         intel_display_power_resume_early(dev_priv);
1326
1327         intel_power_domains_resume(dev_priv);
1328
1329         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1330
1331         return ret;
1332 }
1333
1334 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1335 {
1336         int ret;
1337
1338         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1339                 return 0;
1340
1341         ret = i915_drm_resume_early(&i915->drm);
1342         if (ret)
1343                 return ret;
1344
1345         return i915_drm_resume(&i915->drm);
1346 }
1347
1348 static int i915_pm_prepare(struct device *kdev)
1349 {
1350         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1351
1352         if (!i915) {
1353                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1354                 return -ENODEV;
1355         }
1356
1357         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1358                 return 0;
1359
1360         return i915_drm_prepare(&i915->drm);
1361 }
1362
1363 static int i915_pm_suspend(struct device *kdev)
1364 {
1365         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1366
1367         if (!i915) {
1368                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1369                 return -ENODEV;
1370         }
1371
1372         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1373                 return 0;
1374
1375         return i915_drm_suspend(&i915->drm);
1376 }
1377
1378 static int i915_pm_suspend_late(struct device *kdev)
1379 {
1380         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1381
1382         /*
1383          * We have a suspend ordering issue with the snd-hda driver also
1384          * requiring our device to be power up. Due to the lack of a
1385          * parent/child relationship we currently solve this with an late
1386          * suspend hook.
1387          *
1388          * FIXME: This should be solved with a special hdmi sink device or
1389          * similar so that power domains can be employed.
1390          */
1391         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1392                 return 0;
1393
1394         return i915_drm_suspend_late(&i915->drm, false);
1395 }
1396
1397 static int i915_pm_poweroff_late(struct device *kdev)
1398 {
1399         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1400
1401         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1402                 return 0;
1403
1404         return i915_drm_suspend_late(&i915->drm, true);
1405 }
1406
1407 static int i915_pm_resume_early(struct device *kdev)
1408 {
1409         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1410
1411         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1412                 return 0;
1413
1414         return i915_drm_resume_early(&i915->drm);
1415 }
1416
1417 static int i915_pm_resume(struct device *kdev)
1418 {
1419         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1420
1421         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1422                 return 0;
1423
1424         return i915_drm_resume(&i915->drm);
1425 }
1426
1427 static void i915_pm_complete(struct device *kdev)
1428 {
1429         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1430
1431         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1432                 return;
1433
1434         i915_drm_complete(&i915->drm);
1435 }
1436
1437 /* freeze: before creating the hibernation_image */
1438 static int i915_pm_freeze(struct device *kdev)
1439 {
1440         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1441         int ret;
1442
1443         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1444                 ret = i915_drm_suspend(&i915->drm);
1445                 if (ret)
1446                         return ret;
1447         }
1448
1449         ret = i915_gem_freeze(i915);
1450         if (ret)
1451                 return ret;
1452
1453         return 0;
1454 }
1455
1456 static int i915_pm_freeze_late(struct device *kdev)
1457 {
1458         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1459         int ret;
1460
1461         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1462                 ret = i915_drm_suspend_late(&i915->drm, true);
1463                 if (ret)
1464                         return ret;
1465         }
1466
1467         ret = i915_gem_freeze_late(i915);
1468         if (ret)
1469                 return ret;
1470
1471         return 0;
1472 }
1473
1474 /* thaw: called after creating the hibernation image, but before turning off. */
1475 static int i915_pm_thaw_early(struct device *kdev)
1476 {
1477         return i915_pm_resume_early(kdev);
1478 }
1479
1480 static int i915_pm_thaw(struct device *kdev)
1481 {
1482         return i915_pm_resume(kdev);
1483 }
1484
1485 /* restore: called after loading the hibernation image. */
1486 static int i915_pm_restore_early(struct device *kdev)
1487 {
1488         return i915_pm_resume_early(kdev);
1489 }
1490
1491 static int i915_pm_restore(struct device *kdev)
1492 {
1493         return i915_pm_resume(kdev);
1494 }
1495
1496 static int intel_runtime_suspend(struct device *kdev)
1497 {
1498         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1499         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1500         struct intel_gt *gt;
1501         int ret, i;
1502
1503         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1504                 return -ENODEV;
1505
1506         drm_dbg(&dev_priv->drm, "Suspending device\n");
1507
1508         disable_rpm_wakeref_asserts(rpm);
1509
1510         /*
1511          * We are safe here against re-faults, since the fault handler takes
1512          * an RPM reference.
1513          */
1514         i915_gem_runtime_suspend(dev_priv);
1515
1516         intel_pxp_runtime_suspend(dev_priv->pxp);
1517
1518         for_each_gt(gt, dev_priv, i)
1519                 intel_gt_runtime_suspend(gt);
1520
1521         intel_runtime_pm_disable_interrupts(dev_priv);
1522
1523         for_each_gt(gt, dev_priv, i)
1524                 intel_uncore_suspend(gt->uncore);
1525
1526         intel_display_power_suspend(dev_priv);
1527
1528         ret = vlv_suspend_complete(dev_priv);
1529         if (ret) {
1530                 drm_err(&dev_priv->drm,
1531                         "Runtime suspend failed, disabling it (%d)\n", ret);
1532                 intel_uncore_runtime_resume(&dev_priv->uncore);
1533
1534                 intel_runtime_pm_enable_interrupts(dev_priv);
1535
1536                 for_each_gt(gt, dev_priv, i)
1537                         intel_gt_runtime_resume(gt);
1538
1539                 enable_rpm_wakeref_asserts(rpm);
1540
1541                 return ret;
1542         }
1543
1544         enable_rpm_wakeref_asserts(rpm);
1545         intel_runtime_pm_driver_release(rpm);
1546
1547         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1548                 drm_err(&dev_priv->drm,
1549                         "Unclaimed access detected prior to suspending\n");
1550
1551         rpm->suspended = true;
1552
1553         /*
1554          * FIXME: We really should find a document that references the arguments
1555          * used below!
1556          */
1557         if (IS_BROADWELL(dev_priv)) {
1558                 /*
1559                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1560                  * being detected, and the call we do at intel_runtime_resume()
1561                  * won't be able to restore them. Since PCI_D3hot matches the
1562                  * actual specification and appears to be working, use it.
1563                  */
1564                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1565         } else {
1566                 /*
1567                  * current versions of firmware which depend on this opregion
1568                  * notification have repurposed the D1 definition to mean
1569                  * "runtime suspended" vs. what you would normally expect (D3)
1570                  * to distinguish it from notifications that might be sent via
1571                  * the suspend path.
1572                  */
1573                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1574         }
1575
1576         assert_forcewakes_inactive(&dev_priv->uncore);
1577
1578         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1579                 intel_hpd_poll_enable(dev_priv);
1580
1581         drm_dbg(&dev_priv->drm, "Device suspended\n");
1582         return 0;
1583 }
1584
1585 static int intel_runtime_resume(struct device *kdev)
1586 {
1587         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1588         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1589         struct intel_gt *gt;
1590         int ret, i;
1591
1592         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1593                 return -ENODEV;
1594
1595         drm_dbg(&dev_priv->drm, "Resuming device\n");
1596
1597         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1598         disable_rpm_wakeref_asserts(rpm);
1599
1600         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1601         rpm->suspended = false;
1602         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1603                 drm_dbg(&dev_priv->drm,
1604                         "Unclaimed access during suspend, bios?\n");
1605
1606         intel_display_power_resume(dev_priv);
1607
1608         ret = vlv_resume_prepare(dev_priv, true);
1609
1610         for_each_gt(gt, dev_priv, i)
1611                 intel_uncore_runtime_resume(gt->uncore);
1612
1613         intel_runtime_pm_enable_interrupts(dev_priv);
1614
1615         /*
1616          * No point of rolling back things in case of an error, as the best
1617          * we can do is to hope that things will still work (and disable RPM).
1618          */
1619         for_each_gt(gt, dev_priv, i)
1620                 intel_gt_runtime_resume(gt);
1621
1622         intel_pxp_runtime_resume(dev_priv->pxp);
1623
1624         /*
1625          * On VLV/CHV display interrupts are part of the display
1626          * power well, so hpd is reinitialized from there. For
1627          * everyone else do it here.
1628          */
1629         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1630                 intel_hpd_init(dev_priv);
1631                 intel_hpd_poll_disable(dev_priv);
1632         }
1633
1634         skl_watermark_ipc_update(dev_priv);
1635
1636         enable_rpm_wakeref_asserts(rpm);
1637
1638         if (ret)
1639                 drm_err(&dev_priv->drm,
1640                         "Runtime resume failed, disabling it (%d)\n", ret);
1641         else
1642                 drm_dbg(&dev_priv->drm, "Device resumed\n");
1643
1644         return ret;
1645 }
1646
1647 const struct dev_pm_ops i915_pm_ops = {
1648         /*
1649          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1650          * PMSG_RESUME]
1651          */
1652         .prepare = i915_pm_prepare,
1653         .suspend = i915_pm_suspend,
1654         .suspend_late = i915_pm_suspend_late,
1655         .resume_early = i915_pm_resume_early,
1656         .resume = i915_pm_resume,
1657         .complete = i915_pm_complete,
1658
1659         /*
1660          * S4 event handlers
1661          * @freeze, @freeze_late    : called (1) before creating the
1662          *                            hibernation image [PMSG_FREEZE] and
1663          *                            (2) after rebooting, before restoring
1664          *                            the image [PMSG_QUIESCE]
1665          * @thaw, @thaw_early       : called (1) after creating the hibernation
1666          *                            image, before writing it [PMSG_THAW]
1667          *                            and (2) after failing to create or
1668          *                            restore the image [PMSG_RECOVER]
1669          * @poweroff, @poweroff_late: called after writing the hibernation
1670          *                            image, before rebooting [PMSG_HIBERNATE]
1671          * @restore, @restore_early : called after rebooting and restoring the
1672          *                            hibernation image [PMSG_RESTORE]
1673          */
1674         .freeze = i915_pm_freeze,
1675         .freeze_late = i915_pm_freeze_late,
1676         .thaw_early = i915_pm_thaw_early,
1677         .thaw = i915_pm_thaw,
1678         .poweroff = i915_pm_suspend,
1679         .poweroff_late = i915_pm_poweroff_late,
1680         .restore_early = i915_pm_restore_early,
1681         .restore = i915_pm_restore,
1682
1683         /* S0ix (via runtime suspend) event handlers */
1684         .runtime_suspend = intel_runtime_suspend,
1685         .runtime_resume = intel_runtime_resume,
1686 };
1687
1688 static const struct file_operations i915_driver_fops = {
1689         .owner = THIS_MODULE,
1690         .open = drm_open,
1691         .release = drm_release_noglobal,
1692         .unlocked_ioctl = drm_ioctl,
1693         .mmap = i915_gem_mmap,
1694         .poll = drm_poll,
1695         .read = drm_read,
1696         .compat_ioctl = i915_ioc32_compat_ioctl,
1697         .llseek = noop_llseek,
1698 #ifdef CONFIG_PROC_FS
1699         .show_fdinfo = i915_drm_client_fdinfo,
1700 #endif
1701 };
1702
1703 static int
1704 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1705                           struct drm_file *file)
1706 {
1707         return -ENODEV;
1708 }
1709
1710 static const struct drm_ioctl_desc i915_ioctls[] = {
1711         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1712         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1713         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1714         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1715         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1716         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1717         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1718         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1719         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1720         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1721         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1722         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1723         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1724         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1725         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1726         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1727         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1728         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1729         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1730         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1731         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1732         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1733         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1734         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1735         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1736         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1738         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1739         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1740         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1741         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1742         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1743         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1744         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1745         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1746         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1747         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1748         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1749         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1750         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1751         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1752         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1753         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1754         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1755         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1756         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1757         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1758         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1759         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1760         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1761         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1762         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1763         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1764         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1765         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1766         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1767         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1768         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1769         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1770 };
1771
1772 /*
1773  * Interface history:
1774  *
1775  * 1.1: Original.
1776  * 1.2: Add Power Management
1777  * 1.3: Add vblank support
1778  * 1.4: Fix cmdbuffer path, add heap destroy
1779  * 1.5: Add vblank pipe configuration
1780  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1781  *      - Support vertical blank on secondary display pipe
1782  */
1783 #define DRIVER_MAJOR            1
1784 #define DRIVER_MINOR            6
1785 #define DRIVER_PATCHLEVEL       0
1786
1787 static const struct drm_driver i915_drm_driver = {
1788         /* Don't use MTRRs here; the Xserver or userspace app should
1789          * deal with them for Intel hardware.
1790          */
1791         .driver_features =
1792             DRIVER_GEM |
1793             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1794             DRIVER_SYNCOBJ_TIMELINE,
1795         .release = i915_driver_release,
1796         .open = i915_driver_open,
1797         .lastclose = i915_driver_lastclose,
1798         .postclose = i915_driver_postclose,
1799
1800         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1801         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1802         .gem_prime_import = i915_gem_prime_import,
1803
1804         .dumb_create = i915_gem_dumb_create,
1805         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1806
1807         .ioctls = i915_ioctls,
1808         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1809         .fops = &i915_driver_fops,
1810         .name = DRIVER_NAME,
1811         .desc = DRIVER_DESC,
1812         .date = DRIVER_DATE,
1813         .major = DRIVER_MAJOR,
1814         .minor = DRIVER_MINOR,
1815         .patchlevel = DRIVER_PATCHLEVEL,
1816 };