1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/module.h>
33 #include <linux/oom.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/string_helpers.h>
40 #include <linux/vga_switcheroo.h>
43 #include <drm/drm_aperture.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_ioctl.h>
46 #include <drm/drm_managed.h>
47 #include <drm/drm_probe_helper.h>
49 #include "display/intel_acpi.h"
50 #include "display/intel_bw.h"
51 #include "display/intel_cdclk.h"
52 #include "display/intel_display_types.h"
53 #include "display/intel_dmc.h"
54 #include "display/intel_dp.h"
55 #include "display/intel_dpt.h"
56 #include "display/intel_fbdev.h"
57 #include "display/intel_hotplug.h"
58 #include "display/intel_overlay.h"
59 #include "display/intel_pch_refclk.h"
60 #include "display/intel_pipe_crc.h"
61 #include "display/intel_pps.h"
62 #include "display/intel_sprite.h"
63 #include "display/intel_vga.h"
64 #include "display/skl_watermark.h"
66 #include "gem/i915_gem_context.h"
67 #include "gem/i915_gem_create.h"
68 #include "gem/i915_gem_dmabuf.h"
69 #include "gem/i915_gem_ioctls.h"
70 #include "gem/i915_gem_mman.h"
71 #include "gem/i915_gem_pm.h"
72 #include "gt/intel_gt.h"
73 #include "gt/intel_gt_pm.h"
74 #include "gt/intel_rc6.h"
76 #include "pxp/intel_pxp_pm.h"
78 #include "i915_file_private.h"
79 #include "i915_debugfs.h"
80 #include "i915_driver.h"
81 #include "i915_drm_client.h"
83 #include "i915_getparam.h"
84 #include "i915_ioc32.h"
85 #include "i915_ioctl.h"
87 #include "i915_memcpy.h"
88 #include "i915_perf.h"
89 #include "i915_query.h"
90 #include "i915_suspend.h"
91 #include "i915_switcheroo.h"
92 #include "i915_sysfs.h"
93 #include "i915_utils.h"
94 #include "i915_vgpu.h"
95 #include "intel_dram.h"
96 #include "intel_gvt.h"
97 #include "intel_memory_region.h"
98 #include "intel_pci_config.h"
99 #include "intel_pcode.h"
100 #include "intel_pm.h"
101 #include "intel_region_ttm.h"
102 #include "vlv_suspend.h"
104 /* Intel Rapid Start Technology ACPI device name */
105 static const char irst_name[] = "INT3392";
107 static const struct drm_driver i915_drm_driver;
109 static void i915_release_bridge_dev(struct drm_device *dev,
115 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
117 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
119 dev_priv->bridge_dev =
120 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
121 if (!dev_priv->bridge_dev) {
122 drm_err(&dev_priv->drm, "bridge device not found\n");
126 return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev,
127 dev_priv->bridge_dev);
130 /* Allocate space for the MCH regs if needed, return nonzero on error */
132 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
134 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
135 u32 temp_lo, temp_hi = 0;
139 if (GRAPHICS_VER(dev_priv) >= 4)
140 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
141 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
142 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
144 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
147 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
151 /* Get some space for it */
152 dev_priv->mch_res.name = "i915 MCHBAR";
153 dev_priv->mch_res.flags = IORESOURCE_MEM;
154 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
156 MCHBAR_SIZE, MCHBAR_SIZE,
158 0, pcibios_align_resource,
159 dev_priv->bridge_dev);
161 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
162 dev_priv->mch_res.start = 0;
166 if (GRAPHICS_VER(dev_priv) >= 4)
167 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
168 upper_32_bits(dev_priv->mch_res.start));
170 pci_write_config_dword(dev_priv->bridge_dev, reg,
171 lower_32_bits(dev_priv->mch_res.start));
175 /* Setup MCHBAR if possible, return true if we should disable it again */
177 intel_setup_mchbar(struct drm_i915_private *dev_priv)
179 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
183 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
186 dev_priv->mchbar_need_disable = false;
188 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
189 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
190 enabled = !!(temp & DEVEN_MCHBAR_EN);
192 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
196 /* If it's already enabled, don't have to do anything */
200 if (intel_alloc_mchbar_resource(dev_priv))
203 dev_priv->mchbar_need_disable = true;
205 /* Space is allocated or reserved, so enable it. */
206 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
207 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
208 temp | DEVEN_MCHBAR_EN);
210 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
211 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
216 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
218 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
220 if (dev_priv->mchbar_need_disable) {
221 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
224 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
226 deven_val &= ~DEVEN_MCHBAR_EN;
227 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
232 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
235 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
240 if (dev_priv->mch_res.start)
241 release_resource(&dev_priv->mch_res);
244 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
247 * The i915 workqueue is primarily used for batched retirement of
248 * requests (and thus managing bo) once the task has been completed
249 * by the GPU. i915_retire_requests() is called directly when we
250 * need high-priority retirement, such as waiting for an explicit
253 * It is also used for periodic low-priority events, such as
254 * idle-timers and recording error state.
256 * All tasks on the workqueue are expected to acquire the dev mutex
257 * so there is no point in running more than one instance of the
258 * workqueue at any time. Use an ordered one.
260 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
261 if (dev_priv->wq == NULL)
264 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
265 if (dev_priv->display.hotplug.dp_wq == NULL)
271 destroy_workqueue(dev_priv->wq);
273 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
278 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
280 destroy_workqueue(dev_priv->display.hotplug.dp_wq);
281 destroy_workqueue(dev_priv->wq);
285 * We don't keep the workarounds for pre-production hardware, so we expect our
286 * driver to fail on these machines in one way or another. A little warning on
287 * dmesg may help both the user and the bug triagers.
289 * Our policy for removing pre-production workarounds is to keep the
290 * current gen workarounds as a guide to the bring-up of the next gen
291 * (workarounds have a habit of persisting!). Anything older than that
292 * should be removed along with the complications they introduce.
294 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
298 pre |= IS_HSW_EARLY_SDV(dev_priv);
299 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
300 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
301 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
302 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
303 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
306 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
307 "It may not be fully functional.\n");
308 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
312 static void sanitize_gpu(struct drm_i915_private *i915)
314 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
318 for_each_gt(gt, i915, i)
319 __intel_gt_reset(gt, ALL_ENGINES);
324 * i915_driver_early_probe - setup state not requiring device access
325 * @dev_priv: device private
327 * Initialize everything that is a "SW-only" state, that is state not
328 * requiring accessing the device or exposing the driver via kernel internal
329 * or userspace interfaces. Example steps belonging here: lock initialization,
330 * system memory allocation, setting up device specific attributes and
331 * function hooks not requiring accessing the device.
333 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
337 if (i915_inject_probe_failure(dev_priv))
340 intel_device_info_subplatform_init(dev_priv);
341 intel_step_init(dev_priv);
343 intel_uncore_mmio_debug_init_early(dev_priv);
345 spin_lock_init(&dev_priv->irq_lock);
346 spin_lock_init(&dev_priv->gpu_error.lock);
347 mutex_init(&dev_priv->display.backlight.lock);
349 mutex_init(&dev_priv->sb_lock);
350 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
352 mutex_init(&dev_priv->display.audio.mutex);
353 mutex_init(&dev_priv->display.wm.wm_mutex);
354 mutex_init(&dev_priv->display.pps.mutex);
355 mutex_init(&dev_priv->display.hdcp.comp_mutex);
357 i915_memcpy_init_early(dev_priv);
358 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
360 ret = i915_workqueues_init(dev_priv);
364 ret = vlv_suspend_init(dev_priv);
368 ret = intel_region_ttm_device_init(dev_priv);
372 intel_wopcm_init_early(&dev_priv->wopcm);
374 ret = intel_root_gt_init_early(dev_priv);
378 i915_drm_clients_init(&dev_priv->clients, dev_priv);
380 i915_gem_init_early(dev_priv);
382 /* This must be called before any calls to HAS_PCH_* */
383 intel_detect_pch(dev_priv);
385 intel_pm_setup(dev_priv);
386 ret = intel_power_domains_init(dev_priv);
389 intel_irq_init(dev_priv);
390 intel_init_display_hooks(dev_priv);
391 intel_init_clock_gating_hooks(dev_priv);
393 intel_detect_preproduction_hw(dev_priv);
398 i915_gem_cleanup_early(dev_priv);
399 intel_gt_driver_late_release_all(dev_priv);
400 i915_drm_clients_fini(&dev_priv->clients);
402 intel_region_ttm_device_fini(dev_priv);
404 vlv_suspend_cleanup(dev_priv);
406 i915_workqueues_cleanup(dev_priv);
411 * i915_driver_late_release - cleanup the setup done in
412 * i915_driver_early_probe()
413 * @dev_priv: device private
415 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
417 intel_irq_fini(dev_priv);
418 intel_power_domains_cleanup(dev_priv);
419 i915_gem_cleanup_early(dev_priv);
420 intel_gt_driver_late_release_all(dev_priv);
421 i915_drm_clients_fini(&dev_priv->clients);
422 intel_region_ttm_device_fini(dev_priv);
423 vlv_suspend_cleanup(dev_priv);
424 i915_workqueues_cleanup(dev_priv);
426 cpu_latency_qos_remove_request(&dev_priv->sb_qos);
427 mutex_destroy(&dev_priv->sb_lock);
429 i915_params_free(&dev_priv->params);
433 * i915_driver_mmio_probe - setup device MMIO
434 * @dev_priv: device private
436 * Setup minimal device state necessary for MMIO accesses later in the
437 * initialization sequence. The setup here should avoid any other device-wide
438 * side effects or exposing the driver via kernel internal or user space
441 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
446 if (i915_inject_probe_failure(dev_priv))
449 ret = i915_get_bridge_dev(dev_priv);
453 for_each_gt(gt, dev_priv, i) {
454 ret = intel_uncore_init_mmio(gt->uncore);
458 ret = drmm_add_action_or_reset(&dev_priv->drm,
459 intel_uncore_fini_mmio,
465 /* Try to make sure MCHBAR is enabled before poking at it */
466 intel_setup_mchbar(dev_priv);
467 intel_device_info_runtime_init(dev_priv);
469 for_each_gt(gt, dev_priv, i) {
470 ret = intel_gt_init_mmio(gt);
475 /* As early as possible, scrub existing GPU state before clobbering */
476 sanitize_gpu(dev_priv);
481 intel_teardown_mchbar(dev_priv);
487 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
488 * @dev_priv: device private
490 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
492 intel_teardown_mchbar(dev_priv);
496 * i915_set_dma_info - set all relevant PCI dma info as configured for the
498 * @i915: valid i915 instance
500 * Set the dma max segment size, device and coherent masks. The dma mask set
501 * needs to occur before i915_ggtt_probe_hw.
503 * A couple of platforms have special needs. Address them as well.
506 static int i915_set_dma_info(struct drm_i915_private *i915)
508 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
511 GEM_BUG_ON(!mask_size);
514 * We don't have a max segment size, so set it to the max so sg's
515 * debugging layer doesn't complain
517 dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
519 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
523 /* overlay on gen2 is broken and can't address above 1G */
524 if (GRAPHICS_VER(i915) == 2)
528 * 965GM sometimes incorrectly writes to hardware status page (HWS)
529 * using 32bit addressing, overwriting memory if HWS is located
532 * The documentation also mentions an issue with undefined
533 * behaviour if any general state is accessed within a page above 4GB,
534 * which also needs to be handled carefully.
536 if (IS_I965G(i915) || IS_I965GM(i915))
539 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
546 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
550 static int i915_pcode_init(struct drm_i915_private *i915)
555 for_each_gt(gt, i915, id) {
556 ret = intel_pcode_init(gt->uncore);
558 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
567 * i915_driver_hw_probe - setup state requiring device access
568 * @dev_priv: device private
570 * Setup state that requires accessing the device, but doesn't require
571 * exposing the driver via kernel internal or userspace interfaces.
573 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
575 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
576 struct pci_dev *root_pdev;
579 if (i915_inject_probe_failure(dev_priv))
582 if (HAS_PPGTT(dev_priv)) {
583 if (intel_vgpu_active(dev_priv) &&
584 !intel_vgpu_has_full_ppgtt(dev_priv)) {
585 i915_report_error(dev_priv,
586 "incompatible vGPU found, support for isolated ppGTT required\n");
591 if (HAS_EXECLISTS(dev_priv)) {
593 * Older GVT emulation depends upon intercepting CSB mmio,
594 * which we no longer use, preferring to use the HWSP cache
597 if (intel_vgpu_active(dev_priv) &&
598 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
599 i915_report_error(dev_priv,
600 "old vGPU host found, support for HWSP emulation required\n");
605 /* needs to be done before ggtt probe */
606 intel_dram_edram_detect(dev_priv);
608 ret = i915_set_dma_info(dev_priv);
612 i915_perf_init(dev_priv);
614 ret = intel_gt_assign_ggtt(to_gt(dev_priv));
618 ret = i915_ggtt_probe_hw(dev_priv);
622 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
626 ret = i915_ggtt_init_hw(dev_priv);
630 ret = intel_memory_regions_hw_probe(dev_priv);
634 ret = intel_gt_tiles_init(dev_priv);
636 goto err_mem_regions;
638 ret = i915_ggtt_enable_hw(dev_priv);
640 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
641 goto err_mem_regions;
644 pci_set_master(pdev);
646 /* On the 945G/GM, the chipset reports the MSI capability on the
647 * integrated graphics even though the support isn't actually there
648 * according to the published specs. It doesn't appear to function
649 * correctly in testing on 945G.
650 * This may be a side effect of MSI having been made available for PEG
651 * and the registers being closely associated.
653 * According to chipset errata, on the 965GM, MSI interrupts may
654 * be lost or delayed, and was defeatured. MSI interrupts seem to
655 * get lost on g4x as well, and interrupt delivery seems to stay
656 * properly dead afterwards. So we'll just disable them for all
659 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
660 * interrupts even when in MSI mode. This results in spurious
661 * interrupt warnings if the legacy irq no. is shared with another
662 * device. The kernel then disables that interrupt source and so
663 * prevents the other device from working properly.
665 if (GRAPHICS_VER(dev_priv) >= 5) {
666 if (pci_enable_msi(pdev) < 0)
667 drm_dbg(&dev_priv->drm, "can't enable MSI");
670 ret = intel_gvt_init(dev_priv);
674 intel_opregion_setup(dev_priv);
676 ret = i915_pcode_init(dev_priv);
681 * Fill the dram structure to get the system dram info. This will be
682 * used for memory latency calculation.
684 intel_dram_detect(dev_priv);
686 intel_bw_init_hw(dev_priv);
689 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
690 * This should be totally removed when we handle the pci states properly
691 * on runtime PM and on s2idle cases.
693 root_pdev = pcie_find_root_port(pdev);
695 pci_d3cold_disable(root_pdev);
700 if (pdev->msi_enabled)
701 pci_disable_msi(pdev);
703 intel_memory_regions_driver_release(dev_priv);
705 i915_ggtt_driver_release(dev_priv);
706 i915_gem_drain_freed_objects(dev_priv);
707 i915_ggtt_driver_late_release(dev_priv);
709 i915_perf_fini(dev_priv);
714 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
715 * @dev_priv: device private
717 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
719 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
720 struct pci_dev *root_pdev;
722 i915_perf_fini(dev_priv);
724 if (pdev->msi_enabled)
725 pci_disable_msi(pdev);
727 root_pdev = pcie_find_root_port(pdev);
729 pci_d3cold_enable(root_pdev);
733 * i915_driver_register - register the driver with the rest of the system
734 * @dev_priv: device private
736 * Perform any steps necessary to make the driver available via kernel
737 * internal or userspace interfaces.
739 static void i915_driver_register(struct drm_i915_private *dev_priv)
741 struct drm_device *dev = &dev_priv->drm;
745 i915_gem_driver_register(dev_priv);
746 i915_pmu_register(dev_priv);
748 intel_vgpu_register(dev_priv);
750 /* Reveal our presence to userspace */
751 if (drm_dev_register(dev, 0)) {
752 drm_err(&dev_priv->drm,
753 "Failed to register driver for userspace access!\n");
757 i915_debugfs_register(dev_priv);
758 i915_setup_sysfs(dev_priv);
760 /* Depends on sysfs having been initialized */
761 i915_perf_register(dev_priv);
763 for_each_gt(gt, dev_priv, i)
764 intel_gt_driver_register(gt);
766 intel_display_driver_register(dev_priv);
768 intel_power_domains_enable(dev_priv);
769 intel_runtime_pm_enable(&dev_priv->runtime_pm);
771 intel_register_dsm_handler();
773 if (i915_switcheroo_register(dev_priv))
774 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
778 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
779 * @dev_priv: device private
781 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
786 i915_switcheroo_unregister(dev_priv);
788 intel_unregister_dsm_handler();
790 intel_runtime_pm_disable(&dev_priv->runtime_pm);
791 intel_power_domains_disable(dev_priv);
793 intel_display_driver_unregister(dev_priv);
795 for_each_gt(gt, dev_priv, i)
796 intel_gt_driver_unregister(gt);
798 i915_perf_unregister(dev_priv);
799 i915_pmu_unregister(dev_priv);
801 i915_teardown_sysfs(dev_priv);
802 drm_dev_unplug(&dev_priv->drm);
804 i915_gem_driver_unregister(dev_priv);
808 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
810 drm_printf(p, "iommu: %s\n",
811 str_enabled_disabled(i915_vtd_active(i915)));
814 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
816 if (drm_debug_enabled(DRM_UT_DRIVER)) {
817 struct drm_printer p = drm_debug_printer("i915 device info:");
821 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
822 INTEL_DEVID(dev_priv),
823 INTEL_REVID(dev_priv),
824 intel_platform_name(INTEL_INFO(dev_priv)->platform),
825 intel_subplatform(RUNTIME_INFO(dev_priv),
826 INTEL_INFO(dev_priv)->platform),
827 GRAPHICS_VER(dev_priv));
829 intel_device_info_print(INTEL_INFO(dev_priv),
830 RUNTIME_INFO(dev_priv), &p);
831 i915_print_iommu_status(dev_priv, &p);
832 for_each_gt(gt, dev_priv, i)
833 intel_gt_info_print(>->info, &p);
836 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
837 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
838 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
839 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
840 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
841 drm_info(&dev_priv->drm,
842 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
845 static struct drm_i915_private *
846 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
848 const struct intel_device_info *match_info =
849 (struct intel_device_info *)ent->driver_data;
850 struct intel_device_info *device_info;
851 struct intel_runtime_info *runtime;
852 struct drm_i915_private *i915;
854 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
855 struct drm_i915_private, drm);
859 pci_set_drvdata(pdev, i915);
861 /* Device parameters start as a copy of module parameters. */
862 i915_params_copy(&i915->params, &i915_modparams);
864 /* Setup the write-once "constant" device info */
865 device_info = mkwrite_device_info(i915);
866 memcpy(device_info, match_info, sizeof(*device_info));
868 /* Initialize initial runtime info from static const data and pdev. */
869 runtime = RUNTIME_INFO(i915);
870 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
871 runtime->device_id = pdev->device;
877 * i915_driver_probe - setup chip and create an initial config
879 * @ent: matching PCI ID entry
881 * The driver probe routine has to do several things:
882 * - drive output discovery via intel_modeset_init()
883 * - initialize the memory manager
884 * - allocate initial config memory
885 * - setup the DRM framebuffer with the allocated memory
887 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
889 struct drm_i915_private *i915;
892 i915 = i915_driver_create(pdev, ent);
894 return PTR_ERR(i915);
896 /* Disable nuclear pageflip by default on pre-ILK */
897 if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915) < 5)
898 i915->drm.driver_features &= ~DRIVER_ATOMIC;
900 ret = pci_enable_device(pdev);
904 ret = i915_driver_early_probe(i915);
906 goto out_pci_disable;
908 disable_rpm_wakeref_asserts(&i915->runtime_pm);
910 intel_vgpu_detect(i915);
912 ret = intel_gt_probe_all(i915);
914 goto out_runtime_pm_put;
916 ret = i915_driver_mmio_probe(i915);
918 goto out_tiles_cleanup;
920 ret = i915_driver_hw_probe(i915);
922 goto out_cleanup_mmio;
924 ret = intel_modeset_init_noirq(i915);
928 ret = intel_irq_install(i915);
930 goto out_cleanup_modeset;
932 ret = intel_modeset_init_nogem(i915);
934 goto out_cleanup_irq;
936 ret = i915_gem_init(i915);
938 goto out_cleanup_modeset2;
940 ret = intel_modeset_init(i915);
942 goto out_cleanup_gem;
944 i915_driver_register(i915);
946 enable_rpm_wakeref_asserts(&i915->runtime_pm);
948 i915_welcome_messages(i915);
950 i915->do_release = true;
955 i915_gem_suspend(i915);
956 i915_gem_driver_remove(i915);
957 i915_gem_driver_release(i915);
958 out_cleanup_modeset2:
959 /* FIXME clean up the error path */
960 intel_modeset_driver_remove(i915);
961 intel_irq_uninstall(i915);
962 intel_modeset_driver_remove_noirq(i915);
963 goto out_cleanup_modeset;
965 intel_irq_uninstall(i915);
967 intel_modeset_driver_remove_nogem(i915);
969 i915_driver_hw_remove(i915);
970 intel_memory_regions_driver_release(i915);
971 i915_ggtt_driver_release(i915);
972 i915_gem_drain_freed_objects(i915);
973 i915_ggtt_driver_late_release(i915);
975 i915_driver_mmio_release(i915);
977 intel_gt_release_all(i915);
979 enable_rpm_wakeref_asserts(&i915->runtime_pm);
980 i915_driver_late_release(i915);
982 pci_disable_device(pdev);
984 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
988 void i915_driver_remove(struct drm_i915_private *i915)
990 intel_wakeref_t wakeref;
992 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
994 i915_driver_unregister(i915);
996 /* Flush any external code that still may be under the RCU lock */
999 i915_gem_suspend(i915);
1001 intel_gvt_driver_remove(i915);
1003 intel_modeset_driver_remove(i915);
1005 intel_irq_uninstall(i915);
1007 intel_modeset_driver_remove_noirq(i915);
1009 i915_reset_error_state(i915);
1010 i915_gem_driver_remove(i915);
1012 intel_modeset_driver_remove_nogem(i915);
1014 i915_driver_hw_remove(i915);
1016 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1019 static void i915_driver_release(struct drm_device *dev)
1021 struct drm_i915_private *dev_priv = to_i915(dev);
1022 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1023 intel_wakeref_t wakeref;
1025 if (!dev_priv->do_release)
1028 wakeref = intel_runtime_pm_get(rpm);
1030 i915_gem_driver_release(dev_priv);
1032 intel_memory_regions_driver_release(dev_priv);
1033 i915_ggtt_driver_release(dev_priv);
1034 i915_gem_drain_freed_objects(dev_priv);
1035 i915_ggtt_driver_late_release(dev_priv);
1037 i915_driver_mmio_release(dev_priv);
1039 intel_runtime_pm_put(rpm, wakeref);
1041 intel_runtime_pm_driver_release(rpm);
1043 i915_driver_late_release(dev_priv);
1046 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1048 struct drm_i915_private *i915 = to_i915(dev);
1051 ret = i915_gem_open(i915, file);
1059 * i915_driver_lastclose - clean up after all DRM clients have exited
1062 * Take care of cleaning up after all DRM clients have exited. In the
1063 * mode setting case, we want to restore the kernel's initial mode (just
1064 * in case the last client left us in a bad state).
1066 * Additionally, in the non-mode setting case, we'll tear down the GTT
1067 * and DMA structures, since the kernel won't be using them, and clea
1070 static void i915_driver_lastclose(struct drm_device *dev)
1072 struct drm_i915_private *i915 = to_i915(dev);
1074 intel_fbdev_restore_mode(dev);
1076 if (HAS_DISPLAY(i915))
1077 vga_switcheroo_process_delayed_switch();
1080 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1082 struct drm_i915_file_private *file_priv = file->driver_priv;
1084 i915_gem_context_close(file);
1085 i915_drm_client_put(file_priv->client);
1087 kfree_rcu(file_priv, rcu);
1089 /* Catch up with all the deferred frees from "this" client */
1090 i915_gem_flush_free_objects(to_i915(dev));
1093 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1095 struct drm_device *dev = &dev_priv->drm;
1096 struct intel_encoder *encoder;
1098 if (!HAS_DISPLAY(dev_priv))
1101 drm_modeset_lock_all(dev);
1102 for_each_intel_encoder(dev, encoder)
1103 if (encoder->suspend)
1104 encoder->suspend(encoder);
1105 drm_modeset_unlock_all(dev);
1108 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1110 struct drm_device *dev = &dev_priv->drm;
1111 struct intel_encoder *encoder;
1113 if (!HAS_DISPLAY(dev_priv))
1116 drm_modeset_lock_all(dev);
1117 for_each_intel_encoder(dev, encoder)
1118 if (encoder->shutdown)
1119 encoder->shutdown(encoder);
1120 drm_modeset_unlock_all(dev);
1123 void i915_driver_shutdown(struct drm_i915_private *i915)
1125 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1126 intel_runtime_pm_disable(&i915->runtime_pm);
1127 intel_power_domains_disable(i915);
1129 if (HAS_DISPLAY(i915)) {
1130 drm_kms_helper_poll_disable(&i915->drm);
1132 drm_atomic_helper_shutdown(&i915->drm);
1135 intel_dp_mst_suspend(i915);
1137 intel_runtime_pm_disable_interrupts(i915);
1138 intel_hpd_cancel_work(i915);
1140 intel_suspend_encoders(i915);
1141 intel_shutdown_encoders(i915);
1143 intel_dmc_ucode_suspend(i915);
1145 i915_gem_suspend(i915);
1148 * The only requirement is to reboot with display DC states disabled,
1149 * for now leaving all display power wells in the INIT power domain
1153 * - unify the pci_driver::shutdown sequence here with the
1154 * pci_driver.driver.pm.poweroff,poweroff_late sequence.
1155 * - unify the driver remove and system/runtime suspend sequences with
1156 * the above unified shutdown/poweroff sequence.
1158 intel_power_domains_driver_remove(i915);
1159 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1161 intel_runtime_pm_driver_release(&i915->runtime_pm);
1164 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1166 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1167 if (acpi_target_system_state() < ACPI_STATE_S3)
1173 static int i915_drm_prepare(struct drm_device *dev)
1175 struct drm_i915_private *i915 = to_i915(dev);
1178 * NB intel_display_suspend() may issue new requests after we've
1179 * ostensibly marked the GPU as ready-to-sleep here. We need to
1180 * split out that work and pull it forward so that after point,
1181 * the GPU is not woken again.
1183 return i915_gem_backup_suspend(i915);
1186 static int i915_drm_suspend(struct drm_device *dev)
1188 struct drm_i915_private *dev_priv = to_i915(dev);
1189 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1190 pci_power_t opregion_target_state;
1192 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1194 /* We do a lot of poking in a lot of registers, make sure they work
1196 intel_power_domains_disable(dev_priv);
1197 if (HAS_DISPLAY(dev_priv))
1198 drm_kms_helper_poll_disable(dev);
1200 pci_save_state(pdev);
1202 intel_display_suspend(dev);
1204 intel_dp_mst_suspend(dev_priv);
1206 intel_runtime_pm_disable_interrupts(dev_priv);
1207 intel_hpd_cancel_work(dev_priv);
1209 intel_suspend_encoders(dev_priv);
1211 intel_suspend_hw(dev_priv);
1213 /* Must be called before GGTT is suspended. */
1214 intel_dpt_suspend(dev_priv);
1215 i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1217 i915_save_display(dev_priv);
1219 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1220 intel_opregion_suspend(dev_priv, opregion_target_state);
1222 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1224 dev_priv->suspend_count++;
1226 intel_dmc_ucode_suspend(dev_priv);
1228 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1230 i915_gem_drain_freed_objects(dev_priv);
1235 static enum i915_drm_suspend_mode
1236 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1239 return I915_DRM_SUSPEND_HIBERNATE;
1241 if (suspend_to_idle(dev_priv))
1242 return I915_DRM_SUSPEND_IDLE;
1244 return I915_DRM_SUSPEND_MEM;
1247 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1249 struct drm_i915_private *dev_priv = to_i915(dev);
1250 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1251 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1252 struct intel_gt *gt;
1255 disable_rpm_wakeref_asserts(rpm);
1257 i915_gem_suspend_late(dev_priv);
1259 for_each_gt(gt, dev_priv, i)
1260 intel_uncore_suspend(gt->uncore);
1262 intel_power_domains_suspend(dev_priv,
1263 get_suspend_mode(dev_priv, hibernation));
1265 intel_display_power_suspend_late(dev_priv);
1267 ret = vlv_suspend_complete(dev_priv);
1269 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1270 intel_power_domains_resume(dev_priv);
1275 pci_disable_device(pdev);
1277 * During hibernation on some platforms the BIOS may try to access
1278 * the device even though it's already in D3 and hang the machine. So
1279 * leave the device in D0 on those platforms and hope the BIOS will
1280 * power down the device properly. The issue was seen on multiple old
1281 * GENs with different BIOS vendors, so having an explicit blacklist
1282 * is inpractical; apply the workaround on everything pre GEN6. The
1283 * platforms where the issue was seen:
1284 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1288 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1289 pci_set_power_state(pdev, PCI_D3hot);
1292 enable_rpm_wakeref_asserts(rpm);
1293 if (!dev_priv->uncore.user_forcewake_count)
1294 intel_runtime_pm_driver_release(rpm);
1299 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1304 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1305 state.event != PM_EVENT_FREEZE))
1308 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1311 error = i915_drm_suspend(&i915->drm);
1315 return i915_drm_suspend_late(&i915->drm, false);
1318 static int i915_drm_resume(struct drm_device *dev)
1320 struct drm_i915_private *dev_priv = to_i915(dev);
1323 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1325 ret = i915_pcode_init(dev_priv);
1329 sanitize_gpu(dev_priv);
1331 ret = i915_ggtt_enable_hw(dev_priv);
1333 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1335 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1336 /* Must be called after GGTT is resumed. */
1337 intel_dpt_resume(dev_priv);
1339 intel_dmc_ucode_resume(dev_priv);
1341 i915_restore_display(dev_priv);
1342 intel_pps_unlock_regs_wa(dev_priv);
1344 intel_init_pch_refclk(dev_priv);
1347 * Interrupts have to be enabled before any batches are run. If not the
1348 * GPU will hang. i915_gem_init_hw() will initiate batches to
1349 * update/restore the context.
1351 * drm_mode_config_reset() needs AUX interrupts.
1353 * Modeset enabling in intel_modeset_init_hw() also needs working
1356 intel_runtime_pm_enable_interrupts(dev_priv);
1358 if (HAS_DISPLAY(dev_priv))
1359 drm_mode_config_reset(dev);
1361 i915_gem_resume(dev_priv);
1363 intel_modeset_init_hw(dev_priv);
1364 intel_init_clock_gating(dev_priv);
1365 intel_hpd_init(dev_priv);
1367 /* MST sideband requires HPD interrupts enabled */
1368 intel_dp_mst_resume(dev_priv);
1369 intel_display_resume(dev);
1371 intel_hpd_poll_disable(dev_priv);
1372 if (HAS_DISPLAY(dev_priv))
1373 drm_kms_helper_poll_enable(dev);
1375 intel_opregion_resume(dev_priv);
1377 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1379 intel_power_domains_enable(dev_priv);
1381 intel_gvt_resume(dev_priv);
1383 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1388 static int i915_drm_resume_early(struct drm_device *dev)
1390 struct drm_i915_private *dev_priv = to_i915(dev);
1391 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1392 struct intel_gt *gt;
1396 * We have a resume ordering issue with the snd-hda driver also
1397 * requiring our device to be power up. Due to the lack of a
1398 * parent/child relationship we currently solve this with an early
1401 * FIXME: This should be solved with a special hdmi sink device or
1402 * similar so that power domains can be employed.
1406 * Note that we need to set the power state explicitly, since we
1407 * powered off the device during freeze and the PCI core won't power
1408 * it back up for us during thaw. Powering off the device during
1409 * freeze is not a hard requirement though, and during the
1410 * suspend/resume phases the PCI core makes sure we get here with the
1411 * device powered on. So in case we change our freeze logic and keep
1412 * the device powered we can also remove the following set power state
1415 ret = pci_set_power_state(pdev, PCI_D0);
1417 drm_err(&dev_priv->drm,
1418 "failed to set PCI D0 power state (%d)\n", ret);
1423 * Note that pci_enable_device() first enables any parent bridge
1424 * device and only then sets the power state for this device. The
1425 * bridge enabling is a nop though, since bridge devices are resumed
1426 * first. The order of enabling power and enabling the device is
1427 * imposed by the PCI core as described above, so here we preserve the
1428 * same order for the freeze/thaw phases.
1430 * TODO: eventually we should remove pci_disable_device() /
1431 * pci_enable_enable_device() from suspend/resume. Due to how they
1432 * depend on the device enable refcount we can't anyway depend on them
1433 * disabling/enabling the device.
1435 if (pci_enable_device(pdev))
1438 pci_set_master(pdev);
1440 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1442 ret = vlv_resume_prepare(dev_priv, false);
1444 drm_err(&dev_priv->drm,
1445 "Resume prepare failed: %d, continuing anyway\n", ret);
1447 for_each_gt(gt, dev_priv, i) {
1448 intel_uncore_resume_early(gt->uncore);
1449 intel_gt_check_and_clear_faults(gt);
1452 intel_display_power_resume_early(dev_priv);
1454 intel_power_domains_resume(dev_priv);
1456 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1461 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1465 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1468 ret = i915_drm_resume_early(&i915->drm);
1472 return i915_drm_resume(&i915->drm);
1475 static int i915_pm_prepare(struct device *kdev)
1477 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1480 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1484 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1487 return i915_drm_prepare(&i915->drm);
1490 static int i915_pm_suspend(struct device *kdev)
1492 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1495 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1499 i915_ggtt_mark_pte_lost(i915, false);
1501 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1504 return i915_drm_suspend(&i915->drm);
1507 static int i915_pm_suspend_late(struct device *kdev)
1509 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1512 * We have a suspend ordering issue with the snd-hda driver also
1513 * requiring our device to be power up. Due to the lack of a
1514 * parent/child relationship we currently solve this with an late
1517 * FIXME: This should be solved with a special hdmi sink device or
1518 * similar so that power domains can be employed.
1520 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1523 return i915_drm_suspend_late(&i915->drm, false);
1526 static int i915_pm_poweroff_late(struct device *kdev)
1528 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1530 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1533 return i915_drm_suspend_late(&i915->drm, true);
1536 static int i915_pm_resume_early(struct device *kdev)
1538 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1540 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1543 return i915_drm_resume_early(&i915->drm);
1546 static int i915_pm_resume(struct device *kdev)
1548 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1550 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1554 * If IRST is enabled, or if we can't detect whether it's enabled,
1555 * then we must assume we lost the GGTT page table entries, since
1556 * they are not retained if IRST decided to enter S4.
1558 if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1))
1559 i915_ggtt_mark_pte_lost(i915, true);
1561 return i915_drm_resume(&i915->drm);
1564 /* freeze: before creating the hibernation_image */
1565 static int i915_pm_freeze(struct device *kdev)
1567 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1570 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1571 ret = i915_drm_suspend(&i915->drm);
1576 ret = i915_gem_freeze(i915);
1583 static int i915_pm_freeze_late(struct device *kdev)
1585 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1588 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1589 ret = i915_drm_suspend_late(&i915->drm, true);
1594 ret = i915_gem_freeze_late(i915);
1601 /* thaw: called after creating the hibernation image, but before turning off. */
1602 static int i915_pm_thaw_early(struct device *kdev)
1604 return i915_pm_resume_early(kdev);
1607 static int i915_pm_thaw(struct device *kdev)
1609 return i915_pm_resume(kdev);
1612 /* restore: called after loading the hibernation image. */
1613 static int i915_pm_restore_early(struct device *kdev)
1615 return i915_pm_resume_early(kdev);
1618 static int i915_pm_restore(struct device *kdev)
1620 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1622 i915_ggtt_mark_pte_lost(i915, true);
1623 return i915_pm_resume(kdev);
1626 static int intel_runtime_suspend(struct device *kdev)
1628 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1629 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1630 struct intel_gt *gt;
1633 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1636 drm_dbg(&dev_priv->drm, "Suspending device\n");
1638 disable_rpm_wakeref_asserts(rpm);
1641 * We are safe here against re-faults, since the fault handler takes
1644 i915_gem_runtime_suspend(dev_priv);
1646 for_each_gt(gt, dev_priv, i)
1647 intel_gt_runtime_suspend(gt);
1649 intel_runtime_pm_disable_interrupts(dev_priv);
1651 for_each_gt(gt, dev_priv, i)
1652 intel_uncore_suspend(gt->uncore);
1654 intel_display_power_suspend(dev_priv);
1656 ret = vlv_suspend_complete(dev_priv);
1658 drm_err(&dev_priv->drm,
1659 "Runtime suspend failed, disabling it (%d)\n", ret);
1660 intel_uncore_runtime_resume(&dev_priv->uncore);
1662 intel_runtime_pm_enable_interrupts(dev_priv);
1664 for_each_gt(gt, dev_priv, i)
1665 intel_gt_runtime_resume(gt);
1667 enable_rpm_wakeref_asserts(rpm);
1672 enable_rpm_wakeref_asserts(rpm);
1673 intel_runtime_pm_driver_release(rpm);
1675 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1676 drm_err(&dev_priv->drm,
1677 "Unclaimed access detected prior to suspending\n");
1679 rpm->suspended = true;
1682 * FIXME: We really should find a document that references the arguments
1685 if (IS_BROADWELL(dev_priv)) {
1687 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1688 * being detected, and the call we do at intel_runtime_resume()
1689 * won't be able to restore them. Since PCI_D3hot matches the
1690 * actual specification and appears to be working, use it.
1692 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1695 * current versions of firmware which depend on this opregion
1696 * notification have repurposed the D1 definition to mean
1697 * "runtime suspended" vs. what you would normally expect (D3)
1698 * to distinguish it from notifications that might be sent via
1701 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1704 assert_forcewakes_inactive(&dev_priv->uncore);
1706 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1707 intel_hpd_poll_enable(dev_priv);
1709 drm_dbg(&dev_priv->drm, "Device suspended\n");
1713 static int intel_runtime_resume(struct device *kdev)
1715 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1716 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1717 struct intel_gt *gt;
1720 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1723 drm_dbg(&dev_priv->drm, "Resuming device\n");
1725 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1726 disable_rpm_wakeref_asserts(rpm);
1728 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1729 rpm->suspended = false;
1730 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1731 drm_dbg(&dev_priv->drm,
1732 "Unclaimed access during suspend, bios?\n");
1734 intel_display_power_resume(dev_priv);
1736 ret = vlv_resume_prepare(dev_priv, true);
1738 for_each_gt(gt, dev_priv, i)
1739 intel_uncore_runtime_resume(gt->uncore);
1741 intel_runtime_pm_enable_interrupts(dev_priv);
1744 * No point of rolling back things in case of an error, as the best
1745 * we can do is to hope that things will still work (and disable RPM).
1747 for_each_gt(gt, dev_priv, i)
1748 intel_gt_runtime_resume(gt);
1751 * On VLV/CHV display interrupts are part of the display
1752 * power well, so hpd is reinitialized from there. For
1753 * everyone else do it here.
1755 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1756 intel_hpd_init(dev_priv);
1757 intel_hpd_poll_disable(dev_priv);
1760 skl_watermark_ipc_update(dev_priv);
1762 enable_rpm_wakeref_asserts(rpm);
1765 drm_err(&dev_priv->drm,
1766 "Runtime resume failed, disabling it (%d)\n", ret);
1768 drm_dbg(&dev_priv->drm, "Device resumed\n");
1773 const struct dev_pm_ops i915_pm_ops = {
1775 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1778 .prepare = i915_pm_prepare,
1779 .suspend = i915_pm_suspend,
1780 .suspend_late = i915_pm_suspend_late,
1781 .resume_early = i915_pm_resume_early,
1782 .resume = i915_pm_resume,
1786 * @freeze, @freeze_late : called (1) before creating the
1787 * hibernation image [PMSG_FREEZE] and
1788 * (2) after rebooting, before restoring
1789 * the image [PMSG_QUIESCE]
1790 * @thaw, @thaw_early : called (1) after creating the hibernation
1791 * image, before writing it [PMSG_THAW]
1792 * and (2) after failing to create or
1793 * restore the image [PMSG_RECOVER]
1794 * @poweroff, @poweroff_late: called after writing the hibernation
1795 * image, before rebooting [PMSG_HIBERNATE]
1796 * @restore, @restore_early : called after rebooting and restoring the
1797 * hibernation image [PMSG_RESTORE]
1799 .freeze = i915_pm_freeze,
1800 .freeze_late = i915_pm_freeze_late,
1801 .thaw_early = i915_pm_thaw_early,
1802 .thaw = i915_pm_thaw,
1803 .poweroff = i915_pm_suspend,
1804 .poweroff_late = i915_pm_poweroff_late,
1805 .restore_early = i915_pm_restore_early,
1806 .restore = i915_pm_restore,
1808 /* S0ix (via runtime suspend) event handlers */
1809 .runtime_suspend = intel_runtime_suspend,
1810 .runtime_resume = intel_runtime_resume,
1813 static const struct file_operations i915_driver_fops = {
1814 .owner = THIS_MODULE,
1816 .release = drm_release_noglobal,
1817 .unlocked_ioctl = drm_ioctl,
1818 .mmap = i915_gem_mmap,
1821 .compat_ioctl = i915_ioc32_compat_ioctl,
1822 .llseek = noop_llseek,
1823 #ifdef CONFIG_PROC_FS
1824 .show_fdinfo = i915_drm_client_fdinfo,
1829 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1830 struct drm_file *file)
1835 static const struct drm_ioctl_desc i915_ioctls[] = {
1836 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1837 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1838 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1839 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1840 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1841 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1842 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1843 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1844 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1845 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1846 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1847 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1848 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1849 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1850 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1851 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1852 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1853 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1854 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1855 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1856 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1857 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1858 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1859 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1860 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1861 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1862 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1863 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1864 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1865 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1866 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1867 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1868 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1869 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1870 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1871 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1872 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1873 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1874 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1875 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1876 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1877 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1878 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1879 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1880 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1881 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1882 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1883 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1884 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1885 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1886 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1887 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1888 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1889 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1890 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1891 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1892 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1893 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1894 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1898 * Interface history:
1901 * 1.2: Add Power Management
1902 * 1.3: Add vblank support
1903 * 1.4: Fix cmdbuffer path, add heap destroy
1904 * 1.5: Add vblank pipe configuration
1905 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1906 * - Support vertical blank on secondary display pipe
1908 #define DRIVER_MAJOR 1
1909 #define DRIVER_MINOR 6
1910 #define DRIVER_PATCHLEVEL 0
1912 static const struct drm_driver i915_drm_driver = {
1913 /* Don't use MTRRs here; the Xserver or userspace app should
1914 * deal with them for Intel hardware.
1918 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1919 DRIVER_SYNCOBJ_TIMELINE,
1920 .release = i915_driver_release,
1921 .open = i915_driver_open,
1922 .lastclose = i915_driver_lastclose,
1923 .postclose = i915_driver_postclose,
1925 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1926 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1927 .gem_prime_import = i915_gem_prime_import,
1929 .dumb_create = i915_gem_dumb_create,
1930 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1932 .ioctls = i915_ioctls,
1933 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1934 .fops = &i915_driver_fops,
1935 .name = DRIVER_NAME,
1936 .desc = DRIVER_DESC,
1937 .date = DRIVER_DATE,
1938 .major = DRIVER_MAJOR,
1939 .minor = DRIVER_MINOR,
1940 .patchlevel = DRIVER_PATCHLEVEL,