1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/module.h>
33 #include <linux/oom.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/string_helpers.h>
40 #include <linux/vga_switcheroo.h>
43 #include <drm/drm_aperture.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_ioctl.h>
46 #include <drm/drm_managed.h>
47 #include <drm/drm_probe_helper.h>
49 #include "display/intel_acpi.h"
50 #include "display/intel_bw.h"
51 #include "display/intel_cdclk.h"
52 #include "display/intel_display_types.h"
53 #include "display/intel_dmc.h"
54 #include "display/intel_dp.h"
55 #include "display/intel_dpt.h"
56 #include "display/intel_fbdev.h"
57 #include "display/intel_hotplug.h"
58 #include "display/intel_overlay.h"
59 #include "display/intel_pch_refclk.h"
60 #include "display/intel_pipe_crc.h"
61 #include "display/intel_pps.h"
62 #include "display/intel_sprite.h"
63 #include "display/intel_vga.h"
65 #include "gem/i915_gem_context.h"
66 #include "gem/i915_gem_create.h"
67 #include "gem/i915_gem_dmabuf.h"
68 #include "gem/i915_gem_ioctls.h"
69 #include "gem/i915_gem_mman.h"
70 #include "gem/i915_gem_pm.h"
71 #include "gt/intel_gt.h"
72 #include "gt/intel_gt_pm.h"
73 #include "gt/intel_rc6.h"
75 #include "pxp/intel_pxp_pm.h"
77 #include "i915_file_private.h"
78 #include "i915_debugfs.h"
79 #include "i915_driver.h"
80 #include "i915_drm_client.h"
82 #include "i915_getparam.h"
83 #include "i915_ioc32.h"
84 #include "i915_ioctl.h"
86 #include "i915_memcpy.h"
87 #include "i915_perf.h"
88 #include "i915_query.h"
89 #include "i915_suspend.h"
90 #include "i915_switcheroo.h"
91 #include "i915_sysfs.h"
92 #include "i915_utils.h"
93 #include "i915_vgpu.h"
94 #include "intel_dram.h"
95 #include "intel_gvt.h"
96 #include "intel_memory_region.h"
97 #include "intel_pci_config.h"
98 #include "intel_pcode.h"
100 #include "intel_region_ttm.h"
101 #include "vlv_suspend.h"
103 static const struct drm_driver i915_drm_driver;
105 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
107 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
109 dev_priv->bridge_dev =
110 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
111 if (!dev_priv->bridge_dev) {
112 drm_err(&dev_priv->drm, "bridge device not found\n");
118 /* Allocate space for the MCH regs if needed, return nonzero on error */
120 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
122 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
123 u32 temp_lo, temp_hi = 0;
127 if (GRAPHICS_VER(dev_priv) >= 4)
128 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
129 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
130 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
132 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
135 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
139 /* Get some space for it */
140 dev_priv->mch_res.name = "i915 MCHBAR";
141 dev_priv->mch_res.flags = IORESOURCE_MEM;
142 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
144 MCHBAR_SIZE, MCHBAR_SIZE,
146 0, pcibios_align_resource,
147 dev_priv->bridge_dev);
149 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
150 dev_priv->mch_res.start = 0;
154 if (GRAPHICS_VER(dev_priv) >= 4)
155 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
156 upper_32_bits(dev_priv->mch_res.start));
158 pci_write_config_dword(dev_priv->bridge_dev, reg,
159 lower_32_bits(dev_priv->mch_res.start));
163 /* Setup MCHBAR if possible, return true if we should disable it again */
165 intel_setup_mchbar(struct drm_i915_private *dev_priv)
167 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
171 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
174 dev_priv->mchbar_need_disable = false;
176 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
177 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
178 enabled = !!(temp & DEVEN_MCHBAR_EN);
180 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
184 /* If it's already enabled, don't have to do anything */
188 if (intel_alloc_mchbar_resource(dev_priv))
191 dev_priv->mchbar_need_disable = true;
193 /* Space is allocated or reserved, so enable it. */
194 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
195 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
196 temp | DEVEN_MCHBAR_EN);
198 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
199 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
204 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
206 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
208 if (dev_priv->mchbar_need_disable) {
209 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
212 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
214 deven_val &= ~DEVEN_MCHBAR_EN;
215 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
220 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
223 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
228 if (dev_priv->mch_res.start)
229 release_resource(&dev_priv->mch_res);
232 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
235 * The i915 workqueue is primarily used for batched retirement of
236 * requests (and thus managing bo) once the task has been completed
237 * by the GPU. i915_retire_requests() is called directly when we
238 * need high-priority retirement, such as waiting for an explicit
241 * It is also used for periodic low-priority events, such as
242 * idle-timers and recording error state.
244 * All tasks on the workqueue are expected to acquire the dev mutex
245 * so there is no point in running more than one instance of the
246 * workqueue at any time. Use an ordered one.
248 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
249 if (dev_priv->wq == NULL)
252 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
253 if (dev_priv->hotplug.dp_wq == NULL)
259 destroy_workqueue(dev_priv->wq);
261 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
266 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
268 destroy_workqueue(dev_priv->hotplug.dp_wq);
269 destroy_workqueue(dev_priv->wq);
273 * We don't keep the workarounds for pre-production hardware, so we expect our
274 * driver to fail on these machines in one way or another. A little warning on
275 * dmesg may help both the user and the bug triagers.
277 * Our policy for removing pre-production workarounds is to keep the
278 * current gen workarounds as a guide to the bring-up of the next gen
279 * (workarounds have a habit of persisting!). Anything older than that
280 * should be removed along with the complications they introduce.
282 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
286 pre |= IS_HSW_EARLY_SDV(dev_priv);
287 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
288 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
289 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
290 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
291 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
294 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
295 "It may not be fully functional.\n");
296 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
300 static void sanitize_gpu(struct drm_i915_private *i915)
302 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
303 __intel_gt_reset(to_gt(i915), ALL_ENGINES);
307 * i915_driver_early_probe - setup state not requiring device access
308 * @dev_priv: device private
310 * Initialize everything that is a "SW-only" state, that is state not
311 * requiring accessing the device or exposing the driver via kernel internal
312 * or userspace interfaces. Example steps belonging here: lock initialization,
313 * system memory allocation, setting up device specific attributes and
314 * function hooks not requiring accessing the device.
316 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
320 if (i915_inject_probe_failure(dev_priv))
323 intel_device_info_subplatform_init(dev_priv);
324 intel_step_init(dev_priv);
326 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
328 spin_lock_init(&dev_priv->irq_lock);
329 spin_lock_init(&dev_priv->gpu_error.lock);
330 mutex_init(&dev_priv->backlight_lock);
332 mutex_init(&dev_priv->sb_lock);
333 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
335 mutex_init(&dev_priv->audio.mutex);
336 mutex_init(&dev_priv->wm.wm_mutex);
337 mutex_init(&dev_priv->pps_mutex);
338 mutex_init(&dev_priv->hdcp_comp_mutex);
340 i915_memcpy_init_early(dev_priv);
341 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
343 ret = i915_workqueues_init(dev_priv);
347 ret = vlv_suspend_init(dev_priv);
351 ret = intel_region_ttm_device_init(dev_priv);
355 intel_wopcm_init_early(&dev_priv->wopcm);
357 intel_root_gt_init_early(dev_priv);
359 i915_drm_clients_init(&dev_priv->clients, dev_priv);
361 i915_gem_init_early(dev_priv);
363 /* This must be called before any calls to HAS_PCH_* */
364 intel_detect_pch(dev_priv);
366 intel_pm_setup(dev_priv);
367 ret = intel_power_domains_init(dev_priv);
370 intel_irq_init(dev_priv);
371 intel_init_display_hooks(dev_priv);
372 intel_init_clock_gating_hooks(dev_priv);
374 intel_detect_preproduction_hw(dev_priv);
379 i915_gem_cleanup_early(dev_priv);
380 intel_gt_driver_late_release_all(dev_priv);
381 i915_drm_clients_fini(&dev_priv->clients);
382 intel_region_ttm_device_fini(dev_priv);
384 vlv_suspend_cleanup(dev_priv);
386 i915_workqueues_cleanup(dev_priv);
391 * i915_driver_late_release - cleanup the setup done in
392 * i915_driver_early_probe()
393 * @dev_priv: device private
395 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
397 intel_irq_fini(dev_priv);
398 intel_power_domains_cleanup(dev_priv);
399 i915_gem_cleanup_early(dev_priv);
400 intel_gt_driver_late_release_all(dev_priv);
401 i915_drm_clients_fini(&dev_priv->clients);
402 intel_region_ttm_device_fini(dev_priv);
403 vlv_suspend_cleanup(dev_priv);
404 i915_workqueues_cleanup(dev_priv);
406 cpu_latency_qos_remove_request(&dev_priv->sb_qos);
407 mutex_destroy(&dev_priv->sb_lock);
409 i915_params_free(&dev_priv->params);
413 * i915_driver_mmio_probe - setup device MMIO
414 * @dev_priv: device private
416 * Setup minimal device state necessary for MMIO accesses later in the
417 * initialization sequence. The setup here should avoid any other device-wide
418 * side effects or exposing the driver via kernel internal or user space
421 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
425 if (i915_inject_probe_failure(dev_priv))
428 ret = i915_get_bridge_dev(dev_priv);
432 ret = intel_uncore_init_mmio(&dev_priv->uncore);
436 /* Try to make sure MCHBAR is enabled before poking at it */
437 intel_setup_mchbar(dev_priv);
438 intel_device_info_runtime_init(dev_priv);
440 ret = intel_gt_init_mmio(to_gt(dev_priv));
444 /* As early as possible, scrub existing GPU state before clobbering */
445 sanitize_gpu(dev_priv);
450 intel_teardown_mchbar(dev_priv);
451 intel_uncore_fini_mmio(&dev_priv->uncore);
452 pci_dev_put(dev_priv->bridge_dev);
458 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
459 * @dev_priv: device private
461 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
463 intel_teardown_mchbar(dev_priv);
464 intel_uncore_fini_mmio(&dev_priv->uncore);
465 pci_dev_put(dev_priv->bridge_dev);
469 * i915_set_dma_info - set all relevant PCI dma info as configured for the
471 * @i915: valid i915 instance
473 * Set the dma max segment size, device and coherent masks. The dma mask set
474 * needs to occur before i915_ggtt_probe_hw.
476 * A couple of platforms have special needs. Address them as well.
479 static int i915_set_dma_info(struct drm_i915_private *i915)
481 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
484 GEM_BUG_ON(!mask_size);
487 * We don't have a max segment size, so set it to the max so sg's
488 * debugging layer doesn't complain
490 dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
492 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
496 /* overlay on gen2 is broken and can't address above 1G */
497 if (GRAPHICS_VER(i915) == 2)
501 * 965GM sometimes incorrectly writes to hardware status page (HWS)
502 * using 32bit addressing, overwriting memory if HWS is located
505 * The documentation also mentions an issue with undefined
506 * behaviour if any general state is accessed within a page above 4GB,
507 * which also needs to be handled carefully.
509 if (IS_I965G(i915) || IS_I965GM(i915))
512 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
519 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
524 * i915_driver_hw_probe - setup state requiring device access
525 * @dev_priv: device private
527 * Setup state that requires accessing the device, but doesn't require
528 * exposing the driver via kernel internal or userspace interfaces.
530 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
532 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
533 struct pci_dev *root_pdev;
536 if (i915_inject_probe_failure(dev_priv))
539 if (HAS_PPGTT(dev_priv)) {
540 if (intel_vgpu_active(dev_priv) &&
541 !intel_vgpu_has_full_ppgtt(dev_priv)) {
542 i915_report_error(dev_priv,
543 "incompatible vGPU found, support for isolated ppGTT required\n");
548 if (HAS_EXECLISTS(dev_priv)) {
550 * Older GVT emulation depends upon intercepting CSB mmio,
551 * which we no longer use, preferring to use the HWSP cache
554 if (intel_vgpu_active(dev_priv) &&
555 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
556 i915_report_error(dev_priv,
557 "old vGPU host found, support for HWSP emulation required\n");
562 /* needs to be done before ggtt probe */
563 intel_dram_edram_detect(dev_priv);
565 ret = i915_set_dma_info(dev_priv);
569 i915_perf_init(dev_priv);
571 ret = intel_gt_assign_ggtt(to_gt(dev_priv));
575 ret = i915_ggtt_probe_hw(dev_priv);
579 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
583 ret = i915_ggtt_init_hw(dev_priv);
587 ret = intel_memory_regions_hw_probe(dev_priv);
591 ret = intel_gt_tiles_init(dev_priv);
593 goto err_mem_regions;
595 ret = i915_ggtt_enable_hw(dev_priv);
597 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
598 goto err_mem_regions;
601 pci_set_master(pdev);
603 /* On the 945G/GM, the chipset reports the MSI capability on the
604 * integrated graphics even though the support isn't actually there
605 * according to the published specs. It doesn't appear to function
606 * correctly in testing on 945G.
607 * This may be a side effect of MSI having been made available for PEG
608 * and the registers being closely associated.
610 * According to chipset errata, on the 965GM, MSI interrupts may
611 * be lost or delayed, and was defeatured. MSI interrupts seem to
612 * get lost on g4x as well, and interrupt delivery seems to stay
613 * properly dead afterwards. So we'll just disable them for all
616 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
617 * interrupts even when in MSI mode. This results in spurious
618 * interrupt warnings if the legacy irq no. is shared with another
619 * device. The kernel then disables that interrupt source and so
620 * prevents the other device from working properly.
622 if (GRAPHICS_VER(dev_priv) >= 5) {
623 if (pci_enable_msi(pdev) < 0)
624 drm_dbg(&dev_priv->drm, "can't enable MSI");
627 ret = intel_gvt_init(dev_priv);
631 intel_opregion_setup(dev_priv);
633 ret = intel_pcode_init(dev_priv);
638 * Fill the dram structure to get the system dram info. This will be
639 * used for memory latency calculation.
641 intel_dram_detect(dev_priv);
643 intel_bw_init_hw(dev_priv);
646 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
647 * This should be totally removed when we handle the pci states properly
648 * on runtime PM and on s2idle cases.
650 root_pdev = pcie_find_root_port(pdev);
652 pci_d3cold_disable(root_pdev);
657 if (pdev->msi_enabled)
658 pci_disable_msi(pdev);
660 intel_memory_regions_driver_release(dev_priv);
662 i915_ggtt_driver_release(dev_priv);
663 i915_gem_drain_freed_objects(dev_priv);
664 i915_ggtt_driver_late_release(dev_priv);
666 i915_perf_fini(dev_priv);
671 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
672 * @dev_priv: device private
674 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
676 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
677 struct pci_dev *root_pdev;
679 i915_perf_fini(dev_priv);
681 if (pdev->msi_enabled)
682 pci_disable_msi(pdev);
684 root_pdev = pcie_find_root_port(pdev);
686 pci_d3cold_enable(root_pdev);
690 * i915_driver_register - register the driver with the rest of the system
691 * @dev_priv: device private
693 * Perform any steps necessary to make the driver available via kernel
694 * internal or userspace interfaces.
696 static void i915_driver_register(struct drm_i915_private *dev_priv)
698 struct drm_device *dev = &dev_priv->drm;
700 i915_gem_driver_register(dev_priv);
701 i915_pmu_register(dev_priv);
703 intel_vgpu_register(dev_priv);
705 /* Reveal our presence to userspace */
706 if (drm_dev_register(dev, 0)) {
707 drm_err(&dev_priv->drm,
708 "Failed to register driver for userspace access!\n");
712 i915_debugfs_register(dev_priv);
713 i915_setup_sysfs(dev_priv);
715 /* Depends on sysfs having been initialized */
716 i915_perf_register(dev_priv);
718 intel_gt_driver_register(to_gt(dev_priv));
720 intel_display_driver_register(dev_priv);
722 intel_power_domains_enable(dev_priv);
723 intel_runtime_pm_enable(&dev_priv->runtime_pm);
725 intel_register_dsm_handler();
727 if (i915_switcheroo_register(dev_priv))
728 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
732 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
733 * @dev_priv: device private
735 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
737 i915_switcheroo_unregister(dev_priv);
739 intel_unregister_dsm_handler();
741 intel_runtime_pm_disable(&dev_priv->runtime_pm);
742 intel_power_domains_disable(dev_priv);
744 intel_display_driver_unregister(dev_priv);
746 intel_gt_driver_unregister(to_gt(dev_priv));
748 i915_perf_unregister(dev_priv);
749 i915_pmu_unregister(dev_priv);
751 i915_teardown_sysfs(dev_priv);
752 drm_dev_unplug(&dev_priv->drm);
754 i915_gem_driver_unregister(dev_priv);
758 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
760 drm_printf(p, "iommu: %s\n",
761 str_enabled_disabled(i915_vtd_active(i915)));
764 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
766 if (drm_debug_enabled(DRM_UT_DRIVER)) {
767 struct drm_printer p = drm_debug_printer("i915 device info:");
769 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
770 INTEL_DEVID(dev_priv),
771 INTEL_REVID(dev_priv),
772 intel_platform_name(INTEL_INFO(dev_priv)->platform),
773 intel_subplatform(RUNTIME_INFO(dev_priv),
774 INTEL_INFO(dev_priv)->platform),
775 GRAPHICS_VER(dev_priv));
777 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
778 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
779 i915_print_iommu_status(dev_priv, &p);
780 intel_gt_info_print(&to_gt(dev_priv)->info, &p);
783 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
784 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
785 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
786 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
787 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
788 drm_info(&dev_priv->drm,
789 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
792 static struct drm_i915_private *
793 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
795 const struct intel_device_info *match_info =
796 (struct intel_device_info *)ent->driver_data;
797 struct intel_device_info *device_info;
798 struct drm_i915_private *i915;
800 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
801 struct drm_i915_private, drm);
805 pci_set_drvdata(pdev, i915);
807 /* Device parameters start as a copy of module parameters. */
808 i915_params_copy(&i915->params, &i915_modparams);
810 /* Setup the write-once "constant" device info */
811 device_info = mkwrite_device_info(i915);
812 memcpy(device_info, match_info, sizeof(*device_info));
813 RUNTIME_INFO(i915)->device_id = pdev->device;
819 * i915_driver_probe - setup chip and create an initial config
821 * @ent: matching PCI ID entry
823 * The driver probe routine has to do several things:
824 * - drive output discovery via intel_modeset_init()
825 * - initialize the memory manager
826 * - allocate initial config memory
827 * - setup the DRM framebuffer with the allocated memory
829 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
831 const struct intel_device_info *match_info =
832 (struct intel_device_info *)ent->driver_data;
833 struct drm_i915_private *i915;
836 i915 = i915_driver_create(pdev, ent);
838 return PTR_ERR(i915);
840 /* Disable nuclear pageflip by default on pre-ILK */
841 if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5)
842 i915->drm.driver_features &= ~DRIVER_ATOMIC;
844 ret = pci_enable_device(pdev);
848 ret = i915_driver_early_probe(i915);
850 goto out_pci_disable;
852 disable_rpm_wakeref_asserts(&i915->runtime_pm);
854 intel_vgpu_detect(i915);
856 ret = intel_gt_probe_all(i915);
858 goto out_runtime_pm_put;
860 ret = i915_driver_mmio_probe(i915);
862 goto out_tiles_cleanup;
864 ret = i915_driver_hw_probe(i915);
866 goto out_cleanup_mmio;
868 ret = intel_modeset_init_noirq(i915);
872 ret = intel_irq_install(i915);
874 goto out_cleanup_modeset;
876 ret = intel_modeset_init_nogem(i915);
878 goto out_cleanup_irq;
880 ret = i915_gem_init(i915);
882 goto out_cleanup_modeset2;
884 ret = intel_modeset_init(i915);
886 goto out_cleanup_gem;
888 i915_driver_register(i915);
890 enable_rpm_wakeref_asserts(&i915->runtime_pm);
892 i915_welcome_messages(i915);
894 i915->do_release = true;
899 i915_gem_suspend(i915);
900 i915_gem_driver_remove(i915);
901 i915_gem_driver_release(i915);
902 out_cleanup_modeset2:
903 /* FIXME clean up the error path */
904 intel_modeset_driver_remove(i915);
905 intel_irq_uninstall(i915);
906 intel_modeset_driver_remove_noirq(i915);
907 goto out_cleanup_modeset;
909 intel_irq_uninstall(i915);
911 intel_modeset_driver_remove_nogem(i915);
913 i915_driver_hw_remove(i915);
914 intel_memory_regions_driver_release(i915);
915 i915_ggtt_driver_release(i915);
916 i915_gem_drain_freed_objects(i915);
917 i915_ggtt_driver_late_release(i915);
919 i915_driver_mmio_release(i915);
921 intel_gt_release_all(i915);
923 enable_rpm_wakeref_asserts(&i915->runtime_pm);
924 i915_driver_late_release(i915);
926 pci_disable_device(pdev);
928 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
932 void i915_driver_remove(struct drm_i915_private *i915)
934 disable_rpm_wakeref_asserts(&i915->runtime_pm);
936 i915_driver_unregister(i915);
938 /* Flush any external code that still may be under the RCU lock */
941 i915_gem_suspend(i915);
943 intel_gvt_driver_remove(i915);
945 intel_modeset_driver_remove(i915);
947 intel_irq_uninstall(i915);
949 intel_modeset_driver_remove_noirq(i915);
951 i915_reset_error_state(i915);
952 i915_gem_driver_remove(i915);
954 intel_modeset_driver_remove_nogem(i915);
956 i915_driver_hw_remove(i915);
958 enable_rpm_wakeref_asserts(&i915->runtime_pm);
961 static void i915_driver_release(struct drm_device *dev)
963 struct drm_i915_private *dev_priv = to_i915(dev);
964 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
966 if (!dev_priv->do_release)
969 disable_rpm_wakeref_asserts(rpm);
971 i915_gem_driver_release(dev_priv);
973 intel_memory_regions_driver_release(dev_priv);
974 i915_ggtt_driver_release(dev_priv);
975 i915_gem_drain_freed_objects(dev_priv);
976 i915_ggtt_driver_late_release(dev_priv);
978 i915_driver_mmio_release(dev_priv);
980 enable_rpm_wakeref_asserts(rpm);
981 intel_runtime_pm_driver_release(rpm);
983 i915_driver_late_release(dev_priv);
986 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
988 struct drm_i915_private *i915 = to_i915(dev);
991 ret = i915_gem_open(i915, file);
999 * i915_driver_lastclose - clean up after all DRM clients have exited
1002 * Take care of cleaning up after all DRM clients have exited. In the
1003 * mode setting case, we want to restore the kernel's initial mode (just
1004 * in case the last client left us in a bad state).
1006 * Additionally, in the non-mode setting case, we'll tear down the GTT
1007 * and DMA structures, since the kernel won't be using them, and clea
1010 static void i915_driver_lastclose(struct drm_device *dev)
1012 struct drm_i915_private *i915 = to_i915(dev);
1014 intel_fbdev_restore_mode(dev);
1016 if (HAS_DISPLAY(i915))
1017 vga_switcheroo_process_delayed_switch();
1020 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1022 struct drm_i915_file_private *file_priv = file->driver_priv;
1024 i915_gem_context_close(file);
1025 i915_drm_client_put(file_priv->client);
1027 kfree_rcu(file_priv, rcu);
1029 /* Catch up with all the deferred frees from "this" client */
1030 i915_gem_flush_free_objects(to_i915(dev));
1033 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1035 struct drm_device *dev = &dev_priv->drm;
1036 struct intel_encoder *encoder;
1038 if (!HAS_DISPLAY(dev_priv))
1041 drm_modeset_lock_all(dev);
1042 for_each_intel_encoder(dev, encoder)
1043 if (encoder->suspend)
1044 encoder->suspend(encoder);
1045 drm_modeset_unlock_all(dev);
1048 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1050 struct drm_device *dev = &dev_priv->drm;
1051 struct intel_encoder *encoder;
1053 if (!HAS_DISPLAY(dev_priv))
1056 drm_modeset_lock_all(dev);
1057 for_each_intel_encoder(dev, encoder)
1058 if (encoder->shutdown)
1059 encoder->shutdown(encoder);
1060 drm_modeset_unlock_all(dev);
1063 void i915_driver_shutdown(struct drm_i915_private *i915)
1065 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1066 intel_runtime_pm_disable(&i915->runtime_pm);
1067 intel_power_domains_disable(i915);
1069 i915_gem_suspend(i915);
1071 if (HAS_DISPLAY(i915)) {
1072 drm_kms_helper_poll_disable(&i915->drm);
1074 drm_atomic_helper_shutdown(&i915->drm);
1077 intel_dp_mst_suspend(i915);
1079 intel_runtime_pm_disable_interrupts(i915);
1080 intel_hpd_cancel_work(i915);
1082 intel_suspend_encoders(i915);
1083 intel_shutdown_encoders(i915);
1085 intel_dmc_ucode_suspend(i915);
1088 * The only requirement is to reboot with display DC states disabled,
1089 * for now leaving all display power wells in the INIT power domain
1093 * - unify the pci_driver::shutdown sequence here with the
1094 * pci_driver.driver.pm.poweroff,poweroff_late sequence.
1095 * - unify the driver remove and system/runtime suspend sequences with
1096 * the above unified shutdown/poweroff sequence.
1098 intel_power_domains_driver_remove(i915);
1099 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1101 intel_runtime_pm_driver_release(&i915->runtime_pm);
1104 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1106 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1107 if (acpi_target_system_state() < ACPI_STATE_S3)
1113 static int i915_drm_prepare(struct drm_device *dev)
1115 struct drm_i915_private *i915 = to_i915(dev);
1118 * NB intel_display_suspend() may issue new requests after we've
1119 * ostensibly marked the GPU as ready-to-sleep here. We need to
1120 * split out that work and pull it forward so that after point,
1121 * the GPU is not woken again.
1123 return i915_gem_backup_suspend(i915);
1126 static int i915_drm_suspend(struct drm_device *dev)
1128 struct drm_i915_private *dev_priv = to_i915(dev);
1129 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1130 pci_power_t opregion_target_state;
1132 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1134 /* We do a lot of poking in a lot of registers, make sure they work
1136 intel_power_domains_disable(dev_priv);
1137 if (HAS_DISPLAY(dev_priv))
1138 drm_kms_helper_poll_disable(dev);
1140 pci_save_state(pdev);
1142 intel_display_suspend(dev);
1144 intel_dp_mst_suspend(dev_priv);
1146 intel_runtime_pm_disable_interrupts(dev_priv);
1147 intel_hpd_cancel_work(dev_priv);
1149 intel_suspend_encoders(dev_priv);
1151 intel_suspend_hw(dev_priv);
1153 /* Must be called before GGTT is suspended. */
1154 intel_dpt_suspend(dev_priv);
1155 i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1157 i915_save_display(dev_priv);
1159 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1160 intel_opregion_suspend(dev_priv, opregion_target_state);
1162 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1164 dev_priv->suspend_count++;
1166 intel_dmc_ucode_suspend(dev_priv);
1168 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1173 static enum i915_drm_suspend_mode
1174 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1177 return I915_DRM_SUSPEND_HIBERNATE;
1179 if (suspend_to_idle(dev_priv))
1180 return I915_DRM_SUSPEND_IDLE;
1182 return I915_DRM_SUSPEND_MEM;
1185 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1187 struct drm_i915_private *dev_priv = to_i915(dev);
1188 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1189 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1192 disable_rpm_wakeref_asserts(rpm);
1194 i915_gem_suspend_late(dev_priv);
1196 intel_uncore_suspend(&dev_priv->uncore);
1198 intel_power_domains_suspend(dev_priv,
1199 get_suspend_mode(dev_priv, hibernation));
1201 intel_display_power_suspend_late(dev_priv);
1203 ret = vlv_suspend_complete(dev_priv);
1205 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1206 intel_power_domains_resume(dev_priv);
1211 pci_disable_device(pdev);
1213 * During hibernation on some platforms the BIOS may try to access
1214 * the device even though it's already in D3 and hang the machine. So
1215 * leave the device in D0 on those platforms and hope the BIOS will
1216 * power down the device properly. The issue was seen on multiple old
1217 * GENs with different BIOS vendors, so having an explicit blacklist
1218 * is inpractical; apply the workaround on everything pre GEN6. The
1219 * platforms where the issue was seen:
1220 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1224 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1225 pci_set_power_state(pdev, PCI_D3hot);
1228 enable_rpm_wakeref_asserts(rpm);
1229 if (!dev_priv->uncore.user_forcewake_count)
1230 intel_runtime_pm_driver_release(rpm);
1235 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1240 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1241 state.event != PM_EVENT_FREEZE))
1244 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1247 error = i915_drm_suspend(&i915->drm);
1251 return i915_drm_suspend_late(&i915->drm, false);
1254 static int i915_drm_resume(struct drm_device *dev)
1256 struct drm_i915_private *dev_priv = to_i915(dev);
1259 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1261 ret = intel_pcode_init(dev_priv);
1265 sanitize_gpu(dev_priv);
1267 ret = i915_ggtt_enable_hw(dev_priv);
1269 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1271 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1272 /* Must be called after GGTT is resumed. */
1273 intel_dpt_resume(dev_priv);
1275 intel_dmc_ucode_resume(dev_priv);
1277 i915_restore_display(dev_priv);
1278 intel_pps_unlock_regs_wa(dev_priv);
1280 intel_init_pch_refclk(dev_priv);
1283 * Interrupts have to be enabled before any batches are run. If not the
1284 * GPU will hang. i915_gem_init_hw() will initiate batches to
1285 * update/restore the context.
1287 * drm_mode_config_reset() needs AUX interrupts.
1289 * Modeset enabling in intel_modeset_init_hw() also needs working
1292 intel_runtime_pm_enable_interrupts(dev_priv);
1294 if (HAS_DISPLAY(dev_priv))
1295 drm_mode_config_reset(dev);
1297 i915_gem_resume(dev_priv);
1299 intel_modeset_init_hw(dev_priv);
1300 intel_init_clock_gating(dev_priv);
1301 intel_hpd_init(dev_priv);
1303 /* MST sideband requires HPD interrupts enabled */
1304 intel_dp_mst_resume(dev_priv);
1305 intel_display_resume(dev);
1307 intel_hpd_poll_disable(dev_priv);
1308 if (HAS_DISPLAY(dev_priv))
1309 drm_kms_helper_poll_enable(dev);
1311 intel_opregion_resume(dev_priv);
1313 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1315 intel_power_domains_enable(dev_priv);
1317 intel_gvt_resume(dev_priv);
1319 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1324 static int i915_drm_resume_early(struct drm_device *dev)
1326 struct drm_i915_private *dev_priv = to_i915(dev);
1327 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1331 * We have a resume ordering issue with the snd-hda driver also
1332 * requiring our device to be power up. Due to the lack of a
1333 * parent/child relationship we currently solve this with an early
1336 * FIXME: This should be solved with a special hdmi sink device or
1337 * similar so that power domains can be employed.
1341 * Note that we need to set the power state explicitly, since we
1342 * powered off the device during freeze and the PCI core won't power
1343 * it back up for us during thaw. Powering off the device during
1344 * freeze is not a hard requirement though, and during the
1345 * suspend/resume phases the PCI core makes sure we get here with the
1346 * device powered on. So in case we change our freeze logic and keep
1347 * the device powered we can also remove the following set power state
1350 ret = pci_set_power_state(pdev, PCI_D0);
1352 drm_err(&dev_priv->drm,
1353 "failed to set PCI D0 power state (%d)\n", ret);
1358 * Note that pci_enable_device() first enables any parent bridge
1359 * device and only then sets the power state for this device. The
1360 * bridge enabling is a nop though, since bridge devices are resumed
1361 * first. The order of enabling power and enabling the device is
1362 * imposed by the PCI core as described above, so here we preserve the
1363 * same order for the freeze/thaw phases.
1365 * TODO: eventually we should remove pci_disable_device() /
1366 * pci_enable_enable_device() from suspend/resume. Due to how they
1367 * depend on the device enable refcount we can't anyway depend on them
1368 * disabling/enabling the device.
1370 if (pci_enable_device(pdev))
1373 pci_set_master(pdev);
1375 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1377 ret = vlv_resume_prepare(dev_priv, false);
1379 drm_err(&dev_priv->drm,
1380 "Resume prepare failed: %d, continuing anyway\n", ret);
1382 intel_uncore_resume_early(&dev_priv->uncore);
1384 intel_gt_check_and_clear_faults(to_gt(dev_priv));
1386 intel_display_power_resume_early(dev_priv);
1388 intel_power_domains_resume(dev_priv);
1390 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1395 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1399 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1402 ret = i915_drm_resume_early(&i915->drm);
1406 return i915_drm_resume(&i915->drm);
1409 static int i915_pm_prepare(struct device *kdev)
1411 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1414 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1418 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1421 return i915_drm_prepare(&i915->drm);
1424 static int i915_pm_suspend(struct device *kdev)
1426 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1429 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1433 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1436 return i915_drm_suspend(&i915->drm);
1439 static int i915_pm_suspend_late(struct device *kdev)
1441 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1444 * We have a suspend ordering issue with the snd-hda driver also
1445 * requiring our device to be power up. Due to the lack of a
1446 * parent/child relationship we currently solve this with an late
1449 * FIXME: This should be solved with a special hdmi sink device or
1450 * similar so that power domains can be employed.
1452 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1455 return i915_drm_suspend_late(&i915->drm, false);
1458 static int i915_pm_poweroff_late(struct device *kdev)
1460 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1462 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1465 return i915_drm_suspend_late(&i915->drm, true);
1468 static int i915_pm_resume_early(struct device *kdev)
1470 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1472 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1475 return i915_drm_resume_early(&i915->drm);
1478 static int i915_pm_resume(struct device *kdev)
1480 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1482 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1485 return i915_drm_resume(&i915->drm);
1488 /* freeze: before creating the hibernation_image */
1489 static int i915_pm_freeze(struct device *kdev)
1491 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1494 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1495 ret = i915_drm_suspend(&i915->drm);
1500 ret = i915_gem_freeze(i915);
1507 static int i915_pm_freeze_late(struct device *kdev)
1509 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1512 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1513 ret = i915_drm_suspend_late(&i915->drm, true);
1518 ret = i915_gem_freeze_late(i915);
1525 /* thaw: called after creating the hibernation image, but before turning off. */
1526 static int i915_pm_thaw_early(struct device *kdev)
1528 return i915_pm_resume_early(kdev);
1531 static int i915_pm_thaw(struct device *kdev)
1533 return i915_pm_resume(kdev);
1536 /* restore: called after loading the hibernation image. */
1537 static int i915_pm_restore_early(struct device *kdev)
1539 return i915_pm_resume_early(kdev);
1542 static int i915_pm_restore(struct device *kdev)
1544 return i915_pm_resume(kdev);
1547 static int intel_runtime_suspend(struct device *kdev)
1549 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1550 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1553 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1556 drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1558 disable_rpm_wakeref_asserts(rpm);
1561 * We are safe here against re-faults, since the fault handler takes
1564 i915_gem_runtime_suspend(dev_priv);
1566 intel_gt_runtime_suspend(to_gt(dev_priv));
1568 intel_runtime_pm_disable_interrupts(dev_priv);
1570 intel_uncore_suspend(&dev_priv->uncore);
1572 intel_display_power_suspend(dev_priv);
1574 ret = vlv_suspend_complete(dev_priv);
1576 drm_err(&dev_priv->drm,
1577 "Runtime suspend failed, disabling it (%d)\n", ret);
1578 intel_uncore_runtime_resume(&dev_priv->uncore);
1580 intel_runtime_pm_enable_interrupts(dev_priv);
1582 intel_gt_runtime_resume(to_gt(dev_priv));
1584 enable_rpm_wakeref_asserts(rpm);
1589 enable_rpm_wakeref_asserts(rpm);
1590 intel_runtime_pm_driver_release(rpm);
1592 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1593 drm_err(&dev_priv->drm,
1594 "Unclaimed access detected prior to suspending\n");
1596 rpm->suspended = true;
1599 * FIXME: We really should find a document that references the arguments
1602 if (IS_BROADWELL(dev_priv)) {
1604 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1605 * being detected, and the call we do at intel_runtime_resume()
1606 * won't be able to restore them. Since PCI_D3hot matches the
1607 * actual specification and appears to be working, use it.
1609 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1612 * current versions of firmware which depend on this opregion
1613 * notification have repurposed the D1 definition to mean
1614 * "runtime suspended" vs. what you would normally expect (D3)
1615 * to distinguish it from notifications that might be sent via
1618 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1621 assert_forcewakes_inactive(&dev_priv->uncore);
1623 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1624 intel_hpd_poll_enable(dev_priv);
1626 drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1630 static int intel_runtime_resume(struct device *kdev)
1632 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1633 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1636 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1639 drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1641 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1642 disable_rpm_wakeref_asserts(rpm);
1644 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1645 rpm->suspended = false;
1646 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1647 drm_dbg(&dev_priv->drm,
1648 "Unclaimed access during suspend, bios?\n");
1650 intel_display_power_resume(dev_priv);
1652 ret = vlv_resume_prepare(dev_priv, true);
1654 intel_uncore_runtime_resume(&dev_priv->uncore);
1656 intel_runtime_pm_enable_interrupts(dev_priv);
1659 * No point of rolling back things in case of an error, as the best
1660 * we can do is to hope that things will still work (and disable RPM).
1662 intel_gt_runtime_resume(to_gt(dev_priv));
1665 * On VLV/CHV display interrupts are part of the display
1666 * power well, so hpd is reinitialized from there. For
1667 * everyone else do it here.
1669 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1670 intel_hpd_init(dev_priv);
1671 intel_hpd_poll_disable(dev_priv);
1674 intel_enable_ipc(dev_priv);
1676 enable_rpm_wakeref_asserts(rpm);
1679 drm_err(&dev_priv->drm,
1680 "Runtime resume failed, disabling it (%d)\n", ret);
1682 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1687 const struct dev_pm_ops i915_pm_ops = {
1689 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1692 .prepare = i915_pm_prepare,
1693 .suspend = i915_pm_suspend,
1694 .suspend_late = i915_pm_suspend_late,
1695 .resume_early = i915_pm_resume_early,
1696 .resume = i915_pm_resume,
1700 * @freeze, @freeze_late : called (1) before creating the
1701 * hibernation image [PMSG_FREEZE] and
1702 * (2) after rebooting, before restoring
1703 * the image [PMSG_QUIESCE]
1704 * @thaw, @thaw_early : called (1) after creating the hibernation
1705 * image, before writing it [PMSG_THAW]
1706 * and (2) after failing to create or
1707 * restore the image [PMSG_RECOVER]
1708 * @poweroff, @poweroff_late: called after writing the hibernation
1709 * image, before rebooting [PMSG_HIBERNATE]
1710 * @restore, @restore_early : called after rebooting and restoring the
1711 * hibernation image [PMSG_RESTORE]
1713 .freeze = i915_pm_freeze,
1714 .freeze_late = i915_pm_freeze_late,
1715 .thaw_early = i915_pm_thaw_early,
1716 .thaw = i915_pm_thaw,
1717 .poweroff = i915_pm_suspend,
1718 .poweroff_late = i915_pm_poweroff_late,
1719 .restore_early = i915_pm_restore_early,
1720 .restore = i915_pm_restore,
1722 /* S0ix (via runtime suspend) event handlers */
1723 .runtime_suspend = intel_runtime_suspend,
1724 .runtime_resume = intel_runtime_resume,
1727 static const struct file_operations i915_driver_fops = {
1728 .owner = THIS_MODULE,
1730 .release = drm_release_noglobal,
1731 .unlocked_ioctl = drm_ioctl,
1732 .mmap = i915_gem_mmap,
1735 .compat_ioctl = i915_ioc32_compat_ioctl,
1736 .llseek = noop_llseek,
1737 #ifdef CONFIG_PROC_FS
1738 .show_fdinfo = i915_drm_client_fdinfo,
1743 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1744 struct drm_file *file)
1749 static const struct drm_ioctl_desc i915_ioctls[] = {
1750 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1751 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1752 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1753 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1754 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1755 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1756 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1757 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1758 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1759 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1760 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1761 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1762 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1763 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1764 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1765 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1766 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1767 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1768 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1769 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1770 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1771 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1772 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1773 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1774 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1775 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1776 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1777 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1778 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1779 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1780 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1781 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1782 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1783 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1784 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1785 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1786 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1787 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1788 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1789 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1790 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1791 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1792 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1793 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1794 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1795 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1796 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1797 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1798 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1799 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1800 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1801 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1802 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1803 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1804 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1805 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1806 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1807 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1808 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1812 * Interface history:
1815 * 1.2: Add Power Management
1816 * 1.3: Add vblank support
1817 * 1.4: Fix cmdbuffer path, add heap destroy
1818 * 1.5: Add vblank pipe configuration
1819 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1820 * - Support vertical blank on secondary display pipe
1822 #define DRIVER_MAJOR 1
1823 #define DRIVER_MINOR 6
1824 #define DRIVER_PATCHLEVEL 0
1826 static const struct drm_driver i915_drm_driver = {
1827 /* Don't use MTRRs here; the Xserver or userspace app should
1828 * deal with them for Intel hardware.
1832 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1833 DRIVER_SYNCOBJ_TIMELINE,
1834 .release = i915_driver_release,
1835 .open = i915_driver_open,
1836 .lastclose = i915_driver_lastclose,
1837 .postclose = i915_driver_postclose,
1839 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1840 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1841 .gem_prime_import = i915_gem_prime_import,
1843 .dumb_create = i915_gem_dumb_create,
1844 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1846 .ioctls = i915_ioctls,
1847 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1848 .fops = &i915_driver_fops,
1849 .name = DRIVER_NAME,
1850 .desc = DRIVER_DESC,
1851 .date = DRIVER_DATE,
1852 .major = DRIVER_MAJOR,
1853 .minor = DRIVER_MINOR,
1854 .patchlevel = DRIVER_PATCHLEVEL,