drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc_helper.h"
  34 #include "drm_fb_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include "../../../platform/x86/intel_ips.h"
  40 #include <linux/pci.h>
  41 #include <linux/vgaarb.h>
  42 #include <linux/acpi.h>
  43 #include <linux/pnp.h>
  44 #include <linux/vga_switcheroo.h>
  45 #include <linux/slab.h>
  46 #include <linux/module.h>
  47 #include <acpi/video.h>
  48 #include <asm/pat.h>
  49
  50 static void i915_write_hws_pga(struct drm_device *dev)
  51 {
  52         drm_i915_private_t *dev_priv = dev->dev_private;
  53         u32 addr;
  54
  55         addr = dev_priv->status_page_dmah->busaddr;
  56         if (INTEL_INFO(dev)->gen >= 4)
  57                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  58         I915_WRITE(HWS_PGA, addr);
  59 }
  60
  61 /**
  62  * Sets up the hardware status page for devices that need a physical address
  63  * in the register.
  64  */
  65 static int i915_init_phys_hws(struct drm_device *dev)
  66 {
  67         drm_i915_private_t *dev_priv = dev->dev_private;
  68
  69         /* Program Hardware Status Page */
  70         dev_priv->status_page_dmah =
  71                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  72
  73         if (!dev_priv->status_page_dmah) {
  74                 DRM_ERROR("Can not allocate hardware status page\n");
  75                 return -ENOMEM;
  76         }
  77
  78         memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
  79                   0, PAGE_SIZE);
  80
  81         i915_write_hws_pga(dev);
  82
  83         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  84         return 0;
  85 }
  86
  87 /**
  88  * Frees the hardware status page, whether it's a physical address or a virtual
  89  * address set up by the X Server.
  90  */
  91 static void i915_free_hws(struct drm_device *dev)
  92 {
  93         drm_i915_private_t *dev_priv = dev->dev_private;
  94         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  95
  96         if (dev_priv->status_page_dmah) {
  97                 drm_pci_free(dev, dev_priv->status_page_dmah);
  98                 dev_priv->status_page_dmah = NULL;
  99         }
 100
 101         if (ring->status_page.gfx_addr) {
 102                 ring->status_page.gfx_addr = 0;
 103                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 104         }
 105
 106         /* Need to rewrite hardware status page */
 107         I915_WRITE(HWS_PGA, 0x1ffff000);
 108 }
 109
 110 void i915_kernel_lost_context(struct drm_device * dev)
 111 {
 112         drm_i915_private_t *dev_priv = dev->dev_private;
 113         struct drm_i915_master_private *master_priv;
 114         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 115
 116         /*
 117          * We should never lose context on the ring with modesetting
 118          * as we don't expose it to userspace
 119          */
 120         if (drm_core_check_feature(dev, DRIVER_MODESET))
 121                 return;
 122
 123         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 124         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 125         ring->space = ring->head - (ring->tail + 8);
 126         if (ring->space < 0)
 127                 ring->space += ring->size;
 128
 129         if (!dev->primary->master)
 130                 return;
 131
 132         master_priv = dev->primary->master->driver_priv;
 133         if (ring->head == ring->tail && master_priv->sarea_priv)
 134                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 135 }
 136
 137 static int i915_dma_cleanup(struct drm_device * dev)
 138 {
 139         drm_i915_private_t *dev_priv = dev->dev_private;
 140         int i;
 141
 142         /* Make sure interrupts are disabled here because the uninstall ioctl
 143          * may not have been called from userspace and after dev_private
 144          * is freed, it's too late.
 145          */
 146         if (dev->irq_enabled)
 147                 drm_irq_uninstall(dev);
 148
 149         mutex_lock(&dev->struct_mutex);
 150         for (i = 0; i < I915_NUM_RINGS; i++)
 151                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 152         mutex_unlock(&dev->struct_mutex);
 153
 154         /* Clear the HWS virtual address at teardown */
 155         if (I915_NEED_GFX_HWS(dev))
 156                 i915_free_hws(dev);
 157
 158         return 0;
 159 }
 160
 161 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 162 {
 163         drm_i915_private_t *dev_priv = dev->dev_private;
 164         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 165         int ret;
 166
 167         master_priv->sarea = drm_getsarea(dev);
 168         if (master_priv->sarea) {
 169                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 170                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 171         } else {
 172                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 173         }
 174
 175         if (init->ring_size != 0) {
 176                 if (LP_RING(dev_priv)->obj != NULL) {
 177                         i915_dma_cleanup(dev);
 178                         DRM_ERROR("Client tried to initialize ringbuffer in "
 179                                   "GEM mode\n");
 180                         return -EINVAL;
 181                 }
 182
 183                 ret = intel_render_ring_init_dri(dev,
 184                                                  init->ring_start,
 185                                                  init->ring_size);
 186                 if (ret) {
 187                         i915_dma_cleanup(dev);
 188                         return ret;
 189                 }
 190         }
 191
 192         dev_priv->cpp = init->cpp;
 193         dev_priv->back_offset = init->back_offset;
 194         dev_priv->front_offset = init->front_offset;
 195         dev_priv->current_page = 0;
 196         if (master_priv->sarea_priv)
 197                 master_priv->sarea_priv->pf_current_page = 0;
 198
 199         /* Allow hardware batchbuffers unless told otherwise.
 200          */
 201         dev_priv->allow_batchbuffer = 1;
 202
 203         return 0;
 204 }
 205
 206 static int i915_dma_resume(struct drm_device * dev)
 207 {
 208         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 209         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 210
 211         DRM_DEBUG_DRIVER("%s\n", __func__);
 212
 213         if (ring->map.handle == NULL) {
 214                 DRM_ERROR("can not ioremap virtual address for"
 215                           " ring buffer\n");
 216                 return -ENOMEM;
 217         }
 218
 219         /* Program Hardware Status Page */
 220         if (!ring->status_page.page_addr) {
 221                 DRM_ERROR("Can not find hardware status page\n");
 222                 return -EINVAL;
 223         }
 224         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 225                                 ring->status_page.page_addr);
 226         if (ring->status_page.gfx_addr != 0)
 227                 intel_ring_setup_status_page(ring);
 228         else
 229                 i915_write_hws_pga(dev);
 230
 231         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 232
 233         return 0;
 234 }
 235
 236 static int i915_dma_init(struct drm_device *dev, void *data,
 237                          struct drm_file *file_priv)
 238 {
 239         drm_i915_init_t *init = data;
 240         int retcode = 0;
 241
 242         switch (init->func) {
 243         case I915_INIT_DMA:
 244                 retcode = i915_initialize(dev, init);
 245                 break;
 246         case I915_CLEANUP_DMA:
 247                 retcode = i915_dma_cleanup(dev);
 248                 break;
 249         case I915_RESUME_DMA:
 250                 retcode = i915_dma_resume(dev);
 251                 break;
 252         default:
 253                 retcode = -EINVAL;
 254                 break;
 255         }
 256
 257         return retcode;
 258 }
 259
 260 /* Implement basically the same security restrictions as hardware does
 261  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 262  *
 263  * Most of the calculations below involve calculating the size of a
 264  * particular instruction.  It's important to get the size right as
 265  * that tells us where the next instruction to check is.  Any illegal
 266  * instruction detected will be given a size of zero, which is a
 267  * signal to abort the rest of the buffer.
 268  */
 269 static int validate_cmd(int cmd)
 270 {
 271         switch (((cmd >> 29) & 0x7)) {
 272         case 0x0:
 273                 switch ((cmd >> 23) & 0x3f) {
 274                 case 0x0:
 275                         return 1;       /* MI_NOOP */
 276                 case 0x4:
 277                         return 1;       /* MI_FLUSH */
 278                 default:
 279                         return 0;       /* disallow everything else */
 280                 }
 281                 break;
 282         case 0x1:
 283                 return 0;       /* reserved */
 284         case 0x2:
 285                 return (cmd & 0xff) + 2;        /* 2d commands */
 286         case 0x3:
 287                 if (((cmd >> 24) & 0x1f) <= 0x18)
 288                         return 1;
 289
 290                 switch ((cmd >> 24) & 0x1f) {
 291                 case 0x1c:
 292                         return 1;
 293                 case 0x1d:
 294                         switch ((cmd >> 16) & 0xff) {
 295                         case 0x3:
 296                                 return (cmd & 0x1f) + 2;
 297                         case 0x4:
 298                                 return (cmd & 0xf) + 2;
 299                         default:
 300                                 return (cmd & 0xffff) + 2;
 301                         }
 302                 case 0x1e:
 303                         if (cmd & (1 << 23))
 304                                 return (cmd & 0xffff) + 1;
 305                         else
 306                                 return 1;
 307                 case 0x1f:
 308                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 309                                 return (cmd & 0x1ffff) + 2;
 310                         else if (cmd & (1 << 17))       /* indirect random */
 311                                 if ((cmd & 0xffff) == 0)
 312                                         return 0;       /* unknown length, too hard */
 313                                 else
 314                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 315                         else
 316                                 return 2;       /* indirect sequential */
 317                 default:
 318                         return 0;
 319                 }
 320         default:
 321                 return 0;
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 328 {
 329         drm_i915_private_t *dev_priv = dev->dev_private;
 330         int i, ret;
 331
 332         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 333                 return -EINVAL;
 334
 335         for (i = 0; i < dwords;) {
 336                 int sz = validate_cmd(buffer[i]);
 337                 if (sz == 0 || i + sz > dwords)
 338                         return -EINVAL;
 339                 i += sz;
 340         }
 341
 342         ret = BEGIN_LP_RING((dwords+1)&~1);
 343         if (ret)
 344                 return ret;
 345
 346         for (i = 0; i < dwords; i++)
 347                 OUT_RING(buffer[i]);
 348         if (dwords & 1)
 349                 OUT_RING(0);
 350
 351         ADVANCE_LP_RING();
 352
 353         return 0;
 354 }
 355
 356 int
 357 i915_emit_box(struct drm_device *dev,
 358               struct drm_clip_rect *box,
 359               int DR1, int DR4)
 360 {
 361         struct drm_i915_private *dev_priv = dev->dev_private;
 362         int ret;
 363
 364         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 365             box->y2 <= 0 || box->x2 <= 0) {
 366                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 367                           box->x1, box->y1, box->x2, box->y2);
 368                 return -EINVAL;
 369         }
 370
 371         if (INTEL_INFO(dev)->gen >= 4) {
 372                 ret = BEGIN_LP_RING(4);
 373                 if (ret)
 374                         return ret;
 375
 376                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 377                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 378                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 379                 OUT_RING(DR4);
 380         } else {
 381                 ret = BEGIN_LP_RING(6);
 382                 if (ret)
 383                         return ret;
 384
 385                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 386                 OUT_RING(DR1);
 387                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 388                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 389                 OUT_RING(DR4);
 390                 OUT_RING(0);
 391         }
 392         ADVANCE_LP_RING();
 393
 394         return 0;
 395 }
 396
 397 /* XXX: Emitting the counter should really be moved to part of the IRQ
 398  * emit. For now, do it in both places:
 399  */
 400
 401 static void i915_emit_breadcrumb(struct drm_device *dev)
 402 {
 403         drm_i915_private_t *dev_priv = dev->dev_private;
 404         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 405
 406         dev_priv->counter++;
 407         if (dev_priv->counter > 0x7FFFFFFFUL)
 408                 dev_priv->counter = 0;
 409         if (master_priv->sarea_priv)
 410                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 411
 412         if (BEGIN_LP_RING(4) == 0) {
 413                 OUT_RING(MI_STORE_DWORD_INDEX);
 414                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 415                 OUT_RING(dev_priv->counter);
 416                 OUT_RING(0);
 417                 ADVANCE_LP_RING();
 418         }
 419 }
 420
 421 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 422                                    drm_i915_cmdbuffer_t *cmd,
 423                                    struct drm_clip_rect *cliprects,
 424                                    void *cmdbuf)
 425 {
 426         int nbox = cmd->num_cliprects;
 427         int i = 0, count, ret;
 428
 429         if (cmd->sz & 0x3) {
 430                 DRM_ERROR("alignment");
 431                 return -EINVAL;
 432         }
 433
 434         i915_kernel_lost_context(dev);
 435
 436         count = nbox ? nbox : 1;
 437
 438         for (i = 0; i < count; i++) {
 439                 if (i < nbox) {
 440                         ret = i915_emit_box(dev, &cliprects[i],
 441                                             cmd->DR1, cmd->DR4);
 442                         if (ret)
 443                                 return ret;
 444                 }
 445
 446                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 447                 if (ret)
 448                         return ret;
 449         }
 450
 451         i915_emit_breadcrumb(dev);
 452         return 0;
 453 }
 454
 455 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 456                                      drm_i915_batchbuffer_t * batch,
 457                                      struct drm_clip_rect *cliprects)
 458 {
 459         struct drm_i915_private *dev_priv = dev->dev_private;
 460         int nbox = batch->num_cliprects;
 461         int i, count, ret;
 462
 463         if ((batch->start | batch->used) & 0x7) {
 464                 DRM_ERROR("alignment");
 465                 return -EINVAL;
 466         }
 467
 468         i915_kernel_lost_context(dev);
 469
 470         count = nbox ? nbox : 1;
 471         for (i = 0; i < count; i++) {
 472                 if (i < nbox) {
 473                         ret = i915_emit_box(dev, &cliprects[i],
 474                                             batch->DR1, batch->DR4);
 475                         if (ret)
 476                                 return ret;
 477                 }
 478
 479                 if (!IS_I830(dev) && !IS_845G(dev)) {
 480                         ret = BEGIN_LP_RING(2);
 481                         if (ret)
 482                                 return ret;
 483
 484                         if (INTEL_INFO(dev)->gen >= 4) {
 485                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 486                                 OUT_RING(batch->start);
 487                         } else {
 488                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 489                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 490                         }
 491                 } else {
 492                         ret = BEGIN_LP_RING(4);
 493                         if (ret)
 494                                 return ret;
 495
 496                         OUT_RING(MI_BATCH_BUFFER);
 497                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 498                         OUT_RING(batch->start + batch->used - 4);
 499                         OUT_RING(0);
 500                 }
 501                 ADVANCE_LP_RING();
 502         }
 503
 504
 505         if (IS_G4X(dev) || IS_GEN5(dev)) {
 506                 if (BEGIN_LP_RING(2) == 0) {
 507                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 508                         OUT_RING(MI_NOOP);
 509                         ADVANCE_LP_RING();
 510                 }
 511         }
 512
 513         i915_emit_breadcrumb(dev);
 514         return 0;
 515 }
 516
 517 static int i915_dispatch_flip(struct drm_device * dev)
 518 {
 519         drm_i915_private_t *dev_priv = dev->dev_private;
 520         struct drm_i915_master_private *master_priv =
 521                 dev->primary->master->driver_priv;
 522         int ret;
 523
 524         if (!master_priv->sarea_priv)
 525                 return -EINVAL;
 526
 527         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 528                           __func__,
 529                          dev_priv->current_page,
 530                          master_priv->sarea_priv->pf_current_page);
 531
 532         i915_kernel_lost_context(dev);
 533
 534         ret = BEGIN_LP_RING(10);
 535         if (ret)
 536                 return ret;
 537
 538         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 539         OUT_RING(0);
 540
 541         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 542         OUT_RING(0);
 543         if (dev_priv->current_page == 0) {
 544                 OUT_RING(dev_priv->back_offset);
 545                 dev_priv->current_page = 1;
 546         } else {
 547                 OUT_RING(dev_priv->front_offset);
 548                 dev_priv->current_page = 0;
 549         }
 550         OUT_RING(0);
 551
 552         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 553         OUT_RING(0);
 554
 555         ADVANCE_LP_RING();
 556
 557         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 558
 559         if (BEGIN_LP_RING(4) == 0) {
 560                 OUT_RING(MI_STORE_DWORD_INDEX);
 561                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 562                 OUT_RING(dev_priv->counter);
 563                 OUT_RING(0);
 564                 ADVANCE_LP_RING();
 565         }
 566
 567         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 568         return 0;
 569 }
 570
 571 static int i915_quiescent(struct drm_device *dev)
 572 {
 573         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 574
 575         i915_kernel_lost_context(dev);
 576         return intel_wait_ring_idle(ring);
 577 }
 578
 579 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 580                             struct drm_file *file_priv)
 581 {
 582         int ret;
 583
 584         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 585
 586         mutex_lock(&dev->struct_mutex);
 587         ret = i915_quiescent(dev);
 588         mutex_unlock(&dev->struct_mutex);
 589
 590         return ret;
 591 }
 592
 593 static int i915_batchbuffer(struct drm_device *dev, void *data,
 594                             struct drm_file *file_priv)
 595 {
 596         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 597         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 598         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 599             master_priv->sarea_priv;
 600         drm_i915_batchbuffer_t *batch = data;
 601         int ret;
 602         struct drm_clip_rect *cliprects = NULL;
 603
 604         if (!dev_priv->allow_batchbuffer) {
 605                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 606                 return -EINVAL;
 607         }
 608
 609         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 610                         batch->start, batch->used, batch->num_cliprects);
 611
 612         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 613
 614         if (batch->num_cliprects < 0)
 615                 return -EINVAL;
 616
 617         if (batch->num_cliprects) {
 618                 cliprects = kcalloc(batch->num_cliprects,
 619                                     sizeof(struct drm_clip_rect),
 620                                     GFP_KERNEL);
 621                 if (cliprects == NULL)
 622                         return -ENOMEM;
 623
 624                 ret = copy_from_user(cliprects, batch->cliprects,
 625                                      batch->num_cliprects *
 626                                      sizeof(struct drm_clip_rect));
 627                 if (ret != 0) {
 628                         ret = -EFAULT;
 629                         goto fail_free;
 630                 }
 631         }
 632
 633         mutex_lock(&dev->struct_mutex);
 634         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 635         mutex_unlock(&dev->struct_mutex);
 636
 637         if (sarea_priv)
 638                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 639
 640 fail_free:
 641         kfree(cliprects);
 642
 643         return ret;
 644 }
 645
 646 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 647                           struct drm_file *file_priv)
 648 {
 649         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 650         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 651         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 652             master_priv->sarea_priv;
 653         drm_i915_cmdbuffer_t *cmdbuf = data;
 654         struct drm_clip_rect *cliprects = NULL;
 655         void *batch_data;
 656         int ret;
 657
 658         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 659                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 660
 661         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 662
 663         if (cmdbuf->num_cliprects < 0)
 664                 return -EINVAL;
 665
 666         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 667         if (batch_data == NULL)
 668                 return -ENOMEM;
 669
 670         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 671         if (ret != 0) {
 672                 ret = -EFAULT;
 673                 goto fail_batch_free;
 674         }
 675
 676         if (cmdbuf->num_cliprects) {
 677                 cliprects = kcalloc(cmdbuf->num_cliprects,
 678                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 679                 if (cliprects == NULL) {
 680                         ret = -ENOMEM;
 681                         goto fail_batch_free;
 682                 }
 683
 684                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 685                                      cmdbuf->num_cliprects *
 686                                      sizeof(struct drm_clip_rect));
 687                 if (ret != 0) {
 688                         ret = -EFAULT;
 689                         goto fail_clip_free;
 690                 }
 691         }
 692
 693         mutex_lock(&dev->struct_mutex);
 694         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 695         mutex_unlock(&dev->struct_mutex);
 696         if (ret) {
 697                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 698                 goto fail_clip_free;
 699         }
 700
 701         if (sarea_priv)
 702                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 703
 704 fail_clip_free:
 705         kfree(cliprects);
 706 fail_batch_free:
 707         kfree(batch_data);
 708
 709         return ret;
 710 }
 711
 712 static int i915_flip_bufs(struct drm_device *dev, void *data,
 713                           struct drm_file *file_priv)
 714 {
 715         int ret;
 716
 717         DRM_DEBUG_DRIVER("%s\n", __func__);
 718
 719         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 720
 721         mutex_lock(&dev->struct_mutex);
 722         ret = i915_dispatch_flip(dev);
 723         mutex_unlock(&dev->struct_mutex);
 724
 725         return ret;
 726 }
 727
 728 static int i915_getparam(struct drm_device *dev, void *data,
 729                          struct drm_file *file_priv)
 730 {
 731         drm_i915_private_t *dev_priv = dev->dev_private;
 732         drm_i915_getparam_t *param = data;
 733         int value;
 734
 735         if (!dev_priv) {
 736                 DRM_ERROR("called with no initialization\n");
 737                 return -EINVAL;
 738         }
 739
 740         switch (param->param) {
 741         case I915_PARAM_IRQ_ACTIVE:
 742                 value = dev->pdev->irq ? 1 : 0;
 743                 break;
 744         case I915_PARAM_ALLOW_BATCHBUFFER:
 745                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 746                 break;
 747         case I915_PARAM_LAST_DISPATCH:
 748                 value = READ_BREADCRUMB(dev_priv);
 749                 break;
 750         case I915_PARAM_CHIPSET_ID:
 751                 value = dev->pci_device;
 752                 break;
 753         case I915_PARAM_HAS_GEM:
 754                 value = dev_priv->has_gem;
 755                 break;
 756         case I915_PARAM_NUM_FENCES_AVAIL:
 757                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 758                 break;
 759         case I915_PARAM_HAS_OVERLAY:
 760                 value = dev_priv->overlay ? 1 : 0;
 761                 break;
 762         case I915_PARAM_HAS_PAGEFLIPPING:
 763                 value = 1;
 764                 break;
 765         case I915_PARAM_HAS_EXECBUF2:
 766                 /* depends on GEM */
 767                 value = dev_priv->has_gem;
 768                 break;
 769         case I915_PARAM_HAS_BSD:
 770                 value = HAS_BSD(dev);
 771                 break;
 772         case I915_PARAM_HAS_BLT:
 773                 value = HAS_BLT(dev);
 774                 break;
 775         case I915_PARAM_HAS_RELAXED_FENCING:
 776                 value = 1;
 777                 break;
 778         case I915_PARAM_HAS_COHERENT_RINGS:
 779                 value = 1;
 780                 break;
 781         case I915_PARAM_HAS_EXEC_CONSTANTS:
 782                 value = INTEL_INFO(dev)->gen >= 4;
 783                 break;
 784         case I915_PARAM_HAS_RELAXED_DELTA:
 785                 value = 1;
 786                 break;
 787         case I915_PARAM_HAS_GEN7_SOL_RESET:
 788                 value = 1;
 789                 break;
 790         case I915_PARAM_HAS_LLC:
 791                 value = HAS_LLC(dev);
 792                 break;
 793         case I915_PARAM_HAS_ALIASING_PPGTT:
 794                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 795                 break;
 796         default:
 797                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 798                                  param->param);
 799                 return -EINVAL;
 800         }
 801
 802         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 803                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 804                 return -EFAULT;
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int i915_setparam(struct drm_device *dev, void *data,
 811                          struct drm_file *file_priv)
 812 {
 813         drm_i915_private_t *dev_priv = dev->dev_private;
 814         drm_i915_setparam_t *param = data;
 815
 816         if (!dev_priv) {
 817                 DRM_ERROR("called with no initialization\n");
 818                 return -EINVAL;
 819         }
 820
 821         switch (param->param) {
 822         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 823                 break;
 824         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 825                 dev_priv->tex_lru_log_granularity = param->value;
 826                 break;
 827         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 828                 dev_priv->allow_batchbuffer = param->value;
 829                 break;
 830         case I915_SETPARAM_NUM_USED_FENCES:
 831                 if (param->value > dev_priv->num_fence_regs ||
 832                     param->value < 0)
 833                         return -EINVAL;
 834                 /* Userspace can use first N regs */
 835                 dev_priv->fence_reg_start = param->value;
 836                 break;
 837         default:
 838                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 839                                         param->param);
 840                 return -EINVAL;
 841         }
 842
 843         return 0;
 844 }
 845
 846 static int i915_set_status_page(struct drm_device *dev, void *data,
 847                                 struct drm_file *file_priv)
 848 {
 849         drm_i915_private_t *dev_priv = dev->dev_private;
 850         drm_i915_hws_addr_t *hws = data;
 851         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 852
 853         if (!I915_NEED_GFX_HWS(dev))
 854                 return -EINVAL;
 855
 856         if (!dev_priv) {
 857                 DRM_ERROR("called with no initialization\n");
 858                 return -EINVAL;
 859         }
 860
 861         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 862                 WARN(1, "tried to set status page when mode setting active\n");
 863                 return 0;
 864         }
 865
 866         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 867
 868         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 869
 870         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 871         dev_priv->hws_map.size = 4*1024;
 872         dev_priv->hws_map.type = 0;
 873         dev_priv->hws_map.flags = 0;
 874         dev_priv->hws_map.mtrr = 0;
 875
 876         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 877         if (dev_priv->hws_map.handle == NULL) {
 878                 i915_dma_cleanup(dev);
 879                 ring->status_page.gfx_addr = 0;
 880                 DRM_ERROR("can not ioremap virtual address for"
 881                                 " G33 hw status page\n");
 882                 return -ENOMEM;
 883         }
 884         ring->status_page.page_addr =
 885                 (void __force __iomem *)dev_priv->hws_map.handle;
 886         memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
 887         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 888
 889         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 890                          ring->status_page.gfx_addr);
 891         DRM_DEBUG_DRIVER("load hws at %p\n",
 892                          ring->status_page.page_addr);
 893         return 0;
 894 }
 895
 896 static int i915_get_bridge_dev(struct drm_device *dev)
 897 {
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899
 900         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 901         if (!dev_priv->bridge_dev) {
 902                 DRM_ERROR("bridge device not found\n");
 903                 return -1;
 904         }
 905         return 0;
 906 }
 907
 908 #define MCHBAR_I915 0x44
 909 #define MCHBAR_I965 0x48
 910 #define MCHBAR_SIZE (4*4096)
 911
 912 #define DEVEN_REG 0x54
 913 #define   DEVEN_MCHBAR_EN (1 << 28)
 914
 915 /* Allocate space for the MCH regs if needed, return nonzero on error */
 916 static int
 917 intel_alloc_mchbar_resource(struct drm_device *dev)
 918 {
 919         drm_i915_private_t *dev_priv = dev->dev_private;
 920         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 921         u32 temp_lo, temp_hi = 0;
 922         u64 mchbar_addr;
 923         int ret;
 924
 925         if (INTEL_INFO(dev)->gen >= 4)
 926                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 927         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 928         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 929
 930         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 931 #ifdef CONFIG_PNP
 932         if (mchbar_addr &&
 933             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 934                 return 0;
 935 #endif
 936
 937         /* Get some space for it */
 938         dev_priv->mch_res.name = "i915 MCHBAR";
 939         dev_priv->mch_res.flags = IORESOURCE_MEM;
 940         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 941                                      &dev_priv->mch_res,
 942                                      MCHBAR_SIZE, MCHBAR_SIZE,
 943                                      PCIBIOS_MIN_MEM,
 944                                      0, pcibios_align_resource,
 945                                      dev_priv->bridge_dev);
 946         if (ret) {
 947                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 948                 dev_priv->mch_res.start = 0;
 949                 return ret;
 950         }
 951
 952         if (INTEL_INFO(dev)->gen >= 4)
 953                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 954                                        upper_32_bits(dev_priv->mch_res.start));
 955
 956         pci_write_config_dword(dev_priv->bridge_dev, reg,
 957                                lower_32_bits(dev_priv->mch_res.start));
 958         return 0;
 959 }
 960
 961 /* Setup MCHBAR if possible, return true if we should disable it again */
 962 static void
 963 intel_setup_mchbar(struct drm_device *dev)
 964 {
 965         drm_i915_private_t *dev_priv = dev->dev_private;
 966         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 967         u32 temp;
 968         bool enabled;
 969
 970         dev_priv->mchbar_need_disable = false;
 971
 972         if (IS_I915G(dev) || IS_I915GM(dev)) {
 973                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 974                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 975         } else {
 976                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 977                 enabled = temp & 1;
 978         }
 979
 980         /* If it's already enabled, don't have to do anything */
 981         if (enabled)
 982                 return;
 983
 984         if (intel_alloc_mchbar_resource(dev))
 985                 return;
 986
 987         dev_priv->mchbar_need_disable = true;
 988
 989         /* Space is allocated or reserved, so enable it. */
 990         if (IS_I915G(dev) || IS_I915GM(dev)) {
 991                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 992                                        temp | DEVEN_MCHBAR_EN);
 993         } else {
 994                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 995                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 996         }
 997 }
 998
 999 static void
1000 intel_teardown_mchbar(struct drm_device *dev)
1001 {
1002         drm_i915_private_t *dev_priv = dev->dev_private;
1003         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1004         u32 temp;
1005
1006         if (dev_priv->mchbar_need_disable) {
1007                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1008                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1009                         temp &= ~DEVEN_MCHBAR_EN;
1010                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1011                 } else {
1012                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1013                         temp &= ~1;
1014                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1015                 }
1016         }
1017
1018         if (dev_priv->mch_res.start)
1019                 release_resource(&dev_priv->mch_res);
1020 }
1021
1022 #define PTE_ADDRESS_MASK                0xfffff000
1023 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1024 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1025 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1026 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1027 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1028 #define PTE_VALID                       (1 << 0)
1029
1030 /**
1031  * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1032  *                       a physical one
1033  * @dev: drm device
1034  * @offset: address to translate
1035  *
1036  * Some chip functions require allocations from stolen space and need the
1037  * physical address of the memory in question.
1038  */
1039 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1040 {
1041         struct drm_i915_private *dev_priv = dev->dev_private;
1042         struct pci_dev *pdev = dev_priv->bridge_dev;
1043         u32 base;
1044
1045 #if 0
1046         /* On the machines I have tested the Graphics Base of Stolen Memory
1047          * is unreliable, so compute the base by subtracting the stolen memory
1048          * from the Top of Low Usable DRAM which is where the BIOS places
1049          * the graphics stolen memory.
1050          */
1051         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1052                 /* top 32bits are reserved = 0 */
1053                 pci_read_config_dword(pdev, 0xA4, &base);
1054         } else {
1055                 /* XXX presume 8xx is the same as i915 */
1056                 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1057         }
1058 #else
1059         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1060                 u16 val;
1061                 pci_read_config_word(pdev, 0xb0, &val);
1062                 base = val >> 4 << 20;
1063         } else {
1064                 u8 val;
1065                 pci_read_config_byte(pdev, 0x9c, &val);
1066                 base = val >> 3 << 27;
1067         }
1068         base -= dev_priv->mm.gtt->stolen_size;
1069 #endif
1070
1071         return base + offset;
1072 }
1073
1074 static void i915_warn_stolen(struct drm_device *dev)
1075 {
1076         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1077         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1078 }
1079
1080 static void i915_setup_compression(struct drm_device *dev, int size)
1081 {
1082         struct drm_i915_private *dev_priv = dev->dev_private;
1083         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1084         unsigned long cfb_base;
1085         unsigned long ll_base = 0;
1086
1087         /* Just in case the BIOS is doing something questionable. */
1088         intel_disable_fbc(dev);
1089
1090         compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1091         if (compressed_fb)
1092                 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1093         if (!compressed_fb)
1094                 goto err;
1095
1096         cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1097         if (!cfb_base)
1098                 goto err_fb;
1099
1100         if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1101                 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1102                                                     4096, 4096, 0);
1103                 if (compressed_llb)
1104                         compressed_llb = drm_mm_get_block(compressed_llb,
1105                                                           4096, 4096);
1106                 if (!compressed_llb)
1107                         goto err_fb;
1108
1109                 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1110                 if (!ll_base)
1111                         goto err_llb;
1112         }
1113
1114         dev_priv->cfb_size = size;
1115
1116         dev_priv->compressed_fb = compressed_fb;
1117         if (HAS_PCH_SPLIT(dev))
1118                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1119         else if (IS_GM45(dev)) {
1120                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1121         } else {
1122                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1123                 I915_WRITE(FBC_LL_BASE, ll_base);
1124                 dev_priv->compressed_llb = compressed_llb;
1125         }
1126
1127         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1128                       cfb_base, ll_base, size >> 20);
1129         return;
1130
1131 err_llb:
1132         drm_mm_put_block(compressed_llb);
1133 err_fb:
1134         drm_mm_put_block(compressed_fb);
1135 err:
1136         dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1137         i915_warn_stolen(dev);
1138 }
1139
1140 static void i915_cleanup_compression(struct drm_device *dev)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144         drm_mm_put_block(dev_priv->compressed_fb);
1145         if (dev_priv->compressed_llb)
1146                 drm_mm_put_block(dev_priv->compressed_llb);
1147 }
1148
1149 /* true = enable decode, false = disable decoder */
1150 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1151 {
1152         struct drm_device *dev = cookie;
1153
1154         intel_modeset_vga_set_state(dev, state);
1155         if (state)
1156                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1157                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1158         else
1159                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1160 }
1161
1162 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1163 {
1164         struct drm_device *dev = pci_get_drvdata(pdev);
1165         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1166         if (state == VGA_SWITCHEROO_ON) {
1167                 pr_info("switched on\n");
1168                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1169                 /* i915 resume handler doesn't set to D0 */
1170                 pci_set_power_state(dev->pdev, PCI_D0);
1171                 i915_resume(dev);
1172                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1173         } else {
1174                 pr_err("switched off\n");
1175                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1176                 i915_suspend(dev, pmm);
1177                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1178         }
1179 }
1180
1181 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1182 {
1183         struct drm_device *dev = pci_get_drvdata(pdev);
1184         bool can_switch;
1185
1186         spin_lock(&dev->count_lock);
1187         can_switch = (dev->open_count == 0);
1188         spin_unlock(&dev->count_lock);
1189         return can_switch;
1190 }
1191
1192 static bool
1193 intel_enable_ppgtt(struct drm_device *dev)
1194 {
1195         if (i915_enable_ppgtt >= 0)
1196                 return i915_enable_ppgtt;
1197
1198 #ifdef CONFIG_INTEL_IOMMU
1199         /* Disable ppgtt on SNB if VT-d is on. */
1200         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
1201                 return false;
1202 #endif
1203
1204         return true;
1205 }
1206
1207 static int i915_load_gem_init(struct drm_device *dev)
1208 {
1209         struct drm_i915_private *dev_priv = dev->dev_private;
1210         unsigned long prealloc_size, gtt_size, mappable_size;
1211         int ret;
1212
1213         prealloc_size = dev_priv->mm.gtt->stolen_size;
1214         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1215         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1216
1217         /* Basic memrange allocator for stolen space */
1218         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1219
1220         mutex_lock(&dev->struct_mutex);
1221         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1222                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1223                  * aperture accordingly when using aliasing ppgtt. */
1224                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
1225
1226                 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
1227
1228                 ret = i915_gem_init_aliasing_ppgtt(dev);
1229                 if (ret) {
1230                         mutex_unlock(&dev->struct_mutex);
1231                         return ret;
1232                 }
1233         } else {
1234                 /* Let GEM Manage all of the aperture.
1235                  *
1236                  * However, leave one page at the end still bound to the scratch
1237                  * page.  There are a number of places where the hardware
1238                  * apparently prefetches past the end of the object, and we've
1239                  * seen multiple hangs with the GPU head pointer stuck in a
1240                  * batchbuffer bound at the last page of the aperture.  One page
1241                  * should be enough to keep any prefetching inside of the
1242                  * aperture.
1243                  */
1244                 i915_gem_init_global_gtt(dev, 0, mappable_size,
1245                                          gtt_size);
1246         }
1247
1248         ret = i915_gem_init_hw(dev);
1249         mutex_unlock(&dev->struct_mutex);
1250         if (ret) {
1251                 i915_gem_cleanup_aliasing_ppgtt(dev);
1252                 return ret;
1253         }
1254
1255         /* Try to set up FBC with a reasonable compressed buffer size */
1256         if (I915_HAS_FBC(dev) && i915_powersave) {
1257                 int cfb_size;
1258
1259                 /* Leave 1M for line length buffer & misc. */
1260
1261                 /* Try to get a 32M buffer... */
1262                 if (prealloc_size > (36*1024*1024))
1263                         cfb_size = 32*1024*1024;
1264                 else /* fall back to 7/8 of the stolen space */
1265                         cfb_size = prealloc_size * 7 / 8;
1266                 i915_setup_compression(dev, cfb_size);
1267         }
1268
1269         /* Allow hardware batchbuffers unless told otherwise. */
1270         dev_priv->allow_batchbuffer = 1;
1271         return 0;
1272 }
1273
1274 static int i915_load_modeset_init(struct drm_device *dev)
1275 {
1276         struct drm_i915_private *dev_priv = dev->dev_private;
1277         int ret;
1278
1279         ret = intel_parse_bios(dev);
1280         if (ret)
1281                 DRM_INFO("failed to find VBIOS tables\n");
1282
1283         /* If we have > 1 VGA cards, then we need to arbitrate access
1284          * to the common VGA resources.
1285          *
1286          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1287          * then we do not take part in VGA arbitration and the
1288          * vga_client_register() fails with -ENODEV.
1289          */
1290         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1291         if (ret && ret != -ENODEV)
1292                 goto out;
1293
1294         intel_register_dsm_handler();
1295
1296         ret = vga_switcheroo_register_client(dev->pdev,
1297                                              i915_switcheroo_set_state,
1298                                              NULL,
1299                                              i915_switcheroo_can_switch);
1300         if (ret)
1301                 goto cleanup_vga_client;
1302
1303         /* IIR "flip pending" bit means done if this bit is set */
1304         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1305                 dev_priv->flip_pending_is_done = true;
1306
1307         intel_modeset_init(dev);
1308
1309         ret = i915_load_gem_init(dev);
1310         if (ret)
1311                 goto cleanup_vga_switcheroo;
1312
1313         intel_modeset_gem_init(dev);
1314
1315         ret = drm_irq_install(dev);
1316         if (ret)
1317                 goto cleanup_gem;
1318
1319         /* Always safe in the mode setting case. */
1320         /* FIXME: do pre/post-mode set stuff in core KMS code */
1321         dev->vblank_disable_allowed = 1;
1322
1323         ret = intel_fbdev_init(dev);
1324         if (ret)
1325                 goto cleanup_irq;
1326
1327         drm_kms_helper_poll_init(dev);
1328
1329         /* We're off and running w/KMS */
1330         dev_priv->mm.suspended = 0;
1331
1332         return 0;
1333
1334 cleanup_irq:
1335         drm_irq_uninstall(dev);
1336 cleanup_gem:
1337         mutex_lock(&dev->struct_mutex);
1338         i915_gem_cleanup_ringbuffer(dev);
1339         mutex_unlock(&dev->struct_mutex);
1340         i915_gem_cleanup_aliasing_ppgtt(dev);
1341 cleanup_vga_switcheroo:
1342         vga_switcheroo_unregister_client(dev->pdev);
1343 cleanup_vga_client:
1344         vga_client_register(dev->pdev, NULL, NULL, NULL);
1345 out:
1346         return ret;
1347 }
1348
1349 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1350 {
1351         struct drm_i915_master_private *master_priv;
1352
1353         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1354         if (!master_priv)
1355                 return -ENOMEM;
1356
1357         master->driver_priv = master_priv;
1358         return 0;
1359 }
1360
1361 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1362 {
1363         struct drm_i915_master_private *master_priv = master->driver_priv;
1364
1365         if (!master_priv)
1366                 return;
1367
1368         kfree(master_priv);
1369
1370         master->driver_priv = NULL;
1371 }
1372
1373 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1374 {
1375         drm_i915_private_t *dev_priv = dev->dev_private;
1376         u32 tmp;
1377
1378         tmp = I915_READ(CLKCFG);
1379
1380         switch (tmp & CLKCFG_FSB_MASK) {
1381         case CLKCFG_FSB_533:
1382                 dev_priv->fsb_freq = 533; /* 133*4 */
1383                 break;
1384         case CLKCFG_FSB_800:
1385                 dev_priv->fsb_freq = 800; /* 200*4 */
1386                 break;
1387         case CLKCFG_FSB_667:
1388                 dev_priv->fsb_freq =  667; /* 167*4 */
1389                 break;
1390         case CLKCFG_FSB_400:
1391                 dev_priv->fsb_freq = 400; /* 100*4 */
1392                 break;
1393         }
1394
1395         switch (tmp & CLKCFG_MEM_MASK) {
1396         case CLKCFG_MEM_533:
1397                 dev_priv->mem_freq = 533;
1398                 break;
1399         case CLKCFG_MEM_667:
1400                 dev_priv->mem_freq = 667;
1401                 break;
1402         case CLKCFG_MEM_800:
1403                 dev_priv->mem_freq = 800;
1404                 break;
1405         }
1406
1407         /* detect pineview DDR3 setting */
1408         tmp = I915_READ(CSHRDDR3CTL);
1409         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1410 }
1411
1412 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1413 {
1414         drm_i915_private_t *dev_priv = dev->dev_private;
1415         u16 ddrpll, csipll;
1416
1417         ddrpll = I915_READ16(DDRMPLL1);
1418         csipll = I915_READ16(CSIPLL0);
1419
1420         switch (ddrpll & 0xff) {
1421         case 0xc:
1422                 dev_priv->mem_freq = 800;
1423                 break;
1424         case 0x10:
1425                 dev_priv->mem_freq = 1066;
1426                 break;
1427         case 0x14:
1428                 dev_priv->mem_freq = 1333;
1429                 break;
1430         case 0x18:
1431                 dev_priv->mem_freq = 1600;
1432                 break;
1433         default:
1434                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1435                                  ddrpll & 0xff);
1436                 dev_priv->mem_freq = 0;
1437                 break;
1438         }
1439
1440         dev_priv->r_t = dev_priv->mem_freq;
1441
1442         switch (csipll & 0x3ff) {
1443         case 0x00c:
1444                 dev_priv->fsb_freq = 3200;
1445                 break;
1446         case 0x00e:
1447                 dev_priv->fsb_freq = 3733;
1448                 break;
1449         case 0x010:
1450                 dev_priv->fsb_freq = 4266;
1451                 break;
1452         case 0x012:
1453                 dev_priv->fsb_freq = 4800;
1454                 break;
1455         case 0x014:
1456                 dev_priv->fsb_freq = 5333;
1457                 break;
1458         case 0x016:
1459                 dev_priv->fsb_freq = 5866;
1460                 break;
1461         case 0x018:
1462                 dev_priv->fsb_freq = 6400;
1463                 break;
1464         default:
1465                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1466                                  csipll & 0x3ff);
1467                 dev_priv->fsb_freq = 0;
1468                 break;
1469         }
1470
1471         if (dev_priv->fsb_freq == 3200) {
1472                 dev_priv->c_m = 0;
1473         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1474                 dev_priv->c_m = 1;
1475         } else {
1476                 dev_priv->c_m = 2;
1477         }
1478 }
1479
1480 static const struct cparams {
1481         u16 i;
1482         u16 t;
1483         u16 m;
1484         u16 c;
1485 } cparams[] = {
1486         { 1, 1333, 301, 28664 },
1487         { 1, 1066, 294, 24460 },
1488         { 1, 800, 294, 25192 },
1489         { 0, 1333, 276, 27605 },
1490         { 0, 1066, 276, 27605 },
1491         { 0, 800, 231, 23784 },
1492 };
1493
1494 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1495 {
1496         u64 total_count, diff, ret;
1497         u32 count1, count2, count3, m = 0, c = 0;
1498         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1499         int i;
1500
1501         diff1 = now - dev_priv->last_time1;
1502
1503         /* Prevent division-by-zero if we are asking too fast.
1504          * Also, we don't get interesting results if we are polling
1505          * faster than once in 10ms, so just return the saved value
1506          * in such cases.
1507          */
1508         if (diff1 <= 10)
1509                 return dev_priv->chipset_power;
1510
1511         count1 = I915_READ(DMIEC);
1512         count2 = I915_READ(DDREC);
1513         count3 = I915_READ(CSIEC);
1514
1515         total_count = count1 + count2 + count3;
1516
1517         /* FIXME: handle per-counter overflow */
1518         if (total_count < dev_priv->last_count1) {
1519                 diff = ~0UL - dev_priv->last_count1;
1520                 diff += total_count;
1521         } else {
1522                 diff = total_count - dev_priv->last_count1;
1523         }
1524
1525         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1526                 if (cparams[i].i == dev_priv->c_m &&
1527                     cparams[i].t == dev_priv->r_t) {
1528                         m = cparams[i].m;
1529                         c = cparams[i].c;
1530                         break;
1531                 }
1532         }
1533
1534         diff = div_u64(diff, diff1);
1535         ret = ((m * diff) + c);
1536         ret = div_u64(ret, 10);
1537
1538         dev_priv->last_count1 = total_count;
1539         dev_priv->last_time1 = now;
1540
1541         dev_priv->chipset_power = ret;
1542
1543         return ret;
1544 }
1545
1546 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1547 {
1548         unsigned long m, x, b;
1549         u32 tsfs;
1550
1551         tsfs = I915_READ(TSFS);
1552
1553         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1554         x = I915_READ8(TR1);
1555
1556         b = tsfs & TSFS_INTR_MASK;
1557
1558         return ((m * x) / 127) - b;
1559 }
1560
1561 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1562 {
1563         static const struct v_table {
1564                 u16 vd; /* in .1 mil */
1565                 u16 vm; /* in .1 mil */
1566         } v_table[] = {
1567                 { 0, 0, },
1568                 { 375, 0, },
1569                 { 500, 0, },
1570                 { 625, 0, },
1571                 { 750, 0, },
1572                 { 875, 0, },
1573                 { 1000, 0, },
1574                 { 1125, 0, },
1575                 { 4125, 3000, },
1576                 { 4125, 3000, },
1577                 { 4125, 3000, },
1578                 { 4125, 3000, },
1579                 { 4125, 3000, },
1580                 { 4125, 3000, },
1581                 { 4125, 3000, },
1582                 { 4125, 3000, },
1583                 { 4125, 3000, },
1584                 { 4125, 3000, },
1585                 { 4125, 3000, },
1586                 { 4125, 3000, },
1587                 { 4125, 3000, },
1588                 { 4125, 3000, },
1589                 { 4125, 3000, },
1590                 { 4125, 3000, },
1591                 { 4125, 3000, },
1592                 { 4125, 3000, },
1593                 { 4125, 3000, },
1594                 { 4125, 3000, },
1595                 { 4125, 3000, },
1596                 { 4125, 3000, },
1597                 { 4125, 3000, },
1598                 { 4125, 3000, },
1599                 { 4250, 3125, },
1600                 { 4375, 3250, },
1601                 { 4500, 3375, },
1602                 { 4625, 3500, },
1603                 { 4750, 3625, },
1604                 { 4875, 3750, },
1605                 { 5000, 3875, },
1606                 { 5125, 4000, },
1607                 { 5250, 4125, },
1608                 { 5375, 4250, },
1609                 { 5500, 4375, },
1610                 { 5625, 4500, },
1611                 { 5750, 4625, },
1612                 { 5875, 4750, },
1613                 { 6000, 4875, },
1614                 { 6125, 5000, },
1615                 { 6250, 5125, },
1616                 { 6375, 5250, },
1617                 { 6500, 5375, },
1618                 { 6625, 5500, },
1619                 { 6750, 5625, },
1620                 { 6875, 5750, },
1621                 { 7000, 5875, },
1622                 { 7125, 6000, },
1623                 { 7250, 6125, },
1624                 { 7375, 6250, },
1625                 { 7500, 6375, },
1626                 { 7625, 6500, },
1627                 { 7750, 6625, },
1628                 { 7875, 6750, },
1629                 { 8000, 6875, },
1630                 { 8125, 7000, },
1631                 { 8250, 7125, },
1632                 { 8375, 7250, },
1633                 { 8500, 7375, },
1634                 { 8625, 7500, },
1635                 { 8750, 7625, },
1636                 { 8875, 7750, },
1637                 { 9000, 7875, },
1638                 { 9125, 8000, },
1639                 { 9250, 8125, },
1640                 { 9375, 8250, },
1641                 { 9500, 8375, },
1642                 { 9625, 8500, },
1643                 { 9750, 8625, },
1644                 { 9875, 8750, },
1645                 { 10000, 8875, },
1646                 { 10125, 9000, },
1647                 { 10250, 9125, },
1648                 { 10375, 9250, },
1649                 { 10500, 9375, },
1650                 { 10625, 9500, },
1651                 { 10750, 9625, },
1652                 { 10875, 9750, },
1653                 { 11000, 9875, },
1654                 { 11125, 10000, },
1655                 { 11250, 10125, },
1656                 { 11375, 10250, },
1657                 { 11500, 10375, },
1658                 { 11625, 10500, },
1659                 { 11750, 10625, },
1660                 { 11875, 10750, },
1661                 { 12000, 10875, },
1662                 { 12125, 11000, },
1663                 { 12250, 11125, },
1664                 { 12375, 11250, },
1665                 { 12500, 11375, },
1666                 { 12625, 11500, },
1667                 { 12750, 11625, },
1668                 { 12875, 11750, },
1669                 { 13000, 11875, },
1670                 { 13125, 12000, },
1671                 { 13250, 12125, },
1672                 { 13375, 12250, },
1673                 { 13500, 12375, },
1674                 { 13625, 12500, },
1675                 { 13750, 12625, },
1676                 { 13875, 12750, },
1677                 { 14000, 12875, },
1678                 { 14125, 13000, },
1679                 { 14250, 13125, },
1680                 { 14375, 13250, },
1681                 { 14500, 13375, },
1682                 { 14625, 13500, },
1683                 { 14750, 13625, },
1684                 { 14875, 13750, },
1685                 { 15000, 13875, },
1686                 { 15125, 14000, },
1687                 { 15250, 14125, },
1688                 { 15375, 14250, },
1689                 { 15500, 14375, },
1690                 { 15625, 14500, },
1691                 { 15750, 14625, },
1692                 { 15875, 14750, },
1693                 { 16000, 14875, },
1694                 { 16125, 15000, },
1695         };
1696         if (dev_priv->info->is_mobile)
1697                 return v_table[pxvid].vm;
1698         else
1699                 return v_table[pxvid].vd;
1700 }
1701
1702 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1703 {
1704         struct timespec now, diff1;
1705         u64 diff;
1706         unsigned long diffms;
1707         u32 count;
1708
1709         if (dev_priv->info->gen != 5)
1710                 return;
1711
1712         getrawmonotonic(&now);
1713         diff1 = timespec_sub(now, dev_priv->last_time2);
1714
1715         /* Don't divide by 0 */
1716         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1717         if (!diffms)
1718                 return;
1719
1720         count = I915_READ(GFXEC);
1721
1722         if (count < dev_priv->last_count2) {
1723                 diff = ~0UL - dev_priv->last_count2;
1724                 diff += count;
1725         } else {
1726                 diff = count - dev_priv->last_count2;
1727         }
1728
1729         dev_priv->last_count2 = count;
1730         dev_priv->last_time2 = now;
1731
1732         /* More magic constants... */
1733         diff = diff * 1181;
1734         diff = div_u64(diff, diffms * 10);
1735         dev_priv->gfx_power = diff;
1736 }
1737
1738 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1739 {
1740         unsigned long t, corr, state1, corr2, state2;
1741         u32 pxvid, ext_v;
1742
1743         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1744         pxvid = (pxvid >> 24) & 0x7f;
1745         ext_v = pvid_to_extvid(dev_priv, pxvid);
1746
1747         state1 = ext_v;
1748
1749         t = i915_mch_val(dev_priv);
1750
1751         /* Revel in the empirically derived constants */
1752
1753         /* Correction factor in 1/100000 units */
1754         if (t > 80)
1755                 corr = ((t * 2349) + 135940);
1756         else if (t >= 50)
1757                 corr = ((t * 964) + 29317);
1758         else /* < 50 */
1759                 corr = ((t * 301) + 1004);
1760
1761         corr = corr * ((150142 * state1) / 10000 - 78642);
1762         corr /= 100000;
1763         corr2 = (corr * dev_priv->corr);
1764
1765         state2 = (corr2 * state1) / 10000;
1766         state2 /= 100; /* convert to mW */
1767
1768         i915_update_gfx_val(dev_priv);
1769
1770         return dev_priv->gfx_power + state2;
1771 }
1772
1773 /* Global for IPS driver to get at the current i915 device */
1774 static struct drm_i915_private *i915_mch_dev;
1775 /*
1776  * Lock protecting IPS related data structures
1777  *   - i915_mch_dev
1778  *   - dev_priv->max_delay
1779  *   - dev_priv->min_delay
1780  *   - dev_priv->fmax
1781  *   - dev_priv->gpu_busy
1782  */
1783 static DEFINE_SPINLOCK(mchdev_lock);
1784
1785 /**
1786  * i915_read_mch_val - return value for IPS use
1787  *
1788  * Calculate and return a value for the IPS driver to use when deciding whether
1789  * we have thermal and power headroom to increase CPU or GPU power budget.
1790  */
1791 unsigned long i915_read_mch_val(void)
1792 {
1793         struct drm_i915_private *dev_priv;
1794         unsigned long chipset_val, graphics_val, ret = 0;
1795
1796         spin_lock(&mchdev_lock);
1797         if (!i915_mch_dev)
1798                 goto out_unlock;
1799         dev_priv = i915_mch_dev;
1800
1801         chipset_val = i915_chipset_val(dev_priv);
1802         graphics_val = i915_gfx_val(dev_priv);
1803
1804         ret = chipset_val + graphics_val;
1805
1806 out_unlock:
1807         spin_unlock(&mchdev_lock);
1808
1809         return ret;
1810 }
1811 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1812
1813 /**
1814  * i915_gpu_raise - raise GPU frequency limit
1815  *
1816  * Raise the limit; IPS indicates we have thermal headroom.
1817  */
1818 bool i915_gpu_raise(void)
1819 {
1820         struct drm_i915_private *dev_priv;
1821         bool ret = true;
1822
1823         spin_lock(&mchdev_lock);
1824         if (!i915_mch_dev) {
1825                 ret = false;
1826                 goto out_unlock;
1827         }
1828         dev_priv = i915_mch_dev;
1829
1830         if (dev_priv->max_delay > dev_priv->fmax)
1831                 dev_priv->max_delay--;
1832
1833 out_unlock:
1834         spin_unlock(&mchdev_lock);
1835
1836         return ret;
1837 }
1838 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1839
1840 /**
1841  * i915_gpu_lower - lower GPU frequency limit
1842  *
1843  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1844  * frequency maximum.
1845  */
1846 bool i915_gpu_lower(void)
1847 {
1848         struct drm_i915_private *dev_priv;
1849         bool ret = true;
1850
1851         spin_lock(&mchdev_lock);
1852         if (!i915_mch_dev) {
1853                 ret = false;
1854                 goto out_unlock;
1855         }
1856         dev_priv = i915_mch_dev;
1857
1858         if (dev_priv->max_delay < dev_priv->min_delay)
1859                 dev_priv->max_delay++;
1860
1861 out_unlock:
1862         spin_unlock(&mchdev_lock);
1863
1864         return ret;
1865 }
1866 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1867
1868 /**
1869  * i915_gpu_busy - indicate GPU business to IPS
1870  *
1871  * Tell the IPS driver whether or not the GPU is busy.
1872  */
1873 bool i915_gpu_busy(void)
1874 {
1875         struct drm_i915_private *dev_priv;
1876         bool ret = false;
1877
1878         spin_lock(&mchdev_lock);
1879         if (!i915_mch_dev)
1880                 goto out_unlock;
1881         dev_priv = i915_mch_dev;
1882
1883         ret = dev_priv->busy;
1884
1885 out_unlock:
1886         spin_unlock(&mchdev_lock);
1887
1888         return ret;
1889 }
1890 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1891
1892 /**
1893  * i915_gpu_turbo_disable - disable graphics turbo
1894  *
1895  * Disable graphics turbo by resetting the max frequency and setting the
1896  * current frequency to the default.
1897  */
1898 bool i915_gpu_turbo_disable(void)
1899 {
1900         struct drm_i915_private *dev_priv;
1901         bool ret = true;
1902
1903         spin_lock(&mchdev_lock);
1904         if (!i915_mch_dev) {
1905                 ret = false;
1906                 goto out_unlock;
1907         }
1908         dev_priv = i915_mch_dev;
1909
1910         dev_priv->max_delay = dev_priv->fstart;
1911
1912         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1913                 ret = false;
1914
1915 out_unlock:
1916         spin_unlock(&mchdev_lock);
1917
1918         return ret;
1919 }
1920 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1921
1922 /**
1923  * Tells the intel_ips driver that the i915 driver is now loaded, if
1924  * IPS got loaded first.
1925  *
1926  * This awkward dance is so that neither module has to depend on the
1927  * other in order for IPS to do the appropriate communication of
1928  * GPU turbo limits to i915.
1929  */
1930 static void
1931 ips_ping_for_i915_load(void)
1932 {
1933         void (*link)(void);
1934
1935         link = symbol_get(ips_link_to_i915_driver);
1936         if (link) {
1937                 link();
1938                 symbol_put(ips_link_to_i915_driver);
1939         }
1940 }
1941
1942 static void
1943 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1944                 unsigned long size)
1945 {
1946         dev_priv->mm.gtt_mtrr = -1;
1947
1948 #if defined(CONFIG_X86_PAT)
1949         if (cpu_has_pat)
1950                 return;
1951 #endif
1952
1953         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1954          * one would think, because the kernel disables PAT on first
1955          * generation Core chips because WC PAT gets overridden by a UC
1956          * MTRR if present.  Even if a UC MTRR isn't present.
1957          */
1958         dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1959         if (dev_priv->mm.gtt_mtrr < 0) {
1960                 DRM_INFO("MTRR allocation failed.  Graphics "
1961                          "performance may suffer.\n");
1962         }
1963 }
1964
1965 /**
1966  * i915_driver_load - setup chip and create an initial config
1967  * @dev: DRM device
1968  * @flags: startup flags
1969  *
1970  * The driver load routine has to do several things:
1971  *   - drive output discovery via intel_modeset_init()
1972  *   - initialize the memory manager
1973  *   - allocate initial config memory
1974  *   - setup the DRM framebuffer with the allocated memory
1975  */
1976 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1977 {
1978         struct drm_i915_private *dev_priv;
1979         struct intel_device_info *info;
1980         int ret = 0, mmio_bar;
1981         uint32_t aperture_size;
1982
1983         info = (struct intel_device_info *) flags;
1984
1985         /* Refuse to load on gen6+ without kms enabled. */
1986         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1987                 return -ENODEV;
1988
1989
1990         /* i915 has 4 more counters */
1991         dev->counters += 4;
1992         dev->types[6] = _DRM_STAT_IRQ;
1993         dev->types[7] = _DRM_STAT_PRIMARY;
1994         dev->types[8] = _DRM_STAT_SECONDARY;
1995         dev->types[9] = _DRM_STAT_DMA;
1996
1997         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1998         if (dev_priv == NULL)
1999                 return -ENOMEM;
2000
2001         dev->dev_private = (void *)dev_priv;
2002         dev_priv->dev = dev;
2003         dev_priv->info = info;
2004
2005         if (i915_get_bridge_dev(dev)) {
2006                 ret = -EIO;
2007                 goto free_priv;
2008         }
2009
2010         pci_set_master(dev->pdev);
2011
2012         /* overlay on gen2 is broken and can't address above 1G */
2013         if (IS_GEN2(dev))
2014                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
2015
2016         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
2017          * using 32bit addressing, overwriting memory if HWS is located
2018          * above 4GB.
2019          *
2020          * The documentation also mentions an issue with undefined
2021          * behaviour if any general state is accessed within a page above 4GB,
2022          * which also needs to be handled carefully.
2023          */
2024         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2025                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
2026
2027         mmio_bar = IS_GEN2(dev) ? 1 : 0;
2028         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
2029         if (!dev_priv->regs) {
2030                 DRM_ERROR("failed to map registers\n");
2031                 ret = -EIO;
2032                 goto put_bridge;
2033         }
2034
2035         dev_priv->mm.gtt = intel_gtt_get();
2036         if (!dev_priv->mm.gtt) {
2037                 DRM_ERROR("Failed to initialize GTT\n");
2038                 ret = -ENODEV;
2039                 goto out_rmmap;
2040         }
2041
2042         aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
2043
2044         dev_priv->mm.gtt_mapping =
2045                 io_mapping_create_wc(dev->agp->base, aperture_size);
2046         if (dev_priv->mm.gtt_mapping == NULL) {
2047                 ret = -EIO;
2048                 goto out_rmmap;
2049         }
2050
2051         i915_mtrr_setup(dev_priv, dev->agp->base, aperture_size);
2052
2053         /* The i915 workqueue is primarily used for batched retirement of
2054          * requests (and thus managing bo) once the task has been completed
2055          * by the GPU. i915_gem_retire_requests() is called directly when we
2056          * need high-priority retirement, such as waiting for an explicit
2057          * bo.
2058          *
2059          * It is also used for periodic low-priority events, such as
2060          * idle-timers and recording error state.
2061          *
2062          * All tasks on the workqueue are expected to acquire the dev mutex
2063          * so there is no point in running more than one instance of the
2064          * workqueue at any time: max_active = 1 and NON_REENTRANT.
2065          */
2066         dev_priv->wq = alloc_workqueue("i915",
2067                                        WQ_UNBOUND | WQ_NON_REENTRANT,
2068                                        1);
2069         if (dev_priv->wq == NULL) {
2070                 DRM_ERROR("Failed to create our workqueue.\n");
2071                 ret = -ENOMEM;
2072                 goto out_mtrrfree;
2073         }
2074
2075         /* enable GEM by default */
2076         dev_priv->has_gem = 1;
2077
2078         intel_irq_init(dev);
2079
2080         /* Try to make sure MCHBAR is enabled before poking at it */
2081         intel_setup_mchbar(dev);
2082         intel_setup_gmbus(dev);
2083         intel_opregion_setup(dev);
2084
2085         /* Make sure the bios did its job and set up vital registers */
2086         intel_setup_bios(dev);
2087
2088         i915_gem_load(dev);
2089
2090         /* Init HWS */
2091         if (!I915_NEED_GFX_HWS(dev)) {
2092                 ret = i915_init_phys_hws(dev);
2093                 if (ret)
2094                         goto out_gem_unload;
2095         }
2096
2097         if (IS_PINEVIEW(dev))
2098                 i915_pineview_get_mem_freq(dev);
2099         else if (IS_GEN5(dev))
2100                 i915_ironlake_get_mem_freq(dev);
2101
2102         /* On the 945G/GM, the chipset reports the MSI capability on the
2103          * integrated graphics even though the support isn't actually there
2104          * according to the published specs.  It doesn't appear to function
2105          * correctly in testing on 945G.
2106          * This may be a side effect of MSI having been made available for PEG
2107          * and the registers being closely associated.
2108          *
2109          * According to chipset errata, on the 965GM, MSI interrupts may
2110          * be lost or delayed, but we use them anyways to avoid
2111          * stuck interrupts on some machines.
2112          */
2113         if (!IS_I945G(dev) && !IS_I945GM(dev))
2114                 pci_enable_msi(dev->pdev);
2115
2116         spin_lock_init(&dev_priv->gt_lock);
2117         spin_lock_init(&dev_priv->irq_lock);
2118         spin_lock_init(&dev_priv->error_lock);
2119         spin_lock_init(&dev_priv->rps_lock);
2120
2121         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2122                 dev_priv->num_pipe = 3;
2123         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
2124                 dev_priv->num_pipe = 2;
2125         else
2126                 dev_priv->num_pipe = 1;
2127
2128         ret = drm_vblank_init(dev, dev_priv->num_pipe);
2129         if (ret)
2130                 goto out_gem_unload;
2131
2132         /* Start out suspended */
2133         dev_priv->mm.suspended = 1;
2134
2135         intel_detect_pch(dev);
2136
2137         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2138                 ret = i915_load_modeset_init(dev);
2139                 if (ret < 0) {
2140                         DRM_ERROR("failed to init modeset\n");
2141                         goto out_gem_unload;
2142                 }
2143         }
2144
2145         i915_setup_sysfs(dev);
2146
2147         /* Must be done after probing outputs */
2148         intel_opregion_init(dev);
2149         acpi_video_register();
2150
2151         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2152                     (unsigned long) dev);
2153
2154         if (IS_GEN5(dev)) {
2155                 spin_lock(&mchdev_lock);
2156                 i915_mch_dev = dev_priv;
2157                 dev_priv->mchdev_lock = &mchdev_lock;
2158                 spin_unlock(&mchdev_lock);
2159
2160                 ips_ping_for_i915_load();
2161         }
2162
2163         return 0;
2164
2165 out_gem_unload:
2166         if (dev_priv->mm.inactive_shrinker.shrink)
2167                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2168
2169         if (dev->pdev->msi_enabled)
2170                 pci_disable_msi(dev->pdev);
2171
2172         intel_teardown_gmbus(dev);
2173         intel_teardown_mchbar(dev);
2174         destroy_workqueue(dev_priv->wq);
2175 out_mtrrfree:
2176         if (dev_priv->mm.gtt_mtrr >= 0) {
2177                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2178                          dev->agp->agp_info.aper_size * 1024 * 1024);
2179                 dev_priv->mm.gtt_mtrr = -1;
2180         }
2181         io_mapping_free(dev_priv->mm.gtt_mapping);
2182 out_rmmap:
2183         pci_iounmap(dev->pdev, dev_priv->regs);
2184 put_bridge:
2185         pci_dev_put(dev_priv->bridge_dev);
2186 free_priv:
2187         kfree(dev_priv);
2188         return ret;
2189 }
2190
2191 int i915_driver_unload(struct drm_device *dev)
2192 {
2193         struct drm_i915_private *dev_priv = dev->dev_private;
2194         int ret;
2195
2196         spin_lock(&mchdev_lock);
2197         i915_mch_dev = NULL;
2198         spin_unlock(&mchdev_lock);
2199
2200         i915_teardown_sysfs(dev);
2201
2202         if (dev_priv->mm.inactive_shrinker.shrink)
2203                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2204
2205         mutex_lock(&dev->struct_mutex);
2206         ret = i915_gpu_idle(dev, true);
2207         if (ret)
2208                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2209         mutex_unlock(&dev->struct_mutex);
2210
2211         /* Cancel the retire work handler, which should be idle now. */
2212         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2213
2214         io_mapping_free(dev_priv->mm.gtt_mapping);
2215         if (dev_priv->mm.gtt_mtrr >= 0) {
2216                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2217                          dev->agp->agp_info.aper_size * 1024 * 1024);
2218                 dev_priv->mm.gtt_mtrr = -1;
2219         }
2220
2221         acpi_video_unregister();
2222
2223         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2224                 intel_fbdev_fini(dev);
2225                 intel_modeset_cleanup(dev);
2226
2227                 /*
2228                  * free the memory space allocated for the child device
2229                  * config parsed from VBT
2230                  */
2231                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2232                         kfree(dev_priv->child_dev);
2233                         dev_priv->child_dev = NULL;
2234                         dev_priv->child_dev_num = 0;
2235                 }
2236
2237                 vga_switcheroo_unregister_client(dev->pdev);
2238                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2239         }
2240
2241         /* Free error state after interrupts are fully disabled. */
2242         del_timer_sync(&dev_priv->hangcheck_timer);
2243         cancel_work_sync(&dev_priv->error_work);
2244         i915_destroy_error_state(dev);
2245
2246         if (dev->pdev->msi_enabled)
2247                 pci_disable_msi(dev->pdev);
2248
2249         intel_opregion_fini(dev);
2250
2251         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2252                 /* Flush any outstanding unpin_work. */
2253                 flush_workqueue(dev_priv->wq);
2254
2255                 mutex_lock(&dev->struct_mutex);
2256                 i915_gem_free_all_phys_object(dev);
2257                 i915_gem_cleanup_ringbuffer(dev);
2258                 mutex_unlock(&dev->struct_mutex);
2259                 i915_gem_cleanup_aliasing_ppgtt(dev);
2260                 if (I915_HAS_FBC(dev) && i915_powersave)
2261                         i915_cleanup_compression(dev);
2262                 drm_mm_takedown(&dev_priv->mm.stolen);
2263
2264                 intel_cleanup_overlay(dev);
2265
2266                 if (!I915_NEED_GFX_HWS(dev))
2267                         i915_free_hws(dev);
2268         }
2269
2270         if (dev_priv->regs != NULL)
2271                 pci_iounmap(dev->pdev, dev_priv->regs);
2272
2273         intel_teardown_gmbus(dev);
2274         intel_teardown_mchbar(dev);
2275
2276         destroy_workqueue(dev_priv->wq);
2277
2278         pci_dev_put(dev_priv->bridge_dev);
2279         kfree(dev->dev_private);
2280
2281         return 0;
2282 }
2283
2284 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2285 {
2286         struct drm_i915_file_private *file_priv;
2287
2288         DRM_DEBUG_DRIVER("\n");
2289         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2290         if (!file_priv)
2291                 return -ENOMEM;
2292
2293         file->driver_priv = file_priv;
2294
2295         spin_lock_init(&file_priv->mm.lock);
2296         INIT_LIST_HEAD(&file_priv->mm.request_list);
2297
2298         return 0;
2299 }
2300
2301 /**
2302  * i915_driver_lastclose - clean up after all DRM clients have exited
2303  * @dev: DRM device
2304  *
2305  * Take care of cleaning up after all DRM clients have exited.  In the
2306  * mode setting case, we want to restore the kernel's initial mode (just
2307  * in case the last client left us in a bad state).
2308  *
2309  * Additionally, in the non-mode setting case, we'll tear down the GTT
2310  * and DMA structures, since the kernel won't be using them, and clea
2311  * up any GEM state.
2312  */
2313 void i915_driver_lastclose(struct drm_device * dev)
2314 {
2315         drm_i915_private_t *dev_priv = dev->dev_private;
2316
2317         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2318                 intel_fb_restore_mode(dev);
2319                 vga_switcheroo_process_delayed_switch();
2320                 return;
2321         }
2322
2323         i915_gem_lastclose(dev);
2324
2325         i915_dma_cleanup(dev);
2326 }
2327
2328 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2329 {
2330         i915_gem_release(dev, file_priv);
2331 }
2332
2333 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2334 {
2335         struct drm_i915_file_private *file_priv = file->driver_priv;
2336
2337         kfree(file_priv);
2338 }
2339
2340 struct drm_ioctl_desc i915_ioctls[] = {
2341         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2342         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2343         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2344         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2345         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2346         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2347         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2348         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2349         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2350         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2351         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2352         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2353         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2354         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2355         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2356         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2357         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2358         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2359         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2360         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2361         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2362         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2363         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2364         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2365         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2366         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2367         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2368         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2369         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2370         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2371         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2372         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2373         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2374         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2375         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2376         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2377         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2378         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2379         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2380         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2381         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2382         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2383 };
2384
2385 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2386
2387 /*
2388  * This is really ugly: Because old userspace abused the linux agp interface to
2389  * manage the gtt, we need to claim that all intel devices are agp.  For
2390  * otherwise the drm core refuses to initialize the agp support code.
2391  */
2392 int i915_driver_device_is_agp(struct drm_device * dev)
2393 {
2394         return 1;
2395 }