drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/list_sort.h>
  31 #include "intel_drv.h"
  32
  33 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  34 {
  35         return to_i915(node->minor->dev);
  36 }
  37
  38 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  39  * allocated we need to hook into the minor for release. */
  40 static int
  41 drm_add_fake_info_node(struct drm_minor *minor,
  42                        struct dentry *ent,
  43                        const void *key)
  44 {
  45         struct drm_info_node *node;
  46
  47         node = kmalloc(sizeof(*node), GFP_KERNEL);
  48         if (node == NULL) {
  49                 debugfs_remove(ent);
  50                 return -ENOMEM;
  51         }
  52
  53         node->minor = minor;
  54         node->dent = ent;
  55         node->info_ent = (void *)key;
  56
  57         mutex_lock(&minor->debugfs_lock);
  58         list_add(&node->list, &minor->debugfs_list);
  59         mutex_unlock(&minor->debugfs_lock);
  60
  61         return 0;
  62 }
  63
  64 static int i915_capabilities(struct seq_file *m, void *data)
  65 {
  66         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  67         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  68
  69         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  70         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  71         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  72 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  73         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  74 #undef PRINT_FLAG
  75
  76         return 0;
  77 }
  78
  79 static char get_active_flag(struct drm_i915_gem_object *obj)
  80 {
  81         return i915_gem_object_is_active(obj) ? '*' : ' ';
  82 }
  83
  84 static char get_pin_flag(struct drm_i915_gem_object *obj)
  85 {
  86         return obj->pin_display ? 'p' : ' ';
  87 }
  88
  89 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  90 {
  91         switch (i915_gem_object_get_tiling(obj)) {
  92         default:
  93         case I915_TILING_NONE: return ' ';
  94         case I915_TILING_X: return 'X';
  95         case I915_TILING_Y: return 'Y';
  96         }
  97 }
  98
  99 static char get_global_flag(struct drm_i915_gem_object *obj)
 100 {
 101         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 102 }
 103
 104 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 105 {
 106         return obj->mm.mapping ? 'M' : ' ';
 107 }
 108
 109 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 110 {
 111         u64 size = 0;
 112         struct i915_vma *vma;
 113
 114         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 115                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 116                         size += vma->node.size;
 117         }
 118
 119         return size;
 120 }
 121
 122 static void
 123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 124 {
 125         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 126         struct intel_engine_cs *engine;
 127         struct i915_vma *vma;
 128         unsigned int frontbuffer_bits;
 129         int pin_count = 0;
 130
 131         lockdep_assert_held(&obj->base.dev->struct_mutex);
 132
 133         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 134                    &obj->base,
 135                    get_active_flag(obj),
 136                    get_pin_flag(obj),
 137                    get_tiling_flag(obj),
 138                    get_global_flag(obj),
 139                    get_pin_mapped_flag(obj),
 140                    obj->base.size / 1024,
 141                    obj->base.read_domains,
 142                    obj->base.write_domain,
 143                    i915_cache_level_str(dev_priv, obj->cache_level),
 144                    obj->mm.dirty ? " dirty" : "",
 145                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 146         if (obj->base.name)
 147                 seq_printf(m, " (name: %d)", obj->base.name);
 148         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 149                 if (i915_vma_is_pinned(vma))
 150                         pin_count++;
 151         }
 152         seq_printf(m, " (pinned x %d)", pin_count);
 153         if (obj->pin_display)
 154                 seq_printf(m, " (display)");
 155         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 156                 if (!drm_mm_node_allocated(&vma->node))
 157                         continue;
 158
 159                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 160                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 161                            vma->node.start, vma->node.size);
 162                 if (i915_vma_is_ggtt(vma)) {
 163                         switch (vma->ggtt_view.type) {
 164                         case I915_GGTT_VIEW_NORMAL:
 165                                 seq_puts(m, ", normal");
 166                                 break;
 167
 168                         case I915_GGTT_VIEW_PARTIAL:
 169                                 seq_printf(m, ", partial [%08llx+%x]",
 170                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 171                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 172                                 break;
 173
 174                         case I915_GGTT_VIEW_ROTATED:
 175                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 176                                            vma->ggtt_view.rotated.plane[0].width,
 177                                            vma->ggtt_view.rotated.plane[0].height,
 178                                            vma->ggtt_view.rotated.plane[0].stride,
 179                                            vma->ggtt_view.rotated.plane[0].offset,
 180                                            vma->ggtt_view.rotated.plane[1].width,
 181                                            vma->ggtt_view.rotated.plane[1].height,
 182                                            vma->ggtt_view.rotated.plane[1].stride,
 183                                            vma->ggtt_view.rotated.plane[1].offset);
 184                                 break;
 185
 186                         default:
 187                                 MISSING_CASE(vma->ggtt_view.type);
 188                                 break;
 189                         }
 190                 }
 191                 if (vma->fence)
 192                         seq_printf(m, " , fence: %d%s",
 193                                    vma->fence->id,
 194                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 195                 seq_puts(m, ")");
 196         }
 197         if (obj->stolen)
 198                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 199
 200         engine = i915_gem_object_last_write_engine(obj);
 201         if (engine)
 202                 seq_printf(m, " (%s)", engine->name);
 203
 204         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 205         if (frontbuffer_bits)
 206                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 207 }
 208
 209 static int obj_rank_by_stolen(void *priv,
 210                               struct list_head *A, struct list_head *B)
 211 {
 212         struct drm_i915_gem_object *a =
 213                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 214         struct drm_i915_gem_object *b =
 215                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 216
 217         if (a->stolen->start < b->stolen->start)
 218                 return -1;
 219         if (a->stolen->start > b->stolen->start)
 220                 return 1;
 221         return 0;
 222 }
 223
 224 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 225 {
 226         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 227         struct drm_device *dev = &dev_priv->drm;
 228         struct drm_i915_gem_object *obj;
 229         u64 total_obj_size, total_gtt_size;
 230         LIST_HEAD(stolen);
 231         int count, ret;
 232
 233         ret = mutex_lock_interruptible(&dev->struct_mutex);
 234         if (ret)
 235                 return ret;
 236
 237         total_obj_size = total_gtt_size = count = 0;
 238         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 239                 if (obj->stolen == NULL)
 240                         continue;
 241
 242                 list_add(&obj->obj_exec_link, &stolen);
 243
 244                 total_obj_size += obj->base.size;
 245                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 246                 count++;
 247         }
 248         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 249                 if (obj->stolen == NULL)
 250                         continue;
 251
 252                 list_add(&obj->obj_exec_link, &stolen);
 253
 254                 total_obj_size += obj->base.size;
 255                 count++;
 256         }
 257         list_sort(NULL, &stolen, obj_rank_by_stolen);
 258         seq_puts(m, "Stolen:\n");
 259         while (!list_empty(&stolen)) {
 260                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 261                 seq_puts(m, "   ");
 262                 describe_obj(m, obj);
 263                 seq_putc(m, '\n');
 264                 list_del_init(&obj->obj_exec_link);
 265         }
 266         mutex_unlock(&dev->struct_mutex);
 267
 268         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 269                    count, total_obj_size, total_gtt_size);
 270         return 0;
 271 }
 272
 273 struct file_stats {
 274         struct drm_i915_file_private *file_priv;
 275         unsigned long count;
 276         u64 total, unbound;
 277         u64 global, shared;
 278         u64 active, inactive;
 279 };
 280
 281 static int per_file_stats(int id, void *ptr, void *data)
 282 {
 283         struct drm_i915_gem_object *obj = ptr;
 284         struct file_stats *stats = data;
 285         struct i915_vma *vma;
 286
 287         stats->count++;
 288         stats->total += obj->base.size;
 289         if (!obj->bind_count)
 290                 stats->unbound += obj->base.size;
 291         if (obj->base.name || obj->base.dma_buf)
 292                 stats->shared += obj->base.size;
 293
 294         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 295                 if (!drm_mm_node_allocated(&vma->node))
 296                         continue;
 297
 298                 if (i915_vma_is_ggtt(vma)) {
 299                         stats->global += vma->node.size;
 300                 } else {
 301                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 302
 303                         if (ppgtt->base.file != stats->file_priv)
 304                                 continue;
 305                 }
 306
 307                 if (i915_vma_is_active(vma))
 308                         stats->active += vma->node.size;
 309                 else
 310                         stats->inactive += vma->node.size;
 311         }
 312
 313         return 0;
 314 }
 315
 316 #define print_file_stats(m, name, stats) do { \
 317         if (stats.count) \
 318                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 319                            name, \
 320                            stats.count, \
 321                            stats.total, \
 322                            stats.active, \
 323                            stats.inactive, \
 324                            stats.global, \
 325                            stats.shared, \
 326                            stats.unbound); \
 327 } while (0)
 328
 329 static void print_batch_pool_stats(struct seq_file *m,
 330                                    struct drm_i915_private *dev_priv)
 331 {
 332         struct drm_i915_gem_object *obj;
 333         struct file_stats stats;
 334         struct intel_engine_cs *engine;
 335         enum intel_engine_id id;
 336         int j;
 337
 338         memset(&stats, 0, sizeof(stats));
 339
 340         for_each_engine(engine, dev_priv, id) {
 341                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 342                         list_for_each_entry(obj,
 343                                             &engine->batch_pool.cache_list[j],
 344                                             batch_pool_link)
 345                                 per_file_stats(0, obj, &stats);
 346                 }
 347         }
 348
 349         print_file_stats(m, "[k]batch pool", stats);
 350 }
 351
 352 static int per_file_ctx_stats(int id, void *ptr, void *data)
 353 {
 354         struct i915_gem_context *ctx = ptr;
 355         int n;
 356
 357         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 358                 if (ctx->engine[n].state)
 359                         per_file_stats(0, ctx->engine[n].state->obj, data);
 360                 if (ctx->engine[n].ring)
 361                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 362         }
 363
 364         return 0;
 365 }
 366
 367 static void print_context_stats(struct seq_file *m,
 368                                 struct drm_i915_private *dev_priv)
 369 {
 370         struct drm_device *dev = &dev_priv->drm;
 371         struct file_stats stats;
 372         struct drm_file *file;
 373
 374         memset(&stats, 0, sizeof(stats));
 375
 376         mutex_lock(&dev->struct_mutex);
 377         if (dev_priv->kernel_context)
 378                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 379
 380         list_for_each_entry(file, &dev->filelist, lhead) {
 381                 struct drm_i915_file_private *fpriv = file->driver_priv;
 382                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 383         }
 384         mutex_unlock(&dev->struct_mutex);
 385
 386         print_file_stats(m, "[k]contexts", stats);
 387 }
 388
 389 static int i915_gem_object_info(struct seq_file *m, void *data)
 390 {
 391         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 392         struct drm_device *dev = &dev_priv->drm;
 393         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 394         u32 count, mapped_count, purgeable_count, dpy_count;
 395         u64 size, mapped_size, purgeable_size, dpy_size;
 396         struct drm_i915_gem_object *obj;
 397         struct drm_file *file;
 398         int ret;
 399
 400         ret = mutex_lock_interruptible(&dev->struct_mutex);
 401         if (ret)
 402                 return ret;
 403
 404         seq_printf(m, "%u objects, %llu bytes\n",
 405                    dev_priv->mm.object_count,
 406                    dev_priv->mm.object_memory);
 407
 408         size = count = 0;
 409         mapped_size = mapped_count = 0;
 410         purgeable_size = purgeable_count = 0;
 411         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 412                 size += obj->base.size;
 413                 ++count;
 414
 415                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 416                         purgeable_size += obj->base.size;
 417                         ++purgeable_count;
 418                 }
 419
 420                 if (obj->mm.mapping) {
 421                         mapped_count++;
 422                         mapped_size += obj->base.size;
 423                 }
 424         }
 425         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 426
 427         size = count = dpy_size = dpy_count = 0;
 428         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 429                 size += obj->base.size;
 430                 ++count;
 431
 432                 if (obj->pin_display) {
 433                         dpy_size += obj->base.size;
 434                         ++dpy_count;
 435                 }
 436
 437                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 438                         purgeable_size += obj->base.size;
 439                         ++purgeable_count;
 440                 }
 441
 442                 if (obj->mm.mapping) {
 443                         mapped_count++;
 444                         mapped_size += obj->base.size;
 445                 }
 446         }
 447         seq_printf(m, "%u bound objects, %llu bytes\n",
 448                    count, size);
 449         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 450                    purgeable_count, purgeable_size);
 451         seq_printf(m, "%u mapped objects, %llu bytes\n",
 452                    mapped_count, mapped_size);
 453         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 454                    dpy_count, dpy_size);
 455
 456         seq_printf(m, "%llu [%llu] gtt total\n",
 457                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 458
 459         seq_putc(m, '\n');
 460         print_batch_pool_stats(m, dev_priv);
 461         mutex_unlock(&dev->struct_mutex);
 462
 463         mutex_lock(&dev->filelist_mutex);
 464         print_context_stats(m, dev_priv);
 465         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 466                 struct file_stats stats;
 467                 struct drm_i915_file_private *file_priv = file->driver_priv;
 468                 struct drm_i915_gem_request *request;
 469                 struct task_struct *task;
 470
 471                 memset(&stats, 0, sizeof(stats));
 472                 stats.file_priv = file->driver_priv;
 473                 spin_lock(&file->table_lock);
 474                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 475                 spin_unlock(&file->table_lock);
 476                 /*
 477                  * Although we have a valid reference on file->pid, that does
 478                  * not guarantee that the task_struct who called get_pid() is
 479                  * still alive (e.g. get_pid(current) => fork() => exit()).
 480                  * Therefore, we need to protect this ->comm access using RCU.
 481                  */
 482                 mutex_lock(&dev->struct_mutex);
 483                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 484                                                    struct drm_i915_gem_request,
 485                                                    client_list);
 486                 rcu_read_lock();
 487                 task = pid_task(request && request->ctx->pid ?
 488                                 request->ctx->pid : file->pid,
 489                                 PIDTYPE_PID);
 490                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 491                 rcu_read_unlock();
 492                 mutex_unlock(&dev->struct_mutex);
 493         }
 494         mutex_unlock(&dev->filelist_mutex);
 495
 496         return 0;
 497 }
 498
 499 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 500 {
 501         struct drm_info_node *node = m->private;
 502         struct drm_i915_private *dev_priv = node_to_i915(node);
 503         struct drm_device *dev = &dev_priv->drm;
 504         bool show_pin_display_only = !!node->info_ent->data;
 505         struct drm_i915_gem_object *obj;
 506         u64 total_obj_size, total_gtt_size;
 507         int count, ret;
 508
 509         ret = mutex_lock_interruptible(&dev->struct_mutex);
 510         if (ret)
 511                 return ret;
 512
 513         total_obj_size = total_gtt_size = count = 0;
 514         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 515                 if (show_pin_display_only && !obj->pin_display)
 516                         continue;
 517
 518                 seq_puts(m, "   ");
 519                 describe_obj(m, obj);
 520                 seq_putc(m, '\n');
 521                 total_obj_size += obj->base.size;
 522                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 523                 count++;
 524         }
 525
 526         mutex_unlock(&dev->struct_mutex);
 527
 528         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 529                    count, total_obj_size, total_gtt_size);
 530
 531         return 0;
 532 }
 533
 534 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 535 {
 536         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 537         struct drm_device *dev = &dev_priv->drm;
 538         struct intel_crtc *crtc;
 539         int ret;
 540
 541         ret = mutex_lock_interruptible(&dev->struct_mutex);
 542         if (ret)
 543                 return ret;
 544
 545         for_each_intel_crtc(dev, crtc) {
 546                 const char pipe = pipe_name(crtc->pipe);
 547                 const char plane = plane_name(crtc->plane);
 548                 struct intel_flip_work *work;
 549
 550                 spin_lock_irq(&dev->event_lock);
 551                 work = crtc->flip_work;
 552                 if (work == NULL) {
 553                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 554                                    pipe, plane);
 555                 } else {
 556                         u32 pending;
 557                         u32 addr;
 558
 559                         pending = atomic_read(&work->pending);
 560                         if (pending) {
 561                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 562                                            pipe, plane);
 563                         } else {
 564                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 565                                            pipe, plane);
 566                         }
 567                         if (work->flip_queued_req) {
 568                                 struct intel_engine_cs *engine = work->flip_queued_req->engine;
 569
 570                                 seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n",
 571                                            engine->name,
 572                                            work->flip_queued_req->global_seqno,
 573                                            intel_engine_last_submit(engine),
 574                                            intel_engine_get_seqno(engine),
 575                                            i915_gem_request_completed(work->flip_queued_req));
 576                         } else
 577                                 seq_printf(m, "Flip not associated with any ring\n");
 578                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 579                                    work->flip_queued_vblank,
 580                                    work->flip_ready_vblank,
 581                                    intel_crtc_get_vblank_counter(crtc));
 582                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 583
 584                         if (INTEL_GEN(dev_priv) >= 4)
 585                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 586                         else
 587                                 addr = I915_READ(DSPADDR(crtc->plane));
 588                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 589
 590                         if (work->pending_flip_obj) {
 591                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 592                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 593                         }
 594                 }
 595                 spin_unlock_irq(&dev->event_lock);
 596         }
 597
 598         mutex_unlock(&dev->struct_mutex);
 599
 600         return 0;
 601 }
 602
 603 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 604 {
 605         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 606         struct drm_device *dev = &dev_priv->drm;
 607         struct drm_i915_gem_object *obj;
 608         struct intel_engine_cs *engine;
 609         enum intel_engine_id id;
 610         int total = 0;
 611         int ret, j;
 612
 613         ret = mutex_lock_interruptible(&dev->struct_mutex);
 614         if (ret)
 615                 return ret;
 616
 617         for_each_engine(engine, dev_priv, id) {
 618                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 619                         int count;
 620
 621                         count = 0;
 622                         list_for_each_entry(obj,
 623                                             &engine->batch_pool.cache_list[j],
 624                                             batch_pool_link)
 625                                 count++;
 626                         seq_printf(m, "%s cache[%d]: %d objects\n",
 627                                    engine->name, j, count);
 628
 629                         list_for_each_entry(obj,
 630                                             &engine->batch_pool.cache_list[j],
 631                                             batch_pool_link) {
 632                                 seq_puts(m, "   ");
 633                                 describe_obj(m, obj);
 634                                 seq_putc(m, '\n');
 635                         }
 636
 637                         total += count;
 638                 }
 639         }
 640
 641         seq_printf(m, "total: %d\n", total);
 642
 643         mutex_unlock(&dev->struct_mutex);
 644
 645         return 0;
 646 }
 647
 648 static void print_request(struct seq_file *m,
 649                           struct drm_i915_gem_request *rq,
 650                           const char *prefix)
 651 {
 652         seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
 653                    rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
 654                    rq->priotree.priority,
 655                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 656                    rq->timeline->common->name);
 657 }
 658
 659 static int i915_gem_request_info(struct seq_file *m, void *data)
 660 {
 661         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 662         struct drm_device *dev = &dev_priv->drm;
 663         struct drm_i915_gem_request *req;
 664         struct intel_engine_cs *engine;
 665         enum intel_engine_id id;
 666         int ret, any;
 667
 668         ret = mutex_lock_interruptible(&dev->struct_mutex);
 669         if (ret)
 670                 return ret;
 671
 672         any = 0;
 673         for_each_engine(engine, dev_priv, id) {
 674                 int count;
 675
 676                 count = 0;
 677                 list_for_each_entry(req, &engine->timeline->requests, link)
 678                         count++;
 679                 if (count == 0)
 680                         continue;
 681
 682                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 683                 list_for_each_entry(req, &engine->timeline->requests, link)
 684                         print_request(m, req, "    ");
 685
 686                 any++;
 687         }
 688         mutex_unlock(&dev->struct_mutex);
 689
 690         if (any == 0)
 691                 seq_puts(m, "No requests\n");
 692
 693         return 0;
 694 }
 695
 696 static void i915_ring_seqno_info(struct seq_file *m,
 697                                  struct intel_engine_cs *engine)
 698 {
 699         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 700         struct rb_node *rb;
 701
 702         seq_printf(m, "Current sequence (%s): %x\n",
 703                    engine->name, intel_engine_get_seqno(engine));
 704
 705         spin_lock_irq(&b->lock);
 706         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 707                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
 708
 709                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 710                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 711         }
 712         spin_unlock_irq(&b->lock);
 713 }
 714
 715 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 716 {
 717         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 718         struct intel_engine_cs *engine;
 719         enum intel_engine_id id;
 720
 721         for_each_engine(engine, dev_priv, id)
 722                 i915_ring_seqno_info(m, engine);
 723
 724         return 0;
 725 }
 726
 727
 728 static int i915_interrupt_info(struct seq_file *m, void *data)
 729 {
 730         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 731         struct intel_engine_cs *engine;
 732         enum intel_engine_id id;
 733         int i, pipe;
 734
 735         intel_runtime_pm_get(dev_priv);
 736
 737         if (IS_CHERRYVIEW(dev_priv)) {
 738                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 739                            I915_READ(GEN8_MASTER_IRQ));
 740
 741                 seq_printf(m, "Display IER:\t%08x\n",
 742                            I915_READ(VLV_IER));
 743                 seq_printf(m, "Display IIR:\t%08x\n",
 744                            I915_READ(VLV_IIR));
 745                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 746                            I915_READ(VLV_IIR_RW));
 747                 seq_printf(m, "Display IMR:\t%08x\n",
 748                            I915_READ(VLV_IMR));
 749                 for_each_pipe(dev_priv, pipe) {
 750                         enum intel_display_power_domain power_domain;
 751
 752                         power_domain = POWER_DOMAIN_PIPE(pipe);
 753                         if (!intel_display_power_get_if_enabled(dev_priv,
 754                                                                 power_domain)) {
 755                                 seq_printf(m, "Pipe %c power disabled\n",
 756                                            pipe_name(pipe));
 757                                 continue;
 758                         }
 759
 760                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 761                                    pipe_name(pipe),
 762                                    I915_READ(PIPESTAT(pipe)));
 763
 764                         intel_display_power_put(dev_priv, power_domain);
 765                 }
 766
 767                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 768                 seq_printf(m, "Port hotplug:\t%08x\n",
 769                            I915_READ(PORT_HOTPLUG_EN));
 770                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 771                            I915_READ(VLV_DPFLIPSTAT));
 772                 seq_printf(m, "DPINVGTT:\t%08x\n",
 773                            I915_READ(DPINVGTT));
 774                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 775
 776                 for (i = 0; i < 4; i++) {
 777                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 778                                    i, I915_READ(GEN8_GT_IMR(i)));
 779                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 780                                    i, I915_READ(GEN8_GT_IIR(i)));
 781                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 782                                    i, I915_READ(GEN8_GT_IER(i)));
 783                 }
 784
 785                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 786                            I915_READ(GEN8_PCU_IMR));
 787                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 788                            I915_READ(GEN8_PCU_IIR));
 789                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 790                            I915_READ(GEN8_PCU_IER));
 791         } else if (INTEL_GEN(dev_priv) >= 8) {
 792                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 793                            I915_READ(GEN8_MASTER_IRQ));
 794
 795                 for (i = 0; i < 4; i++) {
 796                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 797                                    i, I915_READ(GEN8_GT_IMR(i)));
 798                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 799                                    i, I915_READ(GEN8_GT_IIR(i)));
 800                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 801                                    i, I915_READ(GEN8_GT_IER(i)));
 802                 }
 803
 804                 for_each_pipe(dev_priv, pipe) {
 805                         enum intel_display_power_domain power_domain;
 806
 807                         power_domain = POWER_DOMAIN_PIPE(pipe);
 808                         if (!intel_display_power_get_if_enabled(dev_priv,
 809                                                                 power_domain)) {
 810                                 seq_printf(m, "Pipe %c power disabled\n",
 811                                            pipe_name(pipe));
 812                                 continue;
 813                         }
 814                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 815                                    pipe_name(pipe),
 816                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 817                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 818                                    pipe_name(pipe),
 819                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 820                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 821                                    pipe_name(pipe),
 822                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 823
 824                         intel_display_power_put(dev_priv, power_domain);
 825                 }
 826
 827                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 828                            I915_READ(GEN8_DE_PORT_IMR));
 829                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 830                            I915_READ(GEN8_DE_PORT_IIR));
 831                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 832                            I915_READ(GEN8_DE_PORT_IER));
 833
 834                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 835                            I915_READ(GEN8_DE_MISC_IMR));
 836                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 837                            I915_READ(GEN8_DE_MISC_IIR));
 838                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 839                            I915_READ(GEN8_DE_MISC_IER));
 840
 841                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 842                            I915_READ(GEN8_PCU_IMR));
 843                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 844                            I915_READ(GEN8_PCU_IIR));
 845                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 846                            I915_READ(GEN8_PCU_IER));
 847         } else if (IS_VALLEYVIEW(dev_priv)) {
 848                 seq_printf(m, "Display IER:\t%08x\n",
 849                            I915_READ(VLV_IER));
 850                 seq_printf(m, "Display IIR:\t%08x\n",
 851                            I915_READ(VLV_IIR));
 852                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 853                            I915_READ(VLV_IIR_RW));
 854                 seq_printf(m, "Display IMR:\t%08x\n",
 855                            I915_READ(VLV_IMR));
 856                 for_each_pipe(dev_priv, pipe)
 857                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 858                                    pipe_name(pipe),
 859                                    I915_READ(PIPESTAT(pipe)));
 860
 861                 seq_printf(m, "Master IER:\t%08x\n",
 862                            I915_READ(VLV_MASTER_IER));
 863
 864                 seq_printf(m, "Render IER:\t%08x\n",
 865                            I915_READ(GTIER));
 866                 seq_printf(m, "Render IIR:\t%08x\n",
 867                            I915_READ(GTIIR));
 868                 seq_printf(m, "Render IMR:\t%08x\n",
 869                            I915_READ(GTIMR));
 870
 871                 seq_printf(m, "PM IER:\t\t%08x\n",
 872                            I915_READ(GEN6_PMIER));
 873                 seq_printf(m, "PM IIR:\t\t%08x\n",
 874                            I915_READ(GEN6_PMIIR));
 875                 seq_printf(m, "PM IMR:\t\t%08x\n",
 876                            I915_READ(GEN6_PMIMR));
 877
 878                 seq_printf(m, "Port hotplug:\t%08x\n",
 879                            I915_READ(PORT_HOTPLUG_EN));
 880                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 881                            I915_READ(VLV_DPFLIPSTAT));
 882                 seq_printf(m, "DPINVGTT:\t%08x\n",
 883                            I915_READ(DPINVGTT));
 884
 885         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 886                 seq_printf(m, "Interrupt enable:    %08x\n",
 887                            I915_READ(IER));
 888                 seq_printf(m, "Interrupt identity:  %08x\n",
 889                            I915_READ(IIR));
 890                 seq_printf(m, "Interrupt mask:      %08x\n",
 891                            I915_READ(IMR));
 892                 for_each_pipe(dev_priv, pipe)
 893                         seq_printf(m, "Pipe %c stat:         %08x\n",
 894                                    pipe_name(pipe),
 895                                    I915_READ(PIPESTAT(pipe)));
 896         } else {
 897                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 898                            I915_READ(DEIER));
 899                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 900                            I915_READ(DEIIR));
 901                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 902                            I915_READ(DEIMR));
 903                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 904                            I915_READ(SDEIER));
 905                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 906                            I915_READ(SDEIIR));
 907                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 908                            I915_READ(SDEIMR));
 909                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 910                            I915_READ(GTIER));
 911                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 912                            I915_READ(GTIIR));
 913                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 914                            I915_READ(GTIMR));
 915         }
 916         for_each_engine(engine, dev_priv, id) {
 917                 if (INTEL_GEN(dev_priv) >= 6) {
 918                         seq_printf(m,
 919                                    "Graphics Interrupt mask (%s):       %08x\n",
 920                                    engine->name, I915_READ_IMR(engine));
 921                 }
 922                 i915_ring_seqno_info(m, engine);
 923         }
 924         intel_runtime_pm_put(dev_priv);
 925
 926         return 0;
 927 }
 928
 929 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 930 {
 931         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 932         struct drm_device *dev = &dev_priv->drm;
 933         int i, ret;
 934
 935         ret = mutex_lock_interruptible(&dev->struct_mutex);
 936         if (ret)
 937                 return ret;
 938
 939         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 940         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 941                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 942
 943                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 944                            i, dev_priv->fence_regs[i].pin_count);
 945                 if (!vma)
 946                         seq_puts(m, "unused");
 947                 else
 948                         describe_obj(m, vma->obj);
 949                 seq_putc(m, '\n');
 950         }
 951
 952         mutex_unlock(&dev->struct_mutex);
 953         return 0;
 954 }
 955
 956 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 957
 958 static ssize_t
 959 i915_error_state_write(struct file *filp,
 960                        const char __user *ubuf,
 961                        size_t cnt,
 962                        loff_t *ppos)
 963 {
 964         struct i915_error_state_file_priv *error_priv = filp->private_data;
 965
 966         DRM_DEBUG_DRIVER("Resetting error state\n");
 967         i915_destroy_error_state(error_priv->i915);
 968
 969         return cnt;
 970 }
 971
 972 static int i915_error_state_open(struct inode *inode, struct file *file)
 973 {
 974         struct drm_i915_private *dev_priv = inode->i_private;
 975         struct i915_error_state_file_priv *error_priv;
 976
 977         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 978         if (!error_priv)
 979                 return -ENOMEM;
 980
 981         error_priv->i915 = dev_priv;
 982
 983         i915_error_state_get(&dev_priv->drm, error_priv);
 984
 985         file->private_data = error_priv;
 986
 987         return 0;
 988 }
 989
 990 static int i915_error_state_release(struct inode *inode, struct file *file)
 991 {
 992         struct i915_error_state_file_priv *error_priv = file->private_data;
 993
 994         i915_error_state_put(error_priv);
 995         kfree(error_priv);
 996
 997         return 0;
 998 }
 999
1000 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1001                                      size_t count, loff_t *pos)
1002 {
1003         struct i915_error_state_file_priv *error_priv = file->private_data;
1004         struct drm_i915_error_state_buf error_str;
1005         loff_t tmp_pos = 0;
1006         ssize_t ret_count = 0;
1007         int ret;
1008
1009         ret = i915_error_state_buf_init(&error_str, error_priv->i915,
1010                                         count, *pos);
1011         if (ret)
1012                 return ret;
1013
1014         ret = i915_error_state_to_str(&error_str, error_priv);
1015         if (ret)
1016                 goto out;
1017
1018         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1019                                             error_str.buf,
1020                                             error_str.bytes);
1021
1022         if (ret_count < 0)
1023                 ret = ret_count;
1024         else
1025                 *pos = error_str.start + ret_count;
1026 out:
1027         i915_error_state_buf_release(&error_str);
1028         return ret ?: ret_count;
1029 }
1030
1031 static const struct file_operations i915_error_state_fops = {
1032         .owner = THIS_MODULE,
1033         .open = i915_error_state_open,
1034         .read = i915_error_state_read,
1035         .write = i915_error_state_write,
1036         .llseek = default_llseek,
1037         .release = i915_error_state_release,
1038 };
1039
1040 #endif
1041
1042 static int
1043 i915_next_seqno_get(void *data, u64 *val)
1044 {
1045         struct drm_i915_private *dev_priv = data;
1046
1047         *val = 1 + atomic_read(&dev_priv->gt.global_timeline.seqno);
1048         return 0;
1049 }
1050
1051 static int
1052 i915_next_seqno_set(void *data, u64 val)
1053 {
1054         struct drm_i915_private *dev_priv = data;
1055         struct drm_device *dev = &dev_priv->drm;
1056         int ret;
1057
1058         ret = mutex_lock_interruptible(&dev->struct_mutex);
1059         if (ret)
1060                 return ret;
1061
1062         ret = i915_gem_set_global_seqno(dev, val);
1063         mutex_unlock(&dev->struct_mutex);
1064
1065         return ret;
1066 }
1067
1068 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1069                         i915_next_seqno_get, i915_next_seqno_set,
1070                         "0x%llx\n");
1071
1072 static int i915_frequency_info(struct seq_file *m, void *unused)
1073 {
1074         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1075         struct drm_device *dev = &dev_priv->drm;
1076         int ret = 0;
1077
1078         intel_runtime_pm_get(dev_priv);
1079
1080         if (IS_GEN5(dev_priv)) {
1081                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1082                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1083
1084                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1085                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1086                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1087                            MEMSTAT_VID_SHIFT);
1088                 seq_printf(m, "Current P-state: %d\n",
1089                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1090         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1091                 u32 freq_sts;
1092
1093                 mutex_lock(&dev_priv->rps.hw_lock);
1094                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1095                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1096                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1097
1098                 seq_printf(m, "actual GPU freq: %d MHz\n",
1099                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1100
1101                 seq_printf(m, "current GPU freq: %d MHz\n",
1102                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1103
1104                 seq_printf(m, "max GPU freq: %d MHz\n",
1105                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1106
1107                 seq_printf(m, "min GPU freq: %d MHz\n",
1108                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1109
1110                 seq_printf(m, "idle GPU freq: %d MHz\n",
1111                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1112
1113                 seq_printf(m,
1114                            "efficient (RPe) frequency: %d MHz\n",
1115                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1116                 mutex_unlock(&dev_priv->rps.hw_lock);
1117         } else if (INTEL_GEN(dev_priv) >= 6) {
1118                 u32 rp_state_limits;
1119                 u32 gt_perf_status;
1120                 u32 rp_state_cap;
1121                 u32 rpmodectl, rpinclimit, rpdeclimit;
1122                 u32 rpstat, cagf, reqf;
1123                 u32 rpupei, rpcurup, rpprevup;
1124                 u32 rpdownei, rpcurdown, rpprevdown;
1125                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1126                 int max_freq;
1127
1128                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1129                 if (IS_GEN9_LP(dev_priv)) {
1130                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1131                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1132                 } else {
1133                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1134                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1135                 }
1136
1137                 /* RPSTAT1 is in the GT power well */
1138                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1139                 if (ret)
1140                         goto out;
1141
1142                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1143
1144                 reqf = I915_READ(GEN6_RPNSWREQ);
1145                 if (IS_GEN9(dev_priv))
1146                         reqf >>= 23;
1147                 else {
1148                         reqf &= ~GEN6_TURBO_DISABLE;
1149                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1150                                 reqf >>= 24;
1151                         else
1152                                 reqf >>= 25;
1153                 }
1154                 reqf = intel_gpu_freq(dev_priv, reqf);
1155
1156                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1157                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1158                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1159
1160                 rpstat = I915_READ(GEN6_RPSTAT1);
1161                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1162                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1163                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1164                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1165                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1166                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1167                 if (IS_GEN9(dev_priv))
1168                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1169                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1170                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1171                 else
1172                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1173                 cagf = intel_gpu_freq(dev_priv, cagf);
1174
1175                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1176                 mutex_unlock(&dev->struct_mutex);
1177
1178                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1179                         pm_ier = I915_READ(GEN6_PMIER);
1180                         pm_imr = I915_READ(GEN6_PMIMR);
1181                         pm_isr = I915_READ(GEN6_PMISR);
1182                         pm_iir = I915_READ(GEN6_PMIIR);
1183                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1184                 } else {
1185                         pm_ier = I915_READ(GEN8_GT_IER(2));
1186                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1187                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1188                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1189                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1190                 }
1191                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1192                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1193                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1194                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1195                 seq_printf(m, "Render p-state ratio: %d\n",
1196                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1197                 seq_printf(m, "Render p-state VID: %d\n",
1198                            gt_perf_status & 0xff);
1199                 seq_printf(m, "Render p-state limit: %d\n",
1200                            rp_state_limits & 0xff);
1201                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1202                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1203                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1204                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1205                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1206                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1207                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1208                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1209                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1210                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1211                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1212                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1213                 seq_printf(m, "Up threshold: %d%%\n",
1214                            dev_priv->rps.up_threshold);
1215
1216                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1217                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1218                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1219                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1220                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1221                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1222                 seq_printf(m, "Down threshold: %d%%\n",
1223                            dev_priv->rps.down_threshold);
1224
1225                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1226                             rp_state_cap >> 16) & 0xff;
1227                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1228                              GEN9_FREQ_SCALER : 1);
1229                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1230                            intel_gpu_freq(dev_priv, max_freq));
1231
1232                 max_freq = (rp_state_cap & 0xff00) >> 8;
1233                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1234                              GEN9_FREQ_SCALER : 1);
1235                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1236                            intel_gpu_freq(dev_priv, max_freq));
1237
1238                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1239                             rp_state_cap >> 0) & 0xff;
1240                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1241                              GEN9_FREQ_SCALER : 1);
1242                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1243                            intel_gpu_freq(dev_priv, max_freq));
1244                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1245                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1246
1247                 seq_printf(m, "Current freq: %d MHz\n",
1248                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1249                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1250                 seq_printf(m, "Idle freq: %d MHz\n",
1251                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1252                 seq_printf(m, "Min freq: %d MHz\n",
1253                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1254                 seq_printf(m, "Boost freq: %d MHz\n",
1255                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1256                 seq_printf(m, "Max freq: %d MHz\n",
1257                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1258                 seq_printf(m,
1259                            "efficient (RPe) frequency: %d MHz\n",
1260                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1261         } else {
1262                 seq_puts(m, "no P-state info available\n");
1263         }
1264
1265         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1266         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1267         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1268
1269 out:
1270         intel_runtime_pm_put(dev_priv);
1271         return ret;
1272 }
1273
1274 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1275                                struct seq_file *m,
1276                                struct intel_instdone *instdone)
1277 {
1278         int slice;
1279         int subslice;
1280
1281         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1282                    instdone->instdone);
1283
1284         if (INTEL_GEN(dev_priv) <= 3)
1285                 return;
1286
1287         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1288                    instdone->slice_common);
1289
1290         if (INTEL_GEN(dev_priv) <= 6)
1291                 return;
1292
1293         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1294                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1295                            slice, subslice, instdone->sampler[slice][subslice]);
1296
1297         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1298                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1299                            slice, subslice, instdone->row[slice][subslice]);
1300 }
1301
1302 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1303 {
1304         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1305         struct intel_engine_cs *engine;
1306         u64 acthd[I915_NUM_ENGINES];
1307         u32 seqno[I915_NUM_ENGINES];
1308         struct intel_instdone instdone;
1309         enum intel_engine_id id;
1310
1311         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1312                 seq_printf(m, "Wedged\n");
1313         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1314                 seq_printf(m, "Reset in progress\n");
1315         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1316                 seq_printf(m, "Waiter holding struct mutex\n");
1317         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1318                 seq_printf(m, "struct_mutex blocked for reset\n");
1319
1320         if (!i915.enable_hangcheck) {
1321                 seq_printf(m, "Hangcheck disabled\n");
1322                 return 0;
1323         }
1324
1325         intel_runtime_pm_get(dev_priv);
1326
1327         for_each_engine(engine, dev_priv, id) {
1328                 acthd[id] = intel_engine_get_active_head(engine);
1329                 seqno[id] = intel_engine_get_seqno(engine);
1330         }
1331
1332         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1333
1334         intel_runtime_pm_put(dev_priv);
1335
1336         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1337                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1338                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1339                                             jiffies));
1340         } else
1341                 seq_printf(m, "Hangcheck inactive\n");
1342
1343         for_each_engine(engine, dev_priv, id) {
1344                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1345                 struct rb_node *rb;
1346
1347                 seq_printf(m, "%s:\n", engine->name);
1348                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1349                            engine->hangcheck.seqno, seqno[id],
1350                            intel_engine_last_submit(engine));
1351                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1352                            yesno(intel_engine_has_waiter(engine)),
1353                            yesno(test_bit(engine->id,
1354                                           &dev_priv->gpu_error.missed_irq_rings)),
1355                            yesno(engine->hangcheck.stalled));
1356
1357                 spin_lock_irq(&b->lock);
1358                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1359                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1360
1361                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1362                                    w->tsk->comm, w->tsk->pid, w->seqno);
1363                 }
1364                 spin_unlock_irq(&b->lock);
1365
1366                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1367                            (long long)engine->hangcheck.acthd,
1368                            (long long)acthd[id]);
1369                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1370                            hangcheck_action_to_str(engine->hangcheck.action),
1371                            engine->hangcheck.action,
1372                            jiffies_to_msecs(jiffies -
1373                                             engine->hangcheck.action_timestamp));
1374
1375                 if (engine->id == RCS) {
1376                         seq_puts(m, "\tinstdone read =\n");
1377
1378                         i915_instdone_info(dev_priv, m, &instdone);
1379
1380                         seq_puts(m, "\tinstdone accu =\n");
1381
1382                         i915_instdone_info(dev_priv, m,
1383                                            &engine->hangcheck.instdone);
1384                 }
1385         }
1386
1387         return 0;
1388 }
1389
1390 static int ironlake_drpc_info(struct seq_file *m)
1391 {
1392         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1393         u32 rgvmodectl, rstdbyctl;
1394         u16 crstandvid;
1395
1396         intel_runtime_pm_get(dev_priv);
1397
1398         rgvmodectl = I915_READ(MEMMODECTL);
1399         rstdbyctl = I915_READ(RSTDBYCTL);
1400         crstandvid = I915_READ16(CRSTANDVID);
1401
1402         intel_runtime_pm_put(dev_priv);
1403
1404         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1405         seq_printf(m, "Boost freq: %d\n",
1406                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1407                    MEMMODE_BOOST_FREQ_SHIFT);
1408         seq_printf(m, "HW control enabled: %s\n",
1409                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1410         seq_printf(m, "SW control enabled: %s\n",
1411                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1412         seq_printf(m, "Gated voltage change: %s\n",
1413                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1414         seq_printf(m, "Starting frequency: P%d\n",
1415                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1416         seq_printf(m, "Max P-state: P%d\n",
1417                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1418         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1419         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1420         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1421         seq_printf(m, "Render standby enabled: %s\n",
1422                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1423         seq_puts(m, "Current RS state: ");
1424         switch (rstdbyctl & RSX_STATUS_MASK) {
1425         case RSX_STATUS_ON:
1426                 seq_puts(m, "on\n");
1427                 break;
1428         case RSX_STATUS_RC1:
1429                 seq_puts(m, "RC1\n");
1430                 break;
1431         case RSX_STATUS_RC1E:
1432                 seq_puts(m, "RC1E\n");
1433                 break;
1434         case RSX_STATUS_RS1:
1435                 seq_puts(m, "RS1\n");
1436                 break;
1437         case RSX_STATUS_RS2:
1438                 seq_puts(m, "RS2 (RC6)\n");
1439                 break;
1440         case RSX_STATUS_RS3:
1441                 seq_puts(m, "RC3 (RC6+)\n");
1442                 break;
1443         default:
1444                 seq_puts(m, "unknown\n");
1445                 break;
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int i915_forcewake_domains(struct seq_file *m, void *data)
1452 {
1453         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1454         struct intel_uncore_forcewake_domain *fw_domain;
1455
1456         spin_lock_irq(&dev_priv->uncore.lock);
1457         for_each_fw_domain(fw_domain, dev_priv) {
1458                 seq_printf(m, "%s.wake_count = %u\n",
1459                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1460                            fw_domain->wake_count);
1461         }
1462         spin_unlock_irq(&dev_priv->uncore.lock);
1463
1464         return 0;
1465 }
1466
1467 static int vlv_drpc_info(struct seq_file *m)
1468 {
1469         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1470         u32 rpmodectl1, rcctl1, pw_status;
1471
1472         intel_runtime_pm_get(dev_priv);
1473
1474         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1475         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1476         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1477
1478         intel_runtime_pm_put(dev_priv);
1479
1480         seq_printf(m, "Video Turbo Mode: %s\n",
1481                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1482         seq_printf(m, "Turbo enabled: %s\n",
1483                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1484         seq_printf(m, "HW control enabled: %s\n",
1485                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1486         seq_printf(m, "SW control enabled: %s\n",
1487                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1488                           GEN6_RP_MEDIA_SW_MODE));
1489         seq_printf(m, "RC6 Enabled: %s\n",
1490                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1491                                         GEN6_RC_CTL_EI_MODE(1))));
1492         seq_printf(m, "Render Power Well: %s\n",
1493                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1494         seq_printf(m, "Media Power Well: %s\n",
1495                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1496
1497         seq_printf(m, "Render RC6 residency since boot: %u\n",
1498                    I915_READ(VLV_GT_RENDER_RC6));
1499         seq_printf(m, "Media RC6 residency since boot: %u\n",
1500                    I915_READ(VLV_GT_MEDIA_RC6));
1501
1502         return i915_forcewake_domains(m, NULL);
1503 }
1504
1505 static int gen6_drpc_info(struct seq_file *m)
1506 {
1507         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1508         struct drm_device *dev = &dev_priv->drm;
1509         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1510         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1511         unsigned forcewake_count;
1512         int count = 0, ret;
1513
1514         ret = mutex_lock_interruptible(&dev->struct_mutex);
1515         if (ret)
1516                 return ret;
1517         intel_runtime_pm_get(dev_priv);
1518
1519         spin_lock_irq(&dev_priv->uncore.lock);
1520         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1521         spin_unlock_irq(&dev_priv->uncore.lock);
1522
1523         if (forcewake_count) {
1524                 seq_puts(m, "RC information inaccurate because somebody "
1525                             "holds a forcewake reference \n");
1526         } else {
1527                 /* NB: we cannot use forcewake, else we read the wrong values */
1528                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1529                         udelay(10);
1530                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1531         }
1532
1533         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1534         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1535
1536         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1537         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1538         if (INTEL_GEN(dev_priv) >= 9) {
1539                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1540                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1541         }
1542         mutex_unlock(&dev->struct_mutex);
1543         mutex_lock(&dev_priv->rps.hw_lock);
1544         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1545         mutex_unlock(&dev_priv->rps.hw_lock);
1546
1547         intel_runtime_pm_put(dev_priv);
1548
1549         seq_printf(m, "Video Turbo Mode: %s\n",
1550                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1551         seq_printf(m, "HW control enabled: %s\n",
1552                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1553         seq_printf(m, "SW control enabled: %s\n",
1554                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1555                           GEN6_RP_MEDIA_SW_MODE));
1556         seq_printf(m, "RC1e Enabled: %s\n",
1557                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1558         seq_printf(m, "RC6 Enabled: %s\n",
1559                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1560         if (INTEL_GEN(dev_priv) >= 9) {
1561                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1562                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1563                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1564                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1565         }
1566         seq_printf(m, "Deep RC6 Enabled: %s\n",
1567                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1568         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1569                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1570         seq_puts(m, "Current RC state: ");
1571         switch (gt_core_status & GEN6_RCn_MASK) {
1572         case GEN6_RC0:
1573                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1574                         seq_puts(m, "Core Power Down\n");
1575                 else
1576                         seq_puts(m, "on\n");
1577                 break;
1578         case GEN6_RC3:
1579                 seq_puts(m, "RC3\n");
1580                 break;
1581         case GEN6_RC6:
1582                 seq_puts(m, "RC6\n");
1583                 break;
1584         case GEN6_RC7:
1585                 seq_puts(m, "RC7\n");
1586                 break;
1587         default:
1588                 seq_puts(m, "Unknown\n");
1589                 break;
1590         }
1591
1592         seq_printf(m, "Core Power Down: %s\n",
1593                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1594         if (INTEL_GEN(dev_priv) >= 9) {
1595                 seq_printf(m, "Render Power Well: %s\n",
1596                         (gen9_powergate_status &
1597                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1598                 seq_printf(m, "Media Power Well: %s\n",
1599                         (gen9_powergate_status &
1600                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1601         }
1602
1603         /* Not exactly sure what this is */
1604         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1605                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1606         seq_printf(m, "RC6 residency since boot: %u\n",
1607                    I915_READ(GEN6_GT_GFX_RC6));
1608         seq_printf(m, "RC6+ residency since boot: %u\n",
1609                    I915_READ(GEN6_GT_GFX_RC6p));
1610         seq_printf(m, "RC6++ residency since boot: %u\n",
1611                    I915_READ(GEN6_GT_GFX_RC6pp));
1612
1613         seq_printf(m, "RC6   voltage: %dmV\n",
1614                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1615         seq_printf(m, "RC6+  voltage: %dmV\n",
1616                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1617         seq_printf(m, "RC6++ voltage: %dmV\n",
1618                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1619         return i915_forcewake_domains(m, NULL);
1620 }
1621
1622 static int i915_drpc_info(struct seq_file *m, void *unused)
1623 {
1624         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1625
1626         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1627                 return vlv_drpc_info(m);
1628         else if (INTEL_GEN(dev_priv) >= 6)
1629                 return gen6_drpc_info(m);
1630         else
1631                 return ironlake_drpc_info(m);
1632 }
1633
1634 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1635 {
1636         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1637
1638         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1639                    dev_priv->fb_tracking.busy_bits);
1640
1641         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1642                    dev_priv->fb_tracking.flip_bits);
1643
1644         return 0;
1645 }
1646
1647 static int i915_fbc_status(struct seq_file *m, void *unused)
1648 {
1649         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1650
1651         if (!HAS_FBC(dev_priv)) {
1652                 seq_puts(m, "FBC unsupported on this chipset\n");
1653                 return 0;
1654         }
1655
1656         intel_runtime_pm_get(dev_priv);
1657         mutex_lock(&dev_priv->fbc.lock);
1658
1659         if (intel_fbc_is_active(dev_priv))
1660                 seq_puts(m, "FBC enabled\n");
1661         else
1662                 seq_printf(m, "FBC disabled: %s\n",
1663                            dev_priv->fbc.no_fbc_reason);
1664
1665         if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1666                 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1667                                 BDW_FBC_COMPRESSION_MASK :
1668                                 IVB_FBC_COMPRESSION_MASK;
1669                 seq_printf(m, "Compressing: %s\n",
1670                            yesno(I915_READ(FBC_STATUS2) & mask));
1671         }
1672
1673         mutex_unlock(&dev_priv->fbc.lock);
1674         intel_runtime_pm_put(dev_priv);
1675
1676         return 0;
1677 }
1678
1679 static int i915_fbc_fc_get(void *data, u64 *val)
1680 {
1681         struct drm_i915_private *dev_priv = data;
1682
1683         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1684                 return -ENODEV;
1685
1686         *val = dev_priv->fbc.false_color;
1687
1688         return 0;
1689 }
1690
1691 static int i915_fbc_fc_set(void *data, u64 val)
1692 {
1693         struct drm_i915_private *dev_priv = data;
1694         u32 reg;
1695
1696         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1697                 return -ENODEV;
1698
1699         mutex_lock(&dev_priv->fbc.lock);
1700
1701         reg = I915_READ(ILK_DPFC_CONTROL);
1702         dev_priv->fbc.false_color = val;
1703
1704         I915_WRITE(ILK_DPFC_CONTROL, val ?
1705                    (reg | FBC_CTL_FALSE_COLOR) :
1706                    (reg & ~FBC_CTL_FALSE_COLOR));
1707
1708         mutex_unlock(&dev_priv->fbc.lock);
1709         return 0;
1710 }
1711
1712 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1713                         i915_fbc_fc_get, i915_fbc_fc_set,
1714                         "%llu\n");
1715
1716 static int i915_ips_status(struct seq_file *m, void *unused)
1717 {
1718         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1719
1720         if (!HAS_IPS(dev_priv)) {
1721                 seq_puts(m, "not supported\n");
1722                 return 0;
1723         }
1724
1725         intel_runtime_pm_get(dev_priv);
1726
1727         seq_printf(m, "Enabled by kernel parameter: %s\n",
1728                    yesno(i915.enable_ips));
1729
1730         if (INTEL_GEN(dev_priv) >= 8) {
1731                 seq_puts(m, "Currently: unknown\n");
1732         } else {
1733                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1734                         seq_puts(m, "Currently: enabled\n");
1735                 else
1736                         seq_puts(m, "Currently: disabled\n");
1737         }
1738
1739         intel_runtime_pm_put(dev_priv);
1740
1741         return 0;
1742 }
1743
1744 static int i915_sr_status(struct seq_file *m, void *unused)
1745 {
1746         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1747         bool sr_enabled = false;
1748
1749         intel_runtime_pm_get(dev_priv);
1750         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1751
1752         if (HAS_PCH_SPLIT(dev_priv))
1753                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1754         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1755                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1756                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1757         else if (IS_I915GM(dev_priv))
1758                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1759         else if (IS_PINEVIEW(dev_priv))
1760                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1761         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1762                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1763
1764         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1765         intel_runtime_pm_put(dev_priv);
1766
1767         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1768
1769         return 0;
1770 }
1771
1772 static int i915_emon_status(struct seq_file *m, void *unused)
1773 {
1774         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1775         struct drm_device *dev = &dev_priv->drm;
1776         unsigned long temp, chipset, gfx;
1777         int ret;
1778
1779         if (!IS_GEN5(dev_priv))
1780                 return -ENODEV;
1781
1782         ret = mutex_lock_interruptible(&dev->struct_mutex);
1783         if (ret)
1784                 return ret;
1785
1786         temp = i915_mch_val(dev_priv);
1787         chipset = i915_chipset_val(dev_priv);
1788         gfx = i915_gfx_val(dev_priv);
1789         mutex_unlock(&dev->struct_mutex);
1790
1791         seq_printf(m, "GMCH temp: %ld\n", temp);
1792         seq_printf(m, "Chipset power: %ld\n", chipset);
1793         seq_printf(m, "GFX power: %ld\n", gfx);
1794         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1795
1796         return 0;
1797 }
1798
1799 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1800 {
1801         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1802         int ret = 0;
1803         int gpu_freq, ia_freq;
1804         unsigned int max_gpu_freq, min_gpu_freq;
1805
1806         if (!HAS_LLC(dev_priv)) {
1807                 seq_puts(m, "unsupported on this chipset\n");
1808                 return 0;
1809         }
1810
1811         intel_runtime_pm_get(dev_priv);
1812
1813         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1814         if (ret)
1815                 goto out;
1816
1817         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1818                 /* Convert GT frequency to 50 HZ units */
1819                 min_gpu_freq =
1820                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1821                 max_gpu_freq =
1822                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1823         } else {
1824                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1825                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1826         }
1827
1828         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1829
1830         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1831                 ia_freq = gpu_freq;
1832                 sandybridge_pcode_read(dev_priv,
1833                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1834                                        &ia_freq);
1835                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1836                            intel_gpu_freq(dev_priv, (gpu_freq *
1837                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1838                                  GEN9_FREQ_SCALER : 1))),
1839                            ((ia_freq >> 0) & 0xff) * 100,
1840                            ((ia_freq >> 8) & 0xff) * 100);
1841         }
1842
1843         mutex_unlock(&dev_priv->rps.hw_lock);
1844
1845 out:
1846         intel_runtime_pm_put(dev_priv);
1847         return ret;
1848 }
1849
1850 static int i915_opregion(struct seq_file *m, void *unused)
1851 {
1852         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1853         struct drm_device *dev = &dev_priv->drm;
1854         struct intel_opregion *opregion = &dev_priv->opregion;
1855         int ret;
1856
1857         ret = mutex_lock_interruptible(&dev->struct_mutex);
1858         if (ret)
1859                 goto out;
1860
1861         if (opregion->header)
1862                 seq_write(m, opregion->header, OPREGION_SIZE);
1863
1864         mutex_unlock(&dev->struct_mutex);
1865
1866 out:
1867         return 0;
1868 }
1869
1870 static int i915_vbt(struct seq_file *m, void *unused)
1871 {
1872         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1873
1874         if (opregion->vbt)
1875                 seq_write(m, opregion->vbt, opregion->vbt_size);
1876
1877         return 0;
1878 }
1879
1880 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1881 {
1882         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1883         struct drm_device *dev = &dev_priv->drm;
1884         struct intel_framebuffer *fbdev_fb = NULL;
1885         struct drm_framebuffer *drm_fb;
1886         int ret;
1887
1888         ret = mutex_lock_interruptible(&dev->struct_mutex);
1889         if (ret)
1890                 return ret;
1891
1892 #ifdef CONFIG_DRM_FBDEV_EMULATION
1893         if (dev_priv->fbdev) {
1894                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1895
1896                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1897                            fbdev_fb->base.width,
1898                            fbdev_fb->base.height,
1899                            fbdev_fb->base.format->depth,
1900                            fbdev_fb->base.format->cpp[0] * 8,
1901                            fbdev_fb->base.modifier,
1902                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1903                 describe_obj(m, fbdev_fb->obj);
1904                 seq_putc(m, '\n');
1905         }
1906 #endif
1907
1908         mutex_lock(&dev->mode_config.fb_lock);
1909         drm_for_each_fb(drm_fb, dev) {
1910                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1911                 if (fb == fbdev_fb)
1912                         continue;
1913
1914                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1915                            fb->base.width,
1916                            fb->base.height,
1917                            fb->base.format->depth,
1918                            fb->base.format->cpp[0] * 8,
1919                            fb->base.modifier,
1920                            drm_framebuffer_read_refcount(&fb->base));
1921                 describe_obj(m, fb->obj);
1922                 seq_putc(m, '\n');
1923         }
1924         mutex_unlock(&dev->mode_config.fb_lock);
1925         mutex_unlock(&dev->struct_mutex);
1926
1927         return 0;
1928 }
1929
1930 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1931 {
1932         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1933                    ring->space, ring->head, ring->tail,
1934                    ring->last_retired_head);
1935 }
1936
1937 static int i915_context_status(struct seq_file *m, void *unused)
1938 {
1939         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1940         struct drm_device *dev = &dev_priv->drm;
1941         struct intel_engine_cs *engine;
1942         struct i915_gem_context *ctx;
1943         enum intel_engine_id id;
1944         int ret;
1945
1946         ret = mutex_lock_interruptible(&dev->struct_mutex);
1947         if (ret)
1948                 return ret;
1949
1950         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1951                 seq_printf(m, "HW context %u ", ctx->hw_id);
1952                 if (ctx->pid) {
1953                         struct task_struct *task;
1954
1955                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1956                         if (task) {
1957                                 seq_printf(m, "(%s [%d]) ",
1958                                            task->comm, task->pid);
1959                                 put_task_struct(task);
1960                         }
1961                 } else if (IS_ERR(ctx->file_priv)) {
1962                         seq_puts(m, "(deleted) ");
1963                 } else {
1964                         seq_puts(m, "(kernel) ");
1965                 }
1966
1967                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1968                 seq_putc(m, '\n');
1969
1970                 for_each_engine(engine, dev_priv, id) {
1971                         struct intel_context *ce = &ctx->engine[engine->id];
1972
1973                         seq_printf(m, "%s: ", engine->name);
1974                         seq_putc(m, ce->initialised ? 'I' : 'i');
1975                         if (ce->state)
1976                                 describe_obj(m, ce->state->obj);
1977                         if (ce->ring)
1978                                 describe_ctx_ring(m, ce->ring);
1979                         seq_putc(m, '\n');
1980                 }
1981
1982                 seq_putc(m, '\n');
1983         }
1984
1985         mutex_unlock(&dev->struct_mutex);
1986
1987         return 0;
1988 }
1989
1990 static void i915_dump_lrc_obj(struct seq_file *m,
1991                               struct i915_gem_context *ctx,
1992                               struct intel_engine_cs *engine)
1993 {
1994         struct i915_vma *vma = ctx->engine[engine->id].state;
1995         struct page *page;
1996         int j;
1997
1998         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1999
2000         if (!vma) {
2001                 seq_puts(m, "\tFake context\n");
2002                 return;
2003         }
2004
2005         if (vma->flags & I915_VMA_GLOBAL_BIND)
2006                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2007                            i915_ggtt_offset(vma));
2008
2009         if (i915_gem_object_pin_pages(vma->obj)) {
2010                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2011                 return;
2012         }
2013
2014         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2015         if (page) {
2016                 u32 *reg_state = kmap_atomic(page);
2017
2018                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2019                         seq_printf(m,
2020                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2021                                    j * 4,
2022                                    reg_state[j], reg_state[j + 1],
2023                                    reg_state[j + 2], reg_state[j + 3]);
2024                 }
2025                 kunmap_atomic(reg_state);
2026         }
2027
2028         i915_gem_object_unpin_pages(vma->obj);
2029         seq_putc(m, '\n');
2030 }
2031
2032 static int i915_dump_lrc(struct seq_file *m, void *unused)
2033 {
2034         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2035         struct drm_device *dev = &dev_priv->drm;
2036         struct intel_engine_cs *engine;
2037         struct i915_gem_context *ctx;
2038         enum intel_engine_id id;
2039         int ret;
2040
2041         if (!i915.enable_execlists) {
2042                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2043                 return 0;
2044         }
2045
2046         ret = mutex_lock_interruptible(&dev->struct_mutex);
2047         if (ret)
2048                 return ret;
2049
2050         list_for_each_entry(ctx, &dev_priv->context_list, link)
2051                 for_each_engine(engine, dev_priv, id)
2052                         i915_dump_lrc_obj(m, ctx, engine);
2053
2054         mutex_unlock(&dev->struct_mutex);
2055
2056         return 0;
2057 }
2058
2059 static const char *swizzle_string(unsigned swizzle)
2060 {
2061         switch (swizzle) {
2062         case I915_BIT_6_SWIZZLE_NONE:
2063                 return "none";
2064         case I915_BIT_6_SWIZZLE_9:
2065                 return "bit9";
2066         case I915_BIT_6_SWIZZLE_9_10:
2067                 return "bit9/bit10";
2068         case I915_BIT_6_SWIZZLE_9_11:
2069                 return "bit9/bit11";
2070         case I915_BIT_6_SWIZZLE_9_10_11:
2071                 return "bit9/bit10/bit11";
2072         case I915_BIT_6_SWIZZLE_9_17:
2073                 return "bit9/bit17";
2074         case I915_BIT_6_SWIZZLE_9_10_17:
2075                 return "bit9/bit10/bit17";
2076         case I915_BIT_6_SWIZZLE_UNKNOWN:
2077                 return "unknown";
2078         }
2079
2080         return "bug";
2081 }
2082
2083 static int i915_swizzle_info(struct seq_file *m, void *data)
2084 {
2085         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2086
2087         intel_runtime_pm_get(dev_priv);
2088
2089         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2090                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2091         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2092                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2093
2094         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2095                 seq_printf(m, "DDC = 0x%08x\n",
2096                            I915_READ(DCC));
2097                 seq_printf(m, "DDC2 = 0x%08x\n",
2098                            I915_READ(DCC2));
2099                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2100                            I915_READ16(C0DRB3));
2101                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2102                            I915_READ16(C1DRB3));
2103         } else if (INTEL_GEN(dev_priv) >= 6) {
2104                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2105                            I915_READ(MAD_DIMM_C0));
2106                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2107                            I915_READ(MAD_DIMM_C1));
2108                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2109                            I915_READ(MAD_DIMM_C2));
2110                 seq_printf(m, "TILECTL = 0x%08x\n",
2111                            I915_READ(TILECTL));
2112                 if (INTEL_GEN(dev_priv) >= 8)
2113                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2114                                    I915_READ(GAMTARBMODE));
2115                 else
2116                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2117                                    I915_READ(ARB_MODE));
2118                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2119                            I915_READ(DISP_ARB_CTL));
2120         }
2121
2122         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2123                 seq_puts(m, "L-shaped memory detected\n");
2124
2125         intel_runtime_pm_put(dev_priv);
2126
2127         return 0;
2128 }
2129
2130 static int per_file_ctx(int id, void *ptr, void *data)
2131 {
2132         struct i915_gem_context *ctx = ptr;
2133         struct seq_file *m = data;
2134         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2135
2136         if (!ppgtt) {
2137                 seq_printf(m, "  no ppgtt for context %d\n",
2138                            ctx->user_handle);
2139                 return 0;
2140         }
2141
2142         if (i915_gem_context_is_default(ctx))
2143                 seq_puts(m, "  default context:\n");
2144         else
2145                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2146         ppgtt->debug_dump(ppgtt, m);
2147
2148         return 0;
2149 }
2150
2151 static void gen8_ppgtt_info(struct seq_file *m,
2152                             struct drm_i915_private *dev_priv)
2153 {
2154         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2155         struct intel_engine_cs *engine;
2156         enum intel_engine_id id;
2157         int i;
2158
2159         if (!ppgtt)
2160                 return;
2161
2162         for_each_engine(engine, dev_priv, id) {
2163                 seq_printf(m, "%s\n", engine->name);
2164                 for (i = 0; i < 4; i++) {
2165                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2166                         pdp <<= 32;
2167                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2168                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2169                 }
2170         }
2171 }
2172
2173 static void gen6_ppgtt_info(struct seq_file *m,
2174                             struct drm_i915_private *dev_priv)
2175 {
2176         struct intel_engine_cs *engine;
2177         enum intel_engine_id id;
2178
2179         if (IS_GEN6(dev_priv))
2180                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2181
2182         for_each_engine(engine, dev_priv, id) {
2183                 seq_printf(m, "%s\n", engine->name);
2184                 if (IS_GEN7(dev_priv))
2185                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2186                                    I915_READ(RING_MODE_GEN7(engine)));
2187                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2188                            I915_READ(RING_PP_DIR_BASE(engine)));
2189                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2190                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2191                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2192                            I915_READ(RING_PP_DIR_DCLV(engine)));
2193         }
2194         if (dev_priv->mm.aliasing_ppgtt) {
2195                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2196
2197                 seq_puts(m, "aliasing PPGTT:\n");
2198                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2199
2200                 ppgtt->debug_dump(ppgtt, m);
2201         }
2202
2203         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2204 }
2205
2206 static int i915_ppgtt_info(struct seq_file *m, void *data)
2207 {
2208         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2209         struct drm_device *dev = &dev_priv->drm;
2210         struct drm_file *file;
2211         int ret;
2212
2213         mutex_lock(&dev->filelist_mutex);
2214         ret = mutex_lock_interruptible(&dev->struct_mutex);
2215         if (ret)
2216                 goto out_unlock;
2217
2218         intel_runtime_pm_get(dev_priv);
2219
2220         if (INTEL_GEN(dev_priv) >= 8)
2221                 gen8_ppgtt_info(m, dev_priv);
2222         else if (INTEL_GEN(dev_priv) >= 6)
2223                 gen6_ppgtt_info(m, dev_priv);
2224
2225         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2226                 struct drm_i915_file_private *file_priv = file->driver_priv;
2227                 struct task_struct *task;
2228
2229                 task = get_pid_task(file->pid, PIDTYPE_PID);
2230                 if (!task) {
2231                         ret = -ESRCH;
2232                         goto out_rpm;
2233                 }
2234                 seq_printf(m, "\nproc: %s\n", task->comm);
2235                 put_task_struct(task);
2236                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2237                              (void *)(unsigned long)m);
2238         }
2239
2240 out_rpm:
2241         intel_runtime_pm_put(dev_priv);
2242         mutex_unlock(&dev->struct_mutex);
2243 out_unlock:
2244         mutex_unlock(&dev->filelist_mutex);
2245         return ret;
2246 }
2247
2248 static int count_irq_waiters(struct drm_i915_private *i915)
2249 {
2250         struct intel_engine_cs *engine;
2251         enum intel_engine_id id;
2252         int count = 0;
2253
2254         for_each_engine(engine, i915, id)
2255                 count += intel_engine_has_waiter(engine);
2256
2257         return count;
2258 }
2259
2260 static const char *rps_power_to_str(unsigned int power)
2261 {
2262         static const char * const strings[] = {
2263                 [LOW_POWER] = "low power",
2264                 [BETWEEN] = "mixed",
2265                 [HIGH_POWER] = "high power",
2266         };
2267
2268         if (power >= ARRAY_SIZE(strings) || !strings[power])
2269                 return "unknown";
2270
2271         return strings[power];
2272 }
2273
2274 static int i915_rps_boost_info(struct seq_file *m, void *data)
2275 {
2276         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2277         struct drm_device *dev = &dev_priv->drm;
2278         struct drm_file *file;
2279
2280         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2281         seq_printf(m, "GPU busy? %s [%d requests]\n",
2282                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2283         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2284         seq_printf(m, "Frequency requested %d\n",
2285                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2286         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2287                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2288                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2289                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2290                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2291         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2292                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2293                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2294                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2295
2296         mutex_lock(&dev->filelist_mutex);
2297         spin_lock(&dev_priv->rps.client_lock);
2298         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2299                 struct drm_i915_file_private *file_priv = file->driver_priv;
2300                 struct task_struct *task;
2301
2302                 rcu_read_lock();
2303                 task = pid_task(file->pid, PIDTYPE_PID);
2304                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2305                            task ? task->comm : "<unknown>",
2306                            task ? task->pid : -1,
2307                            file_priv->rps.boosts,
2308                            list_empty(&file_priv->rps.link) ? "" : ", active");
2309                 rcu_read_unlock();
2310         }
2311         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2312         spin_unlock(&dev_priv->rps.client_lock);
2313         mutex_unlock(&dev->filelist_mutex);
2314
2315         if (INTEL_GEN(dev_priv) >= 6 &&
2316             dev_priv->rps.enabled &&
2317             dev_priv->gt.active_requests) {
2318                 u32 rpup, rpupei;
2319                 u32 rpdown, rpdownei;
2320
2321                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2322                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2323                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2324                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2325                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2326                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2327
2328                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2329                            rps_power_to_str(dev_priv->rps.power));
2330                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2331                            100 * rpup / rpupei,
2332                            dev_priv->rps.up_threshold);
2333                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2334                            100 * rpdown / rpdownei,
2335                            dev_priv->rps.down_threshold);
2336         } else {
2337                 seq_puts(m, "\nRPS Autotuning inactive\n");
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int i915_llc(struct seq_file *m, void *data)
2344 {
2345         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2346         const bool edram = INTEL_GEN(dev_priv) > 8;
2347
2348         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2349         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2350                    intel_uncore_edram_size(dev_priv)/1024/1024);
2351
2352         return 0;
2353 }
2354
2355 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2356 {
2357         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2358         struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
2359
2360         if (!HAS_HUC_UCODE(dev_priv))
2361                 return 0;
2362
2363         seq_puts(m, "HuC firmware status:\n");
2364         seq_printf(m, "\tpath: %s\n", huc_fw->path);
2365         seq_printf(m, "\tfetch: %s\n",
2366                 intel_uc_fw_status_repr(huc_fw->fetch_status));
2367         seq_printf(m, "\tload: %s\n",
2368                 intel_uc_fw_status_repr(huc_fw->load_status));
2369         seq_printf(m, "\tversion wanted: %d.%d\n",
2370                 huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
2371         seq_printf(m, "\tversion found: %d.%d\n",
2372                 huc_fw->major_ver_found, huc_fw->minor_ver_found);
2373         seq_printf(m, "\theader: offset is %d; size = %d\n",
2374                 huc_fw->header_offset, huc_fw->header_size);
2375         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2376                 huc_fw->ucode_offset, huc_fw->ucode_size);
2377         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2378                 huc_fw->rsa_offset, huc_fw->rsa_size);
2379
2380         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2381
2382         return 0;
2383 }
2384
2385 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2386 {
2387         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2388         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
2389         u32 tmp, i;
2390
2391         if (!HAS_GUC_UCODE(dev_priv))
2392                 return 0;
2393
2394         seq_printf(m, "GuC firmware status:\n");
2395         seq_printf(m, "\tpath: %s\n",
2396                 guc_fw->path);
2397         seq_printf(m, "\tfetch: %s\n",
2398                 intel_uc_fw_status_repr(guc_fw->fetch_status));
2399         seq_printf(m, "\tload: %s\n",
2400                 intel_uc_fw_status_repr(guc_fw->load_status));
2401         seq_printf(m, "\tversion wanted: %d.%d\n",
2402                 guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
2403         seq_printf(m, "\tversion found: %d.%d\n",
2404                 guc_fw->major_ver_found, guc_fw->minor_ver_found);
2405         seq_printf(m, "\theader: offset is %d; size = %d\n",
2406                 guc_fw->header_offset, guc_fw->header_size);
2407         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2408                 guc_fw->ucode_offset, guc_fw->ucode_size);
2409         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2410                 guc_fw->rsa_offset, guc_fw->rsa_size);
2411
2412         tmp = I915_READ(GUC_STATUS);
2413
2414         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2415         seq_printf(m, "\tBootrom status = 0x%x\n",
2416                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2417         seq_printf(m, "\tuKernel status = 0x%x\n",
2418                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2419         seq_printf(m, "\tMIA Core status = 0x%x\n",
2420                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2421         seq_puts(m, "\nScratch registers:\n");
2422         for (i = 0; i < 16; i++)
2423                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2424
2425         return 0;
2426 }
2427
2428 static void i915_guc_log_info(struct seq_file *m,
2429                               struct drm_i915_private *dev_priv)
2430 {
2431         struct intel_guc *guc = &dev_priv->guc;
2432
2433         seq_puts(m, "\nGuC logging stats:\n");
2434
2435         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2436                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2437                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2438
2439         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2440                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2441                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2442
2443         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2444                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2445                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2446
2447         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2448                    guc->log.flush_interrupt_count);
2449
2450         seq_printf(m, "\tCapture miss count: %u\n",
2451                    guc->log.capture_miss_count);
2452 }
2453
2454 static void i915_guc_client_info(struct seq_file *m,
2455                                  struct drm_i915_private *dev_priv,
2456                                  struct i915_guc_client *client)
2457 {
2458         struct intel_engine_cs *engine;
2459         enum intel_engine_id id;
2460         uint64_t tot = 0;
2461
2462         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2463                 client->priority, client->ctx_index, client->proc_desc_offset);
2464         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2465                 client->doorbell_id, client->doorbell_offset, client->doorbell_cookie);
2466         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2467                 client->wq_size, client->wq_offset, client->wq_tail);
2468
2469         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2470         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2471         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2472
2473         for_each_engine(engine, dev_priv, id) {
2474                 u64 submissions = client->submissions[id];
2475                 tot += submissions;
2476                 seq_printf(m, "\tSubmissions: %llu %s\n",
2477                                 submissions, engine->name);
2478         }
2479         seq_printf(m, "\tTotal: %llu\n", tot);
2480 }
2481
2482 static int i915_guc_info(struct seq_file *m, void *data)
2483 {
2484         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2485         const struct intel_guc *guc = &dev_priv->guc;
2486         struct intel_engine_cs *engine;
2487         enum intel_engine_id id;
2488         u64 total;
2489
2490         if (!guc->execbuf_client) {
2491                 seq_printf(m, "GuC submission %s\n",
2492                            HAS_GUC_SCHED(dev_priv) ?
2493                            "disabled" :
2494                            "not supported");
2495                 return 0;
2496         }
2497
2498         seq_printf(m, "Doorbell map:\n");
2499         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc->doorbell_bitmap);
2500         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2501
2502         seq_printf(m, "GuC total action count: %llu\n", guc->action_count);
2503         seq_printf(m, "GuC action failure count: %u\n", guc->action_fail);
2504         seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd);
2505         seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status);
2506         seq_printf(m, "GuC last action error code: %d\n", guc->action_err);
2507
2508         total = 0;
2509         seq_printf(m, "\nGuC submissions:\n");
2510         for_each_engine(engine, dev_priv, id) {
2511                 u64 submissions = guc->submissions[id];
2512                 total += submissions;
2513                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2514                         engine->name, submissions, guc->last_seqno[id]);
2515         }
2516         seq_printf(m, "\t%s: %llu\n", "Total", total);
2517
2518         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2519         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2520
2521         i915_guc_log_info(m, dev_priv);
2522
2523         /* Add more as required ... */
2524
2525         return 0;
2526 }
2527
2528 static int i915_guc_log_dump(struct seq_file *m, void *data)
2529 {
2530         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2531         struct drm_i915_gem_object *obj;
2532         int i = 0, pg;
2533
2534         if (!dev_priv->guc.log.vma)
2535                 return 0;
2536
2537         obj = dev_priv->guc.log.vma->obj;
2538         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2539                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2540
2541                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2542                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2543                                    *(log + i), *(log + i + 1),
2544                                    *(log + i + 2), *(log + i + 3));
2545
2546                 kunmap_atomic(log);
2547         }
2548
2549         seq_putc(m, '\n');
2550
2551         return 0;
2552 }
2553
2554 static int i915_guc_log_control_get(void *data, u64 *val)
2555 {
2556         struct drm_device *dev = data;
2557         struct drm_i915_private *dev_priv = to_i915(dev);
2558
2559         if (!dev_priv->guc.log.vma)
2560                 return -EINVAL;
2561
2562         *val = i915.guc_log_level;
2563
2564         return 0;
2565 }
2566
2567 static int i915_guc_log_control_set(void *data, u64 val)
2568 {
2569         struct drm_device *dev = data;
2570         struct drm_i915_private *dev_priv = to_i915(dev);
2571         int ret;
2572
2573         if (!dev_priv->guc.log.vma)
2574                 return -EINVAL;
2575
2576         ret = mutex_lock_interruptible(&dev->struct_mutex);
2577         if (ret)
2578                 return ret;
2579
2580         intel_runtime_pm_get(dev_priv);
2581         ret = i915_guc_log_control(dev_priv, val);
2582         intel_runtime_pm_put(dev_priv);
2583
2584         mutex_unlock(&dev->struct_mutex);
2585         return ret;
2586 }
2587
2588 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2589                         i915_guc_log_control_get, i915_guc_log_control_set,
2590                         "%lld\n");
2591
2592 static const char *psr2_live_status(u32 val)
2593 {
2594         static const char * const live_status[] = {
2595                 "IDLE",
2596                 "CAPTURE",
2597                 "CAPTURE_FS",
2598                 "SLEEP",
2599                 "BUFON_FW",
2600                 "ML_UP",
2601                 "SU_STANDBY",
2602                 "FAST_SLEEP",
2603                 "DEEP_SLEEP",
2604                 "BUF_ON",
2605                 "TG_ON"
2606         };
2607
2608         val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2609         if (val < ARRAY_SIZE(live_status))
2610                 return live_status[val];
2611
2612         return "unknown";
2613 }
2614
2615 static int i915_edp_psr_status(struct seq_file *m, void *data)
2616 {
2617         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2618         u32 psrperf = 0;
2619         u32 stat[3];
2620         enum pipe pipe;
2621         bool enabled = false;
2622
2623         if (!HAS_PSR(dev_priv)) {
2624                 seq_puts(m, "PSR not supported\n");
2625                 return 0;
2626         }
2627
2628         intel_runtime_pm_get(dev_priv);
2629
2630         mutex_lock(&dev_priv->psr.lock);
2631         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2632         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2633         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2634         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2635         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2636                    dev_priv->psr.busy_frontbuffer_bits);
2637         seq_printf(m, "Re-enable work scheduled: %s\n",
2638                    yesno(work_busy(&dev_priv->psr.work.work)));
2639
2640         if (HAS_DDI(dev_priv)) {
2641                 if (dev_priv->psr.psr2_support)
2642                         enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2643                 else
2644                         enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2645         } else {
2646                 for_each_pipe(dev_priv, pipe) {
2647                         enum transcoder cpu_transcoder =
2648                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2649                         enum intel_display_power_domain power_domain;
2650
2651                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2652                         if (!intel_display_power_get_if_enabled(dev_priv,
2653                                                                 power_domain))
2654                                 continue;
2655
2656                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2657                                 VLV_EDP_PSR_CURR_STATE_MASK;
2658                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2659                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2660                                 enabled = true;
2661
2662                         intel_display_power_put(dev_priv, power_domain);
2663                 }
2664         }
2665
2666         seq_printf(m, "Main link in standby mode: %s\n",
2667                    yesno(dev_priv->psr.link_standby));
2668
2669         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2670
2671         if (!HAS_DDI(dev_priv))
2672                 for_each_pipe(dev_priv, pipe) {
2673                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2674                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2675                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2676                 }
2677         seq_puts(m, "\n");
2678
2679         /*
2680          * VLV/CHV PSR has no kind of performance counter
2681          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2682          */
2683         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2684                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2685                         EDP_PSR_PERF_CNT_MASK;
2686
2687                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2688         }
2689         if (dev_priv->psr.psr2_support) {
2690                 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2691
2692                 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2693                            psr2, psr2_live_status(psr2));
2694         }
2695         mutex_unlock(&dev_priv->psr.lock);
2696
2697         intel_runtime_pm_put(dev_priv);
2698         return 0;
2699 }
2700
2701 static int i915_sink_crc(struct seq_file *m, void *data)
2702 {
2703         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2704         struct drm_device *dev = &dev_priv->drm;
2705         struct intel_connector *connector;
2706         struct intel_dp *intel_dp = NULL;
2707         int ret;
2708         u8 crc[6];
2709
2710         drm_modeset_lock_all(dev);
2711         for_each_intel_connector(dev, connector) {
2712                 struct drm_crtc *crtc;
2713
2714                 if (!connector->base.state->best_encoder)
2715                         continue;
2716
2717                 crtc = connector->base.state->crtc;
2718                 if (!crtc->state->active)
2719                         continue;
2720
2721                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2722                         continue;
2723
2724                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2725
2726                 ret = intel_dp_sink_crc(intel_dp, crc);
2727                 if (ret)
2728                         goto out;
2729
2730                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2731                            crc[0], crc[1], crc[2],
2732                            crc[3], crc[4], crc[5]);
2733                 goto out;
2734         }
2735         ret = -ENODEV;
2736 out:
2737         drm_modeset_unlock_all(dev);
2738         return ret;
2739 }
2740
2741 static int i915_energy_uJ(struct seq_file *m, void *data)
2742 {
2743         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2744         u64 power;
2745         u32 units;
2746
2747         if (INTEL_GEN(dev_priv) < 6)
2748                 return -ENODEV;
2749
2750         intel_runtime_pm_get(dev_priv);
2751
2752         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2753         power = (power & 0x1f00) >> 8;
2754         units = 1000000 / (1 << power); /* convert to uJ */
2755         power = I915_READ(MCH_SECP_NRG_STTS);
2756         power *= units;
2757
2758         intel_runtime_pm_put(dev_priv);
2759
2760         seq_printf(m, "%llu", (long long unsigned)power);
2761
2762         return 0;
2763 }
2764
2765 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2766 {
2767         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2768         struct pci_dev *pdev = dev_priv->drm.pdev;
2769
2770         if (!HAS_RUNTIME_PM(dev_priv))
2771                 seq_puts(m, "Runtime power management not supported\n");
2772
2773         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2774         seq_printf(m, "IRQs disabled: %s\n",
2775                    yesno(!intel_irqs_enabled(dev_priv)));
2776 #ifdef CONFIG_PM
2777         seq_printf(m, "Usage count: %d\n",
2778                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2779 #else
2780         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2781 #endif
2782         seq_printf(m, "PCI device power state: %s [%d]\n",
2783                    pci_power_name(pdev->current_state),
2784                    pdev->current_state);
2785
2786         return 0;
2787 }
2788
2789 static int i915_power_domain_info(struct seq_file *m, void *unused)
2790 {
2791         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2792         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2793         int i;
2794
2795         mutex_lock(&power_domains->lock);
2796
2797         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2798         for (i = 0; i < power_domains->power_well_count; i++) {
2799                 struct i915_power_well *power_well;
2800                 enum intel_display_power_domain power_domain;
2801
2802                 power_well = &power_domains->power_wells[i];
2803                 seq_printf(m, "%-25s %d\n", power_well->name,
2804                            power_well->count);
2805
2806                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2807                      power_domain++) {
2808                         if (!(BIT(power_domain) & power_well->domains))
2809                                 continue;
2810
2811                         seq_printf(m, "  %-23s %d\n",
2812                                  intel_display_power_domain_str(power_domain),
2813                                  power_domains->domain_use_count[power_domain]);
2814                 }
2815         }
2816
2817         mutex_unlock(&power_domains->lock);
2818
2819         return 0;
2820 }
2821
2822 static int i915_dmc_info(struct seq_file *m, void *unused)
2823 {
2824         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2825         struct intel_csr *csr;
2826
2827         if (!HAS_CSR(dev_priv)) {
2828                 seq_puts(m, "not supported\n");
2829                 return 0;
2830         }
2831
2832         csr = &dev_priv->csr;
2833
2834         intel_runtime_pm_get(dev_priv);
2835
2836         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2837         seq_printf(m, "path: %s\n", csr->fw_path);
2838
2839         if (!csr->dmc_payload)
2840                 goto out;
2841
2842         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2843                    CSR_VERSION_MINOR(csr->version));
2844
2845         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2846                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2847                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2848                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2849                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2850         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2851                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2852                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2853         }
2854
2855 out:
2856         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2857         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2858         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2859
2860         intel_runtime_pm_put(dev_priv);
2861
2862         return 0;
2863 }
2864
2865 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2866                                  struct drm_display_mode *mode)
2867 {
2868         int i;
2869
2870         for (i = 0; i < tabs; i++)
2871                 seq_putc(m, '\t');
2872
2873         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2874                    mode->base.id, mode->name,
2875                    mode->vrefresh, mode->clock,
2876                    mode->hdisplay, mode->hsync_start,
2877                    mode->hsync_end, mode->htotal,
2878                    mode->vdisplay, mode->vsync_start,
2879                    mode->vsync_end, mode->vtotal,
2880                    mode->type, mode->flags);
2881 }
2882
2883 static void intel_encoder_info(struct seq_file *m,
2884                                struct intel_crtc *intel_crtc,
2885                                struct intel_encoder *intel_encoder)
2886 {
2887         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2888         struct drm_device *dev = &dev_priv->drm;
2889         struct drm_crtc *crtc = &intel_crtc->base;
2890         struct intel_connector *intel_connector;
2891         struct drm_encoder *encoder;
2892
2893         encoder = &intel_encoder->base;
2894         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2895                    encoder->base.id, encoder->name);
2896         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2897                 struct drm_connector *connector = &intel_connector->base;
2898                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2899                            connector->base.id,
2900                            connector->name,
2901                            drm_get_connector_status_name(connector->status));
2902                 if (connector->status == connector_status_connected) {
2903                         struct drm_display_mode *mode = &crtc->mode;
2904                         seq_printf(m, ", mode:\n");
2905                         intel_seq_print_mode(m, 2, mode);
2906                 } else {
2907                         seq_putc(m, '\n');
2908                 }
2909         }
2910 }
2911
2912 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2913 {
2914         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2915         struct drm_device *dev = &dev_priv->drm;
2916         struct drm_crtc *crtc = &intel_crtc->base;
2917         struct intel_encoder *intel_encoder;
2918         struct drm_plane_state *plane_state = crtc->primary->state;
2919         struct drm_framebuffer *fb = plane_state->fb;
2920
2921         if (fb)
2922                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2923                            fb->base.id, plane_state->src_x >> 16,
2924                            plane_state->src_y >> 16, fb->width, fb->height);
2925         else
2926                 seq_puts(m, "\tprimary plane disabled\n");
2927         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2928                 intel_encoder_info(m, intel_crtc, intel_encoder);
2929 }
2930
2931 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2932 {
2933         struct drm_display_mode *mode = panel->fixed_mode;
2934
2935         seq_printf(m, "\tfixed mode:\n");
2936         intel_seq_print_mode(m, 2, mode);
2937 }
2938
2939 static void intel_dp_info(struct seq_file *m,
2940                           struct intel_connector *intel_connector)
2941 {
2942         struct intel_encoder *intel_encoder = intel_connector->encoder;
2943         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2944
2945         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2946         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2947         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2948                 intel_panel_info(m, &intel_connector->panel);
2949
2950         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2951                                 &intel_dp->aux);
2952 }
2953
2954 static void intel_dp_mst_info(struct seq_file *m,
2955                           struct intel_connector *intel_connector)
2956 {
2957         struct intel_encoder *intel_encoder = intel_connector->encoder;
2958         struct intel_dp_mst_encoder *intel_mst =
2959                 enc_to_mst(&intel_encoder->base);
2960         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2961         struct intel_dp *intel_dp = &intel_dig_port->dp;
2962         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2963                                         intel_connector->port);
2964
2965         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2966 }
2967
2968 static void intel_hdmi_info(struct seq_file *m,
2969                             struct intel_connector *intel_connector)
2970 {
2971         struct intel_encoder *intel_encoder = intel_connector->encoder;
2972         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2973
2974         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2975 }
2976
2977 static void intel_lvds_info(struct seq_file *m,
2978                             struct intel_connector *intel_connector)
2979 {
2980         intel_panel_info(m, &intel_connector->panel);
2981 }
2982
2983 static void intel_connector_info(struct seq_file *m,
2984                                  struct drm_connector *connector)
2985 {
2986         struct intel_connector *intel_connector = to_intel_connector(connector);
2987         struct intel_encoder *intel_encoder = intel_connector->encoder;
2988         struct drm_display_mode *mode;
2989
2990         seq_printf(m, "connector %d: type %s, status: %s\n",
2991                    connector->base.id, connector->name,
2992                    drm_get_connector_status_name(connector->status));
2993         if (connector->status == connector_status_connected) {
2994                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2995                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2996                            connector->display_info.width_mm,
2997                            connector->display_info.height_mm);
2998                 seq_printf(m, "\tsubpixel order: %s\n",
2999                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3000                 seq_printf(m, "\tCEA rev: %d\n",
3001                            connector->display_info.cea_rev);
3002         }
3003
3004         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3005                 return;
3006
3007         switch (connector->connector_type) {
3008         case DRM_MODE_CONNECTOR_DisplayPort:
3009         case DRM_MODE_CONNECTOR_eDP:
3010                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3011                         intel_dp_mst_info(m, intel_connector);
3012                 else
3013                         intel_dp_info(m, intel_connector);
3014                 break;
3015         case DRM_MODE_CONNECTOR_LVDS:
3016                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3017                         intel_lvds_info(m, intel_connector);
3018                 break;
3019         case DRM_MODE_CONNECTOR_HDMIA:
3020                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3021                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3022                         intel_hdmi_info(m, intel_connector);
3023                 break;
3024         default:
3025                 break;
3026         }
3027
3028         seq_printf(m, "\tmodes:\n");
3029         list_for_each_entry(mode, &connector->modes, head)
3030                 intel_seq_print_mode(m, 2, mode);
3031 }
3032
3033 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
3034 {
3035         u32 state;
3036
3037         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
3038                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3039         else
3040                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3041
3042         return state;
3043 }
3044
3045 static bool cursor_position(struct drm_i915_private *dev_priv,
3046                             int pipe, int *x, int *y)
3047 {
3048         u32 pos;
3049
3050         pos = I915_READ(CURPOS(pipe));
3051
3052         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3053         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3054                 *x = -*x;
3055
3056         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3057         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3058                 *y = -*y;
3059
3060         return cursor_active(dev_priv, pipe);
3061 }
3062
3063 static const char *plane_type(enum drm_plane_type type)
3064 {
3065         switch (type) {
3066         case DRM_PLANE_TYPE_OVERLAY:
3067                 return "OVL";
3068         case DRM_PLANE_TYPE_PRIMARY:
3069                 return "PRI";
3070         case DRM_PLANE_TYPE_CURSOR:
3071                 return "CUR";
3072         /*
3073          * Deliberately omitting default: to generate compiler warnings
3074          * when a new drm_plane_type gets added.
3075          */
3076         }
3077
3078         return "unknown";
3079 }
3080
3081 static const char *plane_rotation(unsigned int rotation)
3082 {
3083         static char buf[48];
3084         /*
3085          * According to doc only one DRM_ROTATE_ is allowed but this
3086          * will print them all to visualize if the values are misused
3087          */
3088         snprintf(buf, sizeof(buf),
3089                  "%s%s%s%s%s%s(0x%08x)",
3090                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3091                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3092                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3093                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3094                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3095                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3096                  rotation);
3097
3098         return buf;
3099 }
3100
3101 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3102 {
3103         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3104         struct drm_device *dev = &dev_priv->drm;
3105         struct intel_plane *intel_plane;
3106
3107         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3108                 struct drm_plane_state *state;
3109                 struct drm_plane *plane = &intel_plane->base;
3110                 struct drm_format_name_buf format_name;
3111
3112                 if (!plane->state) {
3113                         seq_puts(m, "plane->state is NULL!\n");
3114                         continue;
3115                 }
3116
3117                 state = plane->state;
3118
3119                 if (state->fb) {
3120                         drm_get_format_name(state->fb->format->format,
3121                                             &format_name);
3122                 } else {
3123                         sprintf(format_name.str, "N/A");
3124                 }
3125
3126                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3127                            plane->base.id,
3128                            plane_type(intel_plane->base.type),
3129                            state->crtc_x, state->crtc_y,
3130                            state->crtc_w, state->crtc_h,
3131                            (state->src_x >> 16),
3132                            ((state->src_x & 0xffff) * 15625) >> 10,
3133                            (state->src_y >> 16),
3134                            ((state->src_y & 0xffff) * 15625) >> 10,
3135                            (state->src_w >> 16),
3136                            ((state->src_w & 0xffff) * 15625) >> 10,
3137                            (state->src_h >> 16),
3138                            ((state->src_h & 0xffff) * 15625) >> 10,
3139                            format_name.str,
3140                            plane_rotation(state->rotation));
3141         }
3142 }
3143
3144 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3145 {
3146         struct intel_crtc_state *pipe_config;
3147         int num_scalers = intel_crtc->num_scalers;
3148         int i;
3149
3150         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3151
3152         /* Not all platformas have a scaler */
3153         if (num_scalers) {
3154                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3155                            num_scalers,
3156                            pipe_config->scaler_state.scaler_users,
3157                            pipe_config->scaler_state.scaler_id);
3158
3159                 for (i = 0; i < num_scalers; i++) {
3160                         struct intel_scaler *sc =
3161                                         &pipe_config->scaler_state.scalers[i];
3162
3163                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3164                                    i, yesno(sc->in_use), sc->mode);
3165                 }
3166                 seq_puts(m, "\n");
3167         } else {
3168                 seq_puts(m, "\tNo scalers available on this platform\n");
3169         }
3170 }
3171
3172 static int i915_display_info(struct seq_file *m, void *unused)
3173 {
3174         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3175         struct drm_device *dev = &dev_priv->drm;
3176         struct intel_crtc *crtc;
3177         struct drm_connector *connector;
3178
3179         intel_runtime_pm_get(dev_priv);
3180         drm_modeset_lock_all(dev);
3181         seq_printf(m, "CRTC info\n");
3182         seq_printf(m, "---------\n");
3183         for_each_intel_crtc(dev, crtc) {
3184                 bool active;
3185                 struct intel_crtc_state *pipe_config;
3186                 int x, y;
3187
3188                 pipe_config = to_intel_crtc_state(crtc->base.state);
3189
3190                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3191                            crtc->base.base.id, pipe_name(crtc->pipe),
3192                            yesno(pipe_config->base.active),
3193                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3194                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3195
3196                 if (pipe_config->base.active) {
3197                         intel_crtc_info(m, crtc);
3198
3199                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3200                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3201                                    yesno(crtc->cursor_base),
3202                                    x, y, crtc->base.cursor->state->crtc_w,
3203                                    crtc->base.cursor->state->crtc_h,
3204                                    crtc->cursor_addr, yesno(active));
3205                         intel_scaler_info(m, crtc);
3206                         intel_plane_info(m, crtc);
3207                 }
3208
3209                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3210                            yesno(!crtc->cpu_fifo_underrun_disabled),
3211                            yesno(!crtc->pch_fifo_underrun_disabled));
3212         }
3213
3214         seq_printf(m, "\n");
3215         seq_printf(m, "Connector info\n");
3216         seq_printf(m, "--------------\n");
3217         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3218                 intel_connector_info(m, connector);
3219         }
3220         drm_modeset_unlock_all(dev);
3221         intel_runtime_pm_put(dev_priv);
3222
3223         return 0;
3224 }
3225
3226 static int i915_engine_info(struct seq_file *m, void *unused)
3227 {
3228         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3229         struct intel_engine_cs *engine;
3230         enum intel_engine_id id;
3231
3232         intel_runtime_pm_get(dev_priv);
3233
3234         for_each_engine(engine, dev_priv, id) {
3235                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3236                 struct drm_i915_gem_request *rq;
3237                 struct rb_node *rb;
3238                 u64 addr;
3239
3240                 seq_printf(m, "%s\n", engine->name);
3241                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n",
3242                            intel_engine_get_seqno(engine),
3243                            intel_engine_last_submit(engine),
3244                            engine->hangcheck.seqno,
3245                            jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
3246
3247                 rcu_read_lock();
3248
3249                 seq_printf(m, "\tRequests:\n");
3250
3251                 rq = list_first_entry(&engine->timeline->requests,
3252                                       struct drm_i915_gem_request, link);
3253                 if (&rq->link != &engine->timeline->requests)
3254                         print_request(m, rq, "\t\tfirst  ");
3255
3256                 rq = list_last_entry(&engine->timeline->requests,
3257                                      struct drm_i915_gem_request, link);
3258                 if (&rq->link != &engine->timeline->requests)
3259                         print_request(m, rq, "\t\tlast   ");
3260
3261                 rq = i915_gem_find_active_request(engine);
3262                 if (rq) {
3263                         print_request(m, rq, "\t\tactive ");
3264                         seq_printf(m,
3265                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3266                                    rq->head, rq->postfix, rq->tail,
3267                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3268                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3269                 }
3270
3271                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3272                            I915_READ(RING_START(engine->mmio_base)),
3273                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3274                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3275                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3276                            rq ? rq->ring->head : 0);
3277                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3278                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3279                            rq ? rq->ring->tail : 0);
3280                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3281                            I915_READ(RING_CTL(engine->mmio_base)),
3282                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3283
3284                 rcu_read_unlock();
3285
3286                 addr = intel_engine_get_active_head(engine);
3287                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3288                            upper_32_bits(addr), lower_32_bits(addr));
3289                 addr = intel_engine_get_last_batch_head(engine);
3290                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3291                            upper_32_bits(addr), lower_32_bits(addr));
3292
3293                 if (i915.enable_execlists) {
3294                         u32 ptr, read, write;
3295                         struct rb_node *rb;
3296
3297                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3298                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3299                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3300
3301                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3302                         read = GEN8_CSB_READ_PTR(ptr);
3303                         write = GEN8_CSB_WRITE_PTR(ptr);
3304                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3305                                    read, write);
3306                         if (read >= GEN8_CSB_ENTRIES)
3307                                 read = 0;
3308                         if (write >= GEN8_CSB_ENTRIES)
3309                                 write = 0;
3310                         if (read > write)
3311                                 write += GEN8_CSB_ENTRIES;
3312                         while (read < write) {
3313                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3314
3315                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3316                                            idx,
3317                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3318                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3319                         }
3320
3321                         rcu_read_lock();
3322                         rq = READ_ONCE(engine->execlist_port[0].request);
3323                         if (rq)
3324                                 print_request(m, rq, "\t\tELSP[0] ");
3325                         else
3326                                 seq_printf(m, "\t\tELSP[0] idle\n");
3327                         rq = READ_ONCE(engine->execlist_port[1].request);
3328                         if (rq)
3329                                 print_request(m, rq, "\t\tELSP[1] ");
3330                         else
3331                                 seq_printf(m, "\t\tELSP[1] idle\n");
3332                         rcu_read_unlock();
3333
3334                         spin_lock_irq(&engine->timeline->lock);
3335                         for (rb = engine->execlist_first; rb; rb = rb_next(rb)) {
3336                                 rq = rb_entry(rb, typeof(*rq), priotree.node);
3337                                 print_request(m, rq, "\t\tQ ");
3338                         }
3339                         spin_unlock_irq(&engine->timeline->lock);
3340                 } else if (INTEL_GEN(dev_priv) > 6) {
3341                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3342                                    I915_READ(RING_PP_DIR_BASE(engine)));
3343                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3344                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3345                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3346                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3347                 }
3348
3349                 spin_lock_irq(&b->lock);
3350                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3351                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
3352
3353                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3354                                    w->tsk->comm, w->tsk->pid, w->seqno);
3355                 }
3356                 spin_unlock_irq(&b->lock);
3357
3358                 seq_puts(m, "\n");
3359         }
3360
3361         intel_runtime_pm_put(dev_priv);
3362
3363         return 0;
3364 }
3365
3366 static int i915_semaphore_status(struct seq_file *m, void *unused)
3367 {
3368         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3369         struct drm_device *dev = &dev_priv->drm;
3370         struct intel_engine_cs *engine;
3371         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3372         enum intel_engine_id id;
3373         int j, ret;
3374
3375         if (!i915.semaphores) {
3376                 seq_puts(m, "Semaphores are disabled\n");
3377                 return 0;
3378         }
3379
3380         ret = mutex_lock_interruptible(&dev->struct_mutex);
3381         if (ret)
3382                 return ret;
3383         intel_runtime_pm_get(dev_priv);
3384
3385         if (IS_BROADWELL(dev_priv)) {
3386                 struct page *page;
3387                 uint64_t *seqno;
3388
3389                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3390
3391                 seqno = (uint64_t *)kmap_atomic(page);
3392                 for_each_engine(engine, dev_priv, id) {
3393                         uint64_t offset;
3394
3395                         seq_printf(m, "%s\n", engine->name);
3396
3397                         seq_puts(m, "  Last signal:");
3398                         for (j = 0; j < num_rings; j++) {
3399                                 offset = id * I915_NUM_ENGINES + j;
3400                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3401                                            seqno[offset], offset * 8);
3402                         }
3403                         seq_putc(m, '\n');
3404
3405                         seq_puts(m, "  Last wait:  ");
3406                         for (j = 0; j < num_rings; j++) {
3407                                 offset = id + (j * I915_NUM_ENGINES);
3408                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3409                                            seqno[offset], offset * 8);
3410                         }
3411                         seq_putc(m, '\n');
3412
3413                 }
3414                 kunmap_atomic(seqno);
3415         } else {
3416                 seq_puts(m, "  Last signal:");
3417                 for_each_engine(engine, dev_priv, id)
3418                         for (j = 0; j < num_rings; j++)
3419                                 seq_printf(m, "0x%08x\n",
3420                                            I915_READ(engine->semaphore.mbox.signal[j]));
3421                 seq_putc(m, '\n');
3422         }
3423
3424         intel_runtime_pm_put(dev_priv);
3425         mutex_unlock(&dev->struct_mutex);
3426         return 0;
3427 }
3428
3429 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3430 {
3431         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3432         struct drm_device *dev = &dev_priv->drm;
3433         int i;
3434
3435         drm_modeset_lock_all(dev);
3436         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3437                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3438
3439                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3440                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3441                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3442                 seq_printf(m, " tracked hardware state:\n");
3443                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3444                 seq_printf(m, " dpll_md: 0x%08x\n",
3445                            pll->state.hw_state.dpll_md);
3446                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3447                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3448                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3449         }
3450         drm_modeset_unlock_all(dev);
3451
3452         return 0;
3453 }
3454
3455 static int i915_wa_registers(struct seq_file *m, void *unused)
3456 {
3457         int i;
3458         int ret;
3459         struct intel_engine_cs *engine;
3460         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3461         struct drm_device *dev = &dev_priv->drm;
3462         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3463         enum intel_engine_id id;
3464
3465         ret = mutex_lock_interruptible(&dev->struct_mutex);
3466         if (ret)
3467                 return ret;
3468
3469         intel_runtime_pm_get(dev_priv);
3470
3471         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3472         for_each_engine(engine, dev_priv, id)
3473                 seq_printf(m, "HW whitelist count for %s: %d\n",
3474                            engine->name, workarounds->hw_whitelist_count[id]);
3475         for (i = 0; i < workarounds->count; ++i) {
3476                 i915_reg_t addr;
3477                 u32 mask, value, read;
3478                 bool ok;
3479
3480                 addr = workarounds->reg[i].addr;
3481                 mask = workarounds->reg[i].mask;
3482                 value = workarounds->reg[i].value;
3483                 read = I915_READ(addr);
3484                 ok = (value & mask) == (read & mask);
3485                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3486                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3487         }
3488
3489         intel_runtime_pm_put(dev_priv);
3490         mutex_unlock(&dev->struct_mutex);
3491
3492         return 0;
3493 }
3494
3495 static int i915_ddb_info(struct seq_file *m, void *unused)
3496 {
3497         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3498         struct drm_device *dev = &dev_priv->drm;
3499         struct skl_ddb_allocation *ddb;
3500         struct skl_ddb_entry *entry;
3501         enum pipe pipe;
3502         int plane;
3503
3504         if (INTEL_GEN(dev_priv) < 9)
3505                 return 0;
3506
3507         drm_modeset_lock_all(dev);
3508
3509         ddb = &dev_priv->wm.skl_hw.ddb;
3510
3511         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3512
3513         for_each_pipe(dev_priv, pipe) {
3514                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3515
3516                 for_each_universal_plane(dev_priv, pipe, plane) {
3517                         entry = &ddb->plane[pipe][plane];
3518                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3519                                    entry->start, entry->end,
3520                                    skl_ddb_entry_size(entry));
3521                 }
3522
3523                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3524                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3525                            entry->end, skl_ddb_entry_size(entry));
3526         }
3527
3528         drm_modeset_unlock_all(dev);
3529
3530         return 0;
3531 }
3532
3533 static void drrs_status_per_crtc(struct seq_file *m,
3534                                  struct drm_device *dev,
3535                                  struct intel_crtc *intel_crtc)
3536 {
3537         struct drm_i915_private *dev_priv = to_i915(dev);
3538         struct i915_drrs *drrs = &dev_priv->drrs;
3539         int vrefresh = 0;
3540         struct drm_connector *connector;
3541
3542         drm_for_each_connector(connector, dev) {
3543                 if (connector->state->crtc != &intel_crtc->base)
3544                         continue;
3545
3546                 seq_printf(m, "%s:\n", connector->name);
3547         }
3548
3549         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3550                 seq_puts(m, "\tVBT: DRRS_type: Static");
3551         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3552                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3553         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3554                 seq_puts(m, "\tVBT: DRRS_type: None");
3555         else
3556                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3557
3558         seq_puts(m, "\n\n");
3559
3560         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3561                 struct intel_panel *panel;
3562
3563                 mutex_lock(&drrs->mutex);
3564                 /* DRRS Supported */
3565                 seq_puts(m, "\tDRRS Supported: Yes\n");
3566
3567                 /* disable_drrs() will make drrs->dp NULL */
3568                 if (!drrs->dp) {
3569                         seq_puts(m, "Idleness DRRS: Disabled");
3570                         mutex_unlock(&drrs->mutex);
3571                         return;
3572                 }
3573
3574                 panel = &drrs->dp->attached_connector->panel;
3575                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3576                                         drrs->busy_frontbuffer_bits);
3577
3578                 seq_puts(m, "\n\t\t");
3579                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3580                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3581                         vrefresh = panel->fixed_mode->vrefresh;
3582                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3583                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3584                         vrefresh = panel->downclock_mode->vrefresh;
3585                 } else {
3586                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3587                                                 drrs->refresh_rate_type);
3588                         mutex_unlock(&drrs->mutex);
3589                         return;
3590                 }
3591                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3592
3593                 seq_puts(m, "\n\t\t");
3594                 mutex_unlock(&drrs->mutex);
3595         } else {
3596                 /* DRRS not supported. Print the VBT parameter*/
3597                 seq_puts(m, "\tDRRS Supported : No");
3598         }
3599         seq_puts(m, "\n");
3600 }
3601
3602 static int i915_drrs_status(struct seq_file *m, void *unused)
3603 {
3604         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3605         struct drm_device *dev = &dev_priv->drm;
3606         struct intel_crtc *intel_crtc;
3607         int active_crtc_cnt = 0;
3608
3609         drm_modeset_lock_all(dev);
3610         for_each_intel_crtc(dev, intel_crtc) {
3611                 if (intel_crtc->base.state->active) {
3612                         active_crtc_cnt++;
3613                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3614
3615                         drrs_status_per_crtc(m, dev, intel_crtc);
3616                 }
3617         }
3618         drm_modeset_unlock_all(dev);
3619
3620         if (!active_crtc_cnt)
3621                 seq_puts(m, "No active crtc found\n");
3622
3623         return 0;
3624 }
3625
3626 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3627 {
3628         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3629         struct drm_device *dev = &dev_priv->drm;
3630         struct intel_encoder *intel_encoder;
3631         struct intel_digital_port *intel_dig_port;
3632         struct drm_connector *connector;
3633
3634         drm_modeset_lock_all(dev);
3635         drm_for_each_connector(connector, dev) {
3636                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3637                         continue;
3638
3639                 intel_encoder = intel_attached_encoder(connector);
3640                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3641                         continue;
3642
3643                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3644                 if (!intel_dig_port->dp.can_mst)
3645                         continue;
3646
3647                 seq_printf(m, "MST Source Port %c\n",
3648                            port_name(intel_dig_port->port));
3649                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3650         }
3651         drm_modeset_unlock_all(dev);
3652         return 0;
3653 }
3654
3655 static ssize_t i915_displayport_test_active_write(struct file *file,
3656                                                   const char __user *ubuf,
3657                                                   size_t len, loff_t *offp)
3658 {
3659         char *input_buffer;
3660         int status = 0;
3661         struct drm_device *dev;
3662         struct drm_connector *connector;
3663         struct list_head *connector_list;
3664         struct intel_dp *intel_dp;
3665         int val = 0;
3666
3667         dev = ((struct seq_file *)file->private_data)->private;
3668
3669         connector_list = &dev->mode_config.connector_list;
3670
3671         if (len == 0)
3672                 return 0;
3673
3674         input_buffer = kmalloc(len + 1, GFP_KERNEL);
3675         if (!input_buffer)
3676                 return -ENOMEM;
3677
3678         if (copy_from_user(input_buffer, ubuf, len)) {
3679                 status = -EFAULT;
3680                 goto out;
3681         }
3682
3683         input_buffer[len] = '\0';
3684         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3685
3686         list_for_each_entry(connector, connector_list, head) {
3687                 if (connector->connector_type !=
3688                     DRM_MODE_CONNECTOR_DisplayPort)
3689                         continue;
3690
3691                 if (connector->status == connector_status_connected &&
3692                     connector->encoder != NULL) {
3693                         intel_dp = enc_to_intel_dp(connector->encoder);
3694                         status = kstrtoint(input_buffer, 10, &val);
3695                         if (status < 0)
3696                                 goto out;
3697                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3698                         /* To prevent erroneous activation of the compliance
3699                          * testing code, only accept an actual value of 1 here
3700                          */
3701                         if (val == 1)
3702                                 intel_dp->compliance.test_active = 1;
3703                         else
3704                                 intel_dp->compliance.test_active = 0;
3705                 }
3706         }
3707 out:
3708         kfree(input_buffer);
3709         if (status < 0)
3710                 return status;
3711
3712         *offp += len;
3713         return len;
3714 }
3715
3716 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3717 {
3718         struct drm_device *dev = m->private;
3719         struct drm_connector *connector;
3720         struct list_head *connector_list = &dev->mode_config.connector_list;
3721         struct intel_dp *intel_dp;
3722
3723         list_for_each_entry(connector, connector_list, head) {
3724                 if (connector->connector_type !=
3725                     DRM_MODE_CONNECTOR_DisplayPort)
3726                         continue;
3727
3728                 if (connector->status == connector_status_connected &&
3729                     connector->encoder != NULL) {
3730                         intel_dp = enc_to_intel_dp(connector->encoder);
3731                         if (intel_dp->compliance.test_active)
3732                                 seq_puts(m, "1");
3733                         else
3734                                 seq_puts(m, "0");
3735                 } else
3736                         seq_puts(m, "0");
3737         }
3738
3739         return 0;
3740 }
3741
3742 static int i915_displayport_test_active_open(struct inode *inode,
3743                                              struct file *file)
3744 {
3745         struct drm_i915_private *dev_priv = inode->i_private;
3746
3747         return single_open(file, i915_displayport_test_active_show,
3748                            &dev_priv->drm);
3749 }
3750
3751 static const struct file_operations i915_displayport_test_active_fops = {
3752         .owner = THIS_MODULE,
3753         .open = i915_displayport_test_active_open,
3754         .read = seq_read,
3755         .llseek = seq_lseek,
3756         .release = single_release,
3757         .write = i915_displayport_test_active_write
3758 };
3759
3760 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3761 {
3762         struct drm_device *dev = m->private;
3763         struct drm_connector *connector;
3764         struct list_head *connector_list = &dev->mode_config.connector_list;
3765         struct intel_dp *intel_dp;
3766
3767         list_for_each_entry(connector, connector_list, head) {
3768                 if (connector->connector_type !=
3769                     DRM_MODE_CONNECTOR_DisplayPort)
3770                         continue;
3771
3772                 if (connector->status == connector_status_connected &&
3773                     connector->encoder != NULL) {
3774                         intel_dp = enc_to_intel_dp(connector->encoder);
3775                         seq_printf(m, "%lx", intel_dp->compliance.test_data.edid);
3776                 } else
3777                         seq_puts(m, "0");
3778         }
3779
3780         return 0;
3781 }
3782 static int i915_displayport_test_data_open(struct inode *inode,
3783                                            struct file *file)
3784 {
3785         struct drm_i915_private *dev_priv = inode->i_private;
3786
3787         return single_open(file, i915_displayport_test_data_show,
3788                            &dev_priv->drm);
3789 }
3790
3791 static const struct file_operations i915_displayport_test_data_fops = {
3792         .owner = THIS_MODULE,
3793         .open = i915_displayport_test_data_open,
3794         .read = seq_read,
3795         .llseek = seq_lseek,
3796         .release = single_release
3797 };
3798
3799 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3800 {
3801         struct drm_device *dev = m->private;
3802         struct drm_connector *connector;
3803         struct list_head *connector_list = &dev->mode_config.connector_list;
3804         struct intel_dp *intel_dp;
3805
3806         list_for_each_entry(connector, connector_list, head) {
3807                 if (connector->connector_type !=
3808                     DRM_MODE_CONNECTOR_DisplayPort)
3809                         continue;
3810
3811                 if (connector->status == connector_status_connected &&
3812                     connector->encoder != NULL) {
3813                         intel_dp = enc_to_intel_dp(connector->encoder);
3814                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3815                 } else
3816                         seq_puts(m, "0");
3817         }
3818
3819         return 0;
3820 }
3821
3822 static int i915_displayport_test_type_open(struct inode *inode,
3823                                        struct file *file)
3824 {
3825         struct drm_i915_private *dev_priv = inode->i_private;
3826
3827         return single_open(file, i915_displayport_test_type_show,
3828                            &dev_priv->drm);
3829 }
3830
3831 static const struct file_operations i915_displayport_test_type_fops = {
3832         .owner = THIS_MODULE,
3833         .open = i915_displayport_test_type_open,
3834         .read = seq_read,
3835         .llseek = seq_lseek,
3836         .release = single_release
3837 };
3838
3839 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3840 {
3841         struct drm_i915_private *dev_priv = m->private;
3842         struct drm_device *dev = &dev_priv->drm;
3843         int level;
3844         int num_levels;
3845
3846         if (IS_CHERRYVIEW(dev_priv))
3847                 num_levels = 3;
3848         else if (IS_VALLEYVIEW(dev_priv))
3849                 num_levels = 1;
3850         else
3851                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3852
3853         drm_modeset_lock_all(dev);
3854
3855         for (level = 0; level < num_levels; level++) {
3856                 unsigned int latency = wm[level];
3857
3858                 /*
3859                  * - WM1+ latency values in 0.5us units
3860                  * - latencies are in us on gen9/vlv/chv
3861                  */
3862                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
3863                     IS_CHERRYVIEW(dev_priv))
3864                         latency *= 10;
3865                 else if (level > 0)
3866                         latency *= 5;
3867
3868                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3869                            level, wm[level], latency / 10, latency % 10);
3870         }
3871
3872         drm_modeset_unlock_all(dev);
3873 }
3874
3875 static int pri_wm_latency_show(struct seq_file *m, void *data)
3876 {
3877         struct drm_i915_private *dev_priv = m->private;
3878         const uint16_t *latencies;
3879
3880         if (INTEL_GEN(dev_priv) >= 9)
3881                 latencies = dev_priv->wm.skl_latency;
3882         else
3883                 latencies = dev_priv->wm.pri_latency;
3884
3885         wm_latency_show(m, latencies);
3886
3887         return 0;
3888 }
3889
3890 static int spr_wm_latency_show(struct seq_file *m, void *data)
3891 {
3892         struct drm_i915_private *dev_priv = m->private;
3893         const uint16_t *latencies;
3894
3895         if (INTEL_GEN(dev_priv) >= 9)
3896                 latencies = dev_priv->wm.skl_latency;
3897         else
3898                 latencies = dev_priv->wm.spr_latency;
3899
3900         wm_latency_show(m, latencies);
3901
3902         return 0;
3903 }
3904
3905 static int cur_wm_latency_show(struct seq_file *m, void *data)
3906 {
3907         struct drm_i915_private *dev_priv = m->private;
3908         const uint16_t *latencies;
3909
3910         if (INTEL_GEN(dev_priv) >= 9)
3911                 latencies = dev_priv->wm.skl_latency;
3912         else
3913                 latencies = dev_priv->wm.cur_latency;
3914
3915         wm_latency_show(m, latencies);
3916
3917         return 0;
3918 }
3919
3920 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3921 {
3922         struct drm_i915_private *dev_priv = inode->i_private;
3923
3924         if (INTEL_GEN(dev_priv) < 5)
3925                 return -ENODEV;
3926
3927         return single_open(file, pri_wm_latency_show, dev_priv);
3928 }
3929
3930 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3931 {
3932         struct drm_i915_private *dev_priv = inode->i_private;
3933
3934         if (HAS_GMCH_DISPLAY(dev_priv))
3935                 return -ENODEV;
3936
3937         return single_open(file, spr_wm_latency_show, dev_priv);
3938 }
3939
3940 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3941 {
3942         struct drm_i915_private *dev_priv = inode->i_private;
3943
3944         if (HAS_GMCH_DISPLAY(dev_priv))
3945                 return -ENODEV;
3946
3947         return single_open(file, cur_wm_latency_show, dev_priv);
3948 }
3949
3950 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3951                                 size_t len, loff_t *offp, uint16_t wm[8])
3952 {
3953         struct seq_file *m = file->private_data;
3954         struct drm_i915_private *dev_priv = m->private;
3955         struct drm_device *dev = &dev_priv->drm;
3956         uint16_t new[8] = { 0 };
3957         int num_levels;
3958         int level;
3959         int ret;
3960         char tmp[32];
3961
3962         if (IS_CHERRYVIEW(dev_priv))
3963                 num_levels = 3;
3964         else if (IS_VALLEYVIEW(dev_priv))
3965                 num_levels = 1;
3966         else
3967                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3968
3969         if (len >= sizeof(tmp))
3970                 return -EINVAL;
3971
3972         if (copy_from_user(tmp, ubuf, len))
3973                 return -EFAULT;
3974
3975         tmp[len] = '\0';
3976
3977         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3978                      &new[0], &new[1], &new[2], &new[3],
3979                      &new[4], &new[5], &new[6], &new[7]);
3980         if (ret != num_levels)
3981                 return -EINVAL;
3982
3983         drm_modeset_lock_all(dev);
3984
3985         for (level = 0; level < num_levels; level++)
3986                 wm[level] = new[level];
3987
3988         drm_modeset_unlock_all(dev);
3989
3990         return len;
3991 }
3992
3993
3994 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3995                                     size_t len, loff_t *offp)
3996 {
3997         struct seq_file *m = file->private_data;
3998         struct drm_i915_private *dev_priv = m->private;
3999         uint16_t *latencies;
4000
4001         if (INTEL_GEN(dev_priv) >= 9)
4002                 latencies = dev_priv->wm.skl_latency;
4003         else
4004                 latencies = dev_priv->wm.pri_latency;
4005
4006         return wm_latency_write(file, ubuf, len, offp, latencies);
4007 }
4008
4009 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4010                                     size_t len, loff_t *offp)
4011 {
4012         struct seq_file *m = file->private_data;
4013         struct drm_i915_private *dev_priv = m->private;
4014         uint16_t *latencies;
4015
4016         if (INTEL_GEN(dev_priv) >= 9)
4017                 latencies = dev_priv->wm.skl_latency;
4018         else
4019                 latencies = dev_priv->wm.spr_latency;
4020
4021         return wm_latency_write(file, ubuf, len, offp, latencies);
4022 }
4023
4024 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4025                                     size_t len, loff_t *offp)
4026 {
4027         struct seq_file *m = file->private_data;
4028         struct drm_i915_private *dev_priv = m->private;
4029         uint16_t *latencies;
4030
4031         if (INTEL_GEN(dev_priv) >= 9)
4032                 latencies = dev_priv->wm.skl_latency;
4033         else
4034                 latencies = dev_priv->wm.cur_latency;
4035
4036         return wm_latency_write(file, ubuf, len, offp, latencies);
4037 }
4038
4039 static const struct file_operations i915_pri_wm_latency_fops = {
4040         .owner = THIS_MODULE,
4041         .open = pri_wm_latency_open,
4042         .read = seq_read,
4043         .llseek = seq_lseek,
4044         .release = single_release,
4045         .write = pri_wm_latency_write
4046 };
4047
4048 static const struct file_operations i915_spr_wm_latency_fops = {
4049         .owner = THIS_MODULE,
4050         .open = spr_wm_latency_open,
4051         .read = seq_read,
4052         .llseek = seq_lseek,
4053         .release = single_release,
4054         .write = spr_wm_latency_write
4055 };
4056
4057 static const struct file_operations i915_cur_wm_latency_fops = {
4058         .owner = THIS_MODULE,
4059         .open = cur_wm_latency_open,
4060         .read = seq_read,
4061         .llseek = seq_lseek,
4062         .release = single_release,
4063         .write = cur_wm_latency_write
4064 };
4065
4066 static int
4067 i915_wedged_get(void *data, u64 *val)
4068 {
4069         struct drm_i915_private *dev_priv = data;
4070
4071         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4072
4073         return 0;
4074 }
4075
4076 static int
4077 i915_wedged_set(void *data, u64 val)
4078 {
4079         struct drm_i915_private *dev_priv = data;
4080
4081         /*
4082          * There is no safeguard against this debugfs entry colliding
4083          * with the hangcheck calling same i915_handle_error() in
4084          * parallel, causing an explosion. For now we assume that the
4085          * test harness is responsible enough not to inject gpu hangs
4086          * while it is writing to 'i915_wedged'
4087          */
4088
4089         if (i915_reset_in_progress(&dev_priv->gpu_error))
4090                 return -EAGAIN;
4091
4092         i915_handle_error(dev_priv, val,
4093                           "Manually setting wedged to %llu", val);
4094
4095         return 0;
4096 }
4097
4098 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4099                         i915_wedged_get, i915_wedged_set,
4100                         "%llu\n");
4101
4102 static int
4103 i915_ring_missed_irq_get(void *data, u64 *val)
4104 {
4105         struct drm_i915_private *dev_priv = data;
4106
4107         *val = dev_priv->gpu_error.missed_irq_rings;
4108         return 0;
4109 }
4110
4111 static int
4112 i915_ring_missed_irq_set(void *data, u64 val)
4113 {
4114         struct drm_i915_private *dev_priv = data;
4115         struct drm_device *dev = &dev_priv->drm;
4116         int ret;
4117
4118         /* Lock against concurrent debugfs callers */
4119         ret = mutex_lock_interruptible(&dev->struct_mutex);
4120         if (ret)
4121                 return ret;
4122         dev_priv->gpu_error.missed_irq_rings = val;
4123         mutex_unlock(&dev->struct_mutex);
4124
4125         return 0;
4126 }
4127
4128 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4129                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4130                         "0x%08llx\n");
4131
4132 static int
4133 i915_ring_test_irq_get(void *data, u64 *val)
4134 {
4135         struct drm_i915_private *dev_priv = data;
4136
4137         *val = dev_priv->gpu_error.test_irq_rings;
4138
4139         return 0;
4140 }
4141
4142 static int
4143 i915_ring_test_irq_set(void *data, u64 val)
4144 {
4145         struct drm_i915_private *dev_priv = data;
4146
4147         val &= INTEL_INFO(dev_priv)->ring_mask;
4148         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4149         dev_priv->gpu_error.test_irq_rings = val;
4150
4151         return 0;
4152 }
4153
4154 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4155                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4156                         "0x%08llx\n");
4157
4158 #define DROP_UNBOUND 0x1
4159 #define DROP_BOUND 0x2
4160 #define DROP_RETIRE 0x4
4161 #define DROP_ACTIVE 0x8
4162 #define DROP_FREED 0x10
4163 #define DROP_ALL (DROP_UNBOUND  | \
4164                   DROP_BOUND    | \
4165                   DROP_RETIRE   | \
4166                   DROP_ACTIVE   | \
4167                   DROP_FREED)
4168 static int
4169 i915_drop_caches_get(void *data, u64 *val)
4170 {
4171         *val = DROP_ALL;
4172
4173         return 0;
4174 }
4175
4176 static int
4177 i915_drop_caches_set(void *data, u64 val)
4178 {
4179         struct drm_i915_private *dev_priv = data;
4180         struct drm_device *dev = &dev_priv->drm;
4181         int ret;
4182
4183         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4184
4185         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4186          * on ioctls on -EAGAIN. */
4187         ret = mutex_lock_interruptible(&dev->struct_mutex);
4188         if (ret)
4189                 return ret;
4190
4191         if (val & DROP_ACTIVE) {
4192                 ret = i915_gem_wait_for_idle(dev_priv,
4193                                              I915_WAIT_INTERRUPTIBLE |
4194                                              I915_WAIT_LOCKED);
4195                 if (ret)
4196                         goto unlock;
4197         }
4198
4199         if (val & (DROP_RETIRE | DROP_ACTIVE))
4200                 i915_gem_retire_requests(dev_priv);
4201
4202         if (val & DROP_BOUND)
4203                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4204
4205         if (val & DROP_UNBOUND)
4206                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4207
4208 unlock:
4209         mutex_unlock(&dev->struct_mutex);
4210
4211         if (val & DROP_FREED) {
4212                 synchronize_rcu();
4213                 i915_gem_drain_freed_objects(dev_priv);
4214         }
4215
4216         return ret;
4217 }
4218
4219 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4220                         i915_drop_caches_get, i915_drop_caches_set,
4221                         "0x%08llx\n");
4222
4223 static int
4224 i915_max_freq_get(void *data, u64 *val)
4225 {
4226         struct drm_i915_private *dev_priv = data;
4227
4228         if (INTEL_GEN(dev_priv) < 6)
4229                 return -ENODEV;
4230
4231         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4232         return 0;
4233 }
4234
4235 static int
4236 i915_max_freq_set(void *data, u64 val)
4237 {
4238         struct drm_i915_private *dev_priv = data;
4239         u32 hw_max, hw_min;
4240         int ret;
4241
4242         if (INTEL_GEN(dev_priv) < 6)
4243                 return -ENODEV;
4244
4245         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4246
4247         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4248         if (ret)
4249                 return ret;
4250
4251         /*
4252          * Turbo will still be enabled, but won't go above the set value.
4253          */
4254         val = intel_freq_opcode(dev_priv, val);
4255
4256         hw_max = dev_priv->rps.max_freq;
4257         hw_min = dev_priv->rps.min_freq;
4258
4259         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4260                 mutex_unlock(&dev_priv->rps.hw_lock);
4261                 return -EINVAL;
4262         }
4263
4264         dev_priv->rps.max_freq_softlimit = val;
4265
4266         intel_set_rps(dev_priv, val);
4267
4268         mutex_unlock(&dev_priv->rps.hw_lock);
4269
4270         return 0;
4271 }
4272
4273 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4274                         i915_max_freq_get, i915_max_freq_set,
4275                         "%llu\n");
4276
4277 static int
4278 i915_min_freq_get(void *data, u64 *val)
4279 {
4280         struct drm_i915_private *dev_priv = data;
4281
4282         if (INTEL_GEN(dev_priv) < 6)
4283                 return -ENODEV;
4284
4285         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4286         return 0;
4287 }
4288
4289 static int
4290 i915_min_freq_set(void *data, u64 val)
4291 {
4292         struct drm_i915_private *dev_priv = data;
4293         u32 hw_max, hw_min;
4294         int ret;
4295
4296         if (INTEL_GEN(dev_priv) < 6)
4297                 return -ENODEV;
4298
4299         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4300
4301         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4302         if (ret)
4303                 return ret;
4304
4305         /*
4306          * Turbo will still be enabled, but won't go below the set value.
4307          */
4308         val = intel_freq_opcode(dev_priv, val);
4309
4310         hw_max = dev_priv->rps.max_freq;
4311         hw_min = dev_priv->rps.min_freq;
4312
4313         if (val < hw_min ||
4314             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4315                 mutex_unlock(&dev_priv->rps.hw_lock);
4316                 return -EINVAL;
4317         }
4318
4319         dev_priv->rps.min_freq_softlimit = val;
4320
4321         intel_set_rps(dev_priv, val);
4322
4323         mutex_unlock(&dev_priv->rps.hw_lock);
4324
4325         return 0;
4326 }
4327
4328 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4329                         i915_min_freq_get, i915_min_freq_set,
4330                         "%llu\n");
4331
4332 static int
4333 i915_cache_sharing_get(void *data, u64 *val)
4334 {
4335         struct drm_i915_private *dev_priv = data;
4336         u32 snpcr;
4337
4338         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4339                 return -ENODEV;
4340
4341         intel_runtime_pm_get(dev_priv);
4342
4343         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4344
4345         intel_runtime_pm_put(dev_priv);
4346
4347         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4348
4349         return 0;
4350 }
4351
4352 static int
4353 i915_cache_sharing_set(void *data, u64 val)
4354 {
4355         struct drm_i915_private *dev_priv = data;
4356         u32 snpcr;
4357
4358         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4359                 return -ENODEV;
4360
4361         if (val > 3)
4362                 return -EINVAL;
4363
4364         intel_runtime_pm_get(dev_priv);
4365         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4366
4367         /* Update the cache sharing policy here as well */
4368         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4369         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4370         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4371         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4372
4373         intel_runtime_pm_put(dev_priv);
4374         return 0;
4375 }
4376
4377 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4378                         i915_cache_sharing_get, i915_cache_sharing_set,
4379                         "%llu\n");
4380
4381 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4382                                           struct sseu_dev_info *sseu)
4383 {
4384         int ss_max = 2;
4385         int ss;
4386         u32 sig1[ss_max], sig2[ss_max];
4387
4388         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4389         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4390         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4391         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4392
4393         for (ss = 0; ss < ss_max; ss++) {
4394                 unsigned int eu_cnt;
4395
4396                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4397                         /* skip disabled subslice */
4398                         continue;
4399
4400                 sseu->slice_mask = BIT(0);
4401                 sseu->subslice_mask |= BIT(ss);
4402                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4403                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4404                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4405                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4406                 sseu->eu_total += eu_cnt;
4407                 sseu->eu_per_subslice = max_t(unsigned int,
4408                                               sseu->eu_per_subslice, eu_cnt);
4409         }
4410 }
4411
4412 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4413                                     struct sseu_dev_info *sseu)
4414 {
4415         int s_max = 3, ss_max = 4;
4416         int s, ss;
4417         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4418
4419         /* BXT has a single slice and at most 3 subslices. */
4420         if (IS_GEN9_LP(dev_priv)) {
4421                 s_max = 1;
4422                 ss_max = 3;
4423         }
4424
4425         for (s = 0; s < s_max; s++) {
4426                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4427                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4428                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4429         }
4430
4431         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4432                      GEN9_PGCTL_SSA_EU19_ACK |
4433                      GEN9_PGCTL_SSA_EU210_ACK |
4434                      GEN9_PGCTL_SSA_EU311_ACK;
4435         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4436                      GEN9_PGCTL_SSB_EU19_ACK |
4437                      GEN9_PGCTL_SSB_EU210_ACK |
4438                      GEN9_PGCTL_SSB_EU311_ACK;
4439
4440         for (s = 0; s < s_max; s++) {
4441                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4442                         /* skip disabled slice */
4443                         continue;
4444
4445                 sseu->slice_mask |= BIT(s);
4446
4447                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
4448                         sseu->subslice_mask =
4449                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4450
4451                 for (ss = 0; ss < ss_max; ss++) {
4452                         unsigned int eu_cnt;
4453
4454                         if (IS_GEN9_LP(dev_priv)) {
4455                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4456                                         /* skip disabled subslice */
4457                                         continue;
4458
4459                                 sseu->subslice_mask |= BIT(ss);
4460                         }
4461
4462                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4463                                                eu_mask[ss%2]);
4464                         sseu->eu_total += eu_cnt;
4465                         sseu->eu_per_subslice = max_t(unsigned int,
4466                                                       sseu->eu_per_subslice,
4467                                                       eu_cnt);
4468                 }
4469         }
4470 }
4471
4472 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4473                                          struct sseu_dev_info *sseu)
4474 {
4475         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4476         int s;
4477
4478         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4479
4480         if (sseu->slice_mask) {
4481                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4482                 sseu->eu_per_subslice =
4483                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4484                 sseu->eu_total = sseu->eu_per_subslice *
4485                                  sseu_subslice_total(sseu);
4486
4487                 /* subtract fused off EU(s) from enabled slice(s) */
4488                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4489                         u8 subslice_7eu =
4490                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4491
4492                         sseu->eu_total -= hweight8(subslice_7eu);
4493                 }
4494         }
4495 }
4496
4497 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4498                                  const struct sseu_dev_info *sseu)
4499 {
4500         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4501         const char *type = is_available_info ? "Available" : "Enabled";
4502
4503         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4504                    sseu->slice_mask);
4505         seq_printf(m, "  %s Slice Total: %u\n", type,
4506                    hweight8(sseu->slice_mask));
4507         seq_printf(m, "  %s Subslice Total: %u\n", type,
4508                    sseu_subslice_total(sseu));
4509         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
4510                    sseu->subslice_mask);
4511         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
4512                    hweight8(sseu->subslice_mask));
4513         seq_printf(m, "  %s EU Total: %u\n", type,
4514                    sseu->eu_total);
4515         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4516                    sseu->eu_per_subslice);
4517
4518         if (!is_available_info)
4519                 return;
4520
4521         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4522         if (HAS_POOLED_EU(dev_priv))
4523                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4524
4525         seq_printf(m, "  Has Slice Power Gating: %s\n",
4526                    yesno(sseu->has_slice_pg));
4527         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4528                    yesno(sseu->has_subslice_pg));
4529         seq_printf(m, "  Has EU Power Gating: %s\n",
4530                    yesno(sseu->has_eu_pg));
4531 }
4532
4533 static int i915_sseu_status(struct seq_file *m, void *unused)
4534 {
4535         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4536         struct sseu_dev_info sseu;
4537
4538         if (INTEL_GEN(dev_priv) < 8)
4539                 return -ENODEV;
4540
4541         seq_puts(m, "SSEU Device Info\n");
4542         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4543
4544         seq_puts(m, "SSEU Device Status\n");
4545         memset(&sseu, 0, sizeof(sseu));
4546
4547         intel_runtime_pm_get(dev_priv);
4548
4549         if (IS_CHERRYVIEW(dev_priv)) {
4550                 cherryview_sseu_device_status(dev_priv, &sseu);
4551         } else if (IS_BROADWELL(dev_priv)) {
4552                 broadwell_sseu_device_status(dev_priv, &sseu);
4553         } else if (INTEL_GEN(dev_priv) >= 9) {
4554                 gen9_sseu_device_status(dev_priv, &sseu);
4555         }
4556
4557         intel_runtime_pm_put(dev_priv);
4558
4559         i915_print_sseu_info(m, false, &sseu);
4560
4561         return 0;
4562 }
4563
4564 static int i915_forcewake_open(struct inode *inode, struct file *file)
4565 {
4566         struct drm_i915_private *dev_priv = inode->i_private;
4567
4568         if (INTEL_GEN(dev_priv) < 6)
4569                 return 0;
4570
4571         intel_runtime_pm_get(dev_priv);
4572         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4573
4574         return 0;
4575 }
4576
4577 static int i915_forcewake_release(struct inode *inode, struct file *file)
4578 {
4579         struct drm_i915_private *dev_priv = inode->i_private;
4580
4581         if (INTEL_GEN(dev_priv) < 6)
4582                 return 0;
4583
4584         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4585         intel_runtime_pm_put(dev_priv);
4586
4587         return 0;
4588 }
4589
4590 static const struct file_operations i915_forcewake_fops = {
4591         .owner = THIS_MODULE,
4592         .open = i915_forcewake_open,
4593         .release = i915_forcewake_release,
4594 };
4595
4596 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4597 {
4598         struct dentry *ent;
4599
4600         ent = debugfs_create_file("i915_forcewake_user",
4601                                   S_IRUSR,
4602                                   root, to_i915(minor->dev),
4603                                   &i915_forcewake_fops);
4604         if (!ent)
4605                 return -ENOMEM;
4606
4607         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4608 }
4609
4610 static int i915_debugfs_create(struct dentry *root,
4611                                struct drm_minor *minor,
4612                                const char *name,
4613                                const struct file_operations *fops)
4614 {
4615         struct dentry *ent;
4616
4617         ent = debugfs_create_file(name,
4618                                   S_IRUGO | S_IWUSR,
4619                                   root, to_i915(minor->dev),
4620                                   fops);
4621         if (!ent)
4622                 return -ENOMEM;
4623
4624         return drm_add_fake_info_node(minor, ent, fops);
4625 }
4626
4627 static const struct drm_info_list i915_debugfs_list[] = {
4628         {"i915_capabilities", i915_capabilities, 0},
4629         {"i915_gem_objects", i915_gem_object_info, 0},
4630         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4631         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
4632         {"i915_gem_stolen", i915_gem_stolen_list_info },
4633         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4634         {"i915_gem_request", i915_gem_request_info, 0},
4635         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4636         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4637         {"i915_gem_interrupt", i915_interrupt_info, 0},
4638         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4639         {"i915_guc_info", i915_guc_info, 0},
4640         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4641         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4642         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4643         {"i915_frequency_info", i915_frequency_info, 0},
4644         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4645         {"i915_drpc_info", i915_drpc_info, 0},
4646         {"i915_emon_status", i915_emon_status, 0},
4647         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4648         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4649         {"i915_fbc_status", i915_fbc_status, 0},
4650         {"i915_ips_status", i915_ips_status, 0},
4651         {"i915_sr_status", i915_sr_status, 0},
4652         {"i915_opregion", i915_opregion, 0},
4653         {"i915_vbt", i915_vbt, 0},
4654         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4655         {"i915_context_status", i915_context_status, 0},
4656         {"i915_dump_lrc", i915_dump_lrc, 0},
4657         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4658         {"i915_swizzle_info", i915_swizzle_info, 0},
4659         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4660         {"i915_llc", i915_llc, 0},
4661         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4662         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4663         {"i915_energy_uJ", i915_energy_uJ, 0},
4664         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4665         {"i915_power_domain_info", i915_power_domain_info, 0},
4666         {"i915_dmc_info", i915_dmc_info, 0},
4667         {"i915_display_info", i915_display_info, 0},
4668         {"i915_engine_info", i915_engine_info, 0},
4669         {"i915_semaphore_status", i915_semaphore_status, 0},
4670         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4671         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4672         {"i915_wa_registers", i915_wa_registers, 0},
4673         {"i915_ddb_info", i915_ddb_info, 0},
4674         {"i915_sseu_status", i915_sseu_status, 0},
4675         {"i915_drrs_status", i915_drrs_status, 0},
4676         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4677 };
4678 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4679
4680 static const struct i915_debugfs_files {
4681         const char *name;
4682         const struct file_operations *fops;
4683 } i915_debugfs_files[] = {
4684         {"i915_wedged", &i915_wedged_fops},
4685         {"i915_max_freq", &i915_max_freq_fops},
4686         {"i915_min_freq", &i915_min_freq_fops},
4687         {"i915_cache_sharing", &i915_cache_sharing_fops},
4688         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4689         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4690         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4691 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4692         {"i915_error_state", &i915_error_state_fops},
4693 #endif
4694         {"i915_next_seqno", &i915_next_seqno_fops},
4695         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4696         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4697         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4698         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4699         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4700         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4701         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4702         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4703         {"i915_guc_log_control", &i915_guc_log_control_fops}
4704 };
4705
4706 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4707 {
4708         struct drm_minor *minor = dev_priv->drm.primary;
4709         int ret, i;
4710
4711         ret = i915_forcewake_create(minor->debugfs_root, minor);
4712         if (ret)
4713                 return ret;
4714
4715         ret = intel_pipe_crc_create(minor);
4716         if (ret)
4717                 return ret;
4718
4719         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4720                 ret = i915_debugfs_create(minor->debugfs_root, minor,
4721                                           i915_debugfs_files[i].name,
4722                                           i915_debugfs_files[i].fops);
4723                 if (ret)
4724                         return ret;
4725         }
4726
4727         return drm_debugfs_create_files(i915_debugfs_list,
4728                                         I915_DEBUGFS_ENTRIES,
4729                                         minor->debugfs_root, minor);
4730 }
4731
4732 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
4733 {
4734         struct drm_minor *minor = dev_priv->drm.primary;
4735         int i;
4736
4737         drm_debugfs_remove_files(i915_debugfs_list,
4738                                  I915_DEBUGFS_ENTRIES, minor);
4739
4740         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
4741                                  1, minor);
4742
4743         intel_pipe_crc_cleanup(minor);
4744
4745         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4746                 struct drm_info_list *info_list =
4747                         (struct drm_info_list *)i915_debugfs_files[i].fops;
4748
4749                 drm_debugfs_remove_files(info_list, 1, minor);
4750         }
4751 }
4752
4753 struct dpcd_block {
4754         /* DPCD dump start address. */
4755         unsigned int offset;
4756         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4757         unsigned int end;
4758         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4759         size_t size;
4760         /* Only valid for eDP. */
4761         bool edp;
4762 };
4763
4764 static const struct dpcd_block i915_dpcd_debug[] = {
4765         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4766         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4767         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4768         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4769         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4770         { .offset = DP_SET_POWER },
4771         { .offset = DP_EDP_DPCD_REV },
4772         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4773         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4774         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4775 };
4776
4777 static int i915_dpcd_show(struct seq_file *m, void *data)
4778 {
4779         struct drm_connector *connector = m->private;
4780         struct intel_dp *intel_dp =
4781                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4782         uint8_t buf[16];
4783         ssize_t err;
4784         int i;
4785
4786         if (connector->status != connector_status_connected)
4787                 return -ENODEV;
4788
4789         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4790                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4791                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4792
4793                 if (b->edp &&
4794                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4795                         continue;
4796
4797                 /* low tech for now */
4798                 if (WARN_ON(size > sizeof(buf)))
4799                         continue;
4800
4801                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4802                 if (err <= 0) {
4803                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4804                                   size, b->offset, err);
4805                         continue;
4806                 }
4807
4808                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4809         }
4810
4811         return 0;
4812 }
4813
4814 static int i915_dpcd_open(struct inode *inode, struct file *file)
4815 {
4816         return single_open(file, i915_dpcd_show, inode->i_private);
4817 }
4818
4819 static const struct file_operations i915_dpcd_fops = {
4820         .owner = THIS_MODULE,
4821         .open = i915_dpcd_open,
4822         .read = seq_read,
4823         .llseek = seq_lseek,
4824         .release = single_release,
4825 };
4826
4827 static int i915_panel_show(struct seq_file *m, void *data)
4828 {
4829         struct drm_connector *connector = m->private;
4830         struct intel_dp *intel_dp =
4831                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4832
4833         if (connector->status != connector_status_connected)
4834                 return -ENODEV;
4835
4836         seq_printf(m, "Panel power up delay: %d\n",
4837                    intel_dp->panel_power_up_delay);
4838         seq_printf(m, "Panel power down delay: %d\n",
4839                    intel_dp->panel_power_down_delay);
4840         seq_printf(m, "Backlight on delay: %d\n",
4841                    intel_dp->backlight_on_delay);
4842         seq_printf(m, "Backlight off delay: %d\n",
4843                    intel_dp->backlight_off_delay);
4844
4845         return 0;
4846 }
4847
4848 static int i915_panel_open(struct inode *inode, struct file *file)
4849 {
4850         return single_open(file, i915_panel_show, inode->i_private);
4851 }
4852
4853 static const struct file_operations i915_panel_fops = {
4854         .owner = THIS_MODULE,
4855         .open = i915_panel_open,
4856         .read = seq_read,
4857         .llseek = seq_lseek,
4858         .release = single_release,
4859 };
4860
4861 /**
4862  * i915_debugfs_connector_add - add i915 specific connector debugfs files
4863  * @connector: pointer to a registered drm_connector
4864  *
4865  * Cleanup will be done by drm_connector_unregister() through a call to
4866  * drm_debugfs_connector_remove().
4867  *
4868  * Returns 0 on success, negative error codes on error.
4869  */
4870 int i915_debugfs_connector_add(struct drm_connector *connector)
4871 {
4872         struct dentry *root = connector->debugfs_entry;
4873
4874         /* The connector must have been registered beforehands. */
4875         if (!root)
4876                 return -ENODEV;
4877
4878         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4879             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4880                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4881                                     connector, &i915_dpcd_fops);
4882
4883         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4884                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4885                                     connector, &i915_panel_fops);
4886
4887         return 0;
4888 }