2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Zhi Wang <zhi.a.wang@intel.com>
27 * Ping Gao <ping.a.gao@intel.com>
28 * Tina Zhang <tina.zhang@intel.com>
29 * Chanbin Du <changbin.du@intel.com>
30 * Min He <min.he@intel.com>
31 * Bing Niu <bing.niu@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
36 #include <linux/kthread.h>
41 #define RING_CTX_OFF(x) \
42 offsetof(struct execlist_ring_context, x)
44 static void set_context_pdp_root_pointer(
45 struct execlist_ring_context *ring_context,
50 for (i = 0; i < 8; i++)
51 ring_context->pdps[i].val = pdp[7 - i];
54 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
56 struct drm_i915_gem_object *ctx_obj =
57 workload->req->hw_context->state->obj;
58 struct execlist_ring_context *shadow_ring_context;
61 if (WARN_ON(!workload->shadow_mm))
64 if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
67 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
68 shadow_ring_context = kmap(page);
69 set_context_pdp_root_pointer(shadow_ring_context,
70 (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
75 * when populating shadow ctx from guest, we should not overrride oa related
76 * registers, so that they will not be overlapped by guest oa configs. Thus
77 * made it possible to capture oa data from host for both host and guests.
79 static void sr_oa_regs(struct intel_vgpu_workload *workload,
80 u32 *reg_state, bool save)
82 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
83 u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
84 u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
87 i915_mmio_reg_offset(EU_PERF_CNTL0),
88 i915_mmio_reg_offset(EU_PERF_CNTL1),
89 i915_mmio_reg_offset(EU_PERF_CNTL2),
90 i915_mmio_reg_offset(EU_PERF_CNTL3),
91 i915_mmio_reg_offset(EU_PERF_CNTL4),
92 i915_mmio_reg_offset(EU_PERF_CNTL5),
93 i915_mmio_reg_offset(EU_PERF_CNTL6),
96 if (workload->ring_id != RCS0)
100 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
102 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
103 u32 state_offset = ctx_flexeu0 + i * 2;
105 workload->flex_mmio[i] = reg_state[state_offset + 1];
108 reg_state[ctx_oactxctrl] =
109 i915_mmio_reg_offset(GEN8_OACTXCONTROL);
110 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
112 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
113 u32 state_offset = ctx_flexeu0 + i * 2;
114 u32 mmio = flex_mmio[i];
116 reg_state[state_offset] = mmio;
117 reg_state[state_offset + 1] = workload->flex_mmio[i];
122 static int populate_shadow_context(struct intel_vgpu_workload *workload)
124 struct intel_vgpu *vgpu = workload->vgpu;
125 struct intel_gvt *gvt = vgpu->gvt;
126 int ring_id = workload->ring_id;
127 struct drm_i915_gem_object *ctx_obj =
128 workload->req->hw_context->state->obj;
129 struct execlist_ring_context *shadow_ring_context;
132 unsigned long context_gpa, context_page_num;
135 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
136 shadow_ring_context = kmap(page);
138 sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
139 #define COPY_REG(name) \
140 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
141 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
142 #define COPY_REG_MASKED(name) {\
143 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
144 + RING_CTX_OFF(name.val),\
145 &shadow_ring_context->name.val, 4);\
146 shadow_ring_context->name.val |= 0xffff << 16;\
149 COPY_REG_MASKED(ctx_ctrl);
150 COPY_REG(ctx_timestamp);
152 if (ring_id == RCS0) {
153 COPY_REG(bb_per_ctx_ptr);
154 COPY_REG(rcs_indirect_ctx);
155 COPY_REG(rcs_indirect_ctx_offset);
158 #undef COPY_REG_MASKED
160 intel_gvt_hypervisor_read_gpa(vgpu,
161 workload->ring_context_gpa +
162 sizeof(*shadow_ring_context),
163 (void *)shadow_ring_context +
164 sizeof(*shadow_ring_context),
165 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
167 sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
170 if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
173 gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
174 workload->ctx_desc.lrca);
176 context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
178 context_page_num = context_page_num >> PAGE_SHIFT;
180 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0)
181 context_page_num = 19;
184 while (i < context_page_num) {
185 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
186 (u32)((workload->ctx_desc.lrca + i) <<
187 I915_GTT_PAGE_SHIFT));
188 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
189 gvt_vgpu_err("Invalid guest context descriptor\n");
193 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
195 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
203 static inline bool is_gvt_request(struct i915_request *req)
205 return i915_gem_context_force_single_submission(req->gem_context);
208 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
210 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
211 u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
214 reg = RING_INSTDONE(ring_base);
215 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
216 reg = RING_ACTHD(ring_base);
217 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
218 reg = RING_ACTHD_UDW(ring_base);
219 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
222 static int shadow_context_status_change(struct notifier_block *nb,
223 unsigned long action, void *data)
225 struct i915_request *req = data;
226 struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
227 shadow_ctx_notifier_block[req->engine->id]);
228 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
229 enum intel_engine_id ring_id = req->engine->id;
230 struct intel_vgpu_workload *workload;
233 if (!is_gvt_request(req)) {
234 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
235 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
236 scheduler->engine_owner[ring_id]) {
237 /* Switch ring from vGPU to host. */
238 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
240 scheduler->engine_owner[ring_id] = NULL;
242 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
247 workload = scheduler->current_workload[ring_id];
248 if (unlikely(!workload))
252 case INTEL_CONTEXT_SCHEDULE_IN:
253 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
254 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
255 /* Switch ring from host to vGPU or vGPU to vGPU. */
256 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
257 workload->vgpu, ring_id);
258 scheduler->engine_owner[ring_id] = workload->vgpu;
260 gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
261 ring_id, workload->vgpu->id);
262 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
263 atomic_set(&workload->shadow_ctx_active, 1);
265 case INTEL_CONTEXT_SCHEDULE_OUT:
266 save_ring_hw_state(workload->vgpu, ring_id);
267 atomic_set(&workload->shadow_ctx_active, 0);
269 case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
270 save_ring_hw_state(workload->vgpu, ring_id);
276 wake_up(&workload->shadow_ctx_status_wq);
280 static void shadow_context_descriptor_update(struct intel_context *ce)
286 /* Update bits 0-11 of the context descriptor which includes flags
287 * like GEN8_CTX_* cached in desc_template
289 desc &= U64_MAX << 12;
290 desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1);
295 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
297 struct intel_vgpu *vgpu = workload->vgpu;
298 struct i915_request *req = workload->req;
299 void *shadow_ring_buffer_va;
303 if (IS_GEN(req->i915, 9) && is_inhibit_context(req->hw_context))
304 intel_vgpu_restore_inhibit_context(vgpu, req);
307 * To track whether a request has started on HW, we can emit a
308 * breadcrumb at the beginning of the request and check its
309 * timeline's HWSP to see if the breadcrumb has advanced past the
310 * start of this request. Actually, the request must have the
311 * init_breadcrumb if its timeline set has_init_bread_crumb, or the
312 * scheduler might get a wrong state of it during reset. Since the
313 * requests from gvt always set the has_init_breadcrumb flag, here
314 * need to do the emit_init_breadcrumb for all the requests.
316 if (req->engine->emit_init_breadcrumb) {
317 err = req->engine->emit_init_breadcrumb(req);
319 gvt_vgpu_err("fail to emit init breadcrumb\n");
324 /* allocate shadow ring buffer */
325 cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
327 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n",
332 shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
334 /* get shadow ring buffer va */
335 workload->shadow_ring_buffer_va = cs;
337 memcpy(cs, shadow_ring_buffer_va,
340 cs += workload->rb_len / sizeof(u32);
341 intel_ring_advance(workload->req, cs);
346 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
348 if (!wa_ctx->indirect_ctx.obj)
351 i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
352 i915_gem_object_put(wa_ctx->indirect_ctx.obj);
354 wa_ctx->indirect_ctx.obj = NULL;
355 wa_ctx->indirect_ctx.shadow_va = NULL;
358 static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
359 struct i915_gem_context *ctx)
361 struct intel_vgpu_mm *mm = workload->shadow_mm;
362 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
365 if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed)
368 if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
369 px_dma(&ppgtt->pml4) = mm->ppgtt_mm.shadow_pdps[0];
371 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
372 px_dma(ppgtt->pdp.page_directory[i]) =
373 mm->ppgtt_mm.shadow_pdps[i];
381 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
383 struct intel_vgpu *vgpu = workload->vgpu;
384 struct intel_vgpu_submission *s = &vgpu->submission;
385 struct i915_gem_context *shadow_ctx = s->shadow_ctx;
386 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
387 struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
388 struct i915_request *rq;
391 lockdep_assert_held(&dev_priv->drm.struct_mutex);
396 rq = i915_request_alloc(engine, shadow_ctx);
398 gvt_vgpu_err("fail to allocate gem request\n");
402 workload->req = i915_request_get(rq);
408 * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
409 * shadow it as well, include ringbuffer,wa_ctx and ctx.
410 * @workload: an abstract entity for each execlist submission.
412 * This function is called before the workload submitting to i915, to make
413 * sure the content of the workload is valid.
415 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
417 struct intel_vgpu *vgpu = workload->vgpu;
418 struct intel_vgpu_submission *s = &vgpu->submission;
419 struct i915_gem_context *shadow_ctx = s->shadow_ctx;
420 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
421 struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
422 struct intel_context *ce;
425 lockdep_assert_held(&dev_priv->drm.struct_mutex);
427 if (workload->shadow)
430 /* pin shadow context by gvt even the shadow context will be pinned
431 * when i915 alloc request. That is because gvt will update the guest
432 * context from shadow context when workload is completed, and at that
433 * moment, i915 may already unpined the shadow context to make the
434 * shadow_ctx pages invalid. So gvt need to pin itself. After update
435 * the guest context, gvt can unpin the shadow_ctx safely.
437 ce = intel_context_pin(shadow_ctx, engine);
439 gvt_vgpu_err("fail to pin shadow context\n");
443 shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
444 shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
445 GEN8_CTX_ADDRESSING_MODE_SHIFT;
447 if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
448 shadow_context_descriptor_update(ce);
450 ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
454 if (workload->ring_id == RCS0 && workload->wa_ctx.indirect_ctx.size) {
455 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
460 workload->shadow = true;
463 release_shadow_wa_ctx(&workload->wa_ctx);
465 intel_context_unpin(ce);
469 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
471 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
473 struct intel_gvt *gvt = workload->vgpu->gvt;
474 const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
475 struct intel_vgpu_shadow_bb *bb;
478 list_for_each_entry(bb, &workload->shadow_bb, list) {
479 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
480 * is only updated into ring_scan_buffer, not real ring address
481 * allocated in later copy_workload_to_ring_buffer. pls be noted
482 * shadow_ring_buffer_va is now pointed to real ring buffer va
483 * in copy_workload_to_ring_buffer.
487 bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
491 /* for non-priv bb, scan&shadow is only for
492 * debugging purpose, so the content of shadow bb
493 * is the same as original bb. Therefore,
494 * here, rather than switch to shadow bb's gma
495 * address, we directly use original batch buffer's
496 * gma address, and send original bb to hardware
499 if (bb->clflush & CLFLUSH_AFTER) {
500 drm_clflush_virt_range(bb->va,
502 bb->clflush &= ~CLFLUSH_AFTER;
504 i915_gem_obj_finish_shmem_access(bb->obj);
505 bb->accessing = false;
508 bb->vma = i915_gem_object_ggtt_pin(bb->obj,
510 if (IS_ERR(bb->vma)) {
511 ret = PTR_ERR(bb->vma);
515 /* relocate shadow batch buffer */
516 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
517 if (gmadr_bytes == 8)
518 bb->bb_start_cmd_va[2] = 0;
520 /* No one is going to touch shadow bb from now on. */
521 if (bb->clflush & CLFLUSH_AFTER) {
522 drm_clflush_virt_range(bb->va,
524 bb->clflush &= ~CLFLUSH_AFTER;
527 ret = i915_gem_object_set_to_gtt_domain(bb->obj,
532 i915_gem_obj_finish_shmem_access(bb->obj);
533 bb->accessing = false;
535 ret = i915_vma_move_to_active(bb->vma,
544 release_shadow_batch_buffer(workload);
548 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
550 struct intel_vgpu_workload *workload =
551 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
552 struct i915_request *rq = workload->req;
553 struct execlist_ring_context *shadow_ring_context =
554 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state;
556 shadow_ring_context->bb_per_ctx_ptr.val =
557 (shadow_ring_context->bb_per_ctx_ptr.val &
558 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
559 shadow_ring_context->rcs_indirect_ctx.val =
560 (shadow_ring_context->rcs_indirect_ctx.val &
561 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
564 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
566 struct i915_vma *vma;
567 unsigned char *per_ctx_va =
568 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
569 wa_ctx->indirect_ctx.size;
571 if (wa_ctx->indirect_ctx.size == 0)
574 vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
575 0, CACHELINE_BYTES, 0);
579 /* FIXME: we are not tracking our pinned VMA leaving it
580 * up to the core to fix up the stray pin_count upon
584 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
586 wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
587 memset(per_ctx_va, 0, CACHELINE_BYTES);
589 update_wa_ctx_2_shadow_ctx(wa_ctx);
593 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
595 struct intel_vgpu *vgpu = workload->vgpu;
596 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
597 struct intel_vgpu_shadow_bb *bb, *pos;
599 if (list_empty(&workload->shadow_bb))
602 bb = list_first_entry(&workload->shadow_bb,
603 struct intel_vgpu_shadow_bb, list);
605 mutex_lock(&dev_priv->drm.struct_mutex);
607 list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
610 i915_gem_obj_finish_shmem_access(bb->obj);
612 if (bb->va && !IS_ERR(bb->va))
613 i915_gem_object_unpin_map(bb->obj);
615 if (bb->vma && !IS_ERR(bb->vma)) {
616 i915_vma_unpin(bb->vma);
617 i915_vma_close(bb->vma);
619 __i915_gem_object_release_unless_active(bb->obj);
625 mutex_unlock(&dev_priv->drm.struct_mutex);
628 static int prepare_workload(struct intel_vgpu_workload *workload)
630 struct intel_vgpu *vgpu = workload->vgpu;
633 ret = intel_vgpu_pin_mm(workload->shadow_mm);
635 gvt_vgpu_err("fail to vgpu pin mm\n");
639 update_shadow_pdps(workload);
641 ret = intel_vgpu_sync_oos_pages(workload->vgpu);
643 gvt_vgpu_err("fail to vgpu sync oos pages\n");
647 ret = intel_vgpu_flush_post_shadow(workload->vgpu);
649 gvt_vgpu_err("fail to flush post shadow\n");
653 ret = copy_workload_to_ring_buffer(workload);
655 gvt_vgpu_err("fail to generate request\n");
659 ret = prepare_shadow_batch_buffer(workload);
661 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
665 ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
667 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
668 goto err_shadow_batch;
671 if (workload->prepare) {
672 ret = workload->prepare(workload);
674 goto err_shadow_wa_ctx;
679 release_shadow_wa_ctx(&workload->wa_ctx);
681 release_shadow_batch_buffer(workload);
683 intel_vgpu_unpin_mm(workload->shadow_mm);
687 static int dispatch_workload(struct intel_vgpu_workload *workload)
689 struct intel_vgpu *vgpu = workload->vgpu;
690 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
691 struct intel_vgpu_submission *s = &vgpu->submission;
692 struct i915_gem_context *shadow_ctx = s->shadow_ctx;
693 struct i915_request *rq;
694 int ring_id = workload->ring_id;
697 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
700 mutex_lock(&vgpu->vgpu_lock);
701 mutex_lock(&dev_priv->drm.struct_mutex);
703 ret = set_context_ppgtt_from_shadow(workload, shadow_ctx);
705 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
709 ret = intel_gvt_workload_req_alloc(workload);
713 ret = intel_gvt_scan_and_shadow_workload(workload);
717 ret = populate_shadow_context(workload);
719 release_shadow_wa_ctx(&workload->wa_ctx);
723 ret = prepare_workload(workload);
726 /* We might still need to add request with
727 * clean ctx to retire it properly..
729 rq = fetch_and_zero(&workload->req);
730 i915_request_put(rq);
733 if (!IS_ERR_OR_NULL(workload->req)) {
734 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
735 ring_id, workload->req);
736 i915_request_add(workload->req);
737 workload->dispatched = true;
741 workload->status = ret;
742 mutex_unlock(&dev_priv->drm.struct_mutex);
743 mutex_unlock(&vgpu->vgpu_lock);
747 static struct intel_vgpu_workload *pick_next_workload(
748 struct intel_gvt *gvt, int ring_id)
750 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
751 struct intel_vgpu_workload *workload = NULL;
753 mutex_lock(&gvt->sched_lock);
756 * no current vgpu / will be scheduled out / no workload
759 if (!scheduler->current_vgpu) {
760 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
764 if (scheduler->need_reschedule) {
765 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
769 if (!scheduler->current_vgpu->active ||
770 list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
774 * still have current workload, maybe the workload disptacher
775 * fail to submit it for some reason, resubmit it.
777 if (scheduler->current_workload[ring_id]) {
778 workload = scheduler->current_workload[ring_id];
779 gvt_dbg_sched("ring id %d still have current workload %p\n",
785 * pick a workload as current workload
786 * once current workload is set, schedule policy routines
787 * will wait the current workload is finished when trying to
788 * schedule out a vgpu.
790 scheduler->current_workload[ring_id] = container_of(
791 workload_q_head(scheduler->current_vgpu, ring_id)->next,
792 struct intel_vgpu_workload, list);
794 workload = scheduler->current_workload[ring_id];
796 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
798 atomic_inc(&workload->vgpu->submission.running_workload_num);
800 mutex_unlock(&gvt->sched_lock);
804 static void update_guest_context(struct intel_vgpu_workload *workload)
806 struct i915_request *rq = workload->req;
807 struct intel_vgpu *vgpu = workload->vgpu;
808 struct intel_gvt *gvt = vgpu->gvt;
809 struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
810 struct execlist_ring_context *shadow_ring_context;
813 unsigned long context_gpa, context_page_num;
815 struct drm_i915_private *dev_priv = gvt->dev_priv;
820 gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
821 workload->ctx_desc.lrca);
823 head = workload->rb_head;
824 tail = workload->rb_tail;
825 wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF;
828 if (wrap_count == RB_HEAD_WRAP_CNT_MAX)
834 head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail;
836 ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
837 vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
838 vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
840 context_page_num = rq->engine->context_size;
841 context_page_num = context_page_num >> PAGE_SHIFT;
843 if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0)
844 context_page_num = 19;
848 while (i < context_page_num) {
849 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
850 (u32)((workload->ctx_desc.lrca + i) <<
851 I915_GTT_PAGE_SHIFT));
852 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
853 gvt_vgpu_err("invalid guest context descriptor\n");
857 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
859 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
865 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
866 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
868 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
869 shadow_ring_context = kmap(page);
871 #define COPY_REG(name) \
872 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
873 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
876 COPY_REG(ctx_timestamp);
880 intel_gvt_hypervisor_write_gpa(vgpu,
881 workload->ring_context_gpa +
882 sizeof(*shadow_ring_context),
883 (void *)shadow_ring_context +
884 sizeof(*shadow_ring_context),
885 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
890 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
891 intel_engine_mask_t engine_mask)
893 struct intel_vgpu_submission *s = &vgpu->submission;
894 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
895 struct intel_engine_cs *engine;
896 struct intel_vgpu_workload *pos, *n;
897 intel_engine_mask_t tmp;
899 /* free the unsubmited workloads in the queues. */
900 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
901 list_for_each_entry_safe(pos, n,
902 &s->workload_q_head[engine->id], list) {
903 list_del_init(&pos->list);
904 intel_vgpu_destroy_workload(pos);
906 clear_bit(engine->id, s->shadow_ctx_desc_updated);
910 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
912 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
913 struct intel_vgpu_workload *workload =
914 scheduler->current_workload[ring_id];
915 struct intel_vgpu *vgpu = workload->vgpu;
916 struct intel_vgpu_submission *s = &vgpu->submission;
917 struct i915_request *rq = workload->req;
920 mutex_lock(&vgpu->vgpu_lock);
921 mutex_lock(&gvt->sched_lock);
923 /* For the workload w/ request, needs to wait for the context
924 * switch to make sure request is completed.
925 * For the workload w/o request, directly complete the workload.
928 wait_event(workload->shadow_ctx_status_wq,
929 !atomic_read(&workload->shadow_ctx_active));
931 /* If this request caused GPU hang, req->fence.error will
932 * be set to -EIO. Use -EIO to set workload status so
933 * that when this request caused GPU hang, didn't trigger
934 * context switch interrupt to guest.
936 if (likely(workload->status == -EINPROGRESS)) {
937 if (workload->req->fence.error == -EIO)
938 workload->status = -EIO;
940 workload->status = 0;
943 if (!workload->status &&
944 !(vgpu->resetting_eng & BIT(ring_id))) {
945 update_guest_context(workload);
947 for_each_set_bit(event, workload->pending_events,
949 intel_vgpu_trigger_virtual_event(vgpu, event);
952 /* unpin shadow ctx as the shadow_ctx update is done */
953 mutex_lock(&rq->i915->drm.struct_mutex);
954 intel_context_unpin(rq->hw_context);
955 mutex_unlock(&rq->i915->drm.struct_mutex);
957 i915_request_put(fetch_and_zero(&workload->req));
960 gvt_dbg_sched("ring id %d complete workload %p status %d\n",
961 ring_id, workload, workload->status);
963 scheduler->current_workload[ring_id] = NULL;
965 list_del_init(&workload->list);
967 if (workload->status || vgpu->resetting_eng & BIT(ring_id)) {
968 /* if workload->status is not successful means HW GPU
969 * has occurred GPU hang or something wrong with i915/GVT,
970 * and GVT won't inject context switch interrupt to guest.
971 * So this error is a vGPU hang actually to the guest.
972 * According to this we should emunlate a vGPU hang. If
973 * there are pending workloads which are already submitted
974 * from guest, we should clean them up like HW GPU does.
976 * if it is in middle of engine resetting, the pending
977 * workloads won't be submitted to HW GPU and will be
978 * cleaned up during the resetting process later, so doing
979 * the workload clean up here doesn't have any impact.
981 intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
984 workload->complete(workload);
986 atomic_dec(&s->running_workload_num);
987 wake_up(&scheduler->workload_complete_wq);
989 if (gvt->scheduler.need_reschedule)
990 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
992 mutex_unlock(&gvt->sched_lock);
993 mutex_unlock(&vgpu->vgpu_lock);
996 struct workload_thread_param {
997 struct intel_gvt *gvt;
1001 static int workload_thread(void *priv)
1003 struct workload_thread_param *p = (struct workload_thread_param *)priv;
1004 struct intel_gvt *gvt = p->gvt;
1005 int ring_id = p->ring_id;
1006 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1007 struct intel_vgpu_workload *workload = NULL;
1008 struct intel_vgpu *vgpu = NULL;
1010 bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
1011 DEFINE_WAIT_FUNC(wait, woken_wake_function);
1015 gvt_dbg_core("workload thread for ring %d started\n", ring_id);
1017 while (!kthread_should_stop()) {
1018 add_wait_queue(&scheduler->waitq[ring_id], &wait);
1020 workload = pick_next_workload(gvt, ring_id);
1023 wait_woken(&wait, TASK_INTERRUPTIBLE,
1024 MAX_SCHEDULE_TIMEOUT);
1025 } while (!kthread_should_stop());
1026 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
1031 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
1032 workload->ring_id, workload,
1033 workload->vgpu->id);
1035 intel_runtime_pm_get(gvt->dev_priv);
1037 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
1038 workload->ring_id, workload);
1040 if (need_force_wake)
1041 intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
1044 ret = dispatch_workload(workload);
1047 vgpu = workload->vgpu;
1048 gvt_vgpu_err("fail to dispatch workload, skip\n");
1052 gvt_dbg_sched("ring id %d wait workload %p\n",
1053 workload->ring_id, workload);
1054 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1057 gvt_dbg_sched("will complete workload %p, status: %d\n",
1058 workload, workload->status);
1060 complete_current_workload(gvt, ring_id);
1062 if (need_force_wake)
1063 intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
1066 intel_runtime_pm_put_unchecked(gvt->dev_priv);
1067 if (ret && (vgpu_is_vm_unhealthy(ret)))
1068 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1073 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1075 struct intel_vgpu_submission *s = &vgpu->submission;
1076 struct intel_gvt *gvt = vgpu->gvt;
1077 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1079 if (atomic_read(&s->running_workload_num)) {
1080 gvt_dbg_sched("wait vgpu idle\n");
1082 wait_event(scheduler->workload_complete_wq,
1083 !atomic_read(&s->running_workload_num));
1087 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1089 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1090 struct intel_engine_cs *engine;
1091 enum intel_engine_id i;
1093 gvt_dbg_core("clean workload scheduler\n");
1095 for_each_engine(engine, gvt->dev_priv, i) {
1096 atomic_notifier_chain_unregister(
1097 &engine->context_status_notifier,
1098 &gvt->shadow_ctx_notifier_block[i]);
1099 kthread_stop(scheduler->thread[i]);
1103 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1105 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1106 struct workload_thread_param *param = NULL;
1107 struct intel_engine_cs *engine;
1108 enum intel_engine_id i;
1111 gvt_dbg_core("init workload scheduler\n");
1113 init_waitqueue_head(&scheduler->workload_complete_wq);
1115 for_each_engine(engine, gvt->dev_priv, i) {
1116 init_waitqueue_head(&scheduler->waitq[i]);
1118 param = kzalloc(sizeof(*param), GFP_KERNEL);
1127 scheduler->thread[i] = kthread_run(workload_thread, param,
1128 "gvt workload %d", i);
1129 if (IS_ERR(scheduler->thread[i])) {
1130 gvt_err("fail to create workload thread\n");
1131 ret = PTR_ERR(scheduler->thread[i]);
1135 gvt->shadow_ctx_notifier_block[i].notifier_call =
1136 shadow_context_status_change;
1137 atomic_notifier_chain_register(&engine->context_status_notifier,
1138 &gvt->shadow_ctx_notifier_block[i]);
1142 intel_gvt_clean_workload_scheduler(gvt);
1149 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
1151 struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1154 if (i915_vm_is_4lvl(&i915_ppgtt->vm)) {
1155 px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
1157 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1158 px_dma(i915_ppgtt->pdp.page_directory[i]) =
1159 s->i915_context_pdps[i];
1164 * intel_vgpu_clean_submission - free submission-related resource for vGPU
1167 * This function is called when a vGPU is being destroyed.
1170 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1172 struct intel_vgpu_submission *s = &vgpu->submission;
1174 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1175 i915_context_ppgtt_root_restore(s);
1176 i915_gem_context_put(s->shadow_ctx);
1177 kmem_cache_destroy(s->workloads);
1182 * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1184 * @engine_mask: engines expected to be reset
1186 * This function is called when a vGPU is being destroyed.
1189 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1190 intel_engine_mask_t engine_mask)
1192 struct intel_vgpu_submission *s = &vgpu->submission;
1197 intel_vgpu_clean_workloads(vgpu, engine_mask);
1198 s->ops->reset(vgpu, engine_mask);
1202 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
1204 struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1207 if (i915_vm_is_4lvl(&i915_ppgtt->vm))
1208 s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
1210 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1211 s->i915_context_pdps[i] =
1212 px_dma(i915_ppgtt->pdp.page_directory[i]);
1217 * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1220 * This function is called when a vGPU is being created.
1223 * Zero on success, negative error code if failed.
1226 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1228 struct intel_vgpu_submission *s = &vgpu->submission;
1229 enum intel_engine_id i;
1230 struct intel_engine_cs *engine;
1233 s->shadow_ctx = i915_gem_context_create_gvt(
1234 &vgpu->gvt->dev_priv->drm);
1235 if (IS_ERR(s->shadow_ctx))
1236 return PTR_ERR(s->shadow_ctx);
1238 i915_context_ppgtt_root_save(s);
1240 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1242 s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1243 sizeof(struct intel_vgpu_workload), 0,
1245 offsetof(struct intel_vgpu_workload, rb_tail),
1246 sizeof_field(struct intel_vgpu_workload, rb_tail),
1249 if (!s->workloads) {
1251 goto out_shadow_ctx;
1254 for_each_engine(engine, vgpu->gvt->dev_priv, i)
1255 INIT_LIST_HEAD(&s->workload_q_head[i]);
1257 atomic_set(&s->running_workload_num, 0);
1258 bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1263 i915_gem_context_put(s->shadow_ctx);
1268 * intel_vgpu_select_submission_ops - select virtual submission interface
1270 * @engine_mask: either ALL_ENGINES or target engine mask
1271 * @interface: expected vGPU virtual submission interface
1273 * This function is called when guest configures submission interface.
1276 * Zero on success, negative error code if failed.
1279 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1280 intel_engine_mask_t engine_mask,
1281 unsigned int interface)
1283 struct intel_vgpu_submission *s = &vgpu->submission;
1284 const struct intel_vgpu_submission_ops *ops[] = {
1285 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1286 &intel_vgpu_execlist_submission_ops,
1290 if (WARN_ON(interface >= ARRAY_SIZE(ops)))
1293 if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1297 s->ops->clean(vgpu, engine_mask);
1299 if (interface == 0) {
1301 s->virtual_submission_interface = 0;
1303 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1307 ret = ops[interface]->init(vgpu, engine_mask);
1311 s->ops = ops[interface];
1312 s->virtual_submission_interface = interface;
1315 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1316 vgpu->id, s->ops->name);
1322 * intel_vgpu_destroy_workload - destroy a vGPU workload
1323 * @workload: workload to destroy
1325 * This function is called when destroy a vGPU workload.
1328 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1330 struct intel_vgpu_submission *s = &workload->vgpu->submission;
1332 release_shadow_batch_buffer(workload);
1333 release_shadow_wa_ctx(&workload->wa_ctx);
1335 if (workload->shadow_mm)
1336 intel_vgpu_mm_put(workload->shadow_mm);
1338 kmem_cache_free(s->workloads, workload);
1341 static struct intel_vgpu_workload *
1342 alloc_workload(struct intel_vgpu *vgpu)
1344 struct intel_vgpu_submission *s = &vgpu->submission;
1345 struct intel_vgpu_workload *workload;
1347 workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1349 return ERR_PTR(-ENOMEM);
1351 INIT_LIST_HEAD(&workload->list);
1352 INIT_LIST_HEAD(&workload->shadow_bb);
1354 init_waitqueue_head(&workload->shadow_ctx_status_wq);
1355 atomic_set(&workload->shadow_ctx_active, 0);
1357 workload->status = -EINPROGRESS;
1358 workload->vgpu = vgpu;
1363 #define RING_CTX_OFF(x) \
1364 offsetof(struct execlist_ring_context, x)
1366 static void read_guest_pdps(struct intel_vgpu *vgpu,
1367 u64 ring_context_gpa, u32 pdp[8])
1372 gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1374 for (i = 0; i < 8; i++)
1375 intel_gvt_hypervisor_read_gpa(vgpu,
1376 gpa + i * 8, &pdp[7 - i], 4);
1379 static int prepare_mm(struct intel_vgpu_workload *workload)
1381 struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1382 struct intel_vgpu_mm *mm;
1383 struct intel_vgpu *vgpu = workload->vgpu;
1384 enum intel_gvt_gtt_type root_entry_type;
1385 u64 pdps[GVT_RING_CTX_NR_PDPS];
1387 switch (desc->addressing_mode) {
1388 case 1: /* legacy 32-bit */
1389 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1391 case 3: /* legacy 64-bit */
1392 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1395 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1399 read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1401 mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1405 workload->shadow_mm = mm;
1409 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1410 ((a)->lrca == (b)->lrca))
1412 #define get_last_workload(q) \
1413 (list_empty(q) ? NULL : container_of(q->prev, \
1414 struct intel_vgpu_workload, list))
1416 * intel_vgpu_create_workload - create a vGPU workload
1418 * @ring_id: ring index
1419 * @desc: a guest context descriptor
1421 * This function is called when creating a vGPU workload.
1424 * struct intel_vgpu_workload * on success, negative error code in
1425 * pointer if failed.
1428 struct intel_vgpu_workload *
1429 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
1430 struct execlist_ctx_descriptor_format *desc)
1432 struct intel_vgpu_submission *s = &vgpu->submission;
1433 struct list_head *q = workload_q_head(vgpu, ring_id);
1434 struct intel_vgpu_workload *last_workload = get_last_workload(q);
1435 struct intel_vgpu_workload *workload = NULL;
1436 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1437 u64 ring_context_gpa;
1438 u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1442 ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1443 (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1444 if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1445 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1446 return ERR_PTR(-EINVAL);
1449 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1450 RING_CTX_OFF(ring_header.val), &head, 4);
1452 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1453 RING_CTX_OFF(ring_tail.val), &tail, 4);
1457 head &= RB_HEAD_OFF_MASK;
1458 tail &= RB_TAIL_OFF_MASK;
1460 if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
1461 gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
1462 gvt_dbg_el("ctx head %x real head %lx\n", head,
1463 last_workload->rb_tail);
1465 * cannot use guest context head pointer here,
1466 * as it might not be updated at this time
1468 head = last_workload->rb_tail;
1471 gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
1473 /* record some ring buffer register values for scan and shadow */
1474 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1475 RING_CTX_OFF(rb_start.val), &start, 4);
1476 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1477 RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1478 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1479 RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1481 workload = alloc_workload(vgpu);
1482 if (IS_ERR(workload))
1485 workload->ring_id = ring_id;
1486 workload->ctx_desc = *desc;
1487 workload->ring_context_gpa = ring_context_gpa;
1488 workload->rb_head = head;
1489 workload->guest_rb_head = guest_head;
1490 workload->rb_tail = tail;
1491 workload->rb_start = start;
1492 workload->rb_ctl = ctl;
1494 if (ring_id == RCS0) {
1495 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1496 RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1497 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1498 RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1500 workload->wa_ctx.indirect_ctx.guest_gma =
1501 indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1502 workload->wa_ctx.indirect_ctx.size =
1503 (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1505 workload->wa_ctx.per_ctx.guest_gma =
1506 per_ctx & PER_CTX_ADDR_MASK;
1507 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1510 gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1511 workload, ring_id, head, tail, start, ctl);
1513 ret = prepare_mm(workload);
1515 kmem_cache_free(s->workloads, workload);
1516 return ERR_PTR(ret);
1519 /* Only scan and shadow the first workload in the queue
1520 * as there is only one pre-allocated buf-obj for shadow.
1522 if (list_empty(workload_q_head(vgpu, ring_id))) {
1523 intel_runtime_pm_get(dev_priv);
1524 mutex_lock(&dev_priv->drm.struct_mutex);
1525 ret = intel_gvt_scan_and_shadow_workload(workload);
1526 mutex_unlock(&dev_priv->drm.struct_mutex);
1527 intel_runtime_pm_put_unchecked(dev_priv);
1531 if (vgpu_is_vm_unhealthy(ret))
1532 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1533 intel_vgpu_destroy_workload(workload);
1534 return ERR_PTR(ret);
1541 * intel_vgpu_queue_workload - Qeue a vGPU workload
1542 * @workload: the workload to queue in
1544 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1546 list_add_tail(&workload->list,
1547 workload_q_head(workload->vgpu, workload->ring_id));
1548 intel_gvt_kick_schedule(workload->vgpu->gvt);
1549 wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);