2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Zhi Wang <zhi.a.wang@intel.com>
27 * Ping Gao <ping.a.gao@intel.com>
28 * Tina Zhang <tina.zhang@intel.com>
29 * Chanbin Du <changbin.du@intel.com>
30 * Min He <min.he@intel.com>
31 * Bing Niu <bing.niu@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
36 #include <linux/kthread.h>
41 #define RING_CTX_OFF(x) \
42 offsetof(struct execlist_ring_context, x)
44 static void set_context_pdp_root_pointer(
45 struct execlist_ring_context *ring_context,
50 for (i = 0; i < 8; i++)
51 ring_context->pdps[i].val = pdp[7 - i];
54 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
56 struct drm_i915_gem_object *ctx_obj =
57 workload->req->hw_context->state->obj;
58 struct execlist_ring_context *shadow_ring_context;
61 if (WARN_ON(!workload->shadow_mm))
64 if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
67 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
68 shadow_ring_context = kmap(page);
69 set_context_pdp_root_pointer(shadow_ring_context,
70 (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
75 * when populating shadow ctx from guest, we should not overrride oa related
76 * registers, so that they will not be overlapped by guest oa configs. Thus
77 * made it possible to capture oa data from host for both host and guests.
79 static void sr_oa_regs(struct intel_vgpu_workload *workload,
80 u32 *reg_state, bool save)
82 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
83 u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
84 u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
87 i915_mmio_reg_offset(EU_PERF_CNTL0),
88 i915_mmio_reg_offset(EU_PERF_CNTL1),
89 i915_mmio_reg_offset(EU_PERF_CNTL2),
90 i915_mmio_reg_offset(EU_PERF_CNTL3),
91 i915_mmio_reg_offset(EU_PERF_CNTL4),
92 i915_mmio_reg_offset(EU_PERF_CNTL5),
93 i915_mmio_reg_offset(EU_PERF_CNTL6),
96 if (workload->ring_id != RCS)
100 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
102 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
103 u32 state_offset = ctx_flexeu0 + i * 2;
105 workload->flex_mmio[i] = reg_state[state_offset + 1];
108 reg_state[ctx_oactxctrl] =
109 i915_mmio_reg_offset(GEN8_OACTXCONTROL);
110 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
112 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
113 u32 state_offset = ctx_flexeu0 + i * 2;
114 u32 mmio = flex_mmio[i];
116 reg_state[state_offset] = mmio;
117 reg_state[state_offset + 1] = workload->flex_mmio[i];
122 static int populate_shadow_context(struct intel_vgpu_workload *workload)
124 struct intel_vgpu *vgpu = workload->vgpu;
125 struct intel_gvt *gvt = vgpu->gvt;
126 int ring_id = workload->ring_id;
127 struct drm_i915_gem_object *ctx_obj =
128 workload->req->hw_context->state->obj;
129 struct execlist_ring_context *shadow_ring_context;
132 unsigned long context_gpa, context_page_num;
135 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
136 shadow_ring_context = kmap(page);
138 sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
139 #define COPY_REG(name) \
140 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
141 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
142 #define COPY_REG_MASKED(name) {\
143 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
144 + RING_CTX_OFF(name.val),\
145 &shadow_ring_context->name.val, 4);\
146 shadow_ring_context->name.val |= 0xffff << 16;\
149 COPY_REG_MASKED(ctx_ctrl);
150 COPY_REG(ctx_timestamp);
152 if (ring_id == RCS) {
153 COPY_REG(bb_per_ctx_ptr);
154 COPY_REG(rcs_indirect_ctx);
155 COPY_REG(rcs_indirect_ctx_offset);
158 #undef COPY_REG_MASKED
160 intel_gvt_hypervisor_read_gpa(vgpu,
161 workload->ring_context_gpa +
162 sizeof(*shadow_ring_context),
163 (void *)shadow_ring_context +
164 sizeof(*shadow_ring_context),
165 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
167 sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
170 if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
173 gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
174 workload->ctx_desc.lrca);
176 context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
178 context_page_num = context_page_num >> PAGE_SHIFT;
180 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
181 context_page_num = 19;
184 while (i < context_page_num) {
185 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
186 (u32)((workload->ctx_desc.lrca + i) <<
187 I915_GTT_PAGE_SHIFT));
188 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
189 gvt_vgpu_err("Invalid guest context descriptor\n");
193 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
195 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
203 static inline bool is_gvt_request(struct i915_request *req)
205 return i915_gem_context_force_single_submission(req->gem_context);
208 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
210 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
211 u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
214 reg = RING_INSTDONE(ring_base);
215 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
216 reg = RING_ACTHD(ring_base);
217 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
218 reg = RING_ACTHD_UDW(ring_base);
219 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
222 static int shadow_context_status_change(struct notifier_block *nb,
223 unsigned long action, void *data)
225 struct i915_request *req = data;
226 struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
227 shadow_ctx_notifier_block[req->engine->id]);
228 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
229 enum intel_engine_id ring_id = req->engine->id;
230 struct intel_vgpu_workload *workload;
233 if (!is_gvt_request(req)) {
234 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
235 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
236 scheduler->engine_owner[ring_id]) {
237 /* Switch ring from vGPU to host. */
238 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
240 scheduler->engine_owner[ring_id] = NULL;
242 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
247 workload = scheduler->current_workload[ring_id];
248 if (unlikely(!workload))
252 case INTEL_CONTEXT_SCHEDULE_IN:
253 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
254 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
255 /* Switch ring from host to vGPU or vGPU to vGPU. */
256 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
257 workload->vgpu, ring_id);
258 scheduler->engine_owner[ring_id] = workload->vgpu;
260 gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
261 ring_id, workload->vgpu->id);
262 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
263 atomic_set(&workload->shadow_ctx_active, 1);
265 case INTEL_CONTEXT_SCHEDULE_OUT:
266 save_ring_hw_state(workload->vgpu, ring_id);
267 atomic_set(&workload->shadow_ctx_active, 0);
269 case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
270 save_ring_hw_state(workload->vgpu, ring_id);
276 wake_up(&workload->shadow_ctx_status_wq);
280 static void shadow_context_descriptor_update(struct intel_context *ce)
286 /* Update bits 0-11 of the context descriptor which includes flags
287 * like GEN8_CTX_* cached in desc_template
289 desc &= U64_MAX << 12;
290 desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1);
295 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
297 struct intel_vgpu *vgpu = workload->vgpu;
298 struct i915_request *req = workload->req;
299 void *shadow_ring_buffer_va;
302 if ((IS_KABYLAKE(req->i915) || IS_BROXTON(req->i915)
303 || IS_COFFEELAKE(req->i915))
304 && is_inhibit_context(req->hw_context))
305 intel_vgpu_restore_inhibit_context(vgpu, req);
307 /* allocate shadow ring buffer */
308 cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
310 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n",
315 shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
317 /* get shadow ring buffer va */
318 workload->shadow_ring_buffer_va = cs;
320 memcpy(cs, shadow_ring_buffer_va,
323 cs += workload->rb_len / sizeof(u32);
324 intel_ring_advance(workload->req, cs);
329 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
331 if (!wa_ctx->indirect_ctx.obj)
334 i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
335 i915_gem_object_put(wa_ctx->indirect_ctx.obj);
338 static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
339 struct i915_gem_context *ctx)
341 struct intel_vgpu_mm *mm = workload->shadow_mm;
342 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
345 if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed)
348 if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
349 px_dma(&ppgtt->pml4) = mm->ppgtt_mm.shadow_pdps[0];
351 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
352 px_dma(ppgtt->pdp.page_directory[i]) =
353 mm->ppgtt_mm.shadow_pdps[i];
361 * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
362 * shadow it as well, include ringbuffer,wa_ctx and ctx.
363 * @workload: an abstract entity for each execlist submission.
365 * This function is called before the workload submitting to i915, to make
366 * sure the content of the workload is valid.
368 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
370 struct intel_vgpu *vgpu = workload->vgpu;
371 struct intel_vgpu_submission *s = &vgpu->submission;
372 struct i915_gem_context *shadow_ctx = s->shadow_ctx;
373 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
374 struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
375 struct intel_context *ce;
376 struct i915_request *rq;
379 lockdep_assert_held(&dev_priv->drm.struct_mutex);
384 ret = set_context_ppgtt_from_shadow(workload, shadow_ctx);
386 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
390 /* pin shadow context by gvt even the shadow context will be pinned
391 * when i915 alloc request. That is because gvt will update the guest
392 * context from shadow context when workload is completed, and at that
393 * moment, i915 may already unpined the shadow context to make the
394 * shadow_ctx pages invalid. So gvt need to pin itself. After update
395 * the guest context, gvt can unpin the shadow_ctx safely.
397 ce = intel_context_pin(shadow_ctx, engine);
399 gvt_vgpu_err("fail to pin shadow context\n");
403 shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
404 shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
405 GEN8_CTX_ADDRESSING_MODE_SHIFT;
407 if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
408 shadow_context_descriptor_update(ce);
410 ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
414 if ((workload->ring_id == RCS) &&
415 (workload->wa_ctx.indirect_ctx.size != 0)) {
416 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
421 rq = i915_request_alloc(engine, shadow_ctx);
423 gvt_vgpu_err("fail to allocate gem request\n");
427 workload->req = i915_request_get(rq);
429 ret = populate_shadow_context(workload);
435 rq = fetch_and_zero(&workload->req);
436 i915_request_put(rq);
438 release_shadow_wa_ctx(&workload->wa_ctx);
440 intel_context_unpin(ce);
444 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
446 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
448 struct intel_gvt *gvt = workload->vgpu->gvt;
449 const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
450 struct intel_vgpu_shadow_bb *bb;
453 list_for_each_entry(bb, &workload->shadow_bb, list) {
454 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
455 * is only updated into ring_scan_buffer, not real ring address
456 * allocated in later copy_workload_to_ring_buffer. pls be noted
457 * shadow_ring_buffer_va is now pointed to real ring buffer va
458 * in copy_workload_to_ring_buffer.
462 bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
466 /* for non-priv bb, scan&shadow is only for
467 * debugging purpose, so the content of shadow bb
468 * is the same as original bb. Therefore,
469 * here, rather than switch to shadow bb's gma
470 * address, we directly use original batch buffer's
471 * gma address, and send original bb to hardware
474 if (bb->clflush & CLFLUSH_AFTER) {
475 drm_clflush_virt_range(bb->va,
477 bb->clflush &= ~CLFLUSH_AFTER;
479 i915_gem_obj_finish_shmem_access(bb->obj);
480 bb->accessing = false;
483 bb->vma = i915_gem_object_ggtt_pin(bb->obj,
485 if (IS_ERR(bb->vma)) {
486 ret = PTR_ERR(bb->vma);
490 /* relocate shadow batch buffer */
491 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
492 if (gmadr_bytes == 8)
493 bb->bb_start_cmd_va[2] = 0;
495 /* No one is going to touch shadow bb from now on. */
496 if (bb->clflush & CLFLUSH_AFTER) {
497 drm_clflush_virt_range(bb->va,
499 bb->clflush &= ~CLFLUSH_AFTER;
502 ret = i915_gem_object_set_to_gtt_domain(bb->obj,
507 i915_gem_obj_finish_shmem_access(bb->obj);
508 bb->accessing = false;
510 ret = i915_vma_move_to_active(bb->vma,
519 release_shadow_batch_buffer(workload);
523 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
525 struct intel_vgpu_workload *workload =
526 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
527 struct i915_request *rq = workload->req;
528 struct execlist_ring_context *shadow_ring_context =
529 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state;
531 shadow_ring_context->bb_per_ctx_ptr.val =
532 (shadow_ring_context->bb_per_ctx_ptr.val &
533 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
534 shadow_ring_context->rcs_indirect_ctx.val =
535 (shadow_ring_context->rcs_indirect_ctx.val &
536 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
539 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
541 struct i915_vma *vma;
542 unsigned char *per_ctx_va =
543 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
544 wa_ctx->indirect_ctx.size;
546 if (wa_ctx->indirect_ctx.size == 0)
549 vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
550 0, CACHELINE_BYTES, 0);
554 /* FIXME: we are not tracking our pinned VMA leaving it
555 * up to the core to fix up the stray pin_count upon
559 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
561 wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
562 memset(per_ctx_va, 0, CACHELINE_BYTES);
564 update_wa_ctx_2_shadow_ctx(wa_ctx);
568 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
570 struct intel_vgpu *vgpu = workload->vgpu;
571 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
572 struct intel_vgpu_shadow_bb *bb, *pos;
574 if (list_empty(&workload->shadow_bb))
577 bb = list_first_entry(&workload->shadow_bb,
578 struct intel_vgpu_shadow_bb, list);
580 mutex_lock(&dev_priv->drm.struct_mutex);
582 list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
585 i915_gem_obj_finish_shmem_access(bb->obj);
587 if (bb->va && !IS_ERR(bb->va))
588 i915_gem_object_unpin_map(bb->obj);
590 if (bb->vma && !IS_ERR(bb->vma)) {
591 i915_vma_unpin(bb->vma);
592 i915_vma_close(bb->vma);
594 __i915_gem_object_release_unless_active(bb->obj);
600 mutex_unlock(&dev_priv->drm.struct_mutex);
603 static int prepare_workload(struct intel_vgpu_workload *workload)
605 struct intel_vgpu *vgpu = workload->vgpu;
608 ret = intel_vgpu_pin_mm(workload->shadow_mm);
610 gvt_vgpu_err("fail to vgpu pin mm\n");
614 update_shadow_pdps(workload);
616 ret = intel_vgpu_sync_oos_pages(workload->vgpu);
618 gvt_vgpu_err("fail to vgpu sync oos pages\n");
622 ret = intel_vgpu_flush_post_shadow(workload->vgpu);
624 gvt_vgpu_err("fail to flush post shadow\n");
628 ret = copy_workload_to_ring_buffer(workload);
630 gvt_vgpu_err("fail to generate request\n");
634 ret = prepare_shadow_batch_buffer(workload);
636 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
640 ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
642 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
643 goto err_shadow_batch;
646 if (workload->prepare) {
647 ret = workload->prepare(workload);
649 goto err_shadow_wa_ctx;
654 release_shadow_wa_ctx(&workload->wa_ctx);
656 release_shadow_batch_buffer(workload);
658 intel_vgpu_unpin_mm(workload->shadow_mm);
662 static int dispatch_workload(struct intel_vgpu_workload *workload)
664 struct intel_vgpu *vgpu = workload->vgpu;
665 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
666 int ring_id = workload->ring_id;
669 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
672 mutex_lock(&vgpu->vgpu_lock);
673 mutex_lock(&dev_priv->drm.struct_mutex);
675 ret = intel_gvt_scan_and_shadow_workload(workload);
679 ret = prepare_workload(workload);
683 workload->status = ret;
685 if (!IS_ERR_OR_NULL(workload->req)) {
686 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
687 ring_id, workload->req);
688 i915_request_add(workload->req);
689 workload->dispatched = true;
692 mutex_unlock(&dev_priv->drm.struct_mutex);
693 mutex_unlock(&vgpu->vgpu_lock);
697 static struct intel_vgpu_workload *pick_next_workload(
698 struct intel_gvt *gvt, int ring_id)
700 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
701 struct intel_vgpu_workload *workload = NULL;
703 mutex_lock(&gvt->sched_lock);
706 * no current vgpu / will be scheduled out / no workload
709 if (!scheduler->current_vgpu) {
710 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
714 if (scheduler->need_reschedule) {
715 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
719 if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
723 * still have current workload, maybe the workload disptacher
724 * fail to submit it for some reason, resubmit it.
726 if (scheduler->current_workload[ring_id]) {
727 workload = scheduler->current_workload[ring_id];
728 gvt_dbg_sched("ring id %d still have current workload %p\n",
734 * pick a workload as current workload
735 * once current workload is set, schedule policy routines
736 * will wait the current workload is finished when trying to
737 * schedule out a vgpu.
739 scheduler->current_workload[ring_id] = container_of(
740 workload_q_head(scheduler->current_vgpu, ring_id)->next,
741 struct intel_vgpu_workload, list);
743 workload = scheduler->current_workload[ring_id];
745 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
747 atomic_inc(&workload->vgpu->submission.running_workload_num);
749 mutex_unlock(&gvt->sched_lock);
753 static void update_guest_context(struct intel_vgpu_workload *workload)
755 struct i915_request *rq = workload->req;
756 struct intel_vgpu *vgpu = workload->vgpu;
757 struct intel_gvt *gvt = vgpu->gvt;
758 struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
759 struct execlist_ring_context *shadow_ring_context;
762 unsigned long context_gpa, context_page_num;
765 gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
766 workload->ctx_desc.lrca);
768 context_page_num = rq->engine->context_size;
769 context_page_num = context_page_num >> PAGE_SHIFT;
771 if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS)
772 context_page_num = 19;
776 while (i < context_page_num) {
777 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
778 (u32)((workload->ctx_desc.lrca + i) <<
779 I915_GTT_PAGE_SHIFT));
780 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
781 gvt_vgpu_err("invalid guest context descriptor\n");
785 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
787 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
793 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
794 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
796 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
797 shadow_ring_context = kmap(page);
799 #define COPY_REG(name) \
800 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
801 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
804 COPY_REG(ctx_timestamp);
808 intel_gvt_hypervisor_write_gpa(vgpu,
809 workload->ring_context_gpa +
810 sizeof(*shadow_ring_context),
811 (void *)shadow_ring_context +
812 sizeof(*shadow_ring_context),
813 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
818 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
819 unsigned long engine_mask)
821 struct intel_vgpu_submission *s = &vgpu->submission;
822 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
823 struct intel_engine_cs *engine;
824 struct intel_vgpu_workload *pos, *n;
827 /* free the unsubmited workloads in the queues. */
828 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
829 list_for_each_entry_safe(pos, n,
830 &s->workload_q_head[engine->id], list) {
831 list_del_init(&pos->list);
832 intel_vgpu_destroy_workload(pos);
834 clear_bit(engine->id, s->shadow_ctx_desc_updated);
838 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
840 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
841 struct intel_vgpu_workload *workload =
842 scheduler->current_workload[ring_id];
843 struct intel_vgpu *vgpu = workload->vgpu;
844 struct intel_vgpu_submission *s = &vgpu->submission;
845 struct i915_request *rq = workload->req;
848 mutex_lock(&vgpu->vgpu_lock);
849 mutex_lock(&gvt->sched_lock);
851 /* For the workload w/ request, needs to wait for the context
852 * switch to make sure request is completed.
853 * For the workload w/o request, directly complete the workload.
856 wait_event(workload->shadow_ctx_status_wq,
857 !atomic_read(&workload->shadow_ctx_active));
859 /* If this request caused GPU hang, req->fence.error will
860 * be set to -EIO. Use -EIO to set workload status so
861 * that when this request caused GPU hang, didn't trigger
862 * context switch interrupt to guest.
864 if (likely(workload->status == -EINPROGRESS)) {
865 if (workload->req->fence.error == -EIO)
866 workload->status = -EIO;
868 workload->status = 0;
871 if (!workload->status && !(vgpu->resetting_eng &
872 ENGINE_MASK(ring_id))) {
873 update_guest_context(workload);
875 for_each_set_bit(event, workload->pending_events,
877 intel_vgpu_trigger_virtual_event(vgpu, event);
880 /* unpin shadow ctx as the shadow_ctx update is done */
881 mutex_lock(&rq->i915->drm.struct_mutex);
882 intel_context_unpin(rq->hw_context);
883 mutex_unlock(&rq->i915->drm.struct_mutex);
885 i915_request_put(fetch_and_zero(&workload->req));
888 gvt_dbg_sched("ring id %d complete workload %p status %d\n",
889 ring_id, workload, workload->status);
891 scheduler->current_workload[ring_id] = NULL;
893 list_del_init(&workload->list);
895 if (!workload->status) {
896 release_shadow_batch_buffer(workload);
897 release_shadow_wa_ctx(&workload->wa_ctx);
900 if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id))) {
901 /* if workload->status is not successful means HW GPU
902 * has occurred GPU hang or something wrong with i915/GVT,
903 * and GVT won't inject context switch interrupt to guest.
904 * So this error is a vGPU hang actually to the guest.
905 * According to this we should emunlate a vGPU hang. If
906 * there are pending workloads which are already submitted
907 * from guest, we should clean them up like HW GPU does.
909 * if it is in middle of engine resetting, the pending
910 * workloads won't be submitted to HW GPU and will be
911 * cleaned up during the resetting process later, so doing
912 * the workload clean up here doesn't have any impact.
914 intel_vgpu_clean_workloads(vgpu, ENGINE_MASK(ring_id));
917 workload->complete(workload);
919 atomic_dec(&s->running_workload_num);
920 wake_up(&scheduler->workload_complete_wq);
922 if (gvt->scheduler.need_reschedule)
923 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
925 mutex_unlock(&gvt->sched_lock);
926 mutex_unlock(&vgpu->vgpu_lock);
929 struct workload_thread_param {
930 struct intel_gvt *gvt;
934 static int workload_thread(void *priv)
936 struct workload_thread_param *p = (struct workload_thread_param *)priv;
937 struct intel_gvt *gvt = p->gvt;
938 int ring_id = p->ring_id;
939 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
940 struct intel_vgpu_workload *workload = NULL;
941 struct intel_vgpu *vgpu = NULL;
943 bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
944 DEFINE_WAIT_FUNC(wait, woken_wake_function);
948 gvt_dbg_core("workload thread for ring %d started\n", ring_id);
950 while (!kthread_should_stop()) {
951 add_wait_queue(&scheduler->waitq[ring_id], &wait);
953 workload = pick_next_workload(gvt, ring_id);
956 wait_woken(&wait, TASK_INTERRUPTIBLE,
957 MAX_SCHEDULE_TIMEOUT);
958 } while (!kthread_should_stop());
959 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
964 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
965 workload->ring_id, workload,
968 intel_runtime_pm_get(gvt->dev_priv);
970 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
971 workload->ring_id, workload);
974 intel_uncore_forcewake_get(gvt->dev_priv,
977 ret = dispatch_workload(workload);
980 vgpu = workload->vgpu;
981 gvt_vgpu_err("fail to dispatch workload, skip\n");
985 gvt_dbg_sched("ring id %d wait workload %p\n",
986 workload->ring_id, workload);
987 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
990 gvt_dbg_sched("will complete workload %p, status: %d\n",
991 workload, workload->status);
993 complete_current_workload(gvt, ring_id);
996 intel_uncore_forcewake_put(gvt->dev_priv,
999 intel_runtime_pm_put_unchecked(gvt->dev_priv);
1000 if (ret && (vgpu_is_vm_unhealthy(ret)))
1001 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1006 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1008 struct intel_vgpu_submission *s = &vgpu->submission;
1009 struct intel_gvt *gvt = vgpu->gvt;
1010 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1012 if (atomic_read(&s->running_workload_num)) {
1013 gvt_dbg_sched("wait vgpu idle\n");
1015 wait_event(scheduler->workload_complete_wq,
1016 !atomic_read(&s->running_workload_num));
1020 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1022 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1023 struct intel_engine_cs *engine;
1024 enum intel_engine_id i;
1026 gvt_dbg_core("clean workload scheduler\n");
1028 for_each_engine(engine, gvt->dev_priv, i) {
1029 atomic_notifier_chain_unregister(
1030 &engine->context_status_notifier,
1031 &gvt->shadow_ctx_notifier_block[i]);
1032 kthread_stop(scheduler->thread[i]);
1036 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1038 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1039 struct workload_thread_param *param = NULL;
1040 struct intel_engine_cs *engine;
1041 enum intel_engine_id i;
1044 gvt_dbg_core("init workload scheduler\n");
1046 init_waitqueue_head(&scheduler->workload_complete_wq);
1048 for_each_engine(engine, gvt->dev_priv, i) {
1049 init_waitqueue_head(&scheduler->waitq[i]);
1051 param = kzalloc(sizeof(*param), GFP_KERNEL);
1060 scheduler->thread[i] = kthread_run(workload_thread, param,
1061 "gvt workload %d", i);
1062 if (IS_ERR(scheduler->thread[i])) {
1063 gvt_err("fail to create workload thread\n");
1064 ret = PTR_ERR(scheduler->thread[i]);
1068 gvt->shadow_ctx_notifier_block[i].notifier_call =
1069 shadow_context_status_change;
1070 atomic_notifier_chain_register(&engine->context_status_notifier,
1071 &gvt->shadow_ctx_notifier_block[i]);
1075 intel_gvt_clean_workload_scheduler(gvt);
1082 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
1084 struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1087 if (i915_vm_is_48bit(&i915_ppgtt->vm))
1088 px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
1090 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1091 px_dma(i915_ppgtt->pdp.page_directory[i]) =
1092 s->i915_context_pdps[i];
1097 * intel_vgpu_clean_submission - free submission-related resource for vGPU
1100 * This function is called when a vGPU is being destroyed.
1103 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1105 struct intel_vgpu_submission *s = &vgpu->submission;
1107 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1108 i915_context_ppgtt_root_restore(s);
1109 i915_gem_context_put(s->shadow_ctx);
1110 kmem_cache_destroy(s->workloads);
1115 * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1117 * @engine_mask: engines expected to be reset
1119 * This function is called when a vGPU is being destroyed.
1122 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1123 unsigned long engine_mask)
1125 struct intel_vgpu_submission *s = &vgpu->submission;
1130 intel_vgpu_clean_workloads(vgpu, engine_mask);
1131 s->ops->reset(vgpu, engine_mask);
1135 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
1137 struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
1140 if (i915_vm_is_48bit(&i915_ppgtt->vm))
1141 s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
1143 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1144 s->i915_context_pdps[i] =
1145 px_dma(i915_ppgtt->pdp.page_directory[i]);
1150 * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1153 * This function is called when a vGPU is being created.
1156 * Zero on success, negative error code if failed.
1159 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1161 struct intel_vgpu_submission *s = &vgpu->submission;
1162 enum intel_engine_id i;
1163 struct intel_engine_cs *engine;
1166 s->shadow_ctx = i915_gem_context_create_gvt(
1167 &vgpu->gvt->dev_priv->drm);
1168 if (IS_ERR(s->shadow_ctx))
1169 return PTR_ERR(s->shadow_ctx);
1171 i915_context_ppgtt_root_save(s);
1173 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1175 s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1176 sizeof(struct intel_vgpu_workload), 0,
1178 offsetof(struct intel_vgpu_workload, rb_tail),
1179 sizeof_field(struct intel_vgpu_workload, rb_tail),
1182 if (!s->workloads) {
1184 goto out_shadow_ctx;
1187 for_each_engine(engine, vgpu->gvt->dev_priv, i)
1188 INIT_LIST_HEAD(&s->workload_q_head[i]);
1190 atomic_set(&s->running_workload_num, 0);
1191 bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1196 i915_gem_context_put(s->shadow_ctx);
1201 * intel_vgpu_select_submission_ops - select virtual submission interface
1203 * @engine_mask: either ALL_ENGINES or target engine mask
1204 * @interface: expected vGPU virtual submission interface
1206 * This function is called when guest configures submission interface.
1209 * Zero on success, negative error code if failed.
1212 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1213 unsigned long engine_mask,
1214 unsigned int interface)
1216 struct intel_vgpu_submission *s = &vgpu->submission;
1217 const struct intel_vgpu_submission_ops *ops[] = {
1218 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1219 &intel_vgpu_execlist_submission_ops,
1223 if (WARN_ON(interface >= ARRAY_SIZE(ops)))
1226 if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1230 s->ops->clean(vgpu, engine_mask);
1232 if (interface == 0) {
1234 s->virtual_submission_interface = 0;
1236 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1240 ret = ops[interface]->init(vgpu, engine_mask);
1244 s->ops = ops[interface];
1245 s->virtual_submission_interface = interface;
1248 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1249 vgpu->id, s->ops->name);
1255 * intel_vgpu_destroy_workload - destroy a vGPU workload
1256 * @workload: workload to destroy
1258 * This function is called when destroy a vGPU workload.
1261 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1263 struct intel_vgpu_submission *s = &workload->vgpu->submission;
1265 if (workload->shadow_mm)
1266 intel_vgpu_mm_put(workload->shadow_mm);
1268 kmem_cache_free(s->workloads, workload);
1271 static struct intel_vgpu_workload *
1272 alloc_workload(struct intel_vgpu *vgpu)
1274 struct intel_vgpu_submission *s = &vgpu->submission;
1275 struct intel_vgpu_workload *workload;
1277 workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1279 return ERR_PTR(-ENOMEM);
1281 INIT_LIST_HEAD(&workload->list);
1282 INIT_LIST_HEAD(&workload->shadow_bb);
1284 init_waitqueue_head(&workload->shadow_ctx_status_wq);
1285 atomic_set(&workload->shadow_ctx_active, 0);
1287 workload->status = -EINPROGRESS;
1288 workload->vgpu = vgpu;
1293 #define RING_CTX_OFF(x) \
1294 offsetof(struct execlist_ring_context, x)
1296 static void read_guest_pdps(struct intel_vgpu *vgpu,
1297 u64 ring_context_gpa, u32 pdp[8])
1302 gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1304 for (i = 0; i < 8; i++)
1305 intel_gvt_hypervisor_read_gpa(vgpu,
1306 gpa + i * 8, &pdp[7 - i], 4);
1309 static int prepare_mm(struct intel_vgpu_workload *workload)
1311 struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1312 struct intel_vgpu_mm *mm;
1313 struct intel_vgpu *vgpu = workload->vgpu;
1314 intel_gvt_gtt_type_t root_entry_type;
1315 u64 pdps[GVT_RING_CTX_NR_PDPS];
1317 switch (desc->addressing_mode) {
1318 case 1: /* legacy 32-bit */
1319 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1321 case 3: /* legacy 64-bit */
1322 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1325 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1329 read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1331 mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1335 workload->shadow_mm = mm;
1339 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1340 ((a)->lrca == (b)->lrca))
1342 #define get_last_workload(q) \
1343 (list_empty(q) ? NULL : container_of(q->prev, \
1344 struct intel_vgpu_workload, list))
1346 * intel_vgpu_create_workload - create a vGPU workload
1348 * @ring_id: ring index
1349 * @desc: a guest context descriptor
1351 * This function is called when creating a vGPU workload.
1354 * struct intel_vgpu_workload * on success, negative error code in
1355 * pointer if failed.
1358 struct intel_vgpu_workload *
1359 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
1360 struct execlist_ctx_descriptor_format *desc)
1362 struct intel_vgpu_submission *s = &vgpu->submission;
1363 struct list_head *q = workload_q_head(vgpu, ring_id);
1364 struct intel_vgpu_workload *last_workload = get_last_workload(q);
1365 struct intel_vgpu_workload *workload = NULL;
1366 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1367 u64 ring_context_gpa;
1368 u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1371 ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1372 (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1373 if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1374 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1375 return ERR_PTR(-EINVAL);
1378 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1379 RING_CTX_OFF(ring_header.val), &head, 4);
1381 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1382 RING_CTX_OFF(ring_tail.val), &tail, 4);
1384 head &= RB_HEAD_OFF_MASK;
1385 tail &= RB_TAIL_OFF_MASK;
1387 if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
1388 gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
1389 gvt_dbg_el("ctx head %x real head %lx\n", head,
1390 last_workload->rb_tail);
1392 * cannot use guest context head pointer here,
1393 * as it might not be updated at this time
1395 head = last_workload->rb_tail;
1398 gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
1400 /* record some ring buffer register values for scan and shadow */
1401 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1402 RING_CTX_OFF(rb_start.val), &start, 4);
1403 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1404 RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1405 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1406 RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1408 workload = alloc_workload(vgpu);
1409 if (IS_ERR(workload))
1412 workload->ring_id = ring_id;
1413 workload->ctx_desc = *desc;
1414 workload->ring_context_gpa = ring_context_gpa;
1415 workload->rb_head = head;
1416 workload->rb_tail = tail;
1417 workload->rb_start = start;
1418 workload->rb_ctl = ctl;
1420 if (ring_id == RCS) {
1421 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1422 RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1423 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1424 RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1426 workload->wa_ctx.indirect_ctx.guest_gma =
1427 indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1428 workload->wa_ctx.indirect_ctx.size =
1429 (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1431 workload->wa_ctx.per_ctx.guest_gma =
1432 per_ctx & PER_CTX_ADDR_MASK;
1433 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1436 gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1437 workload, ring_id, head, tail, start, ctl);
1439 ret = prepare_mm(workload);
1441 kmem_cache_free(s->workloads, workload);
1442 return ERR_PTR(ret);
1445 /* Only scan and shadow the first workload in the queue
1446 * as there is only one pre-allocated buf-obj for shadow.
1448 if (list_empty(workload_q_head(vgpu, ring_id))) {
1449 intel_runtime_pm_get(dev_priv);
1450 mutex_lock(&dev_priv->drm.struct_mutex);
1451 ret = intel_gvt_scan_and_shadow_workload(workload);
1452 mutex_unlock(&dev_priv->drm.struct_mutex);
1453 intel_runtime_pm_put_unchecked(dev_priv);
1456 if (ret && (vgpu_is_vm_unhealthy(ret))) {
1457 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1458 intel_vgpu_destroy_workload(workload);
1459 return ERR_PTR(ret);
1466 * intel_vgpu_queue_workload - Qeue a vGPU workload
1467 * @workload: the workload to queue in
1469 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1471 list_add_tail(&workload->list,
1472 workload_q_head(workload->vgpu, workload->ring_id));
1473 intel_gvt_kick_schedule(workload->vgpu->gvt);
1474 wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);