drivers/gpu/drm/i915/gvt/mmio_context.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eddie Dong <eddie.dong@intel.com>
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *
  27  * Contributors:
  28  *    Zhi Wang <zhi.a.wang@intel.com>
  29  *    Changbin Du <changbin.du@intel.com>
  30  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Bing Niu <bing.niu@intel.com>
  33  *
  34  */
  35
  36 #include "i915_drv.h"
  37 #include "gvt.h"
  38 #include "trace.h"
  39
  40 #define GEN9_MOCS_SIZE          64
  41
  42 /* Raw offset is appened to each line for convenience. */
  43 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
  44         {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
  45         {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
  46         {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
  47         {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
  48         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
  49         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
  50         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
  51         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
  52         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
  53         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
  54         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
  55         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
  56         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
  57         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
  58         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
  59         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
  60         {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
  61         {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
  62         {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
  63         {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
  64         {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
  65         {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
  66
  67         {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
  68         {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
  69         {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
  70         {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
  71         {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
  72         {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
  73 };
  74
  75 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
  76         {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
  77         {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
  78         {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
  79         {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
  80         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
  81         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
  82         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
  83         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
  84         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
  85         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
  86         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
  87         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
  88         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
  89         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
  90         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
  91         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
  92         {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
  93         {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
  94         {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
  95         {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
  96         {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
  97         {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
  98
  99         {RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
 100         {RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
 101         {RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
 102         {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
 103         {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
 104         {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
 105         {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
 106         {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
 107         {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
 108         {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
 109         {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
 110         {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
 111         {RCS0, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
 112         {RCS0, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
 113         {RCS0, TRNULLDETCT, 0, false}, /* 0x4de8 */
 114         {RCS0, TRINVTILEDETCT, 0, false}, /* 0x4dec */
 115         {RCS0, TRVADR, 0, false}, /* 0x4df0 */
 116         {RCS0, TRTTE, 0, false}, /* 0x4df4 */
 117
 118         {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
 119         {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
 120         {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
 121         {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
 122         {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
 123
 124         {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
 125
 126         {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
 127
 128         {RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
 129         {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
 130         {RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
 131         {RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
 132
 133         {RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
 134         {RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
 135
 136         {RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
 137         {RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
 138         {RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
 139         {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
 140 };
 141
 142 static struct {
 143         bool initialized;
 144         u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
 145         u32 l3cc_table[GEN9_MOCS_SIZE / 2];
 146 } gen9_render_mocs;
 147
 148 static void load_render_mocs(struct drm_i915_private *dev_priv)
 149 {
 150         i915_reg_t offset;
 151         u32 regs[] = {
 152                 [RCS0]  = 0xc800,
 153                 [VCS0]  = 0xc900,
 154                 [VCS1]  = 0xca00,
 155                 [BCS0]  = 0xcc00,
 156                 [VECS0] = 0xcb00,
 157         };
 158         int ring_id, i;
 159
 160         for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
 161                 if (!HAS_ENGINE(dev_priv, ring_id))
 162                         continue;
 163                 offset.reg = regs[ring_id];
 164                 for (i = 0; i < GEN9_MOCS_SIZE; i++) {
 165                         gen9_render_mocs.control_table[ring_id][i] =
 166                                 I915_READ_FW(offset);
 167                         offset.reg += 4;
 168                 }
 169         }
 170
 171         offset.reg = 0xb020;
 172         for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
 173                 gen9_render_mocs.l3cc_table[i] =
 174                         I915_READ_FW(offset);
 175                 offset.reg += 4;
 176         }
 177         gen9_render_mocs.initialized = true;
 178 }
 179
 180 static int
 181 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
 182                                  struct i915_request *req)
 183 {
 184         u32 *cs;
 185         int ret;
 186         struct engine_mmio *mmio;
 187         struct intel_gvt *gvt = vgpu->gvt;
 188         int ring_id = req->engine->id;
 189         int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];
 190
 191         if (count == 0)
 192                 return 0;
 193
 194         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 195         if (ret)
 196                 return ret;
 197
 198         cs = intel_ring_begin(req, count * 2 + 2);
 199         if (IS_ERR(cs))
 200                 return PTR_ERR(cs);
 201
 202         *cs++ = MI_LOAD_REGISTER_IMM(count);
 203         for (mmio = gvt->engine_mmio_list.mmio;
 204              i915_mmio_reg_valid(mmio->reg); mmio++) {
 205                 if (mmio->ring_id != ring_id ||
 206                     !mmio->in_context)
 207                         continue;
 208
 209                 *cs++ = i915_mmio_reg_offset(mmio->reg);
 210                 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
 211                                 (mmio->mask << 16);
 212                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
 213                               *(cs-2), *(cs-1), vgpu->id, ring_id);
 214         }
 215
 216         *cs++ = MI_NOOP;
 217         intel_ring_advance(req, cs);
 218
 219         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 220         if (ret)
 221                 return ret;
 222
 223         return 0;
 224 }
 225
 226 static int
 227 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu,
 228                                         struct i915_request *req)
 229 {
 230         unsigned int index;
 231         u32 *cs;
 232
 233         cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);
 234         if (IS_ERR(cs))
 235                 return PTR_ERR(cs);
 236
 237         *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
 238
 239         for (index = 0; index < GEN9_MOCS_SIZE; index++) {
 240                 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
 241                 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));
 242                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
 243                               *(cs-2), *(cs-1), vgpu->id, req->engine->id);
 244
 245         }
 246
 247         *cs++ = MI_NOOP;
 248         intel_ring_advance(req, cs);
 249
 250         return 0;
 251 }
 252
 253 static int
 254 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu,
 255                                      struct i915_request *req)
 256 {
 257         unsigned int index;
 258         u32 *cs;
 259
 260         cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);
 261         if (IS_ERR(cs))
 262                 return PTR_ERR(cs);
 263
 264         *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
 265
 266         for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
 267                 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
 268                 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));
 269                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
 270                               *(cs-2), *(cs-1), vgpu->id, req->engine->id);
 271
 272         }
 273
 274         *cs++ = MI_NOOP;
 275         intel_ring_advance(req, cs);
 276
 277         return 0;
 278 }
 279
 280 /*
 281  * Use lri command to initialize the mmio which is in context state image for
 282  * inhibit context, it contains tracked engine mmio, render_mocs and
 283  * render_mocs_l3cc.
 284  */
 285 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
 286                                        struct i915_request *req)
 287 {
 288         int ret;
 289         u32 *cs;
 290
 291         cs = intel_ring_begin(req, 2);
 292         if (IS_ERR(cs))
 293                 return PTR_ERR(cs);
 294
 295         *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
 296         *cs++ = MI_NOOP;
 297         intel_ring_advance(req, cs);
 298
 299         ret = restore_context_mmio_for_inhibit(vgpu, req);
 300         if (ret)
 301                 goto out;
 302
 303         /* no MOCS register in context except render engine */
 304         if (req->engine->id != RCS0)
 305                 goto out;
 306
 307         ret = restore_render_mocs_control_for_inhibit(vgpu, req);
 308         if (ret)
 309                 goto out;
 310
 311         ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req);
 312         if (ret)
 313                 goto out;
 314
 315 out:
 316         cs = intel_ring_begin(req, 2);
 317         if (IS_ERR(cs))
 318                 return PTR_ERR(cs);
 319
 320         *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
 321         *cs++ = MI_NOOP;
 322         intel_ring_advance(req, cs);
 323
 324         return ret;
 325 }
 326
 327 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
 328 {
 329         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 330         struct intel_uncore *uncore = &dev_priv->uncore;
 331         struct intel_vgpu_submission *s = &vgpu->submission;
 332         enum forcewake_domains fw;
 333         i915_reg_t reg;
 334         u32 regs[] = {
 335                 [RCS0]  = 0x4260,
 336                 [VCS0]  = 0x4264,
 337                 [VCS1]  = 0x4268,
 338                 [BCS0]  = 0x426c,
 339                 [VECS0] = 0x4270,
 340         };
 341
 342         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
 343                 return;
 344
 345         if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
 346                 return;
 347
 348         reg = _MMIO(regs[ring_id]);
 349
 350         /* WaForceWakeRenderDuringMmioTLBInvalidate:skl
 351          * we need to put a forcewake when invalidating RCS TLB caches,
 352          * otherwise device can go to RC6 state and interrupt invalidation
 353          * process
 354          */
 355         fw = intel_uncore_forcewake_for_reg(uncore, reg,
 356                                             FW_REG_READ | FW_REG_WRITE);
 357         if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
 358                 fw |= FORCEWAKE_RENDER;
 359
 360         intel_uncore_forcewake_get(uncore, fw);
 361
 362         intel_uncore_write_fw(uncore, reg, 0x1);
 363
 364         if (wait_for_atomic((intel_uncore_read_fw(uncore, reg) == 0), 50))
 365                 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
 366         else
 367                 vgpu_vreg_t(vgpu, reg) = 0;
 368
 369         intel_uncore_forcewake_put(uncore, fw);
 370
 371         gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
 372 }
 373
 374 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
 375                         int ring_id)
 376 {
 377         struct drm_i915_private *dev_priv;
 378         i915_reg_t offset, l3_offset;
 379         u32 old_v, new_v;
 380
 381         u32 regs[] = {
 382                 [RCS0]  = 0xc800,
 383                 [VCS0]  = 0xc900,
 384                 [VCS1]  = 0xca00,
 385                 [BCS0]  = 0xcc00,
 386                 [VECS0] = 0xcb00,
 387         };
 388         int i;
 389
 390         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
 391         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
 392                 return;
 393
 394         if (ring_id == RCS0 &&
 395             (IS_KABYLAKE(dev_priv) ||
 396              IS_BROXTON(dev_priv) ||
 397              IS_COFFEELAKE(dev_priv)))
 398                 return;
 399
 400         if (!pre && !gen9_render_mocs.initialized)
 401                 load_render_mocs(dev_priv);
 402
 403         offset.reg = regs[ring_id];
 404         for (i = 0; i < GEN9_MOCS_SIZE; i++) {
 405                 if (pre)
 406                         old_v = vgpu_vreg_t(pre, offset);
 407                 else
 408                         old_v = gen9_render_mocs.control_table[ring_id][i];
 409                 if (next)
 410                         new_v = vgpu_vreg_t(next, offset);
 411                 else
 412                         new_v = gen9_render_mocs.control_table[ring_id][i];
 413
 414                 if (old_v != new_v)
 415                         I915_WRITE_FW(offset, new_v);
 416
 417                 offset.reg += 4;
 418         }
 419
 420         if (ring_id == RCS0) {
 421                 l3_offset.reg = 0xb020;
 422                 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
 423                         if (pre)
 424                                 old_v = vgpu_vreg_t(pre, l3_offset);
 425                         else
 426                                 old_v = gen9_render_mocs.l3cc_table[i];
 427                         if (next)
 428                                 new_v = vgpu_vreg_t(next, l3_offset);
 429                         else
 430                                 new_v = gen9_render_mocs.l3cc_table[i];
 431
 432                         if (old_v != new_v)
 433                                 I915_WRITE_FW(l3_offset, new_v);
 434
 435                         l3_offset.reg += 4;
 436                 }
 437         }
 438 }
 439
 440 #define CTX_CONTEXT_CONTROL_VAL 0x03
 441
 442 bool is_inhibit_context(struct intel_context *ce)
 443 {
 444         const u32 *reg_state = ce->lrc_reg_state;
 445         u32 inhibit_mask =
 446                 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
 447
 448         return inhibit_mask ==
 449                 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask);
 450 }
 451
 452 /* Switch ring mmio values (context). */
 453 static void switch_mmio(struct intel_vgpu *pre,
 454                         struct intel_vgpu *next,
 455                         int ring_id)
 456 {
 457         struct drm_i915_private *dev_priv;
 458         struct intel_vgpu_submission *s;
 459         struct engine_mmio *mmio;
 460         u32 old_v, new_v;
 461
 462         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
 463         if (INTEL_GEN(dev_priv) >= 9)
 464                 switch_mocs(pre, next, ring_id);
 465
 466         for (mmio = dev_priv->gvt->engine_mmio_list.mmio;
 467              i915_mmio_reg_valid(mmio->reg); mmio++) {
 468                 if (mmio->ring_id != ring_id)
 469                         continue;
 470                 /*
 471                  * No need to do save or restore of the mmio which is in context
 472                  * state image on kabylake, it's initialized by lri command and
 473                  * save or restore with context together.
 474                  */
 475                 if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)
 476                         || IS_COFFEELAKE(dev_priv)) && mmio->in_context)
 477                         continue;
 478
 479                 // save
 480                 if (pre) {
 481                         vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
 482                         if (mmio->mask)
 483                                 vgpu_vreg_t(pre, mmio->reg) &=
 484                                                 ~(mmio->mask << 16);
 485                         old_v = vgpu_vreg_t(pre, mmio->reg);
 486                 } else
 487                         old_v = mmio->value = I915_READ_FW(mmio->reg);
 488
 489                 // restore
 490                 if (next) {
 491                         s = &next->submission;
 492                         /*
 493                          * No need to restore the mmio which is in context state
 494                          * image if it's not inhibit context, it will restore
 495                          * itself.
 496                          */
 497                         if (mmio->in_context &&
 498                             !is_inhibit_context(intel_context_lookup(s->shadow_ctx,
 499                                                                      dev_priv->engine[ring_id])))
 500                                 continue;
 501
 502                         if (mmio->mask)
 503                                 new_v = vgpu_vreg_t(next, mmio->reg) |
 504                                                         (mmio->mask << 16);
 505                         else
 506                                 new_v = vgpu_vreg_t(next, mmio->reg);
 507                 } else {
 508                         if (mmio->in_context)
 509                                 continue;
 510                         if (mmio->mask)
 511                                 new_v = mmio->value | (mmio->mask << 16);
 512                         else
 513                                 new_v = mmio->value;
 514                 }
 515
 516                 I915_WRITE_FW(mmio->reg, new_v);
 517
 518                 trace_render_mmio(pre ? pre->id : 0,
 519                                   next ? next->id : 0,
 520                                   "switch",
 521                                   i915_mmio_reg_offset(mmio->reg),
 522                                   old_v, new_v);
 523         }
 524
 525         if (next)
 526                 handle_tlb_pending_event(next, ring_id);
 527 }
 528
 529 /**
 530  * intel_gvt_switch_render_mmio - switch mmio context of specific engine
 531  * @pre: the last vGPU that own the engine
 532  * @next: the vGPU to switch to
 533  * @ring_id: specify the engine
 534  *
 535  * If pre is null indicates that host own the engine. If next is null
 536  * indicates that we are switching to host workload.
 537  */
 538 void intel_gvt_switch_mmio(struct intel_vgpu *pre,
 539                            struct intel_vgpu *next, int ring_id)
 540 {
 541         struct drm_i915_private *dev_priv;
 542
 543         if (WARN_ON(!pre && !next))
 544                 return;
 545
 546         gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
 547                        pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
 548
 549         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
 550
 551         /**
 552          * We are using raw mmio access wrapper to improve the
 553          * performace for batch mmio read/write, so we need
 554          * handle forcewake mannually.
 555          */
 556         intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
 557         switch_mmio(pre, next, ring_id);
 558         intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 559 }
 560
 561 /**
 562  * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
 563  * @gvt: GVT device
 564  *
 565  */
 566 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
 567 {
 568         struct engine_mmio *mmio;
 569
 570         if (INTEL_GEN(gvt->dev_priv) >= 9)
 571                 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
 572         else
 573                 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;
 574
 575         for (mmio = gvt->engine_mmio_list.mmio;
 576              i915_mmio_reg_valid(mmio->reg); mmio++) {
 577                 if (mmio->in_context) {
 578                         gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
 579                         intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
 580                 }
 581         }
 582 }