2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Kevin Tian <kevin.tian@intel.com>
29 * Tina Zhang <tina.zhang@intel.com>
30 * Min He <min.he@intel.com>
31 * Niu Bing <bing.niu@intel.com>
32 * Zhi Wang <zhi.a.wang@intel.com>
40 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
44 * Zero on success, negative error code if failed
46 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
48 u64 gttmmio_gpa = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0) &
50 return gpa - gttmmio_gpa;
53 #define reg_is_mmio(gvt, reg) \
54 (reg >= 0 && reg < gvt->device_info.mmio_size)
56 #define reg_is_gtt(gvt, reg) \
57 (reg >= gvt->device_info.gtt_start_offset \
58 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
60 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
61 void *p_data, unsigned int bytes, bool read)
63 struct intel_gvt *gvt = NULL;
65 unsigned int offset = 0;
71 mutex_lock(&gvt->lock);
72 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
73 if (reg_is_mmio(gvt, offset)) {
75 intel_vgpu_default_mmio_read(vgpu, offset, p_data,
78 intel_vgpu_default_mmio_write(vgpu, offset, p_data,
80 } else if (reg_is_gtt(gvt, offset) &&
81 vgpu->gtt.ggtt_mm->virtual_page_table) {
82 offset -= gvt->device_info.gtt_start_offset;
83 pt = vgpu->gtt.ggtt_mm->virtual_page_table + offset;
85 memcpy(p_data, pt, bytes);
87 memcpy(pt, p_data, bytes);
89 } else if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
90 struct intel_vgpu_guest_page *gp;
92 /* Since we enter the failsafe mode early during guest boot,
93 * guest may not have chance to set up its ppgtt table, so
94 * there should not be any wp pages for guest. Keep the wp
95 * related code here in case we need to handle it in furture.
97 gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
99 /* remove write protection to prevent furture traps */
100 intel_vgpu_clean_guest_page(vgpu, gp);
102 intel_gvt_hypervisor_read_gpa(vgpu, pa,
105 intel_gvt_hypervisor_write_gpa(vgpu, pa,
109 mutex_unlock(&gvt->lock);
113 * intel_vgpu_emulate_mmio_read - emulate MMIO read
115 * @pa: guest physical address
116 * @p_data: data return buffer
117 * @bytes: access data length
120 * Zero on success, negative error code if failed
122 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
123 void *p_data, unsigned int bytes)
125 struct intel_gvt *gvt = vgpu->gvt;
126 unsigned int offset = 0;
130 if (vgpu->failsafe) {
131 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
134 mutex_lock(&gvt->lock);
136 if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
137 struct intel_vgpu_guest_page *gp;
139 gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
141 ret = intel_gvt_hypervisor_read_gpa(vgpu, pa,
144 gvt_vgpu_err("guest page read error %d, "
145 "gfn 0x%lx, pa 0x%llx, var 0x%x, len %d\n",
146 ret, gp->gfn, pa, *(u32 *)p_data,
149 mutex_unlock(&gvt->lock);
154 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
156 if (WARN_ON(bytes > 8))
159 if (reg_is_gtt(gvt, offset)) {
160 if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
162 if (WARN_ON(bytes != 4 && bytes != 8))
164 if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
167 ret = intel_vgpu_emulate_gtt_mmio_read(vgpu, offset,
171 mutex_unlock(&gvt->lock);
175 if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
176 ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
177 mutex_unlock(&gvt->lock);
181 if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
184 if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
185 if (WARN_ON(!IS_ALIGNED(offset, bytes)))
189 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
193 intel_gvt_mmio_set_accessed(gvt, offset);
194 mutex_unlock(&gvt->lock);
197 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
199 mutex_unlock(&gvt->lock);
204 * intel_vgpu_emulate_mmio_write - emulate MMIO write
206 * @pa: guest physical address
207 * @p_data: write data buffer
208 * @bytes: access data length
211 * Zero on success, negative error code if failed
213 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
214 void *p_data, unsigned int bytes)
216 struct intel_gvt *gvt = vgpu->gvt;
217 unsigned int offset = 0;
220 if (vgpu->failsafe) {
221 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
225 mutex_lock(&gvt->lock);
227 if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
228 struct intel_vgpu_guest_page *gp;
230 gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
232 ret = gp->handler(gp, pa, p_data, bytes);
234 gvt_err("guest page write error %d, "
235 "gfn 0x%lx, pa 0x%llx, "
236 "var 0x%x, len %d\n",
238 *(u32 *)p_data, bytes);
240 mutex_unlock(&gvt->lock);
245 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
247 if (WARN_ON(bytes > 8))
250 if (reg_is_gtt(gvt, offset)) {
251 if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
253 if (WARN_ON(bytes != 4 && bytes != 8))
255 if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
258 ret = intel_vgpu_emulate_gtt_mmio_write(vgpu, offset,
262 mutex_unlock(&gvt->lock);
266 if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
267 ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
268 mutex_unlock(&gvt->lock);
272 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
276 intel_gvt_mmio_set_accessed(gvt, offset);
277 mutex_unlock(&gvt->lock);
280 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
282 mutex_unlock(&gvt->lock);
288 * intel_vgpu_reset_mmio - reset virtual MMIO space
292 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
294 struct intel_gvt *gvt = vgpu->gvt;
295 const struct intel_gvt_device_info *info = &gvt->device_info;
296 void *mmio = gvt->firmware.mmio;
299 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
300 memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
302 vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
304 /* set the bit 0:2(Core C-State ) to C0 */
305 vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0;
307 vgpu->mmio.disable_warn_untrack = false;
309 #define GVT_GEN8_MMIO_RESET_OFFSET (0x44200)
310 /* only reset the engine related, so starting with 0x44200
311 * interrupt include DE,display mmio related will not be
314 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
315 memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
321 * intel_vgpu_init_mmio - init MMIO space
325 * Zero on success, negative error code if failed
327 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
329 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
331 vgpu->mmio.vreg = vzalloc(info->mmio_size * 2);
332 if (!vgpu->mmio.vreg)
335 vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
337 intel_vgpu_reset_mmio(vgpu, true);
343 * intel_vgpu_clean_mmio - clean MMIO space
347 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
349 vfree(vgpu->mmio.vreg);
350 vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;