2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Kevin Tian <kevin.tian@intel.com>
29 * Tina Zhang <tina.zhang@intel.com>
30 * Min He <min.he@intel.com>
31 * Niu Bing <bing.niu@intel.com>
32 * Zhi Wang <zhi.a.wang@intel.com>
40 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
44 * Zero on success, negative error code if failed
46 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
48 u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
49 return gpa - gttmmio_gpa;
52 #define reg_is_mmio(gvt, reg) \
53 (reg >= 0 && reg < gvt->device_info.mmio_size)
55 #define reg_is_gtt(gvt, reg) \
56 (reg >= gvt->device_info.gtt_start_offset \
57 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
59 static bool vgpu_gpa_is_aperture(struct intel_vgpu *vgpu, uint64_t gpa)
61 u64 aperture_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_2);
62 u64 aperture_sz = vgpu_aperture_sz(vgpu);
64 return gpa >= aperture_gpa && gpa < aperture_gpa + aperture_sz;
67 static int vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t gpa,
68 void *pdata, unsigned int size, bool is_read)
70 u64 aperture_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_2);
71 u64 offset = gpa - aperture_gpa;
73 if (!vgpu_gpa_is_aperture(vgpu, gpa + size - 1)) {
74 gvt_vgpu_err("Aperture rw out of range, offset %llx, size %d\n",
79 if (!vgpu->gm.aperture_va) {
80 gvt_vgpu_err("BAR is not enabled\n");
85 memcpy(pdata, vgpu->gm.aperture_va + offset, size);
87 memcpy(vgpu->gm.aperture_va + offset, pdata, size);
91 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
92 void *p_data, unsigned int bytes, bool read)
94 struct intel_gvt *gvt = NULL;
96 unsigned int offset = 0;
102 mutex_lock(&gvt->lock);
103 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
104 if (reg_is_mmio(gvt, offset)) {
106 intel_vgpu_default_mmio_read(vgpu, offset, p_data,
109 intel_vgpu_default_mmio_write(vgpu, offset, p_data,
111 } else if (reg_is_gtt(gvt, offset) &&
112 vgpu->gtt.ggtt_mm->virtual_page_table) {
113 offset -= gvt->device_info.gtt_start_offset;
114 pt = vgpu->gtt.ggtt_mm->virtual_page_table + offset;
116 memcpy(p_data, pt, bytes);
118 memcpy(pt, p_data, bytes);
120 } else if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
121 struct intel_vgpu_guest_page *gp;
123 /* Since we enter the failsafe mode early during guest boot,
124 * guest may not have chance to set up its ppgtt table, so
125 * there should not be any wp pages for guest. Keep the wp
126 * related code here in case we need to handle it in furture.
128 gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
130 /* remove write protection to prevent furture traps */
131 intel_vgpu_clean_guest_page(vgpu, gp);
133 intel_gvt_hypervisor_read_gpa(vgpu, pa,
136 intel_gvt_hypervisor_write_gpa(vgpu, pa,
140 mutex_unlock(&gvt->lock);
144 * intel_vgpu_emulate_mmio_read - emulate MMIO read
146 * @pa: guest physical address
147 * @p_data: data return buffer
148 * @bytes: access data length
151 * Zero on success, negative error code if failed
153 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
154 void *p_data, unsigned int bytes)
156 struct intel_gvt *gvt = vgpu->gvt;
157 unsigned int offset = 0;
161 if (vgpu->failsafe) {
162 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
165 mutex_lock(&gvt->lock);
167 if (vgpu_gpa_is_aperture(vgpu, pa)) {
168 ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, true);
169 mutex_unlock(&gvt->lock);
173 if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
174 struct intel_vgpu_guest_page *gp;
176 gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
178 ret = intel_gvt_hypervisor_read_gpa(vgpu, pa,
181 gvt_vgpu_err("guest page read error %d, "
182 "gfn 0x%lx, pa 0x%llx, var 0x%x, len %d\n",
183 ret, gp->gfn, pa, *(u32 *)p_data,
186 mutex_unlock(&gvt->lock);
191 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
193 if (WARN_ON(bytes > 8))
196 if (reg_is_gtt(gvt, offset)) {
197 if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
199 if (WARN_ON(bytes != 4 && bytes != 8))
201 if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
204 ret = intel_vgpu_emulate_gtt_mmio_read(vgpu, offset,
208 mutex_unlock(&gvt->lock);
212 if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
213 ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
214 mutex_unlock(&gvt->lock);
218 if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
221 if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
222 if (WARN_ON(!IS_ALIGNED(offset, bytes)))
226 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
230 intel_gvt_mmio_set_accessed(gvt, offset);
231 mutex_unlock(&gvt->lock);
234 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
236 mutex_unlock(&gvt->lock);
241 * intel_vgpu_emulate_mmio_write - emulate MMIO write
243 * @pa: guest physical address
244 * @p_data: write data buffer
245 * @bytes: access data length
248 * Zero on success, negative error code if failed
250 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
251 void *p_data, unsigned int bytes)
253 struct intel_gvt *gvt = vgpu->gvt;
254 unsigned int offset = 0;
257 if (vgpu->failsafe) {
258 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
262 mutex_lock(&gvt->lock);
264 if (vgpu_gpa_is_aperture(vgpu, pa)) {
265 ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, false);
266 mutex_unlock(&gvt->lock);
270 if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
271 struct intel_vgpu_guest_page *gp;
273 gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
275 ret = gp->handler(gp, pa, p_data, bytes);
277 gvt_err("guest page write error %d, "
278 "gfn 0x%lx, pa 0x%llx, "
279 "var 0x%x, len %d\n",
281 *(u32 *)p_data, bytes);
283 mutex_unlock(&gvt->lock);
288 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
290 if (WARN_ON(bytes > 8))
293 if (reg_is_gtt(gvt, offset)) {
294 if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
296 if (WARN_ON(bytes != 4 && bytes != 8))
298 if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
301 ret = intel_vgpu_emulate_gtt_mmio_write(vgpu, offset,
305 mutex_unlock(&gvt->lock);
309 if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
310 ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
311 mutex_unlock(&gvt->lock);
315 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
319 intel_gvt_mmio_set_accessed(gvt, offset);
320 mutex_unlock(&gvt->lock);
323 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
325 mutex_unlock(&gvt->lock);
331 * intel_vgpu_reset_mmio - reset virtual MMIO space
335 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
337 struct intel_gvt *gvt = vgpu->gvt;
338 const struct intel_gvt_device_info *info = &gvt->device_info;
339 void *mmio = gvt->firmware.mmio;
342 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
343 memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
345 vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
347 /* set the bit 0:2(Core C-State ) to C0 */
348 vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0;
350 vgpu->mmio.disable_warn_untrack = false;
352 #define GVT_GEN8_MMIO_RESET_OFFSET (0x44200)
353 /* only reset the engine related, so starting with 0x44200
354 * interrupt include DE,display mmio related will not be
357 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
358 memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
364 * intel_vgpu_init_mmio - init MMIO space
368 * Zero on success, negative error code if failed
370 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
372 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
374 vgpu->mmio.vreg = vzalloc(info->mmio_size * 2);
375 if (!vgpu->mmio.vreg)
378 vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
380 intel_vgpu_reset_mmio(vgpu, true);
386 * intel_vgpu_clean_mmio - clean MMIO space
390 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
392 vfree(vgpu->mmio.vreg);
393 vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;