4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Zhi Wang <zhi.a.wang@intel.com>
27 * Zhenyu Wang <zhenyuw@linux.intel.com>
28 * Xiao Zheng <xiao.zheng@intel.com>
31 * Min He <min.he@intel.com>
32 * Bing Niu <bing.niu@intel.com>
38 #include "i915_pvinfo.h"
41 #if defined(VERBOSE_DEBUG)
42 #define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
44 #define gvt_vdbg_mm(fmt, args...)
47 static bool enable_out_of_sync = false;
48 static int preallocated_oos_pages = 8192;
51 * validate a gm address and related range size,
52 * translate it to host gm address
54 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
57 return vgpu_gmadr_is_valid(vgpu, addr);
59 if (vgpu_gmadr_is_aperture(vgpu, addr) &&
60 vgpu_gmadr_is_aperture(vgpu, addr + size - 1))
62 else if (vgpu_gmadr_is_hidden(vgpu, addr) &&
63 vgpu_gmadr_is_hidden(vgpu, addr + size - 1))
66 gvt_dbg_mm("Invalid ggtt range at 0x%llx, size: 0x%x\n",
71 /* translate a guest gmadr to host gmadr */
72 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
74 if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
75 "invalid guest gmadr %llx\n", g_addr))
78 if (vgpu_gmadr_is_aperture(vgpu, g_addr))
79 *h_addr = vgpu_aperture_gmadr_base(vgpu)
80 + (g_addr - vgpu_aperture_offset(vgpu));
82 *h_addr = vgpu_hidden_gmadr_base(vgpu)
83 + (g_addr - vgpu_hidden_offset(vgpu));
87 /* translate a host gmadr to guest gmadr */
88 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
90 if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
91 "invalid host gmadr %llx\n", h_addr))
94 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
95 *g_addr = vgpu_aperture_gmadr_base(vgpu)
96 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
98 *g_addr = vgpu_hidden_gmadr_base(vgpu)
99 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
103 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
104 unsigned long *h_index)
109 ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
114 *h_index = h_addr >> I915_GTT_PAGE_SHIFT;
118 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
119 unsigned long *g_index)
124 ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
129 *g_index = g_addr >> I915_GTT_PAGE_SHIFT;
133 #define gtt_type_is_entry(type) \
134 (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
135 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
136 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
138 #define gtt_type_is_pt(type) \
139 (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
141 #define gtt_type_is_pte_pt(type) \
142 (type == GTT_TYPE_PPGTT_PTE_PT)
144 #define gtt_type_is_root_pointer(type) \
145 (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
147 #define gtt_init_entry(e, t, p, v) do { \
150 memcpy(&(e)->val64, &v, sizeof(v)); \
154 * Mappings between GTT_TYPE* enumerations.
155 * Following information can be found according to the given type:
156 * - type of next level page table
157 * - type of entry inside this level page table
158 * - type of entry with PSE set
160 * If the given type doesn't have such a kind of information,
161 * e.g. give a l4 root entry type, then request to get its PSE type,
162 * give a PTE page table type, then request to get its next level page
163 * table type, as we know l4 root entry doesn't have a PSE bit,
164 * and a PTE page table doesn't have a next level page table type,
165 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
169 struct gtt_type_table_entry {
176 #define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
178 .entry_type = e_type, \
179 .pt_type = cpt_type, \
180 .next_pt_type = npt_type, \
181 .pse_entry_type = pse_type, \
184 static struct gtt_type_table_entry gtt_type_table[] = {
185 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
186 GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
188 GTT_TYPE_PPGTT_PML4_PT,
190 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
191 GTT_TYPE_PPGTT_PML4_ENTRY,
192 GTT_TYPE_PPGTT_PML4_PT,
193 GTT_TYPE_PPGTT_PDP_PT,
195 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
196 GTT_TYPE_PPGTT_PML4_ENTRY,
197 GTT_TYPE_PPGTT_PML4_PT,
198 GTT_TYPE_PPGTT_PDP_PT,
200 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
201 GTT_TYPE_PPGTT_PDP_ENTRY,
202 GTT_TYPE_PPGTT_PDP_PT,
203 GTT_TYPE_PPGTT_PDE_PT,
204 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
205 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
206 GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
208 GTT_TYPE_PPGTT_PDE_PT,
209 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
210 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
211 GTT_TYPE_PPGTT_PDP_ENTRY,
212 GTT_TYPE_PPGTT_PDP_PT,
213 GTT_TYPE_PPGTT_PDE_PT,
214 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
215 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
216 GTT_TYPE_PPGTT_PDE_ENTRY,
217 GTT_TYPE_PPGTT_PDE_PT,
218 GTT_TYPE_PPGTT_PTE_PT,
219 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
220 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
221 GTT_TYPE_PPGTT_PDE_ENTRY,
222 GTT_TYPE_PPGTT_PDE_PT,
223 GTT_TYPE_PPGTT_PTE_PT,
224 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
225 /* We take IPS bit as 'PSE' for PTE level. */
226 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
227 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
228 GTT_TYPE_PPGTT_PTE_PT,
230 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
231 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
232 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
233 GTT_TYPE_PPGTT_PTE_PT,
235 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
236 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
237 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
238 GTT_TYPE_PPGTT_PTE_PT,
240 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
241 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
242 GTT_TYPE_PPGTT_PDE_ENTRY,
243 GTT_TYPE_PPGTT_PDE_PT,
245 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
246 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
247 GTT_TYPE_PPGTT_PDP_ENTRY,
248 GTT_TYPE_PPGTT_PDP_PT,
250 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
251 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
258 static inline int get_next_pt_type(int type)
260 return gtt_type_table[type].next_pt_type;
263 static inline int get_pt_type(int type)
265 return gtt_type_table[type].pt_type;
268 static inline int get_entry_type(int type)
270 return gtt_type_table[type].entry_type;
273 static inline int get_pse_type(int type)
275 return gtt_type_table[type].pse_entry_type;
278 static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
280 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
285 static void ggtt_invalidate(struct drm_i915_private *dev_priv)
287 mmio_hw_access_pre(dev_priv);
288 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
289 mmio_hw_access_post(dev_priv);
292 static void write_pte64(struct drm_i915_private *dev_priv,
293 unsigned long index, u64 pte)
295 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
300 static inline int gtt_get_entry64(void *pt,
301 struct intel_gvt_gtt_entry *e,
302 unsigned long index, bool hypervisor_access, unsigned long gpa,
303 struct intel_vgpu *vgpu)
305 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
308 if (WARN_ON(info->gtt_entry_size != 8))
311 if (hypervisor_access) {
312 ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
313 (index << info->gtt_entry_size_shift),
318 e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
320 e->val64 = *((u64 *)pt + index);
325 static inline int gtt_set_entry64(void *pt,
326 struct intel_gvt_gtt_entry *e,
327 unsigned long index, bool hypervisor_access, unsigned long gpa,
328 struct intel_vgpu *vgpu)
330 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
333 if (WARN_ON(info->gtt_entry_size != 8))
336 if (hypervisor_access) {
337 ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
338 (index << info->gtt_entry_size_shift),
343 write_pte64(vgpu->gvt->dev_priv, index, e->val64);
345 *((u64 *)pt + index) = e->val64;
352 #define ADDR_1G_MASK GENMASK_ULL(GTT_HAW - 1, 30)
353 #define ADDR_2M_MASK GENMASK_ULL(GTT_HAW - 1, 21)
354 #define ADDR_64K_MASK GENMASK_ULL(GTT_HAW - 1, 16)
355 #define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12)
357 #define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)
358 #define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
360 #define GTT_64K_PTE_STRIDE 16
362 static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
366 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
367 pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
368 else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
369 pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
370 else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
371 pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
373 pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
377 static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
379 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
380 e->val64 &= ~ADDR_1G_MASK;
381 pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
382 } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
383 e->val64 &= ~ADDR_2M_MASK;
384 pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
385 } else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
386 e->val64 &= ~ADDR_64K_MASK;
387 pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
389 e->val64 &= ~ADDR_4K_MASK;
390 pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
393 e->val64 |= (pfn << PAGE_SHIFT);
396 static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
398 return !!(e->val64 & _PAGE_PSE);
401 static void gen8_gtt_clear_pse(struct intel_gvt_gtt_entry *e)
403 if (gen8_gtt_test_pse(e)) {
405 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
406 e->val64 &= ~_PAGE_PSE;
407 e->type = GTT_TYPE_PPGTT_PDE_ENTRY;
409 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
410 e->type = GTT_TYPE_PPGTT_PDP_ENTRY;
411 e->val64 &= ~_PAGE_PSE;
419 static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
421 if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
424 return !!(e->val64 & GEN8_PDE_IPS_64K);
427 static void gen8_gtt_clear_ips(struct intel_gvt_gtt_entry *e)
429 if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
432 e->val64 &= ~GEN8_PDE_IPS_64K;
435 static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
438 * i915 writes PDP root pointer registers without present bit,
439 * it also works, so we need to treat root pointer entry
442 if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
443 || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
444 return (e->val64 != 0);
446 return (e->val64 & _PAGE_PRESENT);
449 static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
451 e->val64 &= ~_PAGE_PRESENT;
454 static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
456 e->val64 |= _PAGE_PRESENT;
459 static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
461 return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
464 static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
466 e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
469 static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
471 e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
475 * Per-platform GMA routines.
477 static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
479 unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
481 trace_gma_index(__func__, gma, x);
485 #define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
486 static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
488 unsigned long x = (exp); \
489 trace_gma_index(__func__, gma, x); \
493 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
494 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
495 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
496 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
497 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
499 static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
500 .get_entry = gtt_get_entry64,
501 .set_entry = gtt_set_entry64,
502 .clear_present = gtt_entry_clear_present,
503 .set_present = gtt_entry_set_present,
504 .test_present = gen8_gtt_test_present,
505 .test_pse = gen8_gtt_test_pse,
506 .clear_pse = gen8_gtt_clear_pse,
507 .clear_ips = gen8_gtt_clear_ips,
508 .test_ips = gen8_gtt_test_ips,
509 .clear_64k_splited = gen8_gtt_clear_64k_splited,
510 .set_64k_splited = gen8_gtt_set_64k_splited,
511 .test_64k_splited = gen8_gtt_test_64k_splited,
512 .get_pfn = gen8_gtt_get_pfn,
513 .set_pfn = gen8_gtt_set_pfn,
516 static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
517 .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
518 .gma_to_pte_index = gen8_gma_to_pte_index,
519 .gma_to_pde_index = gen8_gma_to_pde_index,
520 .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
521 .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
522 .gma_to_pml4_index = gen8_gma_to_pml4_index,
525 /* Update entry type per pse and ips bit. */
526 static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
527 struct intel_gvt_gtt_entry *entry, bool ips)
529 switch (entry->type) {
530 case GTT_TYPE_PPGTT_PDE_ENTRY:
531 case GTT_TYPE_PPGTT_PDP_ENTRY:
532 if (pte_ops->test_pse(entry))
533 entry->type = get_pse_type(entry->type);
535 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
537 entry->type = get_pse_type(entry->type);
540 GEM_BUG_ON(!gtt_type_is_entry(entry->type));
543 GEM_BUG_ON(entry->type == GTT_TYPE_INVALID);
549 static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
550 struct intel_gvt_gtt_entry *entry, unsigned long index,
553 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
555 GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
557 entry->type = mm->ppgtt_mm.root_entry_type;
558 pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
559 mm->ppgtt_mm.shadow_pdps,
560 entry, index, false, 0, mm->vgpu);
561 update_entry_type_for_real(pte_ops, entry, false);
564 static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
565 struct intel_gvt_gtt_entry *entry, unsigned long index)
567 _ppgtt_get_root_entry(mm, entry, index, true);
570 static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
571 struct intel_gvt_gtt_entry *entry, unsigned long index)
573 _ppgtt_get_root_entry(mm, entry, index, false);
576 static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
577 struct intel_gvt_gtt_entry *entry, unsigned long index,
580 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
582 pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
583 mm->ppgtt_mm.shadow_pdps,
584 entry, index, false, 0, mm->vgpu);
587 static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
588 struct intel_gvt_gtt_entry *entry, unsigned long index)
590 _ppgtt_set_root_entry(mm, entry, index, true);
593 static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
594 struct intel_gvt_gtt_entry *entry, unsigned long index)
596 _ppgtt_set_root_entry(mm, entry, index, false);
599 static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
600 struct intel_gvt_gtt_entry *entry, unsigned long index)
602 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
604 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
606 entry->type = GTT_TYPE_GGTT_PTE;
607 pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
611 static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
612 struct intel_gvt_gtt_entry *entry, unsigned long index)
614 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
616 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
618 pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
622 static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
623 struct intel_gvt_gtt_entry *entry, unsigned long index)
625 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
627 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
629 pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
632 static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
633 struct intel_gvt_gtt_entry *entry, unsigned long index)
635 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
637 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
639 pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
643 * PPGTT shadow page table helpers.
645 static inline int ppgtt_spt_get_entry(
646 struct intel_vgpu_ppgtt_spt *spt,
647 void *page_table, int type,
648 struct intel_gvt_gtt_entry *e, unsigned long index,
651 struct intel_gvt *gvt = spt->vgpu->gvt;
652 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
655 e->type = get_entry_type(type);
657 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
660 ret = ops->get_entry(page_table, e, index, guest,
661 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
666 update_entry_type_for_real(ops, e, guest ?
667 spt->guest_page.pde_ips : false);
669 gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
670 type, e->type, index, e->val64);
674 static inline int ppgtt_spt_set_entry(
675 struct intel_vgpu_ppgtt_spt *spt,
676 void *page_table, int type,
677 struct intel_gvt_gtt_entry *e, unsigned long index,
680 struct intel_gvt *gvt = spt->vgpu->gvt;
681 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
683 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
686 gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
687 type, e->type, index, e->val64);
689 return ops->set_entry(page_table, e, index, guest,
690 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
694 #define ppgtt_get_guest_entry(spt, e, index) \
695 ppgtt_spt_get_entry(spt, NULL, \
696 spt->guest_page.type, e, index, true)
698 #define ppgtt_set_guest_entry(spt, e, index) \
699 ppgtt_spt_set_entry(spt, NULL, \
700 spt->guest_page.type, e, index, true)
702 #define ppgtt_get_shadow_entry(spt, e, index) \
703 ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
704 spt->shadow_page.type, e, index, false)
706 #define ppgtt_set_shadow_entry(spt, e, index) \
707 ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
708 spt->shadow_page.type, e, index, false)
710 static void *alloc_spt(gfp_t gfp_mask)
712 struct intel_vgpu_ppgtt_spt *spt;
714 spt = kzalloc(sizeof(*spt), gfp_mask);
718 spt->shadow_page.page = alloc_page(gfp_mask);
719 if (!spt->shadow_page.page) {
726 static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
728 __free_page(spt->shadow_page.page);
732 static int detach_oos_page(struct intel_vgpu *vgpu,
733 struct intel_vgpu_oos_page *oos_page);
735 static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
737 struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
739 trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
741 dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
742 PCI_DMA_BIDIRECTIONAL);
744 radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
746 if (spt->guest_page.gfn) {
747 if (spt->guest_page.oos_page)
748 detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
750 intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
753 list_del_init(&spt->post_shadow_list);
757 static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
759 struct intel_vgpu_ppgtt_spt *spt, *spn;
760 struct radix_tree_iter iter;
765 radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
766 spt = radix_tree_deref_slot(slot);
767 list_move(&spt->post_shadow_list, &all_spt);
771 list_for_each_entry_safe(spt, spn, &all_spt, post_shadow_list)
775 static int ppgtt_handle_guest_write_page_table_bytes(
776 struct intel_vgpu_ppgtt_spt *spt,
777 u64 pa, void *p_data, int bytes);
779 static int ppgtt_write_protection_handler(
780 struct intel_vgpu_page_track *page_track,
781 u64 gpa, void *data, int bytes)
783 struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;
787 if (bytes != 4 && bytes != 8)
790 ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
796 /* Find a spt by guest gfn. */
797 static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
798 struct intel_vgpu *vgpu, unsigned long gfn)
800 struct intel_vgpu_page_track *track;
802 track = intel_vgpu_find_page_track(vgpu, gfn);
803 if (track && track->handler == ppgtt_write_protection_handler)
804 return track->priv_data;
809 /* Find the spt by shadow page mfn. */
810 static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
811 struct intel_vgpu *vgpu, unsigned long mfn)
813 return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
816 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
818 /* Allocate shadow page table without guest page. */
819 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
820 struct intel_vgpu *vgpu, enum intel_gvt_gtt_type type)
822 struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
823 struct intel_vgpu_ppgtt_spt *spt = NULL;
828 spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
830 if (reclaim_one_ppgtt_mm(vgpu->gvt))
833 gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
834 return ERR_PTR(-ENOMEM);
838 atomic_set(&spt->refcount, 1);
839 INIT_LIST_HEAD(&spt->post_shadow_list);
844 spt->shadow_page.type = type;
845 daddr = dma_map_page(kdev, spt->shadow_page.page,
846 0, 4096, PCI_DMA_BIDIRECTIONAL);
847 if (dma_mapping_error(kdev, daddr)) {
848 gvt_vgpu_err("fail to map dma addr\n");
852 spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
853 spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
855 ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
862 dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
868 /* Allocate shadow page table associated with specific gfn. */
869 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt_gfn(
870 struct intel_vgpu *vgpu, enum intel_gvt_gtt_type type,
871 unsigned long gfn, bool guest_pde_ips)
873 struct intel_vgpu_ppgtt_spt *spt;
876 spt = ppgtt_alloc_spt(vgpu, type);
883 ret = intel_vgpu_register_page_track(vgpu, gfn,
884 ppgtt_write_protection_handler, spt);
890 spt->guest_page.type = type;
891 spt->guest_page.gfn = gfn;
892 spt->guest_page.pde_ips = guest_pde_ips;
894 trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
899 #define pt_entry_size_shift(spt) \
900 ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
902 #define pt_entries(spt) \
903 (I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
905 #define for_each_present_guest_entry(spt, e, i) \
906 for (i = 0; i < pt_entries(spt); \
907 i += spt->guest_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
908 if (!ppgtt_get_guest_entry(spt, e, i) && \
909 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
911 #define for_each_present_shadow_entry(spt, e, i) \
912 for (i = 0; i < pt_entries(spt); \
913 i += spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
914 if (!ppgtt_get_shadow_entry(spt, e, i) && \
915 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
917 #define for_each_shadow_entry(spt, e, i) \
918 for (i = 0; i < pt_entries(spt); \
919 i += (spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1)) \
920 if (!ppgtt_get_shadow_entry(spt, e, i))
922 static inline void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
924 int v = atomic_read(&spt->refcount);
926 trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
927 atomic_inc(&spt->refcount);
930 static inline int ppgtt_put_spt(struct intel_vgpu_ppgtt_spt *spt)
932 int v = atomic_read(&spt->refcount);
934 trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
935 return atomic_dec_return(&spt->refcount);
938 static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
940 static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
941 struct intel_gvt_gtt_entry *e)
943 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
944 struct intel_vgpu_ppgtt_spt *s;
945 enum intel_gvt_gtt_type cur_pt_type;
947 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
949 if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
950 && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
951 cur_pt_type = get_next_pt_type(e->type);
953 if (!gtt_type_is_pt(cur_pt_type) ||
954 !gtt_type_is_pt(cur_pt_type + 1)) {
955 WARN(1, "Invalid page table type, cur_pt_type is: %d\n", cur_pt_type);
961 if (ops->get_pfn(e) ==
962 vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
965 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
967 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
971 return ppgtt_invalidate_spt(s);
974 static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
975 struct intel_gvt_gtt_entry *entry)
977 struct intel_vgpu *vgpu = spt->vgpu;
978 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
982 pfn = ops->get_pfn(entry);
983 type = spt->shadow_page.type;
985 /* Uninitialized spte or unshadowed spte. */
986 if (!pfn || pfn == vgpu->gtt.scratch_pt[type].page_mfn)
989 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
992 static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
994 struct intel_vgpu *vgpu = spt->vgpu;
995 struct intel_gvt_gtt_entry e;
999 trace_spt_change(spt->vgpu->id, "die", spt,
1000 spt->guest_page.gfn, spt->shadow_page.type);
1002 if (ppgtt_put_spt(spt) > 0)
1005 for_each_present_shadow_entry(spt, &e, index) {
1007 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
1008 gvt_vdbg_mm("invalidate 4K entry\n");
1009 ppgtt_invalidate_pte(spt, &e);
1011 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
1012 /* We don't setup 64K shadow entry so far. */
1013 WARN(1, "suspicious 64K gtt entry\n");
1015 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
1016 gvt_vdbg_mm("invalidate 2M entry\n");
1018 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
1019 WARN(1, "GVT doesn't support 1GB page\n");
1021 case GTT_TYPE_PPGTT_PML4_ENTRY:
1022 case GTT_TYPE_PPGTT_PDP_ENTRY:
1023 case GTT_TYPE_PPGTT_PDE_ENTRY:
1024 gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
1025 ret = ppgtt_invalidate_spt_by_shadow_entry(
1035 trace_spt_change(spt->vgpu->id, "release", spt,
1036 spt->guest_page.gfn, spt->shadow_page.type);
1037 ppgtt_free_spt(spt);
1040 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
1041 spt, e.val64, e.type);
1045 static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
1047 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1049 if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {
1050 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
1051 GAMW_ECO_ENABLE_64K_IPS_FIELD;
1053 return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;
1054 } else if (INTEL_GEN(dev_priv) >= 11) {
1055 /* 64K paging only controlled by IPS bit in PTE now. */
1061 static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
1063 static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
1064 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
1066 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1067 struct intel_vgpu_ppgtt_spt *spt = NULL;
1071 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
1073 if (we->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1074 ips = vgpu_ips_enabled(vgpu) && ops->test_ips(we);
1076 spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
1080 if (ips != spt->guest_page.pde_ips) {
1081 spt->guest_page.pde_ips = ips;
1083 gvt_dbg_mm("reshadow PDE since ips changed\n");
1084 clear_page(spt->shadow_page.vaddr);
1085 ret = ppgtt_populate_spt(spt);
1092 int type = get_next_pt_type(we->type);
1094 if (!gtt_type_is_pt(type)) {
1099 spt = ppgtt_alloc_spt_gfn(vgpu, type, ops->get_pfn(we), ips);
1105 ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
1109 ret = ppgtt_populate_spt(spt);
1113 trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
1114 spt->shadow_page.type);
1119 ppgtt_free_spt(spt);
1122 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1123 spt, we->val64, we->type);
1124 return ERR_PTR(ret);
1127 static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
1128 struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
1130 struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1132 se->type = ge->type;
1133 se->val64 = ge->val64;
1135 /* Because we always split 64KB pages, so clear IPS in shadow PDE. */
1136 if (se->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1139 ops->set_pfn(se, s->shadow_page.mfn);
1143 * Check if can do 2M page
1144 * @vgpu: target vgpu
1145 * @entry: target pfn's gtt entry
1147 * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
1148 * negtive if found err.
1150 static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
1151 struct intel_gvt_gtt_entry *entry)
1153 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1156 if (!HAS_PAGE_SIZES(vgpu->gvt->dev_priv, I915_GTT_PAGE_SIZE_2M))
1159 pfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, ops->get_pfn(entry));
1160 if (pfn == INTEL_GVT_INVALID_ADDR)
1163 return PageTransHuge(pfn_to_page(pfn));
1166 static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
1167 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1168 struct intel_gvt_gtt_entry *se)
1170 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1171 struct intel_vgpu_ppgtt_spt *sub_spt;
1172 struct intel_gvt_gtt_entry sub_se;
1173 unsigned long start_gfn;
1174 dma_addr_t dma_addr;
1175 unsigned long sub_index;
1178 gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
1180 start_gfn = ops->get_pfn(se);
1182 sub_spt = ppgtt_alloc_spt(vgpu, GTT_TYPE_PPGTT_PTE_PT);
1183 if (IS_ERR(sub_spt))
1184 return PTR_ERR(sub_spt);
1186 for_each_shadow_entry(sub_spt, &sub_se, sub_index) {
1187 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu,
1188 start_gfn + sub_index, PAGE_SIZE, &dma_addr);
1190 ppgtt_invalidate_spt(spt);
1193 sub_se.val64 = se->val64;
1195 /* Copy the PAT field from PDE. */
1196 sub_se.val64 &= ~_PAGE_PAT;
1197 sub_se.val64 |= (se->val64 & _PAGE_PAT_LARGE) >> 5;
1199 ops->set_pfn(&sub_se, dma_addr >> PAGE_SHIFT);
1200 ppgtt_set_shadow_entry(sub_spt, &sub_se, sub_index);
1203 /* Clear dirty field. */
1204 se->val64 &= ~_PAGE_DIRTY;
1208 ops->set_pfn(se, sub_spt->shadow_page.mfn);
1209 ppgtt_set_shadow_entry(spt, se, index);
1213 static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
1214 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1215 struct intel_gvt_gtt_entry *se)
1217 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1218 struct intel_gvt_gtt_entry entry = *se;
1219 unsigned long start_gfn;
1220 dma_addr_t dma_addr;
1223 gvt_vdbg_mm("Split 64K gtt entry, index %lu\n", index);
1225 GEM_BUG_ON(index % GTT_64K_PTE_STRIDE);
1227 start_gfn = ops->get_pfn(se);
1229 entry.type = GTT_TYPE_PPGTT_PTE_4K_ENTRY;
1230 ops->set_64k_splited(&entry);
1232 for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1233 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu,
1234 start_gfn + i, PAGE_SIZE, &dma_addr);
1238 ops->set_pfn(&entry, dma_addr >> PAGE_SHIFT);
1239 ppgtt_set_shadow_entry(spt, &entry, index + i);
1244 static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
1245 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1246 struct intel_gvt_gtt_entry *ge)
1248 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1249 struct intel_gvt_gtt_entry se = *ge;
1250 unsigned long gfn, page_size = PAGE_SIZE;
1251 dma_addr_t dma_addr;
1254 if (!pte_ops->test_present(ge))
1257 gfn = pte_ops->get_pfn(ge);
1260 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
1261 gvt_vdbg_mm("shadow 4K gtt entry\n");
1263 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
1264 gvt_vdbg_mm("shadow 64K gtt entry\n");
1266 * The layout of 64K page is special, the page size is
1267 * controlled by uper PDE. To be simple, we always split
1268 * 64K page to smaller 4K pages in shadow PT.
1270 return split_64KB_gtt_entry(vgpu, spt, index, &se);
1271 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
1272 gvt_vdbg_mm("shadow 2M gtt entry\n");
1273 ret = is_2MB_gtt_possible(vgpu, ge);
1275 return split_2MB_gtt_entry(vgpu, spt, index, &se);
1278 page_size = I915_GTT_PAGE_SIZE_2M;
1280 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
1281 gvt_vgpu_err("GVT doesn't support 1GB entry\n");
1288 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, page_size,
1293 pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
1294 ppgtt_set_shadow_entry(spt, &se, index);
1298 static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
1300 struct intel_vgpu *vgpu = spt->vgpu;
1301 struct intel_gvt *gvt = vgpu->gvt;
1302 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1303 struct intel_vgpu_ppgtt_spt *s;
1304 struct intel_gvt_gtt_entry se, ge;
1305 unsigned long gfn, i;
1308 trace_spt_change(spt->vgpu->id, "born", spt,
1309 spt->guest_page.gfn, spt->shadow_page.type);
1311 for_each_present_guest_entry(spt, &ge, i) {
1312 if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
1313 s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1318 ppgtt_get_shadow_entry(spt, &se, i);
1319 ppgtt_generate_shadow_entry(&se, s, &ge);
1320 ppgtt_set_shadow_entry(spt, &se, i);
1322 gfn = ops->get_pfn(&ge);
1323 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
1324 ops->set_pfn(&se, gvt->gtt.scratch_mfn);
1325 ppgtt_set_shadow_entry(spt, &se, i);
1329 ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
1336 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1337 spt, ge.val64, ge.type);
1341 static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
1342 struct intel_gvt_gtt_entry *se, unsigned long index)
1344 struct intel_vgpu *vgpu = spt->vgpu;
1345 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1348 trace_spt_guest_change(spt->vgpu->id, "remove", spt,
1349 spt->shadow_page.type, se->val64, index);
1351 gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
1352 se->type, index, se->val64);
1354 if (!ops->test_present(se))
1357 if (ops->get_pfn(se) ==
1358 vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
1361 if (gtt_type_is_pt(get_next_pt_type(se->type))) {
1362 struct intel_vgpu_ppgtt_spt *s =
1363 intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(se));
1365 gvt_vgpu_err("fail to find guest page\n");
1369 ret = ppgtt_invalidate_spt(s);
1373 /* We don't setup 64K shadow entry so far. */
1374 WARN(se->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY,
1375 "suspicious 64K entry\n");
1376 ppgtt_invalidate_pte(spt, se);
1381 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1382 spt, se->val64, se->type);
1386 static int ppgtt_handle_guest_entry_add(struct intel_vgpu_ppgtt_spt *spt,
1387 struct intel_gvt_gtt_entry *we, unsigned long index)
1389 struct intel_vgpu *vgpu = spt->vgpu;
1390 struct intel_gvt_gtt_entry m;
1391 struct intel_vgpu_ppgtt_spt *s;
1394 trace_spt_guest_change(spt->vgpu->id, "add", spt, spt->shadow_page.type,
1397 gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
1398 we->type, index, we->val64);
1400 if (gtt_type_is_pt(get_next_pt_type(we->type))) {
1401 s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
1406 ppgtt_get_shadow_entry(spt, &m, index);
1407 ppgtt_generate_shadow_entry(&m, s, we);
1408 ppgtt_set_shadow_entry(spt, &m, index);
1410 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
1416 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1417 spt, we->val64, we->type);
1421 static int sync_oos_page(struct intel_vgpu *vgpu,
1422 struct intel_vgpu_oos_page *oos_page)
1424 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1425 struct intel_gvt *gvt = vgpu->gvt;
1426 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1427 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1428 struct intel_gvt_gtt_entry old, new;
1432 trace_oos_change(vgpu->id, "sync", oos_page->id,
1433 spt, spt->guest_page.type);
1435 old.type = new.type = get_entry_type(spt->guest_page.type);
1436 old.val64 = new.val64 = 0;
1438 for (index = 0; index < (I915_GTT_PAGE_SIZE >>
1439 info->gtt_entry_size_shift); index++) {
1440 ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
1441 ops->get_entry(NULL, &new, index, true,
1442 spt->guest_page.gfn << PAGE_SHIFT, vgpu);
1444 if (old.val64 == new.val64
1445 && !test_and_clear_bit(index, spt->post_shadow_bitmap))
1448 trace_oos_sync(vgpu->id, oos_page->id,
1449 spt, spt->guest_page.type,
1452 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, &new);
1456 ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
1459 spt->guest_page.write_cnt = 0;
1460 list_del_init(&spt->post_shadow_list);
1464 static int detach_oos_page(struct intel_vgpu *vgpu,
1465 struct intel_vgpu_oos_page *oos_page)
1467 struct intel_gvt *gvt = vgpu->gvt;
1468 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
1470 trace_oos_change(vgpu->id, "detach", oos_page->id,
1471 spt, spt->guest_page.type);
1473 spt->guest_page.write_cnt = 0;
1474 spt->guest_page.oos_page = NULL;
1475 oos_page->spt = NULL;
1477 list_del_init(&oos_page->vm_list);
1478 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1483 static int attach_oos_page(struct intel_vgpu_oos_page *oos_page,
1484 struct intel_vgpu_ppgtt_spt *spt)
1486 struct intel_gvt *gvt = spt->vgpu->gvt;
1489 ret = intel_gvt_hypervisor_read_gpa(spt->vgpu,
1490 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
1491 oos_page->mem, I915_GTT_PAGE_SIZE);
1495 oos_page->spt = spt;
1496 spt->guest_page.oos_page = oos_page;
1498 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1500 trace_oos_change(spt->vgpu->id, "attach", oos_page->id,
1501 spt, spt->guest_page.type);
1505 static int ppgtt_set_guest_page_sync(struct intel_vgpu_ppgtt_spt *spt)
1507 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1510 ret = intel_vgpu_enable_page_track(spt->vgpu, spt->guest_page.gfn);
1514 trace_oos_change(spt->vgpu->id, "set page sync", oos_page->id,
1515 spt, spt->guest_page.type);
1517 list_del_init(&oos_page->vm_list);
1518 return sync_oos_page(spt->vgpu, oos_page);
1521 static int ppgtt_allocate_oos_page(struct intel_vgpu_ppgtt_spt *spt)
1523 struct intel_gvt *gvt = spt->vgpu->gvt;
1524 struct intel_gvt_gtt *gtt = &gvt->gtt;
1525 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1528 WARN(oos_page, "shadow PPGTT page has already has a oos page\n");
1530 if (list_empty(>t->oos_page_free_list_head)) {
1531 oos_page = container_of(gtt->oos_page_use_list_head.next,
1532 struct intel_vgpu_oos_page, list);
1533 ret = ppgtt_set_guest_page_sync(oos_page->spt);
1536 ret = detach_oos_page(spt->vgpu, oos_page);
1540 oos_page = container_of(gtt->oos_page_free_list_head.next,
1541 struct intel_vgpu_oos_page, list);
1542 return attach_oos_page(oos_page, spt);
1545 static int ppgtt_set_guest_page_oos(struct intel_vgpu_ppgtt_spt *spt)
1547 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
1549 if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n"))
1552 trace_oos_change(spt->vgpu->id, "set page out of sync", oos_page->id,
1553 spt, spt->guest_page.type);
1555 list_add_tail(&oos_page->vm_list, &spt->vgpu->gtt.oos_page_list_head);
1556 return intel_vgpu_disable_page_track(spt->vgpu, spt->guest_page.gfn);
1560 * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
1563 * This function is called before submitting a guest workload to host,
1564 * to sync all the out-of-synced shadow for vGPU
1567 * Zero on success, negative error code if failed.
1569 int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu)
1571 struct list_head *pos, *n;
1572 struct intel_vgpu_oos_page *oos_page;
1575 if (!enable_out_of_sync)
1578 list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
1579 oos_page = container_of(pos,
1580 struct intel_vgpu_oos_page, vm_list);
1581 ret = ppgtt_set_guest_page_sync(oos_page->spt);
1589 * The heart of PPGTT shadow page table.
1591 static int ppgtt_handle_guest_write_page_table(
1592 struct intel_vgpu_ppgtt_spt *spt,
1593 struct intel_gvt_gtt_entry *we, unsigned long index)
1595 struct intel_vgpu *vgpu = spt->vgpu;
1596 int type = spt->shadow_page.type;
1597 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1598 struct intel_gvt_gtt_entry old_se;
1602 new_present = ops->test_present(we);
1605 * Adding the new entry first and then removing the old one, that can
1606 * guarantee the ppgtt table is validated during the window between
1607 * adding and removal.
1609 ppgtt_get_shadow_entry(spt, &old_se, index);
1612 ret = ppgtt_handle_guest_entry_add(spt, we, index);
1617 ret = ppgtt_handle_guest_entry_removal(spt, &old_se, index);
1622 /* For 64KB splited entries, we need clear them all. */
1623 if (ops->test_64k_splited(&old_se) &&
1624 !(index % GTT_64K_PTE_STRIDE)) {
1625 gvt_vdbg_mm("remove splited 64K shadow entries\n");
1626 for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1627 ops->clear_64k_splited(&old_se);
1628 ops->set_pfn(&old_se,
1629 vgpu->gtt.scratch_pt[type].page_mfn);
1630 ppgtt_set_shadow_entry(spt, &old_se, index + i);
1632 } else if (old_se.type == GTT_TYPE_PPGTT_PTE_2M_ENTRY ||
1633 old_se.type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
1634 ops->clear_pse(&old_se);
1635 ops->set_pfn(&old_se,
1636 vgpu->gtt.scratch_pt[type].page_mfn);
1637 ppgtt_set_shadow_entry(spt, &old_se, index);
1639 ops->set_pfn(&old_se,
1640 vgpu->gtt.scratch_pt[type].page_mfn);
1641 ppgtt_set_shadow_entry(spt, &old_se, index);
1647 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1648 spt, we->val64, we->type);
1654 static inline bool can_do_out_of_sync(struct intel_vgpu_ppgtt_spt *spt)
1656 return enable_out_of_sync
1657 && gtt_type_is_pte_pt(spt->guest_page.type)
1658 && spt->guest_page.write_cnt >= 2;
1661 static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt,
1662 unsigned long index)
1664 set_bit(index, spt->post_shadow_bitmap);
1665 if (!list_empty(&spt->post_shadow_list))
1668 list_add_tail(&spt->post_shadow_list,
1669 &spt->vgpu->gtt.post_shadow_list_head);
1673 * intel_vgpu_flush_post_shadow - flush the post shadow transactions
1676 * This function is called before submitting a guest workload to host,
1677 * to flush all the post shadows for a vGPU.
1680 * Zero on success, negative error code if failed.
1682 int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu)
1684 struct list_head *pos, *n;
1685 struct intel_vgpu_ppgtt_spt *spt;
1686 struct intel_gvt_gtt_entry ge;
1687 unsigned long index;
1690 list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
1691 spt = container_of(pos, struct intel_vgpu_ppgtt_spt,
1694 for_each_set_bit(index, spt->post_shadow_bitmap,
1695 GTT_ENTRY_NUM_IN_ONE_PAGE) {
1696 ppgtt_get_guest_entry(spt, &ge, index);
1698 ret = ppgtt_handle_guest_write_page_table(spt,
1702 clear_bit(index, spt->post_shadow_bitmap);
1704 list_del_init(&spt->post_shadow_list);
1709 static int ppgtt_handle_guest_write_page_table_bytes(
1710 struct intel_vgpu_ppgtt_spt *spt,
1711 u64 pa, void *p_data, int bytes)
1713 struct intel_vgpu *vgpu = spt->vgpu;
1714 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1715 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1716 struct intel_gvt_gtt_entry we, se;
1717 unsigned long index;
1720 index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
1722 ppgtt_get_guest_entry(spt, &we, index);
1725 * For page table which has 64K gtt entry, only PTE#0, PTE#16,
1726 * PTE#32, ... PTE#496 are used. Unused PTEs update should be
1729 if (we.type == GTT_TYPE_PPGTT_PTE_64K_ENTRY &&
1730 (index % GTT_64K_PTE_STRIDE)) {
1731 gvt_vdbg_mm("Ignore write to unused PTE entry, index %lu\n",
1736 if (bytes == info->gtt_entry_size) {
1737 ret = ppgtt_handle_guest_write_page_table(spt, &we, index);
1741 if (!test_bit(index, spt->post_shadow_bitmap)) {
1742 int type = spt->shadow_page.type;
1744 ppgtt_get_shadow_entry(spt, &se, index);
1745 ret = ppgtt_handle_guest_entry_removal(spt, &se, index);
1748 ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn);
1749 ppgtt_set_shadow_entry(spt, &se, index);
1751 ppgtt_set_post_shadow(spt, index);
1754 if (!enable_out_of_sync)
1757 spt->guest_page.write_cnt++;
1759 if (spt->guest_page.oos_page)
1760 ops->set_entry(spt->guest_page.oos_page->mem, &we, index,
1763 if (can_do_out_of_sync(spt)) {
1764 if (!spt->guest_page.oos_page)
1765 ppgtt_allocate_oos_page(spt);
1767 ret = ppgtt_set_guest_page_oos(spt);
1774 static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
1776 struct intel_vgpu *vgpu = mm->vgpu;
1777 struct intel_gvt *gvt = vgpu->gvt;
1778 struct intel_gvt_gtt *gtt = &gvt->gtt;
1779 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1780 struct intel_gvt_gtt_entry se;
1783 if (!mm->ppgtt_mm.shadowed)
1786 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
1787 ppgtt_get_shadow_root_entry(mm, &se, index);
1789 if (!ops->test_present(&se))
1792 ppgtt_invalidate_spt_by_shadow_entry(vgpu, &se);
1794 ppgtt_set_shadow_root_entry(mm, &se, index);
1796 trace_spt_guest_change(vgpu->id, "destroy root pointer",
1797 NULL, se.type, se.val64, index);
1800 mm->ppgtt_mm.shadowed = false;
1804 static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
1806 struct intel_vgpu *vgpu = mm->vgpu;
1807 struct intel_gvt *gvt = vgpu->gvt;
1808 struct intel_gvt_gtt *gtt = &gvt->gtt;
1809 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1810 struct intel_vgpu_ppgtt_spt *spt;
1811 struct intel_gvt_gtt_entry ge, se;
1814 if (mm->ppgtt_mm.shadowed)
1817 mm->ppgtt_mm.shadowed = true;
1819 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
1820 ppgtt_get_guest_root_entry(mm, &ge, index);
1822 if (!ops->test_present(&ge))
1825 trace_spt_guest_change(vgpu->id, __func__, NULL,
1826 ge.type, ge.val64, index);
1828 spt = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
1830 gvt_vgpu_err("fail to populate guest root pointer\n");
1834 ppgtt_generate_shadow_entry(&se, spt, &ge);
1835 ppgtt_set_shadow_root_entry(mm, &se, index);
1837 trace_spt_guest_change(vgpu->id, "populate root pointer",
1838 NULL, se.type, se.val64, index);
1843 invalidate_ppgtt_mm(mm);
1847 static struct intel_vgpu_mm *vgpu_alloc_mm(struct intel_vgpu *vgpu)
1849 struct intel_vgpu_mm *mm;
1851 mm = kzalloc(sizeof(*mm), GFP_KERNEL);
1856 kref_init(&mm->ref);
1857 atomic_set(&mm->pincount, 0);
1862 static void vgpu_free_mm(struct intel_vgpu_mm *mm)
1868 * intel_vgpu_create_ppgtt_mm - create a ppgtt mm object for a vGPU
1870 * @root_entry_type: ppgtt root entry type
1871 * @pdps: guest pdps.
1873 * This function is used to create a ppgtt mm object for a vGPU.
1876 * Zero on success, negative error code in pointer if failed.
1878 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
1879 enum intel_gvt_gtt_type root_entry_type, u64 pdps[])
1881 struct intel_gvt *gvt = vgpu->gvt;
1882 struct intel_vgpu_mm *mm;
1885 mm = vgpu_alloc_mm(vgpu);
1887 return ERR_PTR(-ENOMEM);
1889 mm->type = INTEL_GVT_MM_PPGTT;
1891 GEM_BUG_ON(root_entry_type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY &&
1892 root_entry_type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY);
1893 mm->ppgtt_mm.root_entry_type = root_entry_type;
1895 INIT_LIST_HEAD(&mm->ppgtt_mm.list);
1896 INIT_LIST_HEAD(&mm->ppgtt_mm.lru_list);
1898 if (root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
1899 mm->ppgtt_mm.guest_pdps[0] = pdps[0];
1901 memcpy(mm->ppgtt_mm.guest_pdps, pdps,
1902 sizeof(mm->ppgtt_mm.guest_pdps));
1904 ret = shadow_ppgtt_mm(mm);
1906 gvt_vgpu_err("failed to shadow ppgtt mm\n");
1908 return ERR_PTR(ret);
1911 list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1913 mutex_lock(&gvt->gtt.ppgtt_mm_lock);
1914 list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1915 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
1920 static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
1922 struct intel_vgpu_mm *mm;
1923 unsigned long nr_entries;
1925 mm = vgpu_alloc_mm(vgpu);
1927 return ERR_PTR(-ENOMEM);
1929 mm->type = INTEL_GVT_MM_GGTT;
1931 nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
1932 mm->ggtt_mm.virtual_ggtt =
1933 vzalloc(array_size(nr_entries,
1934 vgpu->gvt->device_info.gtt_entry_size));
1935 if (!mm->ggtt_mm.virtual_ggtt) {
1937 return ERR_PTR(-ENOMEM);
1944 * _intel_vgpu_mm_release - destroy a mm object
1945 * @mm_ref: a kref object
1947 * This function is used to destroy a mm object for vGPU
1950 void _intel_vgpu_mm_release(struct kref *mm_ref)
1952 struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref);
1954 if (GEM_WARN_ON(atomic_read(&mm->pincount)))
1955 gvt_err("vgpu mm pin count bug detected\n");
1957 if (mm->type == INTEL_GVT_MM_PPGTT) {
1958 list_del(&mm->ppgtt_mm.list);
1960 mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
1961 list_del(&mm->ppgtt_mm.lru_list);
1962 mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
1964 invalidate_ppgtt_mm(mm);
1966 vfree(mm->ggtt_mm.virtual_ggtt);
1973 * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
1974 * @mm: a vGPU mm object
1976 * This function is called when user doesn't want to use a vGPU mm object
1978 void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
1980 atomic_dec_if_positive(&mm->pincount);
1984 * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1985 * @mm: target vgpu mm
1987 * This function is called when user wants to use a vGPU mm object. If this
1988 * mm object hasn't been shadowed yet, the shadow will be populated at this
1992 * Zero on success, negative error code if failed.
1994 int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
1998 atomic_inc(&mm->pincount);
2000 if (mm->type == INTEL_GVT_MM_PPGTT) {
2001 ret = shadow_ppgtt_mm(mm);
2005 mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2006 list_move_tail(&mm->ppgtt_mm.lru_list,
2007 &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
2008 mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2014 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
2016 struct intel_vgpu_mm *mm;
2017 struct list_head *pos, *n;
2019 mutex_lock(&gvt->gtt.ppgtt_mm_lock);
2021 list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
2022 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.lru_list);
2024 if (atomic_read(&mm->pincount))
2027 list_del_init(&mm->ppgtt_mm.lru_list);
2028 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2029 invalidate_ppgtt_mm(mm);
2032 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2037 * GMA translation APIs.
2039 static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
2040 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
2042 struct intel_vgpu *vgpu = mm->vgpu;
2043 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2044 struct intel_vgpu_ppgtt_spt *s;
2046 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
2051 ppgtt_get_shadow_entry(s, e, index);
2053 ppgtt_get_guest_entry(s, e, index);
2058 * intel_vgpu_gma_to_gpa - translate a gma to GPA
2059 * @mm: mm object. could be a PPGTT or GGTT mm object
2060 * @gma: graphics memory address in this mm object
2062 * This function is used to translate a graphics memory address in specific
2063 * graphics memory space to guest physical address.
2066 * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
2068 unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
2070 struct intel_vgpu *vgpu = mm->vgpu;
2071 struct intel_gvt *gvt = vgpu->gvt;
2072 struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
2073 struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
2074 unsigned long gpa = INTEL_GVT_INVALID_ADDR;
2075 unsigned long gma_index[4];
2076 struct intel_gvt_gtt_entry e;
2080 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT &&
2081 mm->type != INTEL_GVT_MM_PPGTT);
2083 if (mm->type == INTEL_GVT_MM_GGTT) {
2084 if (!vgpu_gmadr_is_valid(vgpu, gma))
2087 ggtt_get_guest_entry(mm, &e,
2088 gma_ops->gma_to_ggtt_pte_index(gma));
2090 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT)
2091 + (gma & ~I915_GTT_PAGE_MASK);
2093 trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
2095 switch (mm->ppgtt_mm.root_entry_type) {
2096 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2097 ppgtt_get_shadow_root_entry(mm, &e, 0);
2099 gma_index[0] = gma_ops->gma_to_pml4_index(gma);
2100 gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma);
2101 gma_index[2] = gma_ops->gma_to_pde_index(gma);
2102 gma_index[3] = gma_ops->gma_to_pte_index(gma);
2105 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2106 ppgtt_get_shadow_root_entry(mm, &e,
2107 gma_ops->gma_to_l3_pdp_index(gma));
2109 gma_index[0] = gma_ops->gma_to_pde_index(gma);
2110 gma_index[1] = gma_ops->gma_to_pte_index(gma);
2117 /* walk the shadow page table and get gpa from guest entry */
2118 for (i = 0; i < levels; i++) {
2119 ret = ppgtt_get_next_level_entry(mm, &e, gma_index[i],
2124 if (!pte_ops->test_present(&e)) {
2125 gvt_dbg_core("GMA 0x%lx is not present\n", gma);
2130 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT) +
2131 (gma & ~I915_GTT_PAGE_MASK);
2132 trace_gma_translate(vgpu->id, "ppgtt", 0,
2133 mm->ppgtt_mm.root_entry_type, gma, gpa);
2138 gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
2139 return INTEL_GVT_INVALID_ADDR;
2142 static int emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
2143 unsigned int off, void *p_data, unsigned int bytes)
2145 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2146 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2147 unsigned long index = off >> info->gtt_entry_size_shift;
2149 struct intel_gvt_gtt_entry e;
2151 if (bytes != 4 && bytes != 8)
2154 gma = index << I915_GTT_PAGE_SHIFT;
2155 if (!intel_gvt_ggtt_validate_range(vgpu,
2156 gma, 1 << I915_GTT_PAGE_SHIFT)) {
2157 gvt_dbg_mm("read invalid ggtt at 0x%lx\n", gma);
2158 memset(p_data, 0, bytes);
2162 ggtt_get_guest_entry(ggtt_mm, &e, index);
2163 memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
2169 * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read
2171 * @off: register offset
2172 * @p_data: data will be returned to guest
2173 * @bytes: data length
2175 * This function is used to emulate the GTT MMIO register read
2178 * Zero on success, error code if failed.
2180 int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
2181 void *p_data, unsigned int bytes)
2183 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2186 if (bytes != 4 && bytes != 8)
2189 off -= info->gtt_start_offset;
2190 ret = emulate_ggtt_mmio_read(vgpu, off, p_data, bytes);
2194 static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
2195 struct intel_gvt_gtt_entry *entry)
2197 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2200 pfn = pte_ops->get_pfn(entry);
2201 if (pfn != vgpu->gvt->gtt.scratch_mfn)
2202 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu,
2206 static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2207 void *p_data, unsigned int bytes)
2209 struct intel_gvt *gvt = vgpu->gvt;
2210 const struct intel_gvt_device_info *info = &gvt->device_info;
2211 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2212 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2213 unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
2214 unsigned long gma, gfn;
2215 struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
2216 struct intel_gvt_gtt_entry m = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
2217 dma_addr_t dma_addr;
2219 struct intel_gvt_partial_pte *partial_pte, *pos, *n;
2220 bool partial_update = false;
2222 if (bytes != 4 && bytes != 8)
2225 gma = g_gtt_index << I915_GTT_PAGE_SHIFT;
2227 /* the VM may configure the whole GM space when ballooning is used */
2228 if (!vgpu_gmadr_is_valid(vgpu, gma))
2231 e.type = GTT_TYPE_GGTT_PTE;
2232 memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
2235 /* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
2236 * write, save the first 4 bytes in a list and update virtual
2237 * PTE. Only update shadow PTE when the second 4 bytes comes.
2239 if (bytes < info->gtt_entry_size) {
2242 list_for_each_entry_safe(pos, n,
2243 &ggtt_mm->ggtt_mm.partial_pte_list, list) {
2244 if (g_gtt_index == pos->offset >>
2245 info->gtt_entry_size_shift) {
2246 if (off != pos->offset) {
2247 /* the second partial part*/
2248 int last_off = pos->offset &
2249 (info->gtt_entry_size - 1);
2251 memcpy((void *)&e.val64 + last_off,
2252 (void *)&pos->data + last_off,
2255 list_del(&pos->list);
2261 /* update of the first partial part */
2262 pos->data = e.val64;
2263 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2269 /* the first partial part */
2270 partial_pte = kzalloc(sizeof(*partial_pte), GFP_KERNEL);
2273 partial_pte->offset = off;
2274 partial_pte->data = e.val64;
2275 list_add_tail(&partial_pte->list,
2276 &ggtt_mm->ggtt_mm.partial_pte_list);
2277 partial_update = true;
2281 if (!partial_update && (ops->test_present(&e))) {
2282 gfn = ops->get_pfn(&e);
2286 /* one PTE update may be issued in multiple writes and the
2287 * first write may not construct a valid gfn
2289 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
2290 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2294 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn,
2295 PAGE_SIZE, &dma_addr);
2297 gvt_vgpu_err("fail to populate guest ggtt entry\n");
2298 /* guest driver may read/write the entry when partial
2299 * update the entry in this situation p2m will fail
2300 * settting the shadow entry to point to a scratch page
2302 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2304 ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
2306 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2307 ops->clear_present(&m);
2311 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2313 ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index);
2314 ggtt_invalidate_pte(vgpu, &e);
2316 ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
2317 ggtt_invalidate(gvt->dev_priv);
2322 * intel_vgpu_emulate_ggtt_mmio_write - emulate GTT MMIO register write
2324 * @off: register offset
2325 * @p_data: data from guest write
2326 * @bytes: data length
2328 * This function is used to emulate the GTT MMIO register write
2331 * Zero on success, error code if failed.
2333 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
2334 unsigned int off, void *p_data, unsigned int bytes)
2336 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2339 if (bytes != 4 && bytes != 8)
2342 off -= info->gtt_start_offset;
2343 ret = emulate_ggtt_mmio_write(vgpu, off, p_data, bytes);
2347 static int alloc_scratch_pages(struct intel_vgpu *vgpu,
2348 enum intel_gvt_gtt_type type)
2350 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2351 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2352 int page_entry_num = I915_GTT_PAGE_SIZE >>
2353 vgpu->gvt->device_info.gtt_entry_size_shift;
2356 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2359 if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
2362 scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
2364 gvt_vgpu_err("fail to allocate scratch page\n");
2368 daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0,
2369 4096, PCI_DMA_BIDIRECTIONAL);
2370 if (dma_mapping_error(dev, daddr)) {
2371 gvt_vgpu_err("fail to dmamap scratch_pt\n");
2372 __free_page(virt_to_page(scratch_pt));
2375 gtt->scratch_pt[type].page_mfn =
2376 (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2377 gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
2378 gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
2379 vgpu->id, type, gtt->scratch_pt[type].page_mfn);
2381 /* Build the tree by full filled the scratch pt with the entries which
2382 * point to the next level scratch pt or scratch page. The
2383 * scratch_pt[type] indicate the scratch pt/scratch page used by the
2385 * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
2386 * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
2387 * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
2389 if (type > GTT_TYPE_PPGTT_PTE_PT) {
2390 struct intel_gvt_gtt_entry se;
2392 memset(&se, 0, sizeof(struct intel_gvt_gtt_entry));
2393 se.type = get_entry_type(type - 1);
2394 ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn);
2396 /* The entry parameters like present/writeable/cache type
2397 * set to the same as i915's scratch page tree.
2399 se.val64 |= _PAGE_PRESENT | _PAGE_RW;
2400 if (type == GTT_TYPE_PPGTT_PDE_PT)
2401 se.val64 |= PPAT_CACHED;
2403 for (i = 0; i < page_entry_num; i++)
2404 ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
2410 static int release_scratch_page_tree(struct intel_vgpu *vgpu)
2413 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2416 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2417 if (vgpu->gtt.scratch_pt[i].page != NULL) {
2418 daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
2419 I915_GTT_PAGE_SHIFT);
2420 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2421 __free_page(vgpu->gtt.scratch_pt[i].page);
2422 vgpu->gtt.scratch_pt[i].page = NULL;
2423 vgpu->gtt.scratch_pt[i].page_mfn = 0;
2430 static int create_scratch_page_tree(struct intel_vgpu *vgpu)
2434 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2435 ret = alloc_scratch_pages(vgpu, i);
2443 release_scratch_page_tree(vgpu);
2448 * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization
2451 * This function is used to initialize per-vGPU graphics memory virtualization
2455 * Zero on success, error code if failed.
2457 int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
2459 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2461 INIT_RADIX_TREE(>t->spt_tree, GFP_KERNEL);
2463 INIT_LIST_HEAD(>t->ppgtt_mm_list_head);
2464 INIT_LIST_HEAD(>t->oos_page_list_head);
2465 INIT_LIST_HEAD(>t->post_shadow_list_head);
2467 gtt->ggtt_mm = intel_vgpu_create_ggtt_mm(vgpu);
2468 if (IS_ERR(gtt->ggtt_mm)) {
2469 gvt_vgpu_err("fail to create mm for ggtt.\n");
2470 return PTR_ERR(gtt->ggtt_mm);
2473 intel_vgpu_reset_ggtt(vgpu, false);
2475 INIT_LIST_HEAD(>t->ggtt_mm->ggtt_mm.partial_pte_list);
2477 return create_scratch_page_tree(vgpu);
2480 static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
2482 struct list_head *pos, *n;
2483 struct intel_vgpu_mm *mm;
2485 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2486 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2487 intel_vgpu_destroy_mm(mm);
2490 if (GEM_WARN_ON(!list_empty(&vgpu->gtt.ppgtt_mm_list_head)))
2491 gvt_err("vgpu ppgtt mm is not fully destroyed\n");
2493 if (GEM_WARN_ON(!radix_tree_empty(&vgpu->gtt.spt_tree))) {
2494 gvt_err("Why we still has spt not freed?\n");
2495 ppgtt_free_all_spt(vgpu);
2499 static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
2501 struct intel_gvt_partial_pte *pos, *next;
2503 list_for_each_entry_safe(pos, next,
2504 &vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list,
2506 gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
2507 pos->offset, pos->data);
2510 intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
2511 vgpu->gtt.ggtt_mm = NULL;
2515 * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization
2518 * This function is used to clean up per-vGPU graphics memory virtualization
2522 * Zero on success, error code if failed.
2524 void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)
2526 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2527 intel_vgpu_destroy_ggtt_mm(vgpu);
2528 release_scratch_page_tree(vgpu);
2531 static void clean_spt_oos(struct intel_gvt *gvt)
2533 struct intel_gvt_gtt *gtt = &gvt->gtt;
2534 struct list_head *pos, *n;
2535 struct intel_vgpu_oos_page *oos_page;
2537 WARN(!list_empty(>t->oos_page_use_list_head),
2538 "someone is still using oos page\n");
2540 list_for_each_safe(pos, n, >t->oos_page_free_list_head) {
2541 oos_page = container_of(pos, struct intel_vgpu_oos_page, list);
2542 list_del(&oos_page->list);
2543 free_page((unsigned long)oos_page->mem);
2548 static int setup_spt_oos(struct intel_gvt *gvt)
2550 struct intel_gvt_gtt *gtt = &gvt->gtt;
2551 struct intel_vgpu_oos_page *oos_page;
2555 INIT_LIST_HEAD(>t->oos_page_free_list_head);
2556 INIT_LIST_HEAD(>t->oos_page_use_list_head);
2558 for (i = 0; i < preallocated_oos_pages; i++) {
2559 oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL);
2564 oos_page->mem = (void *)__get_free_pages(GFP_KERNEL, 0);
2565 if (!oos_page->mem) {
2571 INIT_LIST_HEAD(&oos_page->list);
2572 INIT_LIST_HEAD(&oos_page->vm_list);
2574 list_add_tail(&oos_page->list, >t->oos_page_free_list_head);
2577 gvt_dbg_mm("%d oos pages preallocated\n", i);
2586 * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
2588 * @pdps: pdp root array
2590 * This function is used to find a PPGTT mm object from mm object pool
2593 * pointer to mm object on success, NULL if failed.
2595 struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
2598 struct intel_vgpu_mm *mm;
2599 struct list_head *pos;
2601 list_for_each(pos, &vgpu->gtt.ppgtt_mm_list_head) {
2602 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2604 switch (mm->ppgtt_mm.root_entry_type) {
2605 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2606 if (pdps[0] == mm->ppgtt_mm.guest_pdps[0])
2609 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2610 if (!memcmp(pdps, mm->ppgtt_mm.guest_pdps,
2611 sizeof(mm->ppgtt_mm.guest_pdps)))
2622 * intel_vgpu_get_ppgtt_mm - get or create a PPGTT mm object.
2624 * @root_entry_type: ppgtt root entry type
2627 * This function is used to find or create a PPGTT mm object from a guest.
2630 * Zero on success, negative error code if failed.
2632 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
2633 enum intel_gvt_gtt_type root_entry_type, u64 pdps[])
2635 struct intel_vgpu_mm *mm;
2637 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2639 intel_vgpu_mm_get(mm);
2641 mm = intel_vgpu_create_ppgtt_mm(vgpu, root_entry_type, pdps);
2643 gvt_vgpu_err("fail to create mm\n");
2649 * intel_vgpu_put_ppgtt_mm - find and put a PPGTT mm object.
2653 * This function is used to find a PPGTT mm object from a guest and destroy it.
2656 * Zero on success, negative error code if failed.
2658 int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[])
2660 struct intel_vgpu_mm *mm;
2662 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2664 gvt_vgpu_err("fail to find ppgtt instance.\n");
2667 intel_vgpu_mm_put(mm);
2672 * intel_gvt_init_gtt - initialize mm components of a GVT device
2675 * This function is called at the initialization stage, to initialize
2676 * the mm components of a GVT device.
2679 * zero on success, negative error code if failed.
2681 int intel_gvt_init_gtt(struct intel_gvt *gvt)
2685 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2688 gvt_dbg_core("init gtt\n");
2690 gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2691 gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2693 page = (void *)get_zeroed_page(GFP_KERNEL);
2695 gvt_err("fail to allocate scratch ggtt page\n");
2699 daddr = dma_map_page(dev, virt_to_page(page), 0,
2700 4096, PCI_DMA_BIDIRECTIONAL);
2701 if (dma_mapping_error(dev, daddr)) {
2702 gvt_err("fail to dmamap scratch ggtt page\n");
2703 __free_page(virt_to_page(page));
2707 gvt->gtt.scratch_page = virt_to_page(page);
2708 gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2710 if (enable_out_of_sync) {
2711 ret = setup_spt_oos(gvt);
2713 gvt_err("fail to initialize SPT oos\n");
2714 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2715 __free_page(gvt->gtt.scratch_page);
2719 INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2720 mutex_init(&gvt->gtt.ppgtt_mm_lock);
2725 * intel_gvt_clean_gtt - clean up mm components of a GVT device
2728 * This function is called at the driver unloading stage, to clean up the
2729 * the mm components of a GVT device.
2732 void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2734 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2735 dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
2736 I915_GTT_PAGE_SHIFT);
2738 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2740 __free_page(gvt->gtt.scratch_page);
2742 if (enable_out_of_sync)
2747 * intel_vgpu_invalidate_ppgtt - invalidate PPGTT instances
2750 * This function is called when invalidate all PPGTT instances of a vGPU.
2753 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
2755 struct list_head *pos, *n;
2756 struct intel_vgpu_mm *mm;
2758 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2759 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2760 if (mm->type == INTEL_GVT_MM_PPGTT) {
2761 mutex_lock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2762 list_del_init(&mm->ppgtt_mm.lru_list);
2763 mutex_unlock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2764 if (mm->ppgtt_mm.shadowed)
2765 invalidate_ppgtt_mm(mm);
2771 * intel_vgpu_reset_ggtt - reset the GGTT entry
2773 * @invalidate_old: invalidate old entries
2775 * This function is called at the vGPU create stage
2776 * to reset all the GGTT entries.
2779 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
2781 struct intel_gvt *gvt = vgpu->gvt;
2782 struct drm_i915_private *dev_priv = gvt->dev_priv;
2783 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2784 struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
2785 struct intel_gvt_gtt_entry old_entry;
2789 pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2790 pte_ops->set_present(&entry);
2792 index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2793 num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
2794 while (num_entries--) {
2795 if (invalidate_old) {
2796 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2797 ggtt_invalidate_pte(vgpu, &old_entry);
2799 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2802 index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2803 num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
2804 while (num_entries--) {
2805 if (invalidate_old) {
2806 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2807 ggtt_invalidate_pte(vgpu, &old_entry);
2809 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2812 ggtt_invalidate(dev_priv);
2816 * intel_vgpu_reset_gtt - reset the all GTT related status
2819 * This function is called from vfio core to reset reset all
2820 * GTT related status, including GGTT, PPGTT, scratch page.
2823 void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
2825 /* Shadow pages are only created when there is no page
2826 * table tracking data, so remove page tracking data after
2827 * removing the shadow pages.
2829 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2830 intel_vgpu_reset_ggtt(vgpu, true);