drivers/gpu/drm/i915/gvt/fb_decoder.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Kevin Tian <kevin.tian@intel.com>
  25  *
  26  * Contributors:
  27  *    Bing Niu <bing.niu@intel.com>
  28  *    Xu Han <xu.han@intel.com>
  29  *    Ping Gao <ping.a.gao@intel.com>
  30  *    Xiaoguang Chen <xiaoguang.chen@intel.com>
  31  *    Yang Liu <yang2.liu@intel.com>
  32  *    Tina Zhang <tina.zhang@intel.com>
  33  *
  34  */
  35
  36 #include <uapi/drm/drm_fourcc.h>
  37 #include "i915_drv.h"
  38 #include "gvt.h"
  39 #include "i915_pvinfo.h"
  40
  41 #define PRIMARY_FORMAT_NUM      16
  42 struct pixel_format {
  43         int     drm_format;     /* Pixel format in DRM definition */
  44         int     bpp;            /* Bits per pixel, 0 indicates invalid */
  45         char    *desc;          /* The description */
  46 };
  47
  48 static struct pixel_format bdw_pixel_formats[] = {
  49         {DRM_FORMAT_C8, 8, "8-bit Indexed"},
  50         {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
  51         {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
  52         {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
  53
  54         {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
  55         {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
  56
  57         /* non-supported format has bpp default to 0 */
  58         {0, 0, NULL},
  59 };
  60
  61 static struct pixel_format skl_pixel_formats[] = {
  62         {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
  63         {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
  64         {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
  65         {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
  66
  67         {DRM_FORMAT_C8, 8, "8-bit Indexed"},
  68         {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
  69         {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
  70         {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
  71
  72         {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
  73         {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
  74         {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
  75         {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
  76
  77         /* non-supported format has bpp default to 0 */
  78         {0, 0, NULL},
  79 };
  80
  81 static int bdw_format_to_drm(int format)
  82 {
  83         int bdw_pixel_formats_index = 6;
  84
  85         switch (format) {
  86         case DISPPLANE_8BPP:
  87                 bdw_pixel_formats_index = 0;
  88                 break;
  89         case DISPPLANE_BGRX565:
  90                 bdw_pixel_formats_index = 1;
  91                 break;
  92         case DISPPLANE_BGRX888:
  93                 bdw_pixel_formats_index = 2;
  94                 break;
  95         case DISPPLANE_RGBX101010:
  96                 bdw_pixel_formats_index = 3;
  97                 break;
  98         case DISPPLANE_BGRX101010:
  99                 bdw_pixel_formats_index = 4;
 100                 break;
 101         case DISPPLANE_RGBX888:
 102                 bdw_pixel_formats_index = 5;
 103                 break;
 104
 105         default:
 106                 break;
 107         }
 108
 109         return bdw_pixel_formats_index;
 110 }
 111
 112 static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
 113         int yuv_order)
 114 {
 115         int skl_pixel_formats_index = 12;
 116
 117         switch (format) {
 118         case PLANE_CTL_FORMAT_INDEXED:
 119                 skl_pixel_formats_index = 4;
 120                 break;
 121         case PLANE_CTL_FORMAT_RGB_565:
 122                 skl_pixel_formats_index = 5;
 123                 break;
 124         case PLANE_CTL_FORMAT_XRGB_8888:
 125                 if (rgb_order)
 126                         skl_pixel_formats_index = alpha ? 6 : 7;
 127                 else
 128                         skl_pixel_formats_index = alpha ? 8 : 9;
 129                 break;
 130         case PLANE_CTL_FORMAT_XRGB_2101010:
 131                 skl_pixel_formats_index = rgb_order ? 10 : 11;
 132                 break;
 133         case PLANE_CTL_FORMAT_YUV422:
 134                 skl_pixel_formats_index = yuv_order >> 16;
 135                 if (skl_pixel_formats_index > 3)
 136                         return -EINVAL;
 137                 break;
 138
 139         default:
 140                 break;
 141         }
 142
 143         return skl_pixel_formats_index;
 144 }
 145
 146 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
 147         u32 tiled, int stride_mask, int bpp)
 148 {
 149         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 150
 151         u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
 152         u32 stride = stride_reg;
 153
 154         if (IS_SKYLAKE(dev_priv)
 155                 || IS_KABYLAKE(dev_priv)
 156                 || IS_BROXTON(dev_priv)) {
 157                 switch (tiled) {
 158                 case PLANE_CTL_TILED_LINEAR:
 159                         stride = stride_reg * 64;
 160                         break;
 161                 case PLANE_CTL_TILED_X:
 162                         stride = stride_reg * 512;
 163                         break;
 164                 case PLANE_CTL_TILED_Y:
 165                         stride = stride_reg * 128;
 166                         break;
 167                 case PLANE_CTL_TILED_YF:
 168                         if (bpp == 8)
 169                                 stride = stride_reg * 64;
 170                         else if (bpp == 16 || bpp == 32 || bpp == 64)
 171                                 stride = stride_reg * 128;
 172                         else
 173                                 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
 174                         break;
 175                 default:
 176                         gvt_dbg_core("skl: unsupported tile format:%x\n",
 177                                 tiled);
 178                 }
 179         }
 180
 181         return stride;
 182 }
 183
 184 static int get_active_pipe(struct intel_vgpu *vgpu)
 185 {
 186         int i;
 187
 188         for (i = 0; i < I915_MAX_PIPES; i++)
 189                 if (pipe_is_enabled(vgpu, i))
 190                         break;
 191
 192         return i;
 193 }
 194
 195 /**
 196  * intel_vgpu_decode_primary_plane - Decode primary plane
 197  * @vgpu: input vgpu
 198  * @plane: primary plane to save decoded info
 199  * This function is called for decoding plane
 200  *
 201  * Returns:
 202  * 0 on success, non-zero if failed.
 203  */
 204 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
 205         struct intel_vgpu_primary_plane_format *plane)
 206 {
 207         u32 val, fmt;
 208         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 209         int pipe;
 210
 211         pipe = get_active_pipe(vgpu);
 212         if (pipe >= I915_MAX_PIPES)
 213                 return -ENODEV;
 214
 215         val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
 216         plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
 217         if (!plane->enabled)
 218                 return -ENODEV;
 219
 220         if (IS_SKYLAKE(dev_priv)
 221                 || IS_KABYLAKE(dev_priv)
 222                 || IS_BROXTON(dev_priv)) {
 223                 plane->tiled = val & PLANE_CTL_TILED_MASK;
 224                 fmt = skl_format_to_drm(
 225                         val & PLANE_CTL_FORMAT_MASK,
 226                         val & PLANE_CTL_ORDER_RGBX,
 227                         val & PLANE_CTL_ALPHA_MASK,
 228                         val & PLANE_CTL_YUV422_ORDER_MASK);
 229
 230                 if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
 231                         gvt_vgpu_err("Out-of-bounds pixel format index\n");
 232                         return -EINVAL;
 233                 }
 234
 235                 plane->bpp = skl_pixel_formats[fmt].bpp;
 236                 plane->drm_format = skl_pixel_formats[fmt].drm_format;
 237         } else {
 238                 plane->tiled = val & DISPPLANE_TILED;
 239                 fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
 240                 plane->bpp = bdw_pixel_formats[fmt].bpp;
 241                 plane->drm_format = bdw_pixel_formats[fmt].drm_format;
 242         }
 243
 244         if (!plane->bpp) {
 245                 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
 246                 return -EINVAL;
 247         }
 248
 249         plane->hw_format = fmt;
 250
 251         plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
 252         if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
 253                 return  -EINVAL;
 254
 255         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
 256         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
 257                 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
 258                                 plane->base);
 259                 return  -EINVAL;
 260         }
 261
 262         plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
 263                 (IS_SKYLAKE(dev_priv)
 264                 || IS_KABYLAKE(dev_priv)
 265                 || IS_BROXTON(dev_priv)) ?
 266                         (_PRI_PLANE_STRIDE_MASK >> 6) :
 267                                 _PRI_PLANE_STRIDE_MASK, plane->bpp);
 268
 269         plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
 270                 _PIPE_H_SRCSZ_SHIFT;
 271         plane->width += 1;
 272         plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
 273                         _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
 274         plane->height += 1;     /* raw height is one minus the real value */
 275
 276         val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
 277         plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
 278                 _PRI_PLANE_X_OFF_SHIFT;
 279         plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
 280                 _PRI_PLANE_Y_OFF_SHIFT;
 281
 282         return 0;
 283 }
 284
 285 #define CURSOR_FORMAT_NUM       (1 << 6)
 286 struct cursor_mode_format {
 287         int     drm_format;     /* Pixel format in DRM definition */
 288         u8      bpp;            /* Bits per pixel; 0 indicates invalid */
 289         u32     width;          /* In pixel */
 290         u32     height;         /* In lines */
 291         char    *desc;          /* The description */
 292 };
 293
 294 static struct cursor_mode_format cursor_pixel_formats[] = {
 295         {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
 296         {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
 297         {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
 298         {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
 299
 300         /* non-supported format has bpp default to 0 */
 301         {0, 0, 0, 0, NULL},
 302 };
 303
 304 static int cursor_mode_to_drm(int mode)
 305 {
 306         int cursor_pixel_formats_index = 4;
 307
 308         switch (mode) {
 309         case MCURSOR_MODE_128_ARGB_AX:
 310                 cursor_pixel_formats_index = 0;
 311                 break;
 312         case MCURSOR_MODE_256_ARGB_AX:
 313                 cursor_pixel_formats_index = 1;
 314                 break;
 315         case MCURSOR_MODE_64_ARGB_AX:
 316                 cursor_pixel_formats_index = 2;
 317                 break;
 318         case MCURSOR_MODE_64_32B_AX:
 319                 cursor_pixel_formats_index = 3;
 320                 break;
 321
 322         default:
 323                 break;
 324         }
 325
 326         return cursor_pixel_formats_index;
 327 }
 328
 329 /**
 330  * intel_vgpu_decode_cursor_plane - Decode sprite plane
 331  * @vgpu: input vgpu
 332  * @plane: cursor plane to save decoded info
 333  * This function is called for decoding plane
 334  *
 335  * Returns:
 336  * 0 on success, non-zero if failed.
 337  */
 338 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
 339         struct intel_vgpu_cursor_plane_format *plane)
 340 {
 341         u32 val, mode, index;
 342         u32 alpha_plane, alpha_force;
 343         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 344         int pipe;
 345
 346         pipe = get_active_pipe(vgpu);
 347         if (pipe >= I915_MAX_PIPES)
 348                 return -ENODEV;
 349
 350         val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
 351         mode = val & MCURSOR_MODE;
 352         plane->enabled = (mode != MCURSOR_MODE_DISABLE);
 353         if (!plane->enabled)
 354                 return -ENODEV;
 355
 356         index = cursor_mode_to_drm(mode);
 357
 358         if (!cursor_pixel_formats[index].bpp) {
 359                 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
 360                 return -EINVAL;
 361         }
 362         plane->mode = mode;
 363         plane->bpp = cursor_pixel_formats[index].bpp;
 364         plane->drm_format = cursor_pixel_formats[index].drm_format;
 365         plane->width = cursor_pixel_formats[index].width;
 366         plane->height = cursor_pixel_formats[index].height;
 367
 368         alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
 369                                 _CURSOR_ALPHA_PLANE_SHIFT;
 370         alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
 371                                 _CURSOR_ALPHA_FORCE_SHIFT;
 372         if (alpha_plane || alpha_force)
 373                 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
 374                         alpha_plane, alpha_force);
 375
 376         plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
 377         if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
 378                 return  -EINVAL;
 379
 380         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
 381         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
 382                 gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
 383                                 plane->base);
 384                 return  -EINVAL;
 385         }
 386
 387         val = vgpu_vreg_t(vgpu, CURPOS(pipe));
 388         plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
 389         plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
 390         plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
 391         plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
 392
 393         plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
 394         plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));
 395         return 0;
 396 }
 397
 398 #define SPRITE_FORMAT_NUM       (1 << 3)
 399
 400 static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
 401         [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
 402         [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
 403         [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
 404         [0x4] = {DRM_FORMAT_AYUV, 32,
 405                 "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
 406 };
 407
 408 /**
 409  * intel_vgpu_decode_sprite_plane - Decode sprite plane
 410  * @vgpu: input vgpu
 411  * @plane: sprite plane to save decoded info
 412  * This function is called for decoding plane
 413  *
 414  * Returns:
 415  * 0 on success, non-zero if failed.
 416  */
 417 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
 418         struct intel_vgpu_sprite_plane_format *plane)
 419 {
 420         u32 val, fmt;
 421         u32 color_order, yuv_order;
 422         int drm_format;
 423         int pipe;
 424
 425         pipe = get_active_pipe(vgpu);
 426         if (pipe >= I915_MAX_PIPES)
 427                 return -ENODEV;
 428
 429         val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
 430         plane->enabled = !!(val & SPRITE_ENABLE);
 431         if (!plane->enabled)
 432                 return -ENODEV;
 433
 434         plane->tiled = !!(val & SPRITE_TILED);
 435         color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
 436         yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
 437                                 _SPRITE_YUV_ORDER_SHIFT;
 438
 439         fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
 440         if (!sprite_pixel_formats[fmt].bpp) {
 441                 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
 442                 return -EINVAL;
 443         }
 444         plane->hw_format = fmt;
 445         plane->bpp = sprite_pixel_formats[fmt].bpp;
 446         drm_format = sprite_pixel_formats[fmt].drm_format;
 447
 448         /* Order of RGB values in an RGBxxx buffer may be ordered RGB or
 449          * BGR depending on the state of the color_order field
 450          */
 451         if (!color_order) {
 452                 if (drm_format == DRM_FORMAT_XRGB2101010)
 453                         drm_format = DRM_FORMAT_XBGR2101010;
 454                 else if (drm_format == DRM_FORMAT_XRGB8888)
 455                         drm_format = DRM_FORMAT_XBGR8888;
 456         }
 457
 458         if (drm_format == DRM_FORMAT_YUV422) {
 459                 switch (yuv_order) {
 460                 case 0:
 461                         drm_format = DRM_FORMAT_YUYV;
 462                         break;
 463                 case 1:
 464                         drm_format = DRM_FORMAT_UYVY;
 465                         break;
 466                 case 2:
 467                         drm_format = DRM_FORMAT_YVYU;
 468                         break;
 469                 case 3:
 470                         drm_format = DRM_FORMAT_VYUY;
 471                         break;
 472                 default:
 473                         /* yuv_order has only 2 bits */
 474                         break;
 475                 }
 476         }
 477
 478         plane->drm_format = drm_format;
 479
 480         plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
 481         if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
 482                 return  -EINVAL;
 483
 484         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
 485         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
 486                 gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n",
 487                                 plane->base);
 488                 return  -EINVAL;
 489         }
 490
 491         plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &
 492                                 _SPRITE_STRIDE_MASK;
 493
 494         val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));
 495         plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
 496                 _SPRITE_SIZE_HEIGHT_SHIFT;
 497         plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
 498                 _SPRITE_SIZE_WIDTH_SHIFT;
 499         plane->height += 1;     /* raw height is one minus the real value */
 500         plane->width += 1;      /* raw width is one minus the real value */
 501
 502         val = vgpu_vreg_t(vgpu, SPRPOS(pipe));
 503         plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
 504         plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
 505
 506         val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));
 507         plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
 508                            _SPRITE_OFFSET_START_X_SHIFT;
 509         plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
 510                            _SPRITE_OFFSET_START_Y_SHIFT;
 511
 512         return 0;
 513 }