2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
38 #define GMBUS1_TOTAL_BYTES_SHIFT 16
39 #define GMBUS1_TOTAL_BYTES_MASK 0x1ff
40 #define gmbus1_total_byte_count(v) (((v) >> \
41 GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
42 #define gmbus1_slave_addr(v) (((v) & 0xff) >> 1)
43 #define gmbus1_slave_index(v) (((v) >> 8) & 0xff)
44 #define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
46 /* GMBUS0 bits definitions */
47 #define _GMBUS_PIN_SEL_MASK (0x7)
49 static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
51 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
52 unsigned char chr = 0;
54 if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {
55 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
58 if (edid->current_edid_read >= EDID_SIZE) {
59 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
63 if (!edid->edid_available) {
64 gvt_vgpu_err("Reading EDID but EDID is not available!\n");
68 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
69 struct intel_vgpu_edid_data *edid_data =
70 intel_vgpu_port(vgpu, edid->port)->edid;
72 chr = edid_data->edid_block[edid->current_edid_read];
73 edid->current_edid_read++;
75 gvt_vgpu_err("No EDID available during the reading?\n");
80 static inline int get_port_from_gmbus0(u32 gmbus0)
82 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
87 else if (port_select == 4)
89 else if (port_select == 5)
91 else if (port_select == 6)
96 static void reset_gmbus_controller(struct intel_vgpu *vgpu)
98 vgpu_vreg(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
99 if (!vgpu->display.i2c_edid.edid_available)
100 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
101 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
105 static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
106 unsigned int offset, void *p_data, unsigned int bytes)
108 int port, pin_select;
110 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
112 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
114 intel_vgpu_init_i2c_edid(vgpu);
119 port = get_port_from_gmbus0(pin_select);
120 if (WARN_ON(port < 0))
123 vgpu->display.i2c_edid.state = I2C_GMBUS;
124 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
126 vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
127 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
129 if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
130 !intel_vgpu_port_is_dp(vgpu, port)) {
131 vgpu->display.i2c_edid.port = port;
132 vgpu->display.i2c_edid.edid_available = true;
133 vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
135 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
139 static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
140 void *p_data, unsigned int bytes)
142 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
144 u32 wvalue = *(u32 *)p_data;
146 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
147 if (!(wvalue & GMBUS_SW_CLR_INT)) {
148 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
149 reset_gmbus_controller(vgpu);
152 * TODO: "This bit is cleared to zero when an event
153 * causes the HW_RDY bit transition to occur "
157 * per bspec setting this bit can cause:
158 * 1) INT status bit cleared
159 * 2) HW_RDY bit asserted
161 if (wvalue & GMBUS_SW_CLR_INT) {
162 vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
163 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
166 /* For virtualization, we suppose that HW is always ready,
167 * so GMBUS_SW_RDY should always be cleared
169 if (wvalue & GMBUS_SW_RDY)
170 wvalue &= ~GMBUS_SW_RDY;
172 i2c_edid->gmbus.total_byte_count =
173 gmbus1_total_byte_count(wvalue);
174 slave_addr = gmbus1_slave_addr(wvalue);
176 /* vgpu gmbus only support EDID */
177 if (slave_addr == EDID_ADDR) {
178 i2c_edid->slave_selected = true;
179 } else if (slave_addr != 0) {
181 "vgpu%d: unsupported gmbus slave addr(0x%x)\n"
182 " gmbus operations will be ignored.\n",
183 vgpu->id, slave_addr);
186 if (wvalue & GMBUS_CYCLE_INDEX)
187 i2c_edid->current_edid_read =
188 gmbus1_slave_index(wvalue);
190 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
191 switch (gmbus1_bus_cycle(wvalue)) {
196 * This can only cause a STOP to be generated
197 * if a GMBUS cycle is generated, the GMBUS is
198 * currently in a data/wait/idle phase, or it is in a
201 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
203 intel_vgpu_init_i2c_edid(vgpu);
204 /* After the 'stop' cycle, hw state would become
205 * 'stop phase' and then 'idle phase' after a
206 * few milliseconds. In emulation, we just set
207 * it as 'idle phase' ('stop phase' is not
208 * visible in gmbus interface)
210 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
211 vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
218 /* From hw spec the GMBUS phase
219 * transition like this:
220 * START (-->INDEX) -->DATA
222 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
223 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
226 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
230 * From hw spec the WAIT state will be
232 * (1) in a new GMBUS cycle
233 * (2) by generating a stop
235 vgpu_vreg(vgpu, offset) = wvalue;
240 static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
241 void *p_data, unsigned int bytes)
247 static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
248 void *p_data, unsigned int bytes)
251 unsigned char byte_data;
252 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
253 int byte_left = i2c_edid->gmbus.total_byte_count -
254 i2c_edid->current_edid_read;
255 int byte_count = byte_left;
258 /* Data can only be recevied if previous settings correct */
259 if (vgpu_vreg(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
260 if (byte_left <= 0) {
261 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
267 for (i = 0; i < byte_count; i++) {
268 byte_data = edid_get_byte(vgpu);
269 reg_data |= (byte_data << (i << 3));
272 memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count);
273 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
275 if (byte_left <= 4) {
276 switch (i2c_edid->gmbus.cycle_type) {
279 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
284 i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
287 intel_vgpu_init_i2c_edid(vgpu);
290 * Read GMBUS3 during send operation,
291 * return the latest written value
294 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
295 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
300 static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
301 void *p_data, unsigned int bytes)
303 u32 value = vgpu_vreg(vgpu, offset);
305 if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
306 vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
307 memcpy(p_data, (void *)&value, bytes);
311 static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
312 void *p_data, unsigned int bytes)
314 u32 wvalue = *(u32 *)p_data;
316 if (wvalue & GMBUS_INUSE)
317 vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
318 /* All other bits are read-only */
323 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
326 * This function is used to emulate gmbus register mmio read
329 * Zero on success, negative error code if failed.
332 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
333 unsigned int offset, void *p_data, unsigned int bytes)
335 if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
338 if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
339 return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
340 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
341 return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
343 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
348 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
351 * This function is used to emulate gmbus register mmio write
354 * Zero on success, negative error code if failed.
357 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
358 unsigned int offset, void *p_data, unsigned int bytes)
360 if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
363 if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
364 return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
365 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
366 return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
367 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
368 return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
369 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
370 return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
372 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
385 static inline int get_aux_ch_reg(unsigned int offset)
389 switch (offset & 0xff) {
415 #define AUX_CTL_MSG_LENGTH(reg) \
416 ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \
417 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)
420 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
423 * This function is used to emulate AUX channel register write
426 void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
431 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
432 int msg_length, ret_msg_size;
433 int msg, addr, ctrl, op;
434 u32 value = *(u32 *)p_data;
435 int aux_data_for_write = 0;
436 int reg = get_aux_ch_reg(offset);
438 if (reg != AUX_CH_CTL) {
439 vgpu_vreg(vgpu, offset) = value;
443 msg_length = AUX_CTL_MSG_LENGTH(value);
444 // check the msg in DATA register.
445 msg = vgpu_vreg(vgpu, offset + 4);
446 addr = (msg >> 8) & 0xffff;
447 ctrl = (msg >> 24) & 0xff;
449 if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {
450 /* The ctl write to clear some states */
454 /* Always set the wanted value for vms. */
455 ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
456 vgpu_vreg(vgpu, offset) =
458 ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) &
459 DP_AUX_CH_CTL_MESSAGE_SIZE_MASK);
461 if (msg_length == 3) {
462 if (!(op & GVT_AUX_I2C_MOT)) {
464 intel_vgpu_init_i2c_edid(vgpu);
466 /* start or restart */
467 i2c_edid->aux_ch.i2c_over_aux_ch = true;
468 i2c_edid->aux_ch.aux_ch_mot = true;
470 /* reset the address */
471 intel_vgpu_init_i2c_edid(vgpu);
472 } else if (addr == EDID_ADDR) {
473 i2c_edid->state = I2C_AUX_CH;
474 i2c_edid->port = port_idx;
475 i2c_edid->slave_selected = true;
476 if (intel_vgpu_has_monitor_on_port(vgpu,
478 intel_vgpu_port_is_dp(vgpu, port_idx))
479 i2c_edid->edid_available = true;
482 } else if ((op & 0x1) == GVT_AUX_I2C_WRITE) {
484 * We only support EDID reading from I2C_over_AUX. And
485 * we do not expect the index mode to be used. Right now
486 * the WRITE operation is ignored. It is good enough to
487 * support the gfx driver to do EDID access.
490 if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))
492 if (WARN_ON(msg_length != 4))
494 if (i2c_edid->edid_available && i2c_edid->slave_selected) {
495 unsigned char val = edid_get_byte(vgpu);
497 aux_data_for_write = (val << 16);
499 aux_data_for_write = (0xff << 16);
501 /* write the return value in AUX_CH_DATA reg which includes:
503 * returned byte if it is READ
505 aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24;
506 vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
510 * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
513 * This function is used to initialize vGPU i2c edid emulation stuffs
516 void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
518 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
520 edid->state = I2C_NOT_SPECIFIED;
523 edid->slave_selected = false;
524 edid->edid_available = false;
525 edid->current_edid_read = 0;
527 memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));
529 edid->aux_ch.i2c_over_aux_ch = false;
530 edid->aux_ch.aux_ch_mot = false;