2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
38 static int get_edp_pipe(struct intel_vgpu *vgpu)
40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
43 switch (data & TRANS_DDI_EDP_INPUT_MASK) {
44 case TRANS_DDI_EDP_INPUT_A_ON:
45 case TRANS_DDI_EDP_INPUT_A_ONOFF:
48 case TRANS_DDI_EDP_INPUT_B_ONOFF:
51 case TRANS_DDI_EDP_INPUT_C_ONOFF:
58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
60 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
62 if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
70 static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
72 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
74 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
77 if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
80 if (edp_pipe_is_enabled(vgpu) &&
81 get_edp_pipe(vgpu) == pipe)
86 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
88 /* EDID with 1024x768 as its resolution */
90 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
91 /* Vendor & Product Identification */
92 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
93 /* Version & Revision */
95 /* Basic Display Parameters & Features */
96 0xa5, 0x34, 0x20, 0x78, 0x23,
97 /* Color Characteristics */
98 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
99 /* Established Timings: maximum resolution is 1024x768 */
101 /* Standard Timings. All invalid */
102 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
103 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
104 /* 18 Byte Data Blocks 1: invalid */
105 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
106 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
107 /* 18 Byte Data Blocks 2: invalid */
108 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
109 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
110 /* 18 Byte Data Blocks 3: invalid */
111 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
112 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
113 /* 18 Byte Data Blocks 4: invalid */
114 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
115 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
116 /* Extension Block Count */
122 /* EDID with 1920x1200 as its resolution */
124 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
125 /* Vendor & Product Identification */
126 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
127 /* Version & Revision */
129 /* Basic Display Parameters & Features */
130 0xa5, 0x34, 0x20, 0x78, 0x23,
131 /* Color Characteristics */
132 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
133 /* Established Timings: maximum resolution is 1024x768 */
137 * below new resolutions can be supported:
138 * 1920x1080, 1280x720, 1280x960, 1280x1024,
139 * 1440x900, 1600x1200, 1680x1050
141 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
142 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
143 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
144 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
145 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
146 /* 18 Byte Data Blocks 2: invalid */
147 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
148 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
149 /* 18 Byte Data Blocks 3: invalid */
150 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
151 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
152 /* 18 Byte Data Blocks 4: invalid */
153 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
154 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
155 /* Extension Block Count */
162 #define DPCD_HEADER_SIZE 0xb
164 /* let the virtual display supports DP1.2 */
165 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
166 0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
169 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
171 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
172 vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
173 SDE_PORTC_HOTPLUG_CPT |
174 SDE_PORTD_HOTPLUG_CPT);
176 if (IS_SKYLAKE(dev_priv)) {
177 vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
178 SDE_PORTE_HOTPLUG_SPT);
179 vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
180 SKL_FUSE_DOWNLOAD_STATUS |
181 SKL_FUSE_PG0_DIST_STATUS |
182 SKL_FUSE_PG1_DIST_STATUS |
183 SKL_FUSE_PG2_DIST_STATUS;
184 vgpu_vreg(vgpu, LCPLL1_CTL) |=
187 vgpu_vreg(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;
191 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
192 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
193 vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
196 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
197 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
198 vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
201 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
202 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
203 vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
206 if (IS_SKYLAKE(dev_priv) &&
207 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
208 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
211 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
212 if (IS_BROADWELL(dev_priv))
213 vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |=
214 GEN8_PORT_DP_A_HOTPLUG;
216 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
218 vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
222 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
224 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
233 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
234 int type, unsigned int resolution)
236 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
238 if (WARN_ON(resolution >= GVT_EDID_NUM))
241 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
245 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
251 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
253 port->edid->data_valid = true;
255 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
256 port->dpcd->data_valid = true;
257 port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
260 emulate_monitor_status_change(vgpu);
265 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
266 * be turned on/off when a virtual pipe is enabled/disabled.
269 * This function is used to turn on/off vblank timer according to currently
270 * enabled/disabled virtual pipes.
273 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
275 struct intel_gvt_irq *irq = &gvt->irq;
276 struct intel_vgpu *vgpu;
277 bool have_enabled_pipe = false;
280 if (WARN_ON(!mutex_is_locked(&gvt->lock)))
283 hrtimer_cancel(&irq->vblank_timer.timer);
285 for_each_active_vgpu(gvt, vgpu, id) {
286 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
288 pipe_is_enabled(vgpu, pipe);
289 if (have_enabled_pipe)
294 if (have_enabled_pipe)
295 hrtimer_start(&irq->vblank_timer.timer,
296 ktime_add_ns(ktime_get(), irq->vblank_timer.period),
300 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
302 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
303 struct intel_vgpu_irq *irq = &vgpu->irq;
304 int vblank_event[] = {
305 [PIPE_A] = PIPE_A_VBLANK,
306 [PIPE_B] = PIPE_B_VBLANK,
307 [PIPE_C] = PIPE_C_VBLANK,
311 if (pipe < PIPE_A || pipe > PIPE_C)
314 for_each_set_bit(event, irq->flip_done_event[pipe],
315 INTEL_GVT_EVENT_MAX) {
316 clear_bit(event, irq->flip_done_event[pipe]);
317 if (!pipe_is_enabled(vgpu, pipe))
320 vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
321 intel_vgpu_trigger_virtual_event(vgpu, event);
324 if (pipe_is_enabled(vgpu, pipe)) {
325 vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
326 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
330 static void emulate_vblank(struct intel_vgpu *vgpu)
334 for_each_pipe(vgpu->gvt->dev_priv, pipe)
335 emulate_vblank_on_pipe(vgpu, pipe);
339 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
342 * This function is used to trigger vblank interrupts for vGPUs on GVT device
345 void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
347 struct intel_vgpu *vgpu;
350 if (WARN_ON(!mutex_is_locked(&gvt->lock)))
353 for_each_active_vgpu(gvt, vgpu, id)
354 emulate_vblank(vgpu);
358 * intel_vgpu_clean_display - clean vGPU virtual display emulation
361 * This function is used to clean vGPU virtual display emulation stuffs
364 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
366 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
368 if (IS_SKYLAKE(dev_priv))
369 clean_virtual_dp_monitor(vgpu, PORT_D);
371 clean_virtual_dp_monitor(vgpu, PORT_B);
375 * intel_vgpu_init_display- initialize vGPU virtual display emulation
378 * This function is used to initialize vGPU virtual display emulation stuffs
381 * Zero on success, negative error code if failed.
384 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
386 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
388 intel_vgpu_init_i2c_edid(vgpu);
390 if (IS_SKYLAKE(dev_priv))
391 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
394 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
399 * intel_vgpu_reset_display- reset vGPU virtual display emulation
402 * This function is used to reset vGPU virtual display emulation stuffs
405 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
407 emulate_monitor_status_change(vgpu);