2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Kevin Tian <kevin.tian@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
29 * Min He <min.he@intel.com>
30 * Ping Gao <ping.a.gao@intel.com>
31 * Tina Zhang <tina.zhang@intel.com>
32 * Yulei Zhang <yulei.zhang@intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
37 #include <linux/slab.h>
40 #include "i915_pvinfo.h"
43 #define INVALID_OP (~0U)
47 #define OP_LEN_3D_MEDIA 16
48 #define OP_LEN_MFX_VC 16
49 #define OP_LEN_VEBOX 16
51 #define CMD_TYPE(cmd) (((cmd) >> 29) & 7)
61 const struct sub_op_bits *sub_op;
64 #define MAX_CMD_BUDGET 0x7fffffff
65 #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15)
66 #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9)
67 #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1)
69 #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20)
70 #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10)
71 #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2)
73 /* Render Command Map */
75 /* MI_* command Opcode (28:23) */
76 #define OP_MI_NOOP 0x0
77 #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */
78 #define OP_MI_USER_INTERRUPT 0x2
79 #define OP_MI_WAIT_FOR_EVENT 0x3
80 #define OP_MI_FLUSH 0x4
81 #define OP_MI_ARB_CHECK 0x5
82 #define OP_MI_RS_CONTROL 0x6 /* HSW+ */
83 #define OP_MI_REPORT_HEAD 0x7
84 #define OP_MI_ARB_ON_OFF 0x8
85 #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */
86 #define OP_MI_BATCH_BUFFER_END 0xA
87 #define OP_MI_SUSPEND_FLUSH 0xB
88 #define OP_MI_PREDICATE 0xC /* IVB+ */
89 #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */
90 #define OP_MI_SET_APPID 0xE /* IVB+ */
91 #define OP_MI_RS_CONTEXT 0xF /* HSW+ */
92 #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */
93 #define OP_MI_DISPLAY_FLIP 0x14
94 #define OP_MI_SEMAPHORE_MBOX 0x16
95 #define OP_MI_SET_CONTEXT 0x18
96 #define OP_MI_MATH 0x1A
97 #define OP_MI_URB_CLEAR 0x19
98 #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */
99 #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */
101 #define OP_MI_STORE_DATA_IMM 0x20
102 #define OP_MI_STORE_DATA_INDEX 0x21
103 #define OP_MI_LOAD_REGISTER_IMM 0x22
104 #define OP_MI_UPDATE_GTT 0x23
105 #define OP_MI_STORE_REGISTER_MEM 0x24
106 #define OP_MI_FLUSH_DW 0x26
107 #define OP_MI_CLFLUSH 0x27
108 #define OP_MI_REPORT_PERF_COUNT 0x28
109 #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */
110 #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */
111 #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */
112 #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */
113 #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */
114 #define OP_MI_2E 0x2E /* BDW+ */
115 #define OP_MI_2F 0x2F /* BDW+ */
116 #define OP_MI_BATCH_BUFFER_START 0x31
118 /* Bit definition for dword 0 */
119 #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8)
121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36
123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
125 #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U)
126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U)
128 /* 2D command: Opcode (28:22) */
129 #define OP_2D(x) ((2<<7) | x)
131 #define OP_XY_SETUP_BLT OP_2D(0x1)
132 #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3)
133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11)
134 #define OP_XY_PIXEL_BLT OP_2D(0x24)
135 #define OP_XY_SCANLINES_BLT OP_2D(0x25)
136 #define OP_XY_TEXT_BLT OP_2D(0x26)
137 #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31)
138 #define OP_XY_COLOR_BLT OP_2D(0x50)
139 #define OP_XY_PAT_BLT OP_2D(0x51)
140 #define OP_XY_MONO_PAT_BLT OP_2D(0x52)
141 #define OP_XY_SRC_COPY_BLT OP_2D(0x53)
142 #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54)
143 #define OP_XY_FULL_BLT OP_2D(0x55)
144 #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56)
145 #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57)
146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58)
147 #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59)
148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71)
149 #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72)
150 #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73)
151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74)
152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75)
153 #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76)
154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77)
156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
158 ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
160 #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03)
162 #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01)
163 #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02)
164 #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04)
166 #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B)
168 #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04)
170 #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0)
171 #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1)
172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2)
173 #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3)
174 #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4)
175 #define OP_MEDIA_POOL_STATE OP_3D_MEDIA(0x2, 0x0, 0x5)
177 #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0)
178 #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2)
179 #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3)
180 #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5)
182 #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
183 #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
184 #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
185 #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
186 #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08)
187 #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09)
188 #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A)
189 #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B)
190 #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */
191 #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E)
192 #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F)
193 #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10)
194 #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11)
195 #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12)
196 #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13)
197 #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14)
198 #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15)
199 #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16)
200 #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17)
201 #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18)
202 #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
203 #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
204 #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
205 #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
206 #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
207 #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
208 #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
209 #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
211 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
212 #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
213 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
218 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
223 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
224 #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
225 #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
226 #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
227 #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
228 #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
229 #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
230 #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
232 #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
233 #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
234 #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
235 #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
238 #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
239 #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
240 #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
242 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
243 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
244 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
245 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
247 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
249 #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
250 #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
251 #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
252 #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
253 #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
254 #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
255 #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
256 #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
257 #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
258 #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
259 #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
261 #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
262 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02)
263 #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04)
264 #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05)
265 #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06)
266 #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07)
267 #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08)
268 #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A)
269 #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B)
270 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C)
271 #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D)
272 #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E)
273 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F)
274 #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10)
275 #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11)
276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
280 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
281 #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17)
282 #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18)
283 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
284 #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
285 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
286 #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C)
287 #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00)
288 #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00)
290 /* VCCP Command Parser */
293 * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
294 * git://anongit.freedesktop.org/vaapi/intel-driver
299 #define OP_MFX(pipeline, op, sub_opa, sub_opb) \
306 #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */
307 #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */
308 #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */
309 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */
310 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */
311 #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */
312 #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */
313 #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */
314 #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */
315 #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */
316 #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */
318 #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */
320 #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */
321 #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */
322 #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */
323 #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */
324 #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */
325 #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */
326 #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */
327 #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */
328 #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */
329 #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */
330 #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */
331 #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */
333 #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */
334 #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */
335 #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */
336 #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */
337 #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */
339 #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */
340 #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */
341 #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */
342 #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */
343 #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */
345 #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */
346 #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */
347 #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */
349 #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0)
350 #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2)
351 #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8)
353 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
360 #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0)
361 #define OP_VEB_STATE OP_VEB(2, 4, 0, 2)
362 #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3)
364 struct parser_exec_state;
366 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
368 #define GVT_CMD_HASH_BITS 7
370 /* which DWords need address fix */
371 #define ADDR_FIX_1(x1) (1 << (x1))
372 #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
373 #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
374 #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
375 #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
381 #define F_LEN_MASK (1U<<0)
382 #define F_LEN_CONST 1U
386 * command has its own ip advance logic
387 * e.g. MI_BATCH_START, MI_BATCH_END
389 #define F_IP_ADVANCE_CUSTOM (1<<1)
391 #define F_POST_HANDLE (1<<2)
394 #define R_RCS BIT(RCS0)
395 #define R_VCS1 BIT(VCS0)
396 #define R_VCS2 BIT(VCS1)
397 #define R_VCS (R_VCS1 | R_VCS2)
398 #define R_BCS BIT(BCS0)
399 #define R_VECS BIT(VECS0)
400 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
401 /* rings that support this cmd: BLT/RCS/VCS/VECS */
404 /* devices that support this cmd: SNB/IVB/HSW/... */
407 /* which DWords are address that need fix up.
408 * bit 0 means a 32-bit non address operand in command
409 * bit 1 means address operand, which could be 32-bit
410 * or 64-bit depending on different architectures.(
411 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
412 * No matter the address length, each address only takes
413 * one bit in the bitmap.
417 /* flag == F_LEN_CONST : command length
418 * flag == F_LEN_VAR : length bias bits
419 * Note: length is in DWord
423 parser_cmd_handler handler;
427 struct hlist_node hlist;
428 const struct cmd_info *info;
432 RING_BUFFER_INSTRUCTION,
433 BATCH_BUFFER_INSTRUCTION,
434 BATCH_BUFFER_2ND_LEVEL,
442 struct parser_exec_state {
443 struct intel_vgpu *vgpu;
448 /* batch buffer address type */
451 /* graphics memory address of ring buffer start */
452 unsigned long ring_start;
453 unsigned long ring_size;
454 unsigned long ring_head;
455 unsigned long ring_tail;
457 /* instruction graphics memory address */
458 unsigned long ip_gma;
460 /* mapped va of the instr_gma */
465 /* next instruction when return from batch buffer to ring buffer */
466 unsigned long ret_ip_gma_ring;
468 /* next instruction when return from 2nd batch buffer to batch buffer */
469 unsigned long ret_ip_gma_bb;
471 /* batch buffer address type (GTT or PPGTT)
472 * used when ret from 2nd level batch buffer
474 int saved_buf_addr_type;
477 const struct cmd_info *info;
479 struct intel_vgpu_workload *workload;
482 #define gmadr_dw_number(s) \
483 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
485 static unsigned long bypass_scan_mask = 0;
487 /* ring ALL, type = 0 */
488 static const struct sub_op_bits sub_op_mi[] = {
493 static const struct decode_info decode_info_mi = {
496 ARRAY_SIZE(sub_op_mi),
500 /* ring RCS, command type 2 */
501 static const struct sub_op_bits sub_op_2d[] = {
506 static const struct decode_info decode_info_2d = {
509 ARRAY_SIZE(sub_op_2d),
513 /* ring RCS, command type 3 */
514 static const struct sub_op_bits sub_op_3d_media[] = {
521 static const struct decode_info decode_info_3d_media = {
524 ARRAY_SIZE(sub_op_3d_media),
528 /* ring VCS, command type 3 */
529 static const struct sub_op_bits sub_op_mfx_vc[] = {
537 static const struct decode_info decode_info_mfx_vc = {
540 ARRAY_SIZE(sub_op_mfx_vc),
544 /* ring VECS, command type 3 */
545 static const struct sub_op_bits sub_op_vebox[] = {
553 static const struct decode_info decode_info_vebox = {
556 ARRAY_SIZE(sub_op_vebox),
560 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
565 &decode_info_3d_media,
617 static inline u32 get_opcode(u32 cmd, int ring_id)
619 const struct decode_info *d_info;
621 d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
625 return cmd >> (32 - d_info->op_len);
628 static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
629 unsigned int opcode, int ring_id)
633 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
634 if (opcode == e->info->opcode && e->info->rings & BIT(ring_id))
640 static inline const struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
641 u32 cmd, int ring_id)
645 opcode = get_opcode(cmd, ring_id);
646 if (opcode == INVALID_OP)
649 return find_cmd_entry(gvt, opcode, ring_id);
652 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
654 return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
657 static inline void print_opcode(u32 cmd, int ring_id)
659 const struct decode_info *d_info;
662 d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
666 gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
667 cmd >> (32 - d_info->op_len), d_info->name);
669 for (i = 0; i < d_info->nr_sub_op; i++)
670 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
671 d_info->sub_op[i].low));
676 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
678 return s->ip_va + (index << 2);
681 static inline u32 cmd_val(struct parser_exec_state *s, int index)
683 return *cmd_ptr(s, index);
686 static void parser_exec_state_dump(struct parser_exec_state *s)
691 gvt_dbg_cmd(" vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
692 " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
693 s->ring_id, s->ring_start, s->ring_start + s->ring_size,
694 s->ring_head, s->ring_tail);
696 gvt_dbg_cmd(" %s %s ip_gma(%08lx) ",
697 s->buf_type == RING_BUFFER_INSTRUCTION ?
698 "RING_BUFFER" : "BATCH_BUFFER",
699 s->buf_addr_type == GTT_BUFFER ?
700 "GTT" : "PPGTT", s->ip_gma);
702 if (s->ip_va == NULL) {
703 gvt_dbg_cmd(" ip_va(NULL)");
707 gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n",
708 s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
709 cmd_val(s, 2), cmd_val(s, 3));
711 print_opcode(cmd_val(s, 0), s->ring_id);
713 s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
716 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
717 for (i = 0; i < 8; i++)
718 gvt_dbg_cmd("%08x ", cmd_val(s, i));
721 s->ip_va += 8 * sizeof(u32);
726 static inline void update_ip_va(struct parser_exec_state *s)
728 unsigned long len = 0;
730 if (WARN_ON(s->ring_head == s->ring_tail))
733 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
734 unsigned long ring_top = s->ring_start + s->ring_size;
736 if (s->ring_head > s->ring_tail) {
737 if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
738 len = (s->ip_gma - s->ring_head);
739 else if (s->ip_gma >= s->ring_start &&
740 s->ip_gma <= s->ring_tail)
741 len = (ring_top - s->ring_head) +
742 (s->ip_gma - s->ring_start);
744 len = (s->ip_gma - s->ring_head);
746 s->ip_va = s->rb_va + len;
747 } else {/* shadow batch buffer */
748 s->ip_va = s->ret_bb_va;
752 static inline int ip_gma_set(struct parser_exec_state *s,
753 unsigned long ip_gma)
755 WARN_ON(!IS_ALIGNED(ip_gma, 4));
762 static inline int ip_gma_advance(struct parser_exec_state *s,
765 s->ip_gma += (dw_len << 2);
767 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
768 if (s->ip_gma >= s->ring_start + s->ring_size)
769 s->ip_gma -= s->ring_size;
772 s->ip_va += (dw_len << 2);
778 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
780 if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
783 return (cmd & ((1U << info->len) - 1)) + 2;
787 static inline int cmd_length(struct parser_exec_state *s)
789 return get_cmd_length(s->info, cmd_val(s, 0));
792 /* do not remove this, some platform may need clflush here */
793 #define patch_value(s, addr, val) do { \
797 static bool is_shadowed_mmio(unsigned int offset)
801 if ((offset == 0x2168) || /*BB current head register UDW */
802 (offset == 0x2140) || /*BB current header register */
803 (offset == 0x211c) || /*second BB header register UDW */
804 (offset == 0x2114)) { /*second BB header register UDW */
810 static inline bool is_force_nonpriv_mmio(unsigned int offset)
812 return (offset >= 0x24d0 && offset < 0x2500);
815 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
816 unsigned int offset, unsigned int index, char *cmd)
818 struct intel_gvt *gvt = s->vgpu->gvt;
822 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
824 if (!strcmp(cmd, "lri"))
825 data = cmd_val(s, index + 1);
827 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
832 ring_base = dev_priv->engine[s->ring_id]->mmio_base;
833 nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
835 if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
837 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
839 patch_value(s, cmd_ptr(s, index), nopid);
845 static inline bool is_mocs_mmio(unsigned int offset)
847 return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
848 ((offset >= 0xb020) && (offset <= 0xb0a0));
851 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
852 unsigned int offset, unsigned int index)
854 if (!is_mocs_mmio(offset))
856 vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
860 static int cmd_reg_handler(struct parser_exec_state *s,
861 unsigned int offset, unsigned int index, char *cmd)
863 struct intel_vgpu *vgpu = s->vgpu;
864 struct intel_gvt *gvt = vgpu->gvt;
867 if (offset + 4 > gvt->device_info.mmio_size) {
868 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
873 if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
874 gvt_vgpu_err("%s access to non-render register (%x)\n",
879 if (is_shadowed_mmio(offset)) {
880 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
884 if (is_mocs_mmio(offset) &&
885 mocs_cmd_reg_handler(s, offset, index))
888 if (is_force_nonpriv_mmio(offset) &&
889 force_nonpriv_reg_handler(s, offset, index, cmd))
892 if (offset == i915_mmio_reg_offset(DERRMR) ||
893 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
894 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
895 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
899 * Right now only scan LRI command on KBL and in inhibit context.
900 * It's good enough to support initializing mmio by lri command in
901 * vgpu inhibit context on KBL.
903 if ((IS_KABYLAKE(s->vgpu->gvt->dev_priv)
904 || IS_COFFEELAKE(s->vgpu->gvt->dev_priv)) &&
905 intel_gvt_mmio_is_in_ctx(gvt, offset) &&
906 !strncmp(cmd, "lri", 3)) {
907 intel_gvt_hypervisor_read_gpa(s->vgpu,
908 s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
909 /* check inhibit context */
910 if (ctx_sr_ctl & 1) {
911 u32 data = cmd_val(s, index + 1);
913 if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
914 intel_vgpu_mask_mmio_write(vgpu,
917 vgpu_vreg(vgpu, offset) = data;
921 /* TODO: Update the global mask if this MMIO is a masked-MMIO */
922 intel_gvt_mmio_set_cmd_accessed(gvt, offset);
926 #define cmd_reg(s, i) \
927 (cmd_val(s, i) & GENMASK(22, 2))
929 #define cmd_reg_inhibit(s, i) \
930 (cmd_val(s, i) & GENMASK(22, 18))
932 #define cmd_gma(s, i) \
933 (cmd_val(s, i) & GENMASK(31, 2))
935 #define cmd_gma_hi(s, i) \
936 (cmd_val(s, i) & GENMASK(15, 0))
938 static int cmd_handler_lri(struct parser_exec_state *s)
941 int cmd_len = cmd_length(s);
942 struct intel_gvt *gvt = s->vgpu->gvt;
944 for (i = 1; i < cmd_len; i += 2) {
945 if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) {
946 if (s->ring_id == BCS0 &&
947 cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
950 ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
954 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
961 static int cmd_handler_lrr(struct parser_exec_state *s)
964 int cmd_len = cmd_length(s);
966 for (i = 1; i < cmd_len; i += 2) {
967 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
968 ret |= ((cmd_reg_inhibit(s, i) ||
969 (cmd_reg_inhibit(s, i + 1)))) ?
973 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
976 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
983 static inline int cmd_address_audit(struct parser_exec_state *s,
984 unsigned long guest_gma, int op_size, bool index_mode);
986 static int cmd_handler_lrm(struct parser_exec_state *s)
988 struct intel_gvt *gvt = s->vgpu->gvt;
989 int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
992 int cmd_len = cmd_length(s);
994 for (i = 1; i < cmd_len;) {
995 if (IS_BROADWELL(gvt->dev_priv))
996 ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
999 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1002 if (cmd_val(s, 0) & (1 << 22)) {
1003 gma = cmd_gma(s, i + 1);
1004 if (gmadr_bytes == 8)
1005 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1006 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1010 i += gmadr_dw_number(s) + 1;
1015 static int cmd_handler_srm(struct parser_exec_state *s)
1017 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1020 int cmd_len = cmd_length(s);
1022 for (i = 1; i < cmd_len;) {
1023 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1026 if (cmd_val(s, 0) & (1 << 22)) {
1027 gma = cmd_gma(s, i + 1);
1028 if (gmadr_bytes == 8)
1029 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1030 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1034 i += gmadr_dw_number(s) + 1;
1039 struct cmd_interrupt_event {
1040 int pipe_control_notify;
1042 int mi_user_interrupt;
1045 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1047 .pipe_control_notify = RCS_PIPE_CONTROL,
1048 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1049 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1052 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1053 .mi_flush_dw = BCS_MI_FLUSH_DW,
1054 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1057 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1058 .mi_flush_dw = VCS_MI_FLUSH_DW,
1059 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1062 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1063 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1064 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1067 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1068 .mi_flush_dw = VECS_MI_FLUSH_DW,
1069 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1073 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1075 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1077 bool index_mode = false;
1078 unsigned int post_sync;
1082 post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1085 if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1086 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1088 else if (post_sync) {
1090 ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1091 else if (post_sync == 3)
1092 ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1093 else if (post_sync == 1) {
1095 if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1096 gma = cmd_val(s, 2) & GENMASK(31, 3);
1097 if (gmadr_bytes == 8)
1098 gma |= (cmd_gma_hi(s, 3)) << 32;
1099 /* Store Data Index */
1100 if (cmd_val(s, 1) & (1 << 21))
1102 ret |= cmd_address_audit(s, gma, sizeof(u64),
1107 hws_pga = s->vgpu->hws_pga[s->ring_id];
1108 gma = hws_pga + gma;
1109 patch_value(s, cmd_ptr(s, 2), gma);
1110 val = cmd_val(s, 1) & (~(1 << 21));
1111 patch_value(s, cmd_ptr(s, 1), val);
1120 if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1121 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1122 s->workload->pending_events);
1126 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1128 set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1129 s->workload->pending_events);
1130 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1134 static int cmd_advance_default(struct parser_exec_state *s)
1136 return ip_gma_advance(s, cmd_length(s));
1139 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1143 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1144 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1145 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1146 s->buf_addr_type = s->saved_buf_addr_type;
1148 s->buf_type = RING_BUFFER_INSTRUCTION;
1149 s->buf_addr_type = GTT_BUFFER;
1150 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1151 s->ret_ip_gma_ring -= s->ring_size;
1152 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1157 struct mi_display_flip_command_info {
1161 i915_reg_t stride_reg;
1162 i915_reg_t ctrl_reg;
1163 i915_reg_t surf_reg;
1170 struct plane_code_mapping {
1176 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1177 struct mi_display_flip_command_info *info)
1179 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1180 struct plane_code_mapping gen8_plane_code[] = {
1181 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1182 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1183 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1184 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1185 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1186 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1188 u32 dword0, dword1, dword2;
1191 dword0 = cmd_val(s, 0);
1192 dword1 = cmd_val(s, 1);
1193 dword2 = cmd_val(s, 2);
1195 v = (dword0 & GENMASK(21, 19)) >> 19;
1196 if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1199 info->pipe = gen8_plane_code[v].pipe;
1200 info->plane = gen8_plane_code[v].plane;
1201 info->event = gen8_plane_code[v].event;
1202 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1203 info->tile_val = (dword1 & 0x1);
1204 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1205 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1207 if (info->plane == PLANE_A) {
1208 info->ctrl_reg = DSPCNTR(info->pipe);
1209 info->stride_reg = DSPSTRIDE(info->pipe);
1210 info->surf_reg = DSPSURF(info->pipe);
1211 } else if (info->plane == PLANE_B) {
1212 info->ctrl_reg = SPRCTL(info->pipe);
1213 info->stride_reg = SPRSTRIDE(info->pipe);
1214 info->surf_reg = SPRSURF(info->pipe);
1222 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1223 struct mi_display_flip_command_info *info)
1225 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1226 struct intel_vgpu *vgpu = s->vgpu;
1227 u32 dword0 = cmd_val(s, 0);
1228 u32 dword1 = cmd_val(s, 1);
1229 u32 dword2 = cmd_val(s, 2);
1230 u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1232 info->plane = PRIMARY_PLANE;
1235 case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1236 info->pipe = PIPE_A;
1237 info->event = PRIMARY_A_FLIP_DONE;
1239 case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1240 info->pipe = PIPE_B;
1241 info->event = PRIMARY_B_FLIP_DONE;
1243 case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1244 info->pipe = PIPE_C;
1245 info->event = PRIMARY_C_FLIP_DONE;
1248 case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1249 info->pipe = PIPE_A;
1250 info->event = SPRITE_A_FLIP_DONE;
1251 info->plane = SPRITE_PLANE;
1253 case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1254 info->pipe = PIPE_B;
1255 info->event = SPRITE_B_FLIP_DONE;
1256 info->plane = SPRITE_PLANE;
1258 case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1259 info->pipe = PIPE_C;
1260 info->event = SPRITE_C_FLIP_DONE;
1261 info->plane = SPRITE_PLANE;
1265 gvt_vgpu_err("unknown plane code %d\n", plane);
1269 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1270 info->tile_val = (dword1 & GENMASK(2, 0));
1271 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1272 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1274 info->ctrl_reg = DSPCNTR(info->pipe);
1275 info->stride_reg = DSPSTRIDE(info->pipe);
1276 info->surf_reg = DSPSURF(info->pipe);
1281 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1282 struct mi_display_flip_command_info *info)
1284 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1287 if (!info->async_flip)
1290 if (INTEL_GEN(dev_priv) >= 9) {
1291 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1292 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1293 GENMASK(12, 10)) >> 10;
1295 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1296 GENMASK(15, 6)) >> 6;
1297 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1300 if (stride != info->stride_val)
1301 gvt_dbg_cmd("cannot change stride during async flip\n");
1303 if (tile != info->tile_val)
1304 gvt_dbg_cmd("cannot change tile during async flip\n");
1309 static int gen8_update_plane_mmio_from_mi_display_flip(
1310 struct parser_exec_state *s,
1311 struct mi_display_flip_command_info *info)
1313 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1314 struct intel_vgpu *vgpu = s->vgpu;
1316 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1317 info->surf_val << 12);
1318 if (INTEL_GEN(dev_priv) >= 9) {
1319 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1321 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1322 info->tile_val << 10);
1324 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1325 info->stride_val << 6);
1326 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1327 info->tile_val << 10);
1330 if (info->plane == PLANE_PRIMARY)
1331 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
1333 if (info->async_flip)
1334 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1336 set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1341 static int decode_mi_display_flip(struct parser_exec_state *s,
1342 struct mi_display_flip_command_info *info)
1344 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1346 if (IS_BROADWELL(dev_priv))
1347 return gen8_decode_mi_display_flip(s, info);
1348 if (INTEL_GEN(dev_priv) >= 9)
1349 return skl_decode_mi_display_flip(s, info);
1354 static int check_mi_display_flip(struct parser_exec_state *s,
1355 struct mi_display_flip_command_info *info)
1357 return gen8_check_mi_display_flip(s, info);
1360 static int update_plane_mmio_from_mi_display_flip(
1361 struct parser_exec_state *s,
1362 struct mi_display_flip_command_info *info)
1364 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1367 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1369 struct mi_display_flip_command_info info;
1370 struct intel_vgpu *vgpu = s->vgpu;
1373 int len = cmd_length(s);
1375 ret = decode_mi_display_flip(s, &info);
1377 gvt_vgpu_err("fail to decode MI display flip command\n");
1381 ret = check_mi_display_flip(s, &info);
1383 gvt_vgpu_err("invalid MI display flip command\n");
1387 ret = update_plane_mmio_from_mi_display_flip(s, &info);
1389 gvt_vgpu_err("fail to update plane mmio\n");
1393 for (i = 0; i < len; i++)
1394 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1398 static bool is_wait_for_flip_pending(u32 cmd)
1400 return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1401 MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1402 MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1403 MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1404 MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1405 MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1408 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1410 u32 cmd = cmd_val(s, 0);
1412 if (!is_wait_for_flip_pending(cmd))
1415 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1419 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1422 unsigned long gma_high, gma_low;
1423 struct intel_vgpu *vgpu = s->vgpu;
1424 int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1426 if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1427 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1428 return INTEL_GVT_INVALID_ADDR;
1431 gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1432 if (gmadr_bytes == 4) {
1435 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1436 addr = (((unsigned long)gma_high) << 32) | gma_low;
1441 static inline int cmd_address_audit(struct parser_exec_state *s,
1442 unsigned long guest_gma, int op_size, bool index_mode)
1444 struct intel_vgpu *vgpu = s->vgpu;
1445 u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1449 if (op_size > max_surface_size) {
1450 gvt_vgpu_err("command address audit fail name %s\n",
1456 if (guest_gma >= I915_GTT_PAGE_SIZE) {
1460 } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1468 gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1469 s->info->name, guest_gma, op_size);
1471 pr_err("cmd dump: ");
1472 for (i = 0; i < cmd_length(s); i++) {
1474 pr_err("\n%08x ", cmd_val(s, i));
1476 pr_err("%08x ", cmd_val(s, i));
1478 pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1480 vgpu_aperture_gmadr_base(vgpu),
1481 vgpu_aperture_gmadr_end(vgpu),
1482 vgpu_hidden_gmadr_base(vgpu),
1483 vgpu_hidden_gmadr_end(vgpu));
1487 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1489 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1490 int op_size = (cmd_length(s) - 3) * sizeof(u32);
1491 int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1492 unsigned long gma, gma_low, gma_high;
1496 if (!(cmd_val(s, 0) & (1 << 22)))
1499 gma = cmd_val(s, 2) & GENMASK(31, 2);
1501 if (gmadr_bytes == 8) {
1502 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1503 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1504 gma = (gma_high << 32) | gma_low;
1505 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1507 ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1511 static inline int unexpected_cmd(struct parser_exec_state *s)
1513 struct intel_vgpu *vgpu = s->vgpu;
1515 gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1520 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1522 return unexpected_cmd(s);
1525 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1527 return unexpected_cmd(s);
1530 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1532 return unexpected_cmd(s);
1535 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1537 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1538 int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1540 unsigned long gma, gma_high;
1543 if (!(cmd_val(s, 0) & (1 << 22)))
1546 gma = cmd_val(s, 1) & GENMASK(31, 2);
1547 if (gmadr_bytes == 8) {
1548 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1549 gma = (gma_high << 32) | gma;
1551 ret = cmd_address_audit(s, gma, op_size, false);
1555 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1557 return unexpected_cmd(s);
1560 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1562 return unexpected_cmd(s);
1565 static int cmd_handler_mi_conditional_batch_buffer_end(
1566 struct parser_exec_state *s)
1568 return unexpected_cmd(s);
1571 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1573 return unexpected_cmd(s);
1576 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1578 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1580 bool index_mode = false;
1584 /* Check post-sync and ppgtt bit */
1585 if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1586 gma = cmd_val(s, 1) & GENMASK(31, 3);
1587 if (gmadr_bytes == 8)
1588 gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1589 /* Store Data Index */
1590 if (cmd_val(s, 0) & (1 << 21))
1592 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1596 hws_pga = s->vgpu->hws_pga[s->ring_id];
1597 gma = hws_pga + gma;
1598 patch_value(s, cmd_ptr(s, 1), gma);
1599 val = cmd_val(s, 0) & (~(1 << 21));
1600 patch_value(s, cmd_ptr(s, 0), val);
1603 /* Check notify bit */
1604 if ((cmd_val(s, 0) & (1 << 8)))
1605 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1606 s->workload->pending_events);
1610 static void addr_type_update_snb(struct parser_exec_state *s)
1612 if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1613 (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1614 s->buf_addr_type = PPGTT_BUFFER;
1619 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1620 unsigned long gma, unsigned long end_gma, void *va)
1622 unsigned long copy_len, offset;
1623 unsigned long len = 0;
1626 while (gma != end_gma) {
1627 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1628 if (gpa == INTEL_GVT_INVALID_ADDR) {
1629 gvt_vgpu_err("invalid gma address: %lx\n", gma);
1633 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1635 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1636 I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1638 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1648 * Check whether a batch buffer needs to be scanned. Currently
1649 * the only criteria is based on privilege.
1651 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1653 /* Decide privilege based on address space */
1654 if (cmd_val(s, 0) & (1 << 8) &&
1655 !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1660 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1662 unsigned long gma = 0;
1663 const struct cmd_info *info;
1665 bool bb_end = false;
1666 struct intel_vgpu *vgpu = s->vgpu;
1668 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1669 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1673 /* get the start gm address of the batch buffer */
1674 gma = get_gma_bb_from_cmd(s, 1);
1675 if (gma == INTEL_GVT_INVALID_ADDR)
1678 cmd = cmd_val(s, 0);
1679 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1681 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1682 cmd, get_opcode(cmd, s->ring_id),
1683 (s->buf_addr_type == PPGTT_BUFFER) ?
1684 "ppgtt" : "ggtt", s->ring_id, s->workload);
1688 if (copy_gma_to_hva(s->vgpu, mm,
1689 gma, gma + 4, &cmd) < 0)
1691 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1693 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1694 cmd, get_opcode(cmd, s->ring_id),
1695 (s->buf_addr_type == PPGTT_BUFFER) ?
1696 "ppgtt" : "ggtt", s->ring_id, s->workload);
1700 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1702 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1703 if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1704 /* chained batch buffer */
1707 cmd_len = get_cmd_length(info, cmd) << 2;
1708 *bb_size += cmd_len;
1715 static int perform_bb_shadow(struct parser_exec_state *s)
1717 struct intel_vgpu *vgpu = s->vgpu;
1718 struct intel_vgpu_shadow_bb *bb;
1719 unsigned long gma = 0;
1720 unsigned long bb_size;
1722 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1723 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1724 unsigned long gma_start_offset = 0;
1726 /* get the start gm address of the batch buffer */
1727 gma = get_gma_bb_from_cmd(s, 1);
1728 if (gma == INTEL_GVT_INVALID_ADDR)
1731 ret = find_bb_size(s, &bb_size);
1735 bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1739 bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1741 /* the gma_start_offset stores the batch buffer's start gma's
1742 * offset relative to page boundary. so for non-privileged batch
1743 * buffer, the shadowed gem object holds exactly the same page
1744 * layout as original gem object. This is for the convience of
1745 * replacing the whole non-privilged batch buffer page to this
1746 * shadowed one in PPGTT at the same gma address. (this replacing
1747 * action is not implemented yet now, but may be necessary in
1749 * for prileged batch buffer, we just change start gma address to
1750 * that of shadowed page.
1753 gma_start_offset = gma & ~I915_GTT_PAGE_MASK;
1755 bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1756 roundup(bb_size + gma_start_offset, PAGE_SIZE));
1757 if (IS_ERR(bb->obj)) {
1758 ret = PTR_ERR(bb->obj);
1762 ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1766 bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1767 if (IS_ERR(bb->va)) {
1768 ret = PTR_ERR(bb->va);
1769 goto err_finish_shmem_access;
1772 if (bb->clflush & CLFLUSH_BEFORE) {
1773 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1774 bb->clflush &= ~CLFLUSH_BEFORE;
1777 ret = copy_gma_to_hva(s->vgpu, mm,
1779 bb->va + gma_start_offset);
1781 gvt_vgpu_err("fail to copy guest ring buffer\n");
1786 INIT_LIST_HEAD(&bb->list);
1787 list_add(&bb->list, &s->workload->shadow_bb);
1789 bb->accessing = true;
1790 bb->bb_start_cmd_va = s->ip_va;
1792 if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1793 bb->bb_offset = s->ip_va - s->rb_va;
1798 * ip_va saves the virtual address of the shadow batch buffer, while
1799 * ip_gma saves the graphics address of the original batch buffer.
1800 * As the shadow batch buffer is just a copy from the originial one,
1801 * it should be right to use shadow batch buffer'va and original batch
1802 * buffer's gma in pair. After all, we don't want to pin the shadow
1803 * buffer here (too early).
1805 s->ip_va = bb->va + gma_start_offset;
1809 i915_gem_object_unpin_map(bb->obj);
1810 err_finish_shmem_access:
1811 i915_gem_obj_finish_shmem_access(bb->obj);
1813 i915_gem_object_put(bb->obj);
1819 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1823 struct intel_vgpu *vgpu = s->vgpu;
1825 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1826 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1830 second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1831 if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1832 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1836 s->saved_buf_addr_type = s->buf_addr_type;
1837 addr_type_update_snb(s);
1838 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1839 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1840 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1841 } else if (second_level) {
1842 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1843 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1844 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1847 if (batch_buffer_needs_scan(s)) {
1848 ret = perform_bb_shadow(s);
1850 gvt_vgpu_err("invalid shadow batch buffer\n");
1852 /* emulate a batch buffer end to do return right */
1853 ret = cmd_handler_mi_batch_buffer_end(s);
1860 static int mi_noop_index;
1862 static const struct cmd_info cmd_info[] = {
1863 {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1865 {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1868 {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1869 0, 1, cmd_handler_mi_user_interrupt},
1871 {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1872 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1874 {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1876 {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1879 {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1882 {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1885 {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1888 {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1891 {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1892 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1893 cmd_handler_mi_batch_buffer_end},
1895 {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1898 {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1901 {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1904 {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1907 {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1910 {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1911 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1913 {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1916 {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1918 {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1920 {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1921 D_BDW_PLUS, 0, 8, NULL},
1923 {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL,
1924 D_BDW_PLUS, ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1926 {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1927 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1929 {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1930 0, 8, cmd_handler_mi_store_data_index},
1932 {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1933 D_ALL, 0, 8, cmd_handler_lri},
1935 {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1936 cmd_handler_mi_update_gtt},
1938 {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1939 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1941 {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1942 cmd_handler_mi_flush_dw},
1944 {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1945 10, cmd_handler_mi_clflush},
1947 {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1948 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1950 {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1951 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1953 {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1954 D_ALL, 0, 8, cmd_handler_lrr},
1956 {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1959 {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1960 ADDR_FIX_1(2), 8, NULL},
1962 {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1963 ADDR_FIX_1(2), 8, NULL},
1965 {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1966 8, cmd_handler_mi_op_2e},
1968 {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1969 8, cmd_handler_mi_op_2f},
1971 {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1972 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1973 cmd_handler_mi_batch_buffer_start},
1975 {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1976 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1977 cmd_handler_mi_conditional_batch_buffer_end},
1979 {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1980 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1982 {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1983 ADDR_FIX_2(4, 7), 8, NULL},
1985 {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1988 {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1989 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1991 {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1993 {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1996 {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1997 ADDR_FIX_1(3), 8, NULL},
1999 {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2002 {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2003 ADDR_FIX_1(4), 8, NULL},
2005 {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2006 ADDR_FIX_2(4, 5), 8, NULL},
2008 {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2009 ADDR_FIX_1(4), 8, NULL},
2011 {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2012 ADDR_FIX_2(4, 7), 8, NULL},
2014 {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2015 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2017 {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2019 {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2020 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2022 {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2023 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2025 {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2026 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2027 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2029 {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2030 D_ALL, ADDR_FIX_1(4), 8, NULL},
2032 {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2033 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2035 {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2036 D_ALL, ADDR_FIX_1(4), 8, NULL},
2038 {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2039 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2041 {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2042 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2044 {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2045 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2046 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2048 {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2049 ADDR_FIX_2(4, 5), 8, NULL},
2051 {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2052 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2054 {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2055 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2056 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2058 {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2059 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2060 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2062 {"3DSTATE_BLEND_STATE_POINTERS",
2063 OP_3DSTATE_BLEND_STATE_POINTERS,
2064 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2066 {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2067 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2068 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2070 {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2071 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2072 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2074 {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2075 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2076 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2078 {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2079 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2080 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2082 {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2083 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2084 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2086 {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2087 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2088 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2090 {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2091 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2092 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2094 {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2095 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2096 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2098 {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2099 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2100 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2102 {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2103 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2104 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2106 {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2107 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2108 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2110 {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2113 {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2116 {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2119 {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2122 {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2123 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2125 {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2126 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2128 {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2129 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2131 {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2132 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2134 {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2135 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2137 {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2138 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2140 {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2141 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2143 {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2144 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2146 {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2147 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2149 {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2150 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2152 {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2153 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2155 {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2156 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2158 {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2159 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2161 {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2162 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2164 {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2165 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2167 {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2168 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2170 {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2171 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2173 {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2174 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2176 {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2177 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2179 {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2180 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2182 {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2183 D_BDW_PLUS, 0, 8, NULL},
2185 {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2188 {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2189 D_BDW_PLUS, 0, 8, NULL},
2191 {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2192 D_BDW_PLUS, 0, 8, NULL},
2194 {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2197 {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2198 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2200 {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2203 {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2206 {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2209 {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2212 {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2213 D_BDW_PLUS, 0, 8, NULL},
2215 {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2216 R_RCS, D_ALL, 0, 8, NULL},
2218 {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2219 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2221 {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2222 R_RCS, D_ALL, 0, 1, NULL},
2224 {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2226 {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2227 R_RCS, D_ALL, 0, 8, NULL},
2229 {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2230 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2232 {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2234 {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2236 {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2238 {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2239 D_BDW_PLUS, 0, 8, NULL},
2241 {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2242 D_BDW_PLUS, 0, 8, NULL},
2244 {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2247 {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2248 D_BDW_PLUS, 0, 8, NULL},
2250 {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2251 D_BDW_PLUS, 0, 8, NULL},
2253 {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2255 {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2257 {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2259 {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2262 {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2264 {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2266 {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2267 R_RCS, D_ALL, 0, 8, NULL},
2269 {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2270 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2272 {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2275 {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2276 D_ALL, ADDR_FIX_1(2), 8, NULL},
2278 {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2279 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2281 {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2282 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2284 {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2287 {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2290 {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2293 {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2294 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2296 {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2297 D_BDW_PLUS, 0, 8, NULL},
2299 {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2300 D_ALL, ADDR_FIX_1(2), 8, NULL},
2302 {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2303 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2305 {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2306 R_RCS, D_ALL, 0, 8, NULL},
2308 {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2309 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2311 {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2312 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2314 {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2315 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2317 {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2318 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2320 {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2321 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2323 {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2324 R_RCS, D_ALL, 0, 8, NULL},
2326 {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2329 {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2330 ADDR_FIX_2(2, 4), 8, NULL},
2332 {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2333 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2334 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2336 {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2337 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2339 {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2340 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2341 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2343 {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2344 D_BDW_PLUS, 0, 8, NULL},
2346 {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2347 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2349 {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2351 {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2354 {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2355 ADDR_FIX_1(1), 8, NULL},
2357 {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2359 {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2360 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2362 {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2363 ADDR_FIX_1(1), 8, NULL},
2365 {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2367 {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2369 {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2372 {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2373 D_SKL_PLUS, 0, 8, NULL},
2375 {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2376 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2378 {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2381 {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2384 {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2387 {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2389 {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2392 {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2395 {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2398 {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2401 {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2404 {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2405 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2407 {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2408 R_VCS, D_ALL, 0, 12, NULL},
2410 {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2411 R_VCS, D_ALL, 0, 12, NULL},
2413 {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2414 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2416 {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2417 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2419 {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2420 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2422 {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2424 {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2425 R_VCS, D_ALL, 0, 12, NULL},
2427 {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2428 R_VCS, D_ALL, 0, 12, NULL},
2430 {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2431 R_VCS, D_ALL, 0, 12, NULL},
2433 {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2434 R_VCS, D_ALL, 0, 12, NULL},
2436 {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2437 R_VCS, D_ALL, 0, 12, NULL},
2439 {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2440 R_VCS, D_ALL, 0, 12, NULL},
2442 {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2443 R_VCS, D_ALL, 0, 6, NULL},
2445 {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2446 R_VCS, D_ALL, 0, 12, NULL},
2448 {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2449 R_VCS, D_ALL, 0, 12, NULL},
2451 {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2452 R_VCS, D_ALL, 0, 12, NULL},
2454 {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2455 R_VCS, D_ALL, 0, 12, NULL},
2457 {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2458 R_VCS, D_ALL, 0, 12, NULL},
2460 {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2461 R_VCS, D_ALL, 0, 12, NULL},
2463 {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2464 R_VCS, D_ALL, 0, 12, NULL},
2465 {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2466 R_VCS, D_ALL, 0, 12, NULL},
2468 {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2469 R_VCS, D_ALL, 0, 12, NULL},
2471 {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2472 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2474 {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2475 R_VCS, D_ALL, 0, 12, NULL},
2477 {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2478 R_VCS, D_ALL, 0, 12, NULL},
2480 {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2481 R_VCS, D_ALL, 0, 12, NULL},
2483 {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2484 R_VCS, D_ALL, 0, 12, NULL},
2486 {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2487 R_VCS, D_ALL, 0, 12, NULL},
2489 {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2490 R_VCS, D_ALL, 0, 12, NULL},
2492 {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2493 R_VCS, D_ALL, 0, 12, NULL},
2495 {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2496 R_VCS, D_ALL, 0, 12, NULL},
2498 {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2499 R_VCS, D_ALL, 0, 12, NULL},
2501 {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2502 R_VCS, D_ALL, 0, 12, NULL},
2504 {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2505 R_VCS, D_ALL, 0, 12, NULL},
2507 {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2510 {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2512 {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2514 {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2515 R_VCS, D_ALL, 0, 12, NULL},
2517 {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2518 R_VCS, D_ALL, 0, 12, NULL},
2520 {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2521 R_VCS, D_ALL, 0, 12, NULL},
2523 {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2525 {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2528 {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2532 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2534 hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2537 /* call the cmd handler, and advance ip */
2538 static int cmd_parser_exec(struct parser_exec_state *s)
2540 struct intel_vgpu *vgpu = s->vgpu;
2541 const struct cmd_info *info;
2545 cmd = cmd_val(s, 0);
2547 /* fastpath for MI_NOOP */
2549 info = &cmd_info[mi_noop_index];
2551 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2554 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2555 cmd, get_opcode(cmd, s->ring_id),
2556 (s->buf_addr_type == PPGTT_BUFFER) ?
2557 "ppgtt" : "ggtt", s->ring_id, s->workload);
2563 trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2564 cmd_length(s), s->buf_type, s->buf_addr_type,
2565 s->workload, info->name);
2567 if (info->handler) {
2568 ret = info->handler(s);
2570 gvt_vgpu_err("%s handler error\n", info->name);
2575 if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2576 ret = cmd_advance_default(s);
2578 gvt_vgpu_err("%s IP advance error\n", info->name);
2585 static inline bool gma_out_of_range(unsigned long gma,
2586 unsigned long gma_head, unsigned int gma_tail)
2588 if (gma_tail >= gma_head)
2589 return (gma < gma_head) || (gma > gma_tail);
2591 return (gma > gma_tail) && (gma < gma_head);
2594 /* Keep the consistent return type, e.g EBADRQC for unknown
2595 * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2596 * works as the input of VM healthy status.
2598 static int command_scan(struct parser_exec_state *s,
2599 unsigned long rb_head, unsigned long rb_tail,
2600 unsigned long rb_start, unsigned long rb_len)
2603 unsigned long gma_head, gma_tail, gma_bottom;
2605 struct intel_vgpu *vgpu = s->vgpu;
2607 gma_head = rb_start + rb_head;
2608 gma_tail = rb_start + rb_tail;
2609 gma_bottom = rb_start + rb_len;
2611 while (s->ip_gma != gma_tail) {
2612 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2613 if (!(s->ip_gma >= rb_start) ||
2614 !(s->ip_gma < gma_bottom)) {
2615 gvt_vgpu_err("ip_gma %lx out of ring scope."
2616 "(base:0x%lx, bottom: 0x%lx)\n",
2617 s->ip_gma, rb_start,
2619 parser_exec_state_dump(s);
2622 if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2623 gvt_vgpu_err("ip_gma %lx out of range."
2624 "base 0x%lx head 0x%lx tail 0x%lx\n",
2625 s->ip_gma, rb_start,
2627 parser_exec_state_dump(s);
2631 ret = cmd_parser_exec(s);
2633 gvt_vgpu_err("cmd parser error\n");
2634 parser_exec_state_dump(s);
2642 static int scan_workload(struct intel_vgpu_workload *workload)
2644 unsigned long gma_head, gma_tail, gma_bottom;
2645 struct parser_exec_state s;
2648 /* ring base is page aligned */
2649 if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2652 gma_head = workload->rb_start + workload->rb_head;
2653 gma_tail = workload->rb_start + workload->rb_tail;
2654 gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl);
2656 s.buf_type = RING_BUFFER_INSTRUCTION;
2657 s.buf_addr_type = GTT_BUFFER;
2658 s.vgpu = workload->vgpu;
2659 s.ring_id = workload->ring_id;
2660 s.ring_start = workload->rb_start;
2661 s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2662 s.ring_head = gma_head;
2663 s.ring_tail = gma_tail;
2664 s.rb_va = workload->shadow_ring_buffer_va;
2665 s.workload = workload;
2666 s.is_ctx_wa = false;
2668 if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2669 gma_head == gma_tail)
2672 if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2677 ret = ip_gma_set(&s, gma_head);
2681 ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2682 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2688 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2691 unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2692 struct parser_exec_state s;
2694 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2695 struct intel_vgpu_workload,
2698 /* ring base is page aligned */
2699 if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2700 I915_GTT_PAGE_SIZE)))
2703 ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2704 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2706 gma_head = wa_ctx->indirect_ctx.guest_gma;
2707 gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2708 gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2710 s.buf_type = RING_BUFFER_INSTRUCTION;
2711 s.buf_addr_type = GTT_BUFFER;
2712 s.vgpu = workload->vgpu;
2713 s.ring_id = workload->ring_id;
2714 s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2715 s.ring_size = ring_size;
2716 s.ring_head = gma_head;
2717 s.ring_tail = gma_tail;
2718 s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2719 s.workload = workload;
2722 if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2727 ret = ip_gma_set(&s, gma_head);
2731 ret = command_scan(&s, 0, ring_tail,
2732 wa_ctx->indirect_ctx.guest_gma, ring_size);
2737 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2739 struct intel_vgpu *vgpu = workload->vgpu;
2740 struct intel_vgpu_submission *s = &vgpu->submission;
2741 unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2742 void *shadow_ring_buffer_va;
2743 int ring_id = workload->ring_id;
2746 guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2748 /* calculate workload ring buffer size */
2749 workload->rb_len = (workload->rb_tail + guest_rb_size -
2750 workload->rb_head) % guest_rb_size;
2752 gma_head = workload->rb_start + workload->rb_head;
2753 gma_tail = workload->rb_start + workload->rb_tail;
2754 gma_top = workload->rb_start + guest_rb_size;
2756 if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2759 /* realloc the new ring buffer if needed */
2760 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2763 gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2766 s->ring_scan_buffer[ring_id] = p;
2767 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2770 shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2772 /* get shadow ring buffer va */
2773 workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2775 /* head > tail --> copy head <-> top */
2776 if (gma_head > gma_tail) {
2777 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2778 gma_head, gma_top, shadow_ring_buffer_va);
2780 gvt_vgpu_err("fail to copy guest ring buffer\n");
2783 shadow_ring_buffer_va += ret;
2784 gma_head = workload->rb_start;
2787 /* copy head or start <-> tail */
2788 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2789 shadow_ring_buffer_va);
2791 gvt_vgpu_err("fail to copy guest ring buffer\n");
2797 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2800 struct intel_vgpu *vgpu = workload->vgpu;
2802 ret = shadow_workload_ring_buffer(workload);
2804 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2808 ret = scan_workload(workload);
2810 gvt_vgpu_err("scan workload error\n");
2816 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2818 int ctx_size = wa_ctx->indirect_ctx.size;
2819 unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2820 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2821 struct intel_vgpu_workload,
2823 struct intel_vgpu *vgpu = workload->vgpu;
2824 struct drm_i915_gem_object *obj;
2828 obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2829 roundup(ctx_size + CACHELINE_BYTES,
2832 return PTR_ERR(obj);
2834 /* get the va of the shadow batch buffer */
2835 map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2837 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2842 ret = i915_gem_object_set_to_cpu_domain(obj, false);
2844 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2848 ret = copy_gma_to_hva(workload->vgpu,
2849 workload->vgpu->gtt.ggtt_mm,
2850 guest_gma, guest_gma + ctx_size,
2853 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2857 wa_ctx->indirect_ctx.obj = obj;
2858 wa_ctx->indirect_ctx.shadow_va = map;
2862 i915_gem_object_unpin_map(obj);
2864 i915_gem_object_put(obj);
2868 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2870 u32 per_ctx_start[CACHELINE_DWORDS] = {0};
2871 unsigned char *bb_start_sva;
2873 if (!wa_ctx->per_ctx.valid)
2876 per_ctx_start[0] = 0x18800001;
2877 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2879 bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2880 wa_ctx->indirect_ctx.size;
2882 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2887 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2890 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2891 struct intel_vgpu_workload,
2893 struct intel_vgpu *vgpu = workload->vgpu;
2895 if (wa_ctx->indirect_ctx.size == 0)
2898 ret = shadow_indirect_ctx(wa_ctx);
2900 gvt_vgpu_err("fail to shadow indirect ctx\n");
2904 combine_wa_ctx(wa_ctx);
2906 ret = scan_wa_ctx(wa_ctx);
2908 gvt_vgpu_err("scan wa ctx error\n");
2915 static const struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2916 unsigned int opcode, unsigned long rings)
2918 const struct cmd_info *info = NULL;
2921 for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2922 info = find_cmd_entry(gvt, opcode, ring);
2929 static int init_cmd_table(struct intel_gvt *gvt)
2932 struct cmd_entry *e;
2933 const struct cmd_info *info;
2934 unsigned int gen_type;
2936 gen_type = intel_gvt_get_device_type(gvt);
2938 for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2939 if (!(cmd_info[i].devices & gen_type))
2942 e = kzalloc(sizeof(*e), GFP_KERNEL);
2946 e->info = &cmd_info[i];
2947 info = find_cmd_entry_any_ring(gvt,
2948 e->info->opcode, e->info->rings);
2950 gvt_err("%s %s duplicated\n", e->info->name,
2955 if (cmd_info[i].opcode == OP_MI_NOOP)
2958 INIT_HLIST_NODE(&e->hlist);
2959 add_cmd_entry(gvt, e);
2960 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2961 e->info->name, e->info->opcode, e->info->flag,
2962 e->info->devices, e->info->rings);
2967 static void clean_cmd_table(struct intel_gvt *gvt)
2969 struct hlist_node *tmp;
2970 struct cmd_entry *e;
2973 hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2976 hash_init(gvt->cmd_table);
2979 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2981 clean_cmd_table(gvt);
2984 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2988 ret = init_cmd_table(gvt);
2990 intel_gvt_clean_cmd_parser(gvt);