drivers/gpu/drm/i915/gvt/cmd_parser.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27  *
  28  * Contributors:
  29  *    Min He <min.he@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Yulei Zhang <yulei.zhang@intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include <linux/slab.h>
  38
  39 #include "i915_drv.h"
  40 #include "gt/intel_ring.h"
  41 #include "gvt.h"
  42 #include "i915_pvinfo.h"
  43 #include "trace.h"
  44
  45 #define INVALID_OP    (~0U)
  46
  47 #define OP_LEN_MI           9
  48 #define OP_LEN_2D           10
  49 #define OP_LEN_3D_MEDIA     16
  50 #define OP_LEN_MFX_VC       16
  51 #define OP_LEN_VEBOX        16
  52
  53 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
  54
  55 struct sub_op_bits {
  56         int hi;
  57         int low;
  58 };
  59 struct decode_info {
  60         const char *name;
  61         int op_len;
  62         int nr_sub_op;
  63         const struct sub_op_bits *sub_op;
  64 };
  65
  66 #define   MAX_CMD_BUDGET                        0x7fffffff
  67 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  68 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  69 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  70
  71 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  72 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  73 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  74
  75 /* Render Command Map */
  76
  77 /* MI_* command Opcode (28:23) */
  78 #define OP_MI_NOOP                          0x0
  79 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  80 #define OP_MI_USER_INTERRUPT                0x2
  81 #define OP_MI_WAIT_FOR_EVENT                0x3
  82 #define OP_MI_FLUSH                         0x4
  83 #define OP_MI_ARB_CHECK                     0x5
  84 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  85 #define OP_MI_REPORT_HEAD                   0x7
  86 #define OP_MI_ARB_ON_OFF                    0x8
  87 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  88 #define OP_MI_BATCH_BUFFER_END              0xA
  89 #define OP_MI_SUSPEND_FLUSH                 0xB
  90 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
  91 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
  92 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
  93 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
  94 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
  95 #define OP_MI_DISPLAY_FLIP                  0x14
  96 #define OP_MI_SEMAPHORE_MBOX                0x16
  97 #define OP_MI_SET_CONTEXT                   0x18
  98 #define OP_MI_MATH                          0x1A
  99 #define OP_MI_URB_CLEAR                     0x19
 100 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
 101 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
 102
 103 #define OP_MI_STORE_DATA_IMM                0x20
 104 #define OP_MI_STORE_DATA_INDEX              0x21
 105 #define OP_MI_LOAD_REGISTER_IMM             0x22
 106 #define OP_MI_UPDATE_GTT                    0x23
 107 #define OP_MI_STORE_REGISTER_MEM            0x24
 108 #define OP_MI_FLUSH_DW                      0x26
 109 #define OP_MI_CLFLUSH                       0x27
 110 #define OP_MI_REPORT_PERF_COUNT             0x28
 111 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 112 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 113 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 114 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 115 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 116 #define OP_MI_2E                            0x2E  /* BDW+ */
 117 #define OP_MI_2F                            0x2F  /* BDW+ */
 118 #define OP_MI_BATCH_BUFFER_START            0x31
 119
 120 /* Bit definition for dword 0 */
 121 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
 122
 123 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 124
 125 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 126 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 127 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
 128 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 129
 130 /* 2D command: Opcode (28:22) */
 131 #define OP_2D(x)    ((2<<7) | x)
 132
 133 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
 134 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 135 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 136 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 137 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 138 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
 139 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 140 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
 141 #define OP_XY_PAT_BLT                               OP_2D(0x51)
 142 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 143 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 144 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 145 #define OP_XY_FULL_BLT                              OP_2D(0x55)
 146 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 147 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 148 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 149 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 150 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 151 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 152 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 153 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 154 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 155 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 156 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 157
 158 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 159 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 160         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 161
 162 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 163
 164 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 165 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 166 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
 167
 168 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 169
 170 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 171
 172 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 173 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 174 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 175 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 176 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 177 #define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)
 178
 179 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 180 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 181 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 182 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 183
 184 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 185 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 186 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 187 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 188 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 189 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 190 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 191 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 192 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 193 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 194 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 195 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 196 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 197 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 198 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 199 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 200 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 201 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 202 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 203 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 204 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 205 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 206 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 207 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 208 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 209 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 210 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 211 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 212 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 213 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 214 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 215 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 218 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 219 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 220 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 223 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 224 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 225 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 226 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 227 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 228 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 229 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 230 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 231 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 232 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 233 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 234 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 235 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 236 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 237 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 238 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 239 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 240 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 241 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 242 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 243 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 244 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 245 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 246 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 247 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 248 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 249 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 250
 251 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 252 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 253 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 254 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 255 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 256 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 257 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 258 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 259 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 260 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 261 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 262
 263 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 264 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 265 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 266 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 267 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 268 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 269 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 270 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 271 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 272 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 273 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
 274 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 275 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 276 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 277 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 280 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 281 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 282 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 283 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 284 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 285 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 286 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 287 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 288 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 289 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 290 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 291
 292 /* VCCP Command Parser */
 293
 294 /*
 295  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 296  * git://anongit.freedesktop.org/vaapi/intel-driver
 297  * src/i965_defines.h
 298  *
 299  */
 300
 301 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 302         (3 << 13 | \
 303          (pipeline) << 11 | \
 304          (op) << 8 | \
 305          (sub_opa) << 5 | \
 306          (sub_opb))
 307
 308 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 309 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 310 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 311 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 312 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 313 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 314 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 315 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 316 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 317 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 318 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 319
 320 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 321
 322 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 323 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 324 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 325 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 326 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 327 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 328 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 329 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 330 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
 331 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 332 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 333 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 334
 335 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 336 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 337 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 338 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 339 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 340
 341 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 342 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 343 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 344 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 345 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 346
 347 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 348 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 349 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 350
 351 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 352 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 353 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 354
 355 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 356         (3 << 13 | \
 357          (pipeline) << 11 | \
 358          (op) << 8 | \
 359          (sub_opa) << 5 | \
 360          (sub_opb))
 361
 362 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 363 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 364 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 365
 366 struct parser_exec_state;
 367
 368 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 369
 370 #define GVT_CMD_HASH_BITS   7
 371
 372 /* which DWords need address fix */
 373 #define ADDR_FIX_1(x1)                  (1 << (x1))
 374 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 375 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 376 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 377 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 378
 379 #define DWORD_FIELD(dword, end, start) \
 380         FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
 381
 382 #define OP_LENGTH_BIAS 2
 383 #define CMD_LEN(value)  (value + OP_LENGTH_BIAS)
 384
 385 static int gvt_check_valid_cmd_length(int len, int valid_len)
 386 {
 387         if (valid_len != len) {
 388                 gvt_err("len is not valid:  len=%u  valid_len=%u\n",
 389                         len, valid_len);
 390                 return -EFAULT;
 391         }
 392         return 0;
 393 }
 394
 395 struct cmd_info {
 396         const char *name;
 397         u32 opcode;
 398
 399 #define F_LEN_MASK      3U
 400 #define F_LEN_CONST  1U
 401 #define F_LEN_VAR    0U
 402 /* value is const although LEN maybe variable */
 403 #define F_LEN_VAR_FIXED    (1<<1)
 404
 405 /*
 406  * command has its own ip advance logic
 407  * e.g. MI_BATCH_START, MI_BATCH_END
 408  */
 409 #define F_IP_ADVANCE_CUSTOM (1<<2)
 410         u32 flag;
 411
 412 #define R_RCS   BIT(RCS0)
 413 #define R_VCS1  BIT(VCS0)
 414 #define R_VCS2  BIT(VCS1)
 415 #define R_VCS   (R_VCS1 | R_VCS2)
 416 #define R_BCS   BIT(BCS0)
 417 #define R_VECS  BIT(VECS0)
 418 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 419         /* rings that support this cmd: BLT/RCS/VCS/VECS */
 420         u16 rings;
 421
 422         /* devices that support this cmd: SNB/IVB/HSW/... */
 423         u16 devices;
 424
 425         /* which DWords are address that need fix up.
 426          * bit 0 means a 32-bit non address operand in command
 427          * bit 1 means address operand, which could be 32-bit
 428          * or 64-bit depending on different architectures.(
 429          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 430          * No matter the address length, each address only takes
 431          * one bit in the bitmap.
 432          */
 433         u16 addr_bitmap;
 434
 435         /* flag == F_LEN_CONST : command length
 436          * flag == F_LEN_VAR : length bias bits
 437          * Note: length is in DWord
 438          */
 439         u32 len;
 440
 441         parser_cmd_handler handler;
 442
 443         /* valid length in DWord */
 444         u32 valid_len;
 445 };
 446
 447 struct cmd_entry {
 448         struct hlist_node hlist;
 449         const struct cmd_info *info;
 450 };
 451
 452 enum {
 453         RING_BUFFER_INSTRUCTION,
 454         BATCH_BUFFER_INSTRUCTION,
 455         BATCH_BUFFER_2ND_LEVEL,
 456 };
 457
 458 enum {
 459         GTT_BUFFER,
 460         PPGTT_BUFFER
 461 };
 462
 463 struct parser_exec_state {
 464         struct intel_vgpu *vgpu;
 465         int ring_id;
 466
 467         int buf_type;
 468
 469         /* batch buffer address type */
 470         int buf_addr_type;
 471
 472         /* graphics memory address of ring buffer start */
 473         unsigned long ring_start;
 474         unsigned long ring_size;
 475         unsigned long ring_head;
 476         unsigned long ring_tail;
 477
 478         /* instruction graphics memory address */
 479         unsigned long ip_gma;
 480
 481         /* mapped va of the instr_gma */
 482         void *ip_va;
 483         void *rb_va;
 484
 485         void *ret_bb_va;
 486         /* next instruction when return from  batch buffer to ring buffer */
 487         unsigned long ret_ip_gma_ring;
 488
 489         /* next instruction when return from 2nd batch buffer to batch buffer */
 490         unsigned long ret_ip_gma_bb;
 491
 492         /* batch buffer address type (GTT or PPGTT)
 493          * used when ret from 2nd level batch buffer
 494          */
 495         int saved_buf_addr_type;
 496         bool is_ctx_wa;
 497
 498         const struct cmd_info *info;
 499
 500         struct intel_vgpu_workload *workload;
 501 };
 502
 503 #define gmadr_dw_number(s)      \
 504         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 505
 506 static unsigned long bypass_scan_mask = 0;
 507
 508 /* ring ALL, type = 0 */
 509 static const struct sub_op_bits sub_op_mi[] = {
 510         {31, 29},
 511         {28, 23},
 512 };
 513
 514 static const struct decode_info decode_info_mi = {
 515         "MI",
 516         OP_LEN_MI,
 517         ARRAY_SIZE(sub_op_mi),
 518         sub_op_mi,
 519 };
 520
 521 /* ring RCS, command type 2 */
 522 static const struct sub_op_bits sub_op_2d[] = {
 523         {31, 29},
 524         {28, 22},
 525 };
 526
 527 static const struct decode_info decode_info_2d = {
 528         "2D",
 529         OP_LEN_2D,
 530         ARRAY_SIZE(sub_op_2d),
 531         sub_op_2d,
 532 };
 533
 534 /* ring RCS, command type 3 */
 535 static const struct sub_op_bits sub_op_3d_media[] = {
 536         {31, 29},
 537         {28, 27},
 538         {26, 24},
 539         {23, 16},
 540 };
 541
 542 static const struct decode_info decode_info_3d_media = {
 543         "3D_Media",
 544         OP_LEN_3D_MEDIA,
 545         ARRAY_SIZE(sub_op_3d_media),
 546         sub_op_3d_media,
 547 };
 548
 549 /* ring VCS, command type 3 */
 550 static const struct sub_op_bits sub_op_mfx_vc[] = {
 551         {31, 29},
 552         {28, 27},
 553         {26, 24},
 554         {23, 21},
 555         {20, 16},
 556 };
 557
 558 static const struct decode_info decode_info_mfx_vc = {
 559         "MFX_VC",
 560         OP_LEN_MFX_VC,
 561         ARRAY_SIZE(sub_op_mfx_vc),
 562         sub_op_mfx_vc,
 563 };
 564
 565 /* ring VECS, command type 3 */
 566 static const struct sub_op_bits sub_op_vebox[] = {
 567         {31, 29},
 568         {28, 27},
 569         {26, 24},
 570         {23, 21},
 571         {20, 16},
 572 };
 573
 574 static const struct decode_info decode_info_vebox = {
 575         "VEBOX",
 576         OP_LEN_VEBOX,
 577         ARRAY_SIZE(sub_op_vebox),
 578         sub_op_vebox,
 579 };
 580
 581 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 582         [RCS0] = {
 583                 &decode_info_mi,
 584                 NULL,
 585                 NULL,
 586                 &decode_info_3d_media,
 587                 NULL,
 588                 NULL,
 589                 NULL,
 590                 NULL,
 591         },
 592
 593         [VCS0] = {
 594                 &decode_info_mi,
 595                 NULL,
 596                 NULL,
 597                 &decode_info_mfx_vc,
 598                 NULL,
 599                 NULL,
 600                 NULL,
 601                 NULL,
 602         },
 603
 604         [BCS0] = {
 605                 &decode_info_mi,
 606                 NULL,
 607                 &decode_info_2d,
 608                 NULL,
 609                 NULL,
 610                 NULL,
 611                 NULL,
 612                 NULL,
 613         },
 614
 615         [VECS0] = {
 616                 &decode_info_mi,
 617                 NULL,
 618                 NULL,
 619                 &decode_info_vebox,
 620                 NULL,
 621                 NULL,
 622                 NULL,
 623                 NULL,
 624         },
 625
 626         [VCS1] = {
 627                 &decode_info_mi,
 628                 NULL,
 629                 NULL,
 630                 &decode_info_mfx_vc,
 631                 NULL,
 632                 NULL,
 633                 NULL,
 634                 NULL,
 635         },
 636 };
 637
 638 static inline u32 get_opcode(u32 cmd, int ring_id)
 639 {
 640         const struct decode_info *d_info;
 641
 642         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 643         if (d_info == NULL)
 644                 return INVALID_OP;
 645
 646         return cmd >> (32 - d_info->op_len);
 647 }
 648
 649 static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
 650                 unsigned int opcode, int ring_id)
 651 {
 652         struct cmd_entry *e;
 653
 654         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 655                 if (opcode == e->info->opcode && e->info->rings & BIT(ring_id))
 656                         return e->info;
 657         }
 658         return NULL;
 659 }
 660
 661 static inline const struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
 662                 u32 cmd, int ring_id)
 663 {
 664         u32 opcode;
 665
 666         opcode = get_opcode(cmd, ring_id);
 667         if (opcode == INVALID_OP)
 668                 return NULL;
 669
 670         return find_cmd_entry(gvt, opcode, ring_id);
 671 }
 672
 673 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 674 {
 675         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 676 }
 677
 678 static inline void print_opcode(u32 cmd, int ring_id)
 679 {
 680         const struct decode_info *d_info;
 681         int i;
 682
 683         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 684         if (d_info == NULL)
 685                 return;
 686
 687         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 688                         cmd >> (32 - d_info->op_len), d_info->name);
 689
 690         for (i = 0; i < d_info->nr_sub_op; i++)
 691                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 692                                         d_info->sub_op[i].low));
 693
 694         pr_err("\n");
 695 }
 696
 697 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 698 {
 699         return s->ip_va + (index << 2);
 700 }
 701
 702 static inline u32 cmd_val(struct parser_exec_state *s, int index)
 703 {
 704         return *cmd_ptr(s, index);
 705 }
 706
 707 static void parser_exec_state_dump(struct parser_exec_state *s)
 708 {
 709         int cnt = 0;
 710         int i;
 711
 712         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
 713                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
 714                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
 715                         s->ring_head, s->ring_tail);
 716
 717         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 718                         s->buf_type == RING_BUFFER_INSTRUCTION ?
 719                         "RING_BUFFER" : "BATCH_BUFFER",
 720                         s->buf_addr_type == GTT_BUFFER ?
 721                         "GTT" : "PPGTT", s->ip_gma);
 722
 723         if (s->ip_va == NULL) {
 724                 gvt_dbg_cmd(" ip_va(NULL)");
 725                 return;
 726         }
 727
 728         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 729                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 730                         cmd_val(s, 2), cmd_val(s, 3));
 731
 732         print_opcode(cmd_val(s, 0), s->ring_id);
 733
 734         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 735
 736         while (cnt < 1024) {
 737                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 738                 for (i = 0; i < 8; i++)
 739                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
 740                 gvt_dbg_cmd("\n");
 741
 742                 s->ip_va += 8 * sizeof(u32);
 743                 cnt += 8;
 744         }
 745 }
 746
 747 static inline void update_ip_va(struct parser_exec_state *s)
 748 {
 749         unsigned long len = 0;
 750
 751         if (WARN_ON(s->ring_head == s->ring_tail))
 752                 return;
 753
 754         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 755                 unsigned long ring_top = s->ring_start + s->ring_size;
 756
 757                 if (s->ring_head > s->ring_tail) {
 758                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 759                                 len = (s->ip_gma - s->ring_head);
 760                         else if (s->ip_gma >= s->ring_start &&
 761                                         s->ip_gma <= s->ring_tail)
 762                                 len = (ring_top - s->ring_head) +
 763                                         (s->ip_gma - s->ring_start);
 764                 } else
 765                         len = (s->ip_gma - s->ring_head);
 766
 767                 s->ip_va = s->rb_va + len;
 768         } else {/* shadow batch buffer */
 769                 s->ip_va = s->ret_bb_va;
 770         }
 771 }
 772
 773 static inline int ip_gma_set(struct parser_exec_state *s,
 774                 unsigned long ip_gma)
 775 {
 776         WARN_ON(!IS_ALIGNED(ip_gma, 4));
 777
 778         s->ip_gma = ip_gma;
 779         update_ip_va(s);
 780         return 0;
 781 }
 782
 783 static inline int ip_gma_advance(struct parser_exec_state *s,
 784                 unsigned int dw_len)
 785 {
 786         s->ip_gma += (dw_len << 2);
 787
 788         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 789                 if (s->ip_gma >= s->ring_start + s->ring_size)
 790                         s->ip_gma -= s->ring_size;
 791                 update_ip_va(s);
 792         } else {
 793                 s->ip_va += (dw_len << 2);
 794         }
 795
 796         return 0;
 797 }
 798
 799 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
 800 {
 801         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 802                 return info->len;
 803         else
 804                 return (cmd & ((1U << info->len) - 1)) + 2;
 805         return 0;
 806 }
 807
 808 static inline int cmd_length(struct parser_exec_state *s)
 809 {
 810         return get_cmd_length(s->info, cmd_val(s, 0));
 811 }
 812
 813 /* do not remove this, some platform may need clflush here */
 814 #define patch_value(s, addr, val) do { \
 815         *addr = val; \
 816 } while (0)
 817
 818 static bool is_shadowed_mmio(unsigned int offset)
 819 {
 820         bool ret = false;
 821
 822         if ((offset == 0x2168) || /*BB current head register UDW */
 823             (offset == 0x2140) || /*BB current header register */
 824             (offset == 0x211c) || /*second BB header register UDW */
 825             (offset == 0x2114)) { /*second BB header register UDW */
 826                 ret = true;
 827         }
 828         return ret;
 829 }
 830
 831 static inline bool is_force_nonpriv_mmio(unsigned int offset)
 832 {
 833         return (offset >= 0x24d0 && offset < 0x2500);
 834 }
 835
 836 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 837                 unsigned int offset, unsigned int index, char *cmd)
 838 {
 839         struct intel_gvt *gvt = s->vgpu->gvt;
 840         unsigned int data;
 841         u32 ring_base;
 842         u32 nopid;
 843         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
 844
 845         if (!strcmp(cmd, "lri"))
 846                 data = cmd_val(s, index + 1);
 847         else {
 848                 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
 849                         offset, cmd);
 850                 return -EINVAL;
 851         }
 852
 853         ring_base = dev_priv->engine[s->ring_id]->mmio_base;
 854         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
 855
 856         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
 857                         data != nopid) {
 858                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
 859                         offset, data);
 860                 patch_value(s, cmd_ptr(s, index), nopid);
 861                 return 0;
 862         }
 863         return 0;
 864 }
 865
 866 static inline bool is_mocs_mmio(unsigned int offset)
 867 {
 868         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 869                 ((offset >= 0xb020) && (offset <= 0xb0a0));
 870 }
 871
 872 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
 873                                 unsigned int offset, unsigned int index)
 874 {
 875         if (!is_mocs_mmio(offset))
 876                 return -EINVAL;
 877         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
 878         return 0;
 879 }
 880
 881 static int cmd_reg_handler(struct parser_exec_state *s,
 882         unsigned int offset, unsigned int index, char *cmd)
 883 {
 884         struct intel_vgpu *vgpu = s->vgpu;
 885         struct intel_gvt *gvt = vgpu->gvt;
 886         u32 ctx_sr_ctl;
 887
 888         if (offset + 4 > gvt->device_info.mmio_size) {
 889                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 890                                 cmd, offset);
 891                 return -EFAULT;
 892         }
 893
 894         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
 895                 gvt_vgpu_err("%s access to non-render register (%x)\n",
 896                                 cmd, offset);
 897                 return -EBADRQC;
 898         }
 899
 900         if (is_shadowed_mmio(offset)) {
 901                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
 902                 return 0;
 903         }
 904
 905         if (is_mocs_mmio(offset) &&
 906             mocs_cmd_reg_handler(s, offset, index))
 907                 return -EINVAL;
 908
 909         if (is_force_nonpriv_mmio(offset) &&
 910                 force_nonpriv_reg_handler(s, offset, index, cmd))
 911                 return -EPERM;
 912
 913         if (offset == i915_mmio_reg_offset(DERRMR) ||
 914                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 915                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 916                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 917         }
 918
 919         /* TODO
 920          * In order to let workload with inhibit context to generate
 921          * correct image data into memory, vregs values will be loaded to
 922          * hw via LRIs in the workload with inhibit context. But as
 923          * indirect context is loaded prior to LRIs in workload, we don't
 924          * want reg values specified in indirect context overwritten by
 925          * LRIs in workloads. So, when scanning an indirect context, we
 926          * update reg values in it into vregs, so LRIs in workload with
 927          * inhibit context will restore with correct values
 928          */
 929         if (IS_GEN(gvt->dev_priv, 9) &&
 930                         intel_gvt_mmio_is_in_ctx(gvt, offset) &&
 931                         !strncmp(cmd, "lri", 3)) {
 932                 intel_gvt_hypervisor_read_gpa(s->vgpu,
 933                         s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
 934                 /* check inhibit context */
 935                 if (ctx_sr_ctl & 1) {
 936                         u32 data = cmd_val(s, index + 1);
 937
 938                         if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
 939                                 intel_vgpu_mask_mmio_write(vgpu,
 940                                                         offset, &data, 4);
 941                         else
 942                                 vgpu_vreg(vgpu, offset) = data;
 943                 }
 944         }
 945
 946         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
 947         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
 948         return 0;
 949 }
 950
 951 #define cmd_reg(s, i) \
 952         (cmd_val(s, i) & GENMASK(22, 2))
 953
 954 #define cmd_reg_inhibit(s, i) \
 955         (cmd_val(s, i) & GENMASK(22, 18))
 956
 957 #define cmd_gma(s, i) \
 958         (cmd_val(s, i) & GENMASK(31, 2))
 959
 960 #define cmd_gma_hi(s, i) \
 961         (cmd_val(s, i) & GENMASK(15, 0))
 962
 963 static int cmd_handler_lri(struct parser_exec_state *s)
 964 {
 965         int i, ret = 0;
 966         int cmd_len = cmd_length(s);
 967         struct intel_gvt *gvt = s->vgpu->gvt;
 968         u32 valid_len = CMD_LEN(1);
 969
 970         /*
 971          * Official intel docs are somewhat sloppy , check the definition of
 972          * MI_LOAD_REGISTER_IMM.
 973          */
 974         #define MAX_VALID_LEN 127
 975         if ((cmd_len < valid_len) || (cmd_len > MAX_VALID_LEN)) {
 976                 gvt_err("len is not valid:  len=%u  valid_len=%u\n",
 977                         cmd_len, valid_len);
 978                 return -EFAULT;
 979         }
 980
 981         for (i = 1; i < cmd_len; i += 2) {
 982                 if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) {
 983                         if (s->ring_id == BCS0 &&
 984                             cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
 985                                 ret |= 0;
 986                         else
 987                                 ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
 988                 }
 989                 if (ret)
 990                         break;
 991                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
 992                 if (ret)
 993                         break;
 994         }
 995         return ret;
 996 }
 997
 998 static int cmd_handler_lrr(struct parser_exec_state *s)
 999 {
1000         int i, ret = 0;
1001         int cmd_len = cmd_length(s);
1002
1003         for (i = 1; i < cmd_len; i += 2) {
1004                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
1005                         ret |= ((cmd_reg_inhibit(s, i) ||
1006                                         (cmd_reg_inhibit(s, i + 1)))) ?
1007                                 -EBADRQC : 0;
1008                 if (ret)
1009                         break;
1010                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1011                 if (ret)
1012                         break;
1013                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1014                 if (ret)
1015                         break;
1016         }
1017         return ret;
1018 }
1019
1020 static inline int cmd_address_audit(struct parser_exec_state *s,
1021                 unsigned long guest_gma, int op_size, bool index_mode);
1022
1023 static int cmd_handler_lrm(struct parser_exec_state *s)
1024 {
1025         struct intel_gvt *gvt = s->vgpu->gvt;
1026         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1027         unsigned long gma;
1028         int i, ret = 0;
1029         int cmd_len = cmd_length(s);
1030
1031         for (i = 1; i < cmd_len;) {
1032                 if (IS_BROADWELL(gvt->dev_priv))
1033                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1034                 if (ret)
1035                         break;
1036                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1037                 if (ret)
1038                         break;
1039                 if (cmd_val(s, 0) & (1 << 22)) {
1040                         gma = cmd_gma(s, i + 1);
1041                         if (gmadr_bytes == 8)
1042                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1043                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1044                         if (ret)
1045                                 break;
1046                 }
1047                 i += gmadr_dw_number(s) + 1;
1048         }
1049         return ret;
1050 }
1051
1052 static int cmd_handler_srm(struct parser_exec_state *s)
1053 {
1054         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1055         unsigned long gma;
1056         int i, ret = 0;
1057         int cmd_len = cmd_length(s);
1058
1059         for (i = 1; i < cmd_len;) {
1060                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1061                 if (ret)
1062                         break;
1063                 if (cmd_val(s, 0) & (1 << 22)) {
1064                         gma = cmd_gma(s, i + 1);
1065                         if (gmadr_bytes == 8)
1066                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1067                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1068                         if (ret)
1069                                 break;
1070                 }
1071                 i += gmadr_dw_number(s) + 1;
1072         }
1073         return ret;
1074 }
1075
1076 struct cmd_interrupt_event {
1077         int pipe_control_notify;
1078         int mi_flush_dw;
1079         int mi_user_interrupt;
1080 };
1081
1082 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1083         [RCS0] = {
1084                 .pipe_control_notify = RCS_PIPE_CONTROL,
1085                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1086                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1087         },
1088         [BCS0] = {
1089                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1090                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1091                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1092         },
1093         [VCS0] = {
1094                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1095                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1096                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1097         },
1098         [VCS1] = {
1099                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1100                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1101                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1102         },
1103         [VECS0] = {
1104                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1105                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1106                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1107         },
1108 };
1109
1110 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1111 {
1112         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1113         unsigned long gma;
1114         bool index_mode = false;
1115         unsigned int post_sync;
1116         int ret = 0;
1117         u32 hws_pga, val;
1118
1119         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1120
1121         /* LRI post sync */
1122         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1123                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1124         /* post sync */
1125         else if (post_sync) {
1126                 if (post_sync == 2)
1127                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1128                 else if (post_sync == 3)
1129                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1130                 else if (post_sync == 1) {
1131                         /* check ggtt*/
1132                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1133                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1134                                 if (gmadr_bytes == 8)
1135                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1136                                 /* Store Data Index */
1137                                 if (cmd_val(s, 1) & (1 << 21))
1138                                         index_mode = true;
1139                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1140                                                 index_mode);
1141                                 if (ret)
1142                                         return ret;
1143                                 if (index_mode) {
1144                                         hws_pga = s->vgpu->hws_pga[s->ring_id];
1145                                         gma = hws_pga + gma;
1146                                         patch_value(s, cmd_ptr(s, 2), gma);
1147                                         val = cmd_val(s, 1) & (~(1 << 21));
1148                                         patch_value(s, cmd_ptr(s, 1), val);
1149                                 }
1150                         }
1151                 }
1152         }
1153
1154         if (ret)
1155                 return ret;
1156
1157         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1158                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1159                                 s->workload->pending_events);
1160         return 0;
1161 }
1162
1163 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1164 {
1165         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1166                         s->workload->pending_events);
1167         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1168         return 0;
1169 }
1170
1171 static int cmd_advance_default(struct parser_exec_state *s)
1172 {
1173         return ip_gma_advance(s, cmd_length(s));
1174 }
1175
1176 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1177 {
1178         int ret;
1179
1180         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1181                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1182                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1183                 s->buf_addr_type = s->saved_buf_addr_type;
1184         } else {
1185                 s->buf_type = RING_BUFFER_INSTRUCTION;
1186                 s->buf_addr_type = GTT_BUFFER;
1187                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1188                         s->ret_ip_gma_ring -= s->ring_size;
1189                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1190         }
1191         return ret;
1192 }
1193
1194 struct mi_display_flip_command_info {
1195         int pipe;
1196         int plane;
1197         int event;
1198         i915_reg_t stride_reg;
1199         i915_reg_t ctrl_reg;
1200         i915_reg_t surf_reg;
1201         u64 stride_val;
1202         u64 tile_val;
1203         u64 surf_val;
1204         bool async_flip;
1205 };
1206
1207 struct plane_code_mapping {
1208         int pipe;
1209         int plane;
1210         int event;
1211 };
1212
1213 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1214                 struct mi_display_flip_command_info *info)
1215 {
1216         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1217         struct plane_code_mapping gen8_plane_code[] = {
1218                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1219                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1220                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1221                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1222                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1223                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1224         };
1225         u32 dword0, dword1, dword2;
1226         u32 v;
1227
1228         dword0 = cmd_val(s, 0);
1229         dword1 = cmd_val(s, 1);
1230         dword2 = cmd_val(s, 2);
1231
1232         v = (dword0 & GENMASK(21, 19)) >> 19;
1233         if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1234                 return -EBADRQC;
1235
1236         info->pipe = gen8_plane_code[v].pipe;
1237         info->plane = gen8_plane_code[v].plane;
1238         info->event = gen8_plane_code[v].event;
1239         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1240         info->tile_val = (dword1 & 0x1);
1241         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1242         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1243
1244         if (info->plane == PLANE_A) {
1245                 info->ctrl_reg = DSPCNTR(info->pipe);
1246                 info->stride_reg = DSPSTRIDE(info->pipe);
1247                 info->surf_reg = DSPSURF(info->pipe);
1248         } else if (info->plane == PLANE_B) {
1249                 info->ctrl_reg = SPRCTL(info->pipe);
1250                 info->stride_reg = SPRSTRIDE(info->pipe);
1251                 info->surf_reg = SPRSURF(info->pipe);
1252         } else {
1253                 drm_WARN_ON(&dev_priv->drm, 1);
1254                 return -EBADRQC;
1255         }
1256         return 0;
1257 }
1258
1259 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1260                 struct mi_display_flip_command_info *info)
1261 {
1262         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1263         struct intel_vgpu *vgpu = s->vgpu;
1264         u32 dword0 = cmd_val(s, 0);
1265         u32 dword1 = cmd_val(s, 1);
1266         u32 dword2 = cmd_val(s, 2);
1267         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1268
1269         info->plane = PRIMARY_PLANE;
1270
1271         switch (plane) {
1272         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1273                 info->pipe = PIPE_A;
1274                 info->event = PRIMARY_A_FLIP_DONE;
1275                 break;
1276         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1277                 info->pipe = PIPE_B;
1278                 info->event = PRIMARY_B_FLIP_DONE;
1279                 break;
1280         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1281                 info->pipe = PIPE_C;
1282                 info->event = PRIMARY_C_FLIP_DONE;
1283                 break;
1284
1285         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1286                 info->pipe = PIPE_A;
1287                 info->event = SPRITE_A_FLIP_DONE;
1288                 info->plane = SPRITE_PLANE;
1289                 break;
1290         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1291                 info->pipe = PIPE_B;
1292                 info->event = SPRITE_B_FLIP_DONE;
1293                 info->plane = SPRITE_PLANE;
1294                 break;
1295         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1296                 info->pipe = PIPE_C;
1297                 info->event = SPRITE_C_FLIP_DONE;
1298                 info->plane = SPRITE_PLANE;
1299                 break;
1300
1301         default:
1302                 gvt_vgpu_err("unknown plane code %d\n", plane);
1303                 return -EBADRQC;
1304         }
1305
1306         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1307         info->tile_val = (dword1 & GENMASK(2, 0));
1308         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1309         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1310
1311         info->ctrl_reg = DSPCNTR(info->pipe);
1312         info->stride_reg = DSPSTRIDE(info->pipe);
1313         info->surf_reg = DSPSURF(info->pipe);
1314
1315         return 0;
1316 }
1317
1318 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1319                 struct mi_display_flip_command_info *info)
1320 {
1321         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1322         u32 stride, tile;
1323
1324         if (!info->async_flip)
1325                 return 0;
1326
1327         if (INTEL_GEN(dev_priv) >= 9) {
1328                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1329                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1330                                 GENMASK(12, 10)) >> 10;
1331         } else {
1332                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1333                                 GENMASK(15, 6)) >> 6;
1334                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1335         }
1336
1337         if (stride != info->stride_val)
1338                 gvt_dbg_cmd("cannot change stride during async flip\n");
1339
1340         if (tile != info->tile_val)
1341                 gvt_dbg_cmd("cannot change tile during async flip\n");
1342
1343         return 0;
1344 }
1345
1346 static int gen8_update_plane_mmio_from_mi_display_flip(
1347                 struct parser_exec_state *s,
1348                 struct mi_display_flip_command_info *info)
1349 {
1350         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1351         struct intel_vgpu *vgpu = s->vgpu;
1352
1353         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1354                       info->surf_val << 12);
1355         if (INTEL_GEN(dev_priv) >= 9) {
1356                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1357                               info->stride_val);
1358                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1359                               info->tile_val << 10);
1360         } else {
1361                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1362                               info->stride_val << 6);
1363                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1364                               info->tile_val << 10);
1365         }
1366
1367         if (info->plane == PLANE_PRIMARY)
1368                 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
1369
1370         if (info->async_flip)
1371                 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1372         else
1373                 set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1374
1375         return 0;
1376 }
1377
1378 static int decode_mi_display_flip(struct parser_exec_state *s,
1379                 struct mi_display_flip_command_info *info)
1380 {
1381         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1382
1383         if (IS_BROADWELL(dev_priv))
1384                 return gen8_decode_mi_display_flip(s, info);
1385         if (INTEL_GEN(dev_priv) >= 9)
1386                 return skl_decode_mi_display_flip(s, info);
1387
1388         return -ENODEV;
1389 }
1390
1391 static int check_mi_display_flip(struct parser_exec_state *s,
1392                 struct mi_display_flip_command_info *info)
1393 {
1394         return gen8_check_mi_display_flip(s, info);
1395 }
1396
1397 static int update_plane_mmio_from_mi_display_flip(
1398                 struct parser_exec_state *s,
1399                 struct mi_display_flip_command_info *info)
1400 {
1401         return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1402 }
1403
1404 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1405 {
1406         struct mi_display_flip_command_info info;
1407         struct intel_vgpu *vgpu = s->vgpu;
1408         int ret;
1409         int i;
1410         int len = cmd_length(s);
1411         u32 valid_len = CMD_LEN(1);
1412
1413         /* Flip Type == Stereo 3D Flip */
1414         if (DWORD_FIELD(2, 1, 0) == 2)
1415                 valid_len++;
1416         ret = gvt_check_valid_cmd_length(cmd_length(s),
1417                         valid_len);
1418         if (ret)
1419                 return ret;
1420
1421         ret = decode_mi_display_flip(s, &info);
1422         if (ret) {
1423                 gvt_vgpu_err("fail to decode MI display flip command\n");
1424                 return ret;
1425         }
1426
1427         ret = check_mi_display_flip(s, &info);
1428         if (ret) {
1429                 gvt_vgpu_err("invalid MI display flip command\n");
1430                 return ret;
1431         }
1432
1433         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1434         if (ret) {
1435                 gvt_vgpu_err("fail to update plane mmio\n");
1436                 return ret;
1437         }
1438
1439         for (i = 0; i < len; i++)
1440                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1441         return 0;
1442 }
1443
1444 static bool is_wait_for_flip_pending(u32 cmd)
1445 {
1446         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1447                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1448                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1449                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1450                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1451                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1452 }
1453
1454 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1455 {
1456         u32 cmd = cmd_val(s, 0);
1457
1458         if (!is_wait_for_flip_pending(cmd))
1459                 return 0;
1460
1461         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1462         return 0;
1463 }
1464
1465 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1466 {
1467         unsigned long addr;
1468         unsigned long gma_high, gma_low;
1469         struct intel_vgpu *vgpu = s->vgpu;
1470         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1471
1472         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1473                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1474                 return INTEL_GVT_INVALID_ADDR;
1475         }
1476
1477         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1478         if (gmadr_bytes == 4) {
1479                 addr = gma_low;
1480         } else {
1481                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1482                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1483         }
1484         return addr;
1485 }
1486
1487 static inline int cmd_address_audit(struct parser_exec_state *s,
1488                 unsigned long guest_gma, int op_size, bool index_mode)
1489 {
1490         struct intel_vgpu *vgpu = s->vgpu;
1491         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1492         int i;
1493         int ret;
1494
1495         if (op_size > max_surface_size) {
1496                 gvt_vgpu_err("command address audit fail name %s\n",
1497                         s->info->name);
1498                 return -EFAULT;
1499         }
1500
1501         if (index_mode) {
1502                 if (guest_gma >= I915_GTT_PAGE_SIZE) {
1503                         ret = -EFAULT;
1504                         goto err;
1505                 }
1506         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1507                 ret = -EFAULT;
1508                 goto err;
1509         }
1510
1511         return 0;
1512
1513 err:
1514         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1515                         s->info->name, guest_gma, op_size);
1516
1517         pr_err("cmd dump: ");
1518         for (i = 0; i < cmd_length(s); i++) {
1519                 if (!(i % 4))
1520                         pr_err("\n%08x ", cmd_val(s, i));
1521                 else
1522                         pr_err("%08x ", cmd_val(s, i));
1523         }
1524         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1525                         vgpu->id,
1526                         vgpu_aperture_gmadr_base(vgpu),
1527                         vgpu_aperture_gmadr_end(vgpu),
1528                         vgpu_hidden_gmadr_base(vgpu),
1529                         vgpu_hidden_gmadr_end(vgpu));
1530         return ret;
1531 }
1532
1533 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1534 {
1535         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1536         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1537         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1538         unsigned long gma, gma_low, gma_high;
1539         u32 valid_len = CMD_LEN(2);
1540         int ret = 0;
1541
1542         /* check ppggt */
1543         if (!(cmd_val(s, 0) & (1 << 22)))
1544                 return 0;
1545
1546         /* check if QWORD */
1547         if (DWORD_FIELD(0, 21, 21))
1548                 valid_len++;
1549         ret = gvt_check_valid_cmd_length(cmd_length(s),
1550                         valid_len);
1551         if (ret)
1552                 return ret;
1553
1554         gma = cmd_val(s, 2) & GENMASK(31, 2);
1555
1556         if (gmadr_bytes == 8) {
1557                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1558                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1559                 gma = (gma_high << 32) | gma_low;
1560                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1561         }
1562         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1563         return ret;
1564 }
1565
1566 static inline int unexpected_cmd(struct parser_exec_state *s)
1567 {
1568         struct intel_vgpu *vgpu = s->vgpu;
1569
1570         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1571
1572         return -EBADRQC;
1573 }
1574
1575 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1576 {
1577         return unexpected_cmd(s);
1578 }
1579
1580 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1581 {
1582         return unexpected_cmd(s);
1583 }
1584
1585 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1586 {
1587         return unexpected_cmd(s);
1588 }
1589
1590 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1591 {
1592         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1593         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1594                         sizeof(u32);
1595         unsigned long gma, gma_high;
1596         u32 valid_len = CMD_LEN(1);
1597         int ret = 0;
1598
1599         if (!(cmd_val(s, 0) & (1 << 22)))
1600                 return ret;
1601
1602         /* check inline data */
1603         if (cmd_val(s, 0) & BIT(18))
1604                 valid_len = CMD_LEN(9);
1605         ret = gvt_check_valid_cmd_length(cmd_length(s),
1606                         valid_len);
1607         if (ret)
1608                 return ret;
1609
1610         gma = cmd_val(s, 1) & GENMASK(31, 2);
1611         if (gmadr_bytes == 8) {
1612                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1613                 gma = (gma_high << 32) | gma;
1614         }
1615         ret = cmd_address_audit(s, gma, op_size, false);
1616         return ret;
1617 }
1618
1619 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1620 {
1621         return unexpected_cmd(s);
1622 }
1623
1624 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1625 {
1626         return unexpected_cmd(s);
1627 }
1628
1629 static int cmd_handler_mi_conditional_batch_buffer_end(
1630                 struct parser_exec_state *s)
1631 {
1632         return unexpected_cmd(s);
1633 }
1634
1635 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1636 {
1637         return unexpected_cmd(s);
1638 }
1639
1640 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1641 {
1642         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1643         unsigned long gma;
1644         bool index_mode = false;
1645         int ret = 0;
1646         u32 hws_pga, val;
1647         u32 valid_len = CMD_LEN(2);
1648
1649         ret = gvt_check_valid_cmd_length(cmd_length(s),
1650                         valid_len);
1651         if (ret) {
1652                 /* Check again for Qword */
1653                 ret = gvt_check_valid_cmd_length(cmd_length(s),
1654                         ++valid_len);
1655                 return ret;
1656         }
1657
1658         /* Check post-sync and ppgtt bit */
1659         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1660                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1661                 if (gmadr_bytes == 8)
1662                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1663                 /* Store Data Index */
1664                 if (cmd_val(s, 0) & (1 << 21))
1665                         index_mode = true;
1666                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1667                 if (ret)
1668                         return ret;
1669                 if (index_mode) {
1670                         hws_pga = s->vgpu->hws_pga[s->ring_id];
1671                         gma = hws_pga + gma;
1672                         patch_value(s, cmd_ptr(s, 1), gma);
1673                         val = cmd_val(s, 0) & (~(1 << 21));
1674                         patch_value(s, cmd_ptr(s, 0), val);
1675                 }
1676         }
1677         /* Check notify bit */
1678         if ((cmd_val(s, 0) & (1 << 8)))
1679                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1680                                 s->workload->pending_events);
1681         return ret;
1682 }
1683
1684 static void addr_type_update_snb(struct parser_exec_state *s)
1685 {
1686         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1687                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1688                 s->buf_addr_type = PPGTT_BUFFER;
1689         }
1690 }
1691
1692
1693 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1694                 unsigned long gma, unsigned long end_gma, void *va)
1695 {
1696         unsigned long copy_len, offset;
1697         unsigned long len = 0;
1698         unsigned long gpa;
1699
1700         while (gma != end_gma) {
1701                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1702                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1703                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1704                         return -EFAULT;
1705                 }
1706
1707                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1708
1709                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1710                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1711
1712                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1713
1714                 len += copy_len;
1715                 gma += copy_len;
1716         }
1717         return len;
1718 }
1719
1720
1721 /*
1722  * Check whether a batch buffer needs to be scanned. Currently
1723  * the only criteria is based on privilege.
1724  */
1725 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1726 {
1727         /* Decide privilege based on address space */
1728         if (cmd_val(s, 0) & (1 << 8) &&
1729                         !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1730                 return 0;
1731         return 1;
1732 }
1733
1734 static int find_bb_size(struct parser_exec_state *s,
1735                         unsigned long *bb_size,
1736                         unsigned long *bb_end_cmd_offset)
1737 {
1738         unsigned long gma = 0;
1739         const struct cmd_info *info;
1740         u32 cmd_len = 0;
1741         bool bb_end = false;
1742         struct intel_vgpu *vgpu = s->vgpu;
1743         u32 cmd;
1744         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1745                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1746
1747         *bb_size = 0;
1748         *bb_end_cmd_offset = 0;
1749
1750         /* get the start gm address of the batch buffer */
1751         gma = get_gma_bb_from_cmd(s, 1);
1752         if (gma == INTEL_GVT_INVALID_ADDR)
1753                 return -EFAULT;
1754
1755         cmd = cmd_val(s, 0);
1756         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1757         if (info == NULL) {
1758                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1759                                 cmd, get_opcode(cmd, s->ring_id),
1760                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1761                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1762                 return -EBADRQC;
1763         }
1764         do {
1765                 if (copy_gma_to_hva(s->vgpu, mm,
1766                                 gma, gma + 4, &cmd) < 0)
1767                         return -EFAULT;
1768                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1769                 if (info == NULL) {
1770                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1771                                 cmd, get_opcode(cmd, s->ring_id),
1772                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1773                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1774                         return -EBADRQC;
1775                 }
1776
1777                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1778                         bb_end = true;
1779                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1780                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1781                                 /* chained batch buffer */
1782                                 bb_end = true;
1783                 }
1784
1785                 if (bb_end)
1786                         *bb_end_cmd_offset = *bb_size;
1787
1788                 cmd_len = get_cmd_length(info, cmd) << 2;
1789                 *bb_size += cmd_len;
1790                 gma += cmd_len;
1791         } while (!bb_end);
1792
1793         return 0;
1794 }
1795
1796 static int audit_bb_end(struct parser_exec_state *s, void *va)
1797 {
1798         struct intel_vgpu *vgpu = s->vgpu;
1799         u32 cmd = *(u32 *)va;
1800         const struct cmd_info *info;
1801
1802         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1803         if (info == NULL) {
1804                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1805                         cmd, get_opcode(cmd, s->ring_id),
1806                         (s->buf_addr_type == PPGTT_BUFFER) ?
1807                         "ppgtt" : "ggtt", s->ring_id, s->workload);
1808                 return -EBADRQC;
1809         }
1810
1811         if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1812             ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1813              (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1814                 return 0;
1815
1816         return -EBADRQC;
1817 }
1818
1819 static int perform_bb_shadow(struct parser_exec_state *s)
1820 {
1821         struct intel_vgpu *vgpu = s->vgpu;
1822         struct intel_vgpu_shadow_bb *bb;
1823         unsigned long gma = 0;
1824         unsigned long bb_size;
1825         unsigned long bb_end_cmd_offset;
1826         int ret = 0;
1827         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1828                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1829         unsigned long start_offset = 0;
1830
1831         /* get the start gm address of the batch buffer */
1832         gma = get_gma_bb_from_cmd(s, 1);
1833         if (gma == INTEL_GVT_INVALID_ADDR)
1834                 return -EFAULT;
1835
1836         ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1837         if (ret)
1838                 return ret;
1839
1840         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1841         if (!bb)
1842                 return -ENOMEM;
1843
1844         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1845
1846         /* the start_offset stores the batch buffer's start gma's
1847          * offset relative to page boundary. so for non-privileged batch
1848          * buffer, the shadowed gem object holds exactly the same page
1849          * layout as original gem object. This is for the convience of
1850          * replacing the whole non-privilged batch buffer page to this
1851          * shadowed one in PPGTT at the same gma address. (this replacing
1852          * action is not implemented yet now, but may be necessary in
1853          * future).
1854          * for prileged batch buffer, we just change start gma address to
1855          * that of shadowed page.
1856          */
1857         if (bb->ppgtt)
1858                 start_offset = gma & ~I915_GTT_PAGE_MASK;
1859
1860         bb->obj = i915_gem_object_create_shmem(s->vgpu->gvt->dev_priv,
1861                                                round_up(bb_size + start_offset,
1862                                                         PAGE_SIZE));
1863         if (IS_ERR(bb->obj)) {
1864                 ret = PTR_ERR(bb->obj);
1865                 goto err_free_bb;
1866         }
1867
1868         ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush);
1869         if (ret)
1870                 goto err_free_obj;
1871
1872         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1873         if (IS_ERR(bb->va)) {
1874                 ret = PTR_ERR(bb->va);
1875                 goto err_finish_shmem_access;
1876         }
1877
1878         if (bb->clflush & CLFLUSH_BEFORE) {
1879                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1880                 bb->clflush &= ~CLFLUSH_BEFORE;
1881         }
1882
1883         ret = copy_gma_to_hva(s->vgpu, mm,
1884                               gma, gma + bb_size,
1885                               bb->va + start_offset);
1886         if (ret < 0) {
1887                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1888                 ret = -EFAULT;
1889                 goto err_unmap;
1890         }
1891
1892         ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1893         if (ret)
1894                 goto err_unmap;
1895
1896         INIT_LIST_HEAD(&bb->list);
1897         list_add(&bb->list, &s->workload->shadow_bb);
1898
1899         bb->accessing = true;
1900         bb->bb_start_cmd_va = s->ip_va;
1901
1902         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1903                 bb->bb_offset = s->ip_va - s->rb_va;
1904         else
1905                 bb->bb_offset = 0;
1906
1907         /*
1908          * ip_va saves the virtual address of the shadow batch buffer, while
1909          * ip_gma saves the graphics address of the original batch buffer.
1910          * As the shadow batch buffer is just a copy from the originial one,
1911          * it should be right to use shadow batch buffer'va and original batch
1912          * buffer's gma in pair. After all, we don't want to pin the shadow
1913          * buffer here (too early).
1914          */
1915         s->ip_va = bb->va + start_offset;
1916         s->ip_gma = gma;
1917         return 0;
1918 err_unmap:
1919         i915_gem_object_unpin_map(bb->obj);
1920 err_finish_shmem_access:
1921         i915_gem_object_finish_access(bb->obj);
1922 err_free_obj:
1923         i915_gem_object_put(bb->obj);
1924 err_free_bb:
1925         kfree(bb);
1926         return ret;
1927 }
1928
1929 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1930 {
1931         bool second_level;
1932         int ret = 0;
1933         struct intel_vgpu *vgpu = s->vgpu;
1934
1935         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1936                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1937                 return -EFAULT;
1938         }
1939
1940         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1941         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1942                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1943                 return -EFAULT;
1944         }
1945
1946         s->saved_buf_addr_type = s->buf_addr_type;
1947         addr_type_update_snb(s);
1948         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1949                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1950                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1951         } else if (second_level) {
1952                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1953                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1954                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1955         }
1956
1957         if (batch_buffer_needs_scan(s)) {
1958                 ret = perform_bb_shadow(s);
1959                 if (ret < 0)
1960                         gvt_vgpu_err("invalid shadow batch buffer\n");
1961         } else {
1962                 /* emulate a batch buffer end to do return right */
1963                 ret = cmd_handler_mi_batch_buffer_end(s);
1964                 if (ret < 0)
1965                         return ret;
1966         }
1967         return ret;
1968 }
1969
1970 static int mi_noop_index;
1971
1972 static const struct cmd_info cmd_info[] = {
1973         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1974
1975         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1976                 0, 1, NULL},
1977
1978         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1979                 0, 1, cmd_handler_mi_user_interrupt},
1980
1981         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1982                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1983
1984         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1985
1986         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1987                 NULL},
1988
1989         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1990                 NULL},
1991
1992         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1993                 NULL},
1994
1995         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1996                 NULL},
1997
1998         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1999                 D_ALL, 0, 1, NULL},
2000
2001         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2002                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2003                 cmd_handler_mi_batch_buffer_end},
2004
2005         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2006                 0, 1, NULL},
2007
2008         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2009                 NULL},
2010
2011         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2012                 D_ALL, 0, 1, NULL},
2013
2014         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2015                 NULL},
2016
2017         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2018                 NULL},
2019
2020         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2021                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2022
2023         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2024                 R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2025
2026         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2027
2028         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2029                 D_ALL, 0, 8, NULL, CMD_LEN(0)},
2030
2031         {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2032                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2033                 NULL, CMD_LEN(0)},
2034
2035         {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2036                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2037                 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2038
2039         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2040                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2041
2042         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2043                 0, 8, cmd_handler_mi_store_data_index},
2044
2045         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2046                 D_ALL, 0, 8, cmd_handler_lri},
2047
2048         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2049                 cmd_handler_mi_update_gtt},
2050
2051         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2052                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2053                 cmd_handler_srm, CMD_LEN(2)},
2054
2055         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2056                 cmd_handler_mi_flush_dw},
2057
2058         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2059                 10, cmd_handler_mi_clflush},
2060
2061         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2062                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2063                 cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2064
2065         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2066                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2067                 cmd_handler_lrm, CMD_LEN(2)},
2068
2069         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2070                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2071                 cmd_handler_lrr, CMD_LEN(1)},
2072
2073         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2074                 F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2075                 8, NULL, CMD_LEN(2)},
2076
2077         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2078                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2079
2080         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2081                 ADDR_FIX_1(2), 8, NULL},
2082
2083         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2084                 ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2085
2086         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2087                 8, cmd_handler_mi_op_2f},
2088
2089         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2090                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2091                 cmd_handler_mi_batch_buffer_start},
2092
2093         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2094                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2095                 cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2096
2097         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2098                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2099
2100         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2101                 ADDR_FIX_2(4, 7), 8, NULL},
2102
2103         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2104                 0, 8, NULL},
2105
2106         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2107                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2108
2109         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2110
2111         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2112                 0, 8, NULL},
2113
2114         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2115                 ADDR_FIX_1(3), 8, NULL},
2116
2117         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2118                 D_ALL, 0, 8, NULL},
2119
2120         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2121                 ADDR_FIX_1(4), 8, NULL},
2122
2123         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2124                 ADDR_FIX_2(4, 5), 8, NULL},
2125
2126         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2127                 ADDR_FIX_1(4), 8, NULL},
2128
2129         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2130                 ADDR_FIX_2(4, 7), 8, NULL},
2131
2132         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2133                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2134
2135         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2136
2137         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2138                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2139
2140         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2141                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2142
2143         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2144                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2145                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2146
2147         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2148                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2149
2150         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2151                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2152
2153         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2154                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2155
2156         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2157                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2158
2159         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2160                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2161
2162         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2163                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2164                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2165
2166         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2167                 ADDR_FIX_2(4, 5), 8, NULL},
2168
2169         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2170                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2171
2172         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2173                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2174                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2175
2176         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2177                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2178                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2179
2180         {"3DSTATE_BLEND_STATE_POINTERS",
2181                 OP_3DSTATE_BLEND_STATE_POINTERS,
2182                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2183
2184         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2185                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2186                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2187
2188         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2189                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2190                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2191
2192         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2193                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2194                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2195
2196         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2197                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2198                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2199
2200         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2201                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2202                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2203
2204         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2205                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2206                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2207
2208         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2209                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2210                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2211
2212         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2213                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2214                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2215
2216         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2217                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2218                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2219
2220         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2221                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2222                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2223
2224         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2225                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2226                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2227
2228         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2229                 0, 8, NULL},
2230
2231         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2232                 0, 8, NULL},
2233
2234         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2235                 0, 8, NULL},
2236
2237         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2238                 0, 8, NULL},
2239
2240         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2241                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2242
2243         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2244                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2245
2246         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2247                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2248
2249         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2250                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2251
2252         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2253                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2254
2255         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2256                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2257
2258         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2259                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2260
2261         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2262                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2263
2264         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2265                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2266
2267         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2268                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2269
2270         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2271                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2272
2273         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2274                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2275
2276         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2277                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2278
2279         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2280                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2281
2282         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2283                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2284
2285         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2286                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2287
2288         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2289                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2290
2291         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2292                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2293
2294         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2295                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2296
2297         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2298                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2299
2300         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2301                 D_BDW_PLUS, 0, 8, NULL},
2302
2303         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2304                 NULL},
2305
2306         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2307                 D_BDW_PLUS, 0, 8, NULL},
2308
2309         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2310                 D_BDW_PLUS, 0, 8, NULL},
2311
2312         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2313                 8, NULL},
2314
2315         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2316                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2317
2318         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2319                 8, NULL},
2320
2321         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2322                 NULL},
2323
2324         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2325                 NULL},
2326
2327         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2328                 NULL},
2329
2330         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2331                 D_BDW_PLUS, 0, 8, NULL},
2332
2333         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2334                 R_RCS, D_ALL, 0, 8, NULL},
2335
2336         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2337                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2338
2339         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2340                 R_RCS, D_ALL, 0, 1, NULL},
2341
2342         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2343
2344         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2345                 R_RCS, D_ALL, 0, 8, NULL},
2346
2347         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2348                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2349
2350         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2351
2352         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2353
2354         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2355
2356         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2357                 D_BDW_PLUS, 0, 8, NULL},
2358
2359         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2360                 D_BDW_PLUS, 0, 8, NULL},
2361
2362         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2363                 D_ALL, 0, 8, NULL},
2364
2365         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2366                 D_BDW_PLUS, 0, 8, NULL},
2367
2368         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2369                 D_BDW_PLUS, 0, 8, NULL},
2370
2371         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2372
2373         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2374
2375         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2376
2377         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2378                 D_ALL, 0, 8, NULL},
2379
2380         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2381
2382         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2383
2384         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2385                 R_RCS, D_ALL, 0, 8, NULL},
2386
2387         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2388                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2389
2390         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2391                 0, 8, NULL},
2392
2393         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2394                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2395
2396         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2397                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2398
2399         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2400                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2401
2402         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2403                 D_ALL, 0, 8, NULL},
2404
2405         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2406                 D_ALL, 0, 8, NULL},
2407
2408         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2409                 D_ALL, 0, 8, NULL},
2410
2411         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2412                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2413
2414         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2415                 D_BDW_PLUS, 0, 8, NULL},
2416
2417         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2418                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2419
2420         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2421                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2422
2423         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2424                 R_RCS, D_ALL, 0, 8, NULL},
2425
2426         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2427                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2428
2429         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2430                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2431
2432         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2433                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2434
2435         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2436                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2437
2438         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2439                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2440
2441         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2442                 R_RCS, D_ALL, 0, 8, NULL},
2443
2444         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2445                 D_ALL, 0, 9, NULL},
2446
2447         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2448                 ADDR_FIX_2(2, 4), 8, NULL},
2449
2450         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2451                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2452                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2453
2454         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2455                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2456
2457         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2458                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2459                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2460
2461         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2462                 D_BDW_PLUS, 0, 8, NULL},
2463
2464         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2465                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2466
2467         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2468
2469         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2470                 1, NULL},
2471
2472         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2473                 ADDR_FIX_1(1), 8, NULL},
2474
2475         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2476
2477         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2478                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2479
2480         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2481                 ADDR_FIX_1(1), 8, NULL},
2482
2483         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2484
2485         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2486
2487         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2488                 0, 8, NULL},
2489
2490         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2491                 D_SKL_PLUS, 0, 8, NULL},
2492
2493         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2494                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2495
2496         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2497                 0, 16, NULL},
2498
2499         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2500                 0, 16, NULL},
2501
2502         {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2503                 0, 16, NULL},
2504
2505         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2506
2507         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2508                 0, 16, NULL},
2509
2510         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2511                 0, 16, NULL},
2512
2513         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2514                 0, 16, NULL},
2515
2516         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2517                 0, 8, NULL},
2518
2519         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2520                 NULL},
2521
2522         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2523                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2524
2525         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2526                 R_VCS, D_ALL, 0, 12, NULL},
2527
2528         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2529                 R_VCS, D_ALL, 0, 12, NULL},
2530
2531         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2532                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2533
2534         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2535                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2536
2537         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2538                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2539
2540         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2541
2542         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2543                 R_VCS, D_ALL, 0, 12, NULL},
2544
2545         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2546                 R_VCS, D_ALL, 0, 12, NULL},
2547
2548         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2549                 R_VCS, D_ALL, 0, 12, NULL},
2550
2551         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2552                 R_VCS, D_ALL, 0, 12, NULL},
2553
2554         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2555                 R_VCS, D_ALL, 0, 12, NULL},
2556
2557         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2558                 R_VCS, D_ALL, 0, 12, NULL},
2559
2560         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2561                 R_VCS, D_ALL, 0, 6, NULL},
2562
2563         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2564                 R_VCS, D_ALL, 0, 12, NULL},
2565
2566         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2567                 R_VCS, D_ALL, 0, 12, NULL},
2568
2569         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2570                 R_VCS, D_ALL, 0, 12, NULL},
2571
2572         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2573                 R_VCS, D_ALL, 0, 12, NULL},
2574
2575         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2576                 R_VCS, D_ALL, 0, 12, NULL},
2577
2578         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2579                 R_VCS, D_ALL, 0, 12, NULL},
2580
2581         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2582                 R_VCS, D_ALL, 0, 12, NULL},
2583         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2584                 R_VCS, D_ALL, 0, 12, NULL},
2585
2586         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2587                 R_VCS, D_ALL, 0, 12, NULL},
2588
2589         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2590                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2591
2592         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2593                 R_VCS, D_ALL, 0, 12, NULL},
2594
2595         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2596                 R_VCS, D_ALL, 0, 12, NULL},
2597
2598         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2599                 R_VCS, D_ALL, 0, 12, NULL},
2600
2601         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2602                 R_VCS, D_ALL, 0, 12, NULL},
2603
2604         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2605                 R_VCS, D_ALL, 0, 12, NULL},
2606
2607         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2608                 R_VCS, D_ALL, 0, 12, NULL},
2609
2610         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2611                 R_VCS, D_ALL, 0, 12, NULL},
2612
2613         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2614                 R_VCS, D_ALL, 0, 12, NULL},
2615
2616         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2617                 R_VCS, D_ALL, 0, 12, NULL},
2618
2619         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2620                 R_VCS, D_ALL, 0, 12, NULL},
2621
2622         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2623                 R_VCS, D_ALL, 0, 12, NULL},
2624
2625         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2626                 0, 16, NULL},
2627
2628         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2629
2630         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2631
2632         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2633                 R_VCS, D_ALL, 0, 12, NULL},
2634
2635         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2636                 R_VCS, D_ALL, 0, 12, NULL},
2637
2638         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2639                 R_VCS, D_ALL, 0, 12, NULL},
2640
2641         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2642
2643         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2644                 0, 12, NULL},
2645
2646         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2647                 0, 12, NULL},
2648 };
2649
2650 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2651 {
2652         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2653 }
2654
2655 /* call the cmd handler, and advance ip */
2656 static int cmd_parser_exec(struct parser_exec_state *s)
2657 {
2658         struct intel_vgpu *vgpu = s->vgpu;
2659         const struct cmd_info *info;
2660         u32 cmd;
2661         int ret = 0;
2662
2663         cmd = cmd_val(s, 0);
2664
2665         /* fastpath for MI_NOOP */
2666         if (cmd == MI_NOOP)
2667                 info = &cmd_info[mi_noop_index];
2668         else
2669                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2670
2671         if (info == NULL) {
2672                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2673                                 cmd, get_opcode(cmd, s->ring_id),
2674                                 (s->buf_addr_type == PPGTT_BUFFER) ?
2675                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
2676                 return -EBADRQC;
2677         }
2678
2679         s->info = info;
2680
2681         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2682                           cmd_length(s), s->buf_type, s->buf_addr_type,
2683                           s->workload, info->name);
2684
2685         if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2686                 ret = gvt_check_valid_cmd_length(cmd_length(s),
2687                         info->valid_len);
2688                 if (ret)
2689                         return ret;
2690         }
2691
2692         if (info->handler) {
2693                 ret = info->handler(s);
2694                 if (ret < 0) {
2695                         gvt_vgpu_err("%s handler error\n", info->name);
2696                         return ret;
2697                 }
2698         }
2699
2700         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2701                 ret = cmd_advance_default(s);
2702                 if (ret) {
2703                         gvt_vgpu_err("%s IP advance error\n", info->name);
2704                         return ret;
2705                 }
2706         }
2707         return 0;
2708 }
2709
2710 static inline bool gma_out_of_range(unsigned long gma,
2711                 unsigned long gma_head, unsigned int gma_tail)
2712 {
2713         if (gma_tail >= gma_head)
2714                 return (gma < gma_head) || (gma > gma_tail);
2715         else
2716                 return (gma > gma_tail) && (gma < gma_head);
2717 }
2718
2719 /* Keep the consistent return type, e.g EBADRQC for unknown
2720  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2721  * works as the input of VM healthy status.
2722  */
2723 static int command_scan(struct parser_exec_state *s,
2724                 unsigned long rb_head, unsigned long rb_tail,
2725                 unsigned long rb_start, unsigned long rb_len)
2726 {
2727
2728         unsigned long gma_head, gma_tail, gma_bottom;
2729         int ret = 0;
2730         struct intel_vgpu *vgpu = s->vgpu;
2731
2732         gma_head = rb_start + rb_head;
2733         gma_tail = rb_start + rb_tail;
2734         gma_bottom = rb_start +  rb_len;
2735
2736         while (s->ip_gma != gma_tail) {
2737                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2738                         if (!(s->ip_gma >= rb_start) ||
2739                                 !(s->ip_gma < gma_bottom)) {
2740                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2741                                         "(base:0x%lx, bottom: 0x%lx)\n",
2742                                         s->ip_gma, rb_start,
2743                                         gma_bottom);
2744                                 parser_exec_state_dump(s);
2745                                 return -EFAULT;
2746                         }
2747                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2748                                 gvt_vgpu_err("ip_gma %lx out of range."
2749                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2750                                         s->ip_gma, rb_start,
2751                                         rb_head, rb_tail);
2752                                 parser_exec_state_dump(s);
2753                                 break;
2754                         }
2755                 }
2756                 ret = cmd_parser_exec(s);
2757                 if (ret) {
2758                         gvt_vgpu_err("cmd parser error\n");
2759                         parser_exec_state_dump(s);
2760                         break;
2761                 }
2762         }
2763
2764         return ret;
2765 }
2766
2767 static int scan_workload(struct intel_vgpu_workload *workload)
2768 {
2769         unsigned long gma_head, gma_tail, gma_bottom;
2770         struct parser_exec_state s;
2771         int ret = 0;
2772
2773         /* ring base is page aligned */
2774         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2775                 return -EINVAL;
2776
2777         gma_head = workload->rb_start + workload->rb_head;
2778         gma_tail = workload->rb_start + workload->rb_tail;
2779         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2780
2781         s.buf_type = RING_BUFFER_INSTRUCTION;
2782         s.buf_addr_type = GTT_BUFFER;
2783         s.vgpu = workload->vgpu;
2784         s.ring_id = workload->ring_id;
2785         s.ring_start = workload->rb_start;
2786         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2787         s.ring_head = gma_head;
2788         s.ring_tail = gma_tail;
2789         s.rb_va = workload->shadow_ring_buffer_va;
2790         s.workload = workload;
2791         s.is_ctx_wa = false;
2792
2793         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2794                 gma_head == gma_tail)
2795                 return 0;
2796
2797         ret = ip_gma_set(&s, gma_head);
2798         if (ret)
2799                 goto out;
2800
2801         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2802                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2803
2804 out:
2805         return ret;
2806 }
2807
2808 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2809 {
2810
2811         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2812         struct parser_exec_state s;
2813         int ret = 0;
2814         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2815                                 struct intel_vgpu_workload,
2816                                 wa_ctx);
2817
2818         /* ring base is page aligned */
2819         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2820                                         I915_GTT_PAGE_SIZE)))
2821                 return -EINVAL;
2822
2823         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2824         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2825                         PAGE_SIZE);
2826         gma_head = wa_ctx->indirect_ctx.guest_gma;
2827         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2828         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2829
2830         s.buf_type = RING_BUFFER_INSTRUCTION;
2831         s.buf_addr_type = GTT_BUFFER;
2832         s.vgpu = workload->vgpu;
2833         s.ring_id = workload->ring_id;
2834         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2835         s.ring_size = ring_size;
2836         s.ring_head = gma_head;
2837         s.ring_tail = gma_tail;
2838         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2839         s.workload = workload;
2840         s.is_ctx_wa = true;
2841
2842         ret = ip_gma_set(&s, gma_head);
2843         if (ret)
2844                 goto out;
2845
2846         ret = command_scan(&s, 0, ring_tail,
2847                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2848 out:
2849         return ret;
2850 }
2851
2852 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2853 {
2854         struct intel_vgpu *vgpu = workload->vgpu;
2855         struct intel_vgpu_submission *s = &vgpu->submission;
2856         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2857         void *shadow_ring_buffer_va;
2858         int ring_id = workload->ring_id;
2859         int ret;
2860
2861         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2862
2863         /* calculate workload ring buffer size */
2864         workload->rb_len = (workload->rb_tail + guest_rb_size -
2865                         workload->rb_head) % guest_rb_size;
2866
2867         gma_head = workload->rb_start + workload->rb_head;
2868         gma_tail = workload->rb_start + workload->rb_tail;
2869         gma_top = workload->rb_start + guest_rb_size;
2870
2871         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2872                 void *p;
2873
2874                 /* realloc the new ring buffer if needed */
2875                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2876                                 GFP_KERNEL);
2877                 if (!p) {
2878                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2879                         return -ENOMEM;
2880                 }
2881                 s->ring_scan_buffer[ring_id] = p;
2882                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2883         }
2884
2885         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2886
2887         /* get shadow ring buffer va */
2888         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2889
2890         /* head > tail --> copy head <-> top */
2891         if (gma_head > gma_tail) {
2892                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2893                                       gma_head, gma_top, shadow_ring_buffer_va);
2894                 if (ret < 0) {
2895                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2896                         return ret;
2897                 }
2898                 shadow_ring_buffer_va += ret;
2899                 gma_head = workload->rb_start;
2900         }
2901
2902         /* copy head or start <-> tail */
2903         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2904                                 shadow_ring_buffer_va);
2905         if (ret < 0) {
2906                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2907                 return ret;
2908         }
2909         return 0;
2910 }
2911
2912 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2913 {
2914         int ret;
2915         struct intel_vgpu *vgpu = workload->vgpu;
2916
2917         ret = shadow_workload_ring_buffer(workload);
2918         if (ret) {
2919                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2920                 return ret;
2921         }
2922
2923         ret = scan_workload(workload);
2924         if (ret) {
2925                 gvt_vgpu_err("scan workload error\n");
2926                 return ret;
2927         }
2928         return 0;
2929 }
2930
2931 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2932 {
2933         int ctx_size = wa_ctx->indirect_ctx.size;
2934         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2935         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2936                                         struct intel_vgpu_workload,
2937                                         wa_ctx);
2938         struct intel_vgpu *vgpu = workload->vgpu;
2939         struct drm_i915_gem_object *obj;
2940         int ret = 0;
2941         void *map;
2942
2943         obj = i915_gem_object_create_shmem(workload->vgpu->gvt->dev_priv,
2944                                            roundup(ctx_size + CACHELINE_BYTES,
2945                                                    PAGE_SIZE));
2946         if (IS_ERR(obj))
2947                 return PTR_ERR(obj);
2948
2949         /* get the va of the shadow batch buffer */
2950         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2951         if (IS_ERR(map)) {
2952                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2953                 ret = PTR_ERR(map);
2954                 goto put_obj;
2955         }
2956
2957         i915_gem_object_lock(obj);
2958         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2959         i915_gem_object_unlock(obj);
2960         if (ret) {
2961                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2962                 goto unmap_src;
2963         }
2964
2965         ret = copy_gma_to_hva(workload->vgpu,
2966                                 workload->vgpu->gtt.ggtt_mm,
2967                                 guest_gma, guest_gma + ctx_size,
2968                                 map);
2969         if (ret < 0) {
2970                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2971                 goto unmap_src;
2972         }
2973
2974         wa_ctx->indirect_ctx.obj = obj;
2975         wa_ctx->indirect_ctx.shadow_va = map;
2976         return 0;
2977
2978 unmap_src:
2979         i915_gem_object_unpin_map(obj);
2980 put_obj:
2981         i915_gem_object_put(obj);
2982         return ret;
2983 }
2984
2985 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2986 {
2987         u32 per_ctx_start[CACHELINE_DWORDS] = {0};
2988         unsigned char *bb_start_sva;
2989
2990         if (!wa_ctx->per_ctx.valid)
2991                 return 0;
2992
2993         per_ctx_start[0] = 0x18800001;
2994         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2995
2996         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2997                                 wa_ctx->indirect_ctx.size;
2998
2999         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3000
3001         return 0;
3002 }
3003
3004 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3005 {
3006         int ret;
3007         struct intel_vgpu_workload *workload = container_of(wa_ctx,
3008                                         struct intel_vgpu_workload,
3009                                         wa_ctx);
3010         struct intel_vgpu *vgpu = workload->vgpu;
3011
3012         if (wa_ctx->indirect_ctx.size == 0)
3013                 return 0;
3014
3015         ret = shadow_indirect_ctx(wa_ctx);
3016         if (ret) {
3017                 gvt_vgpu_err("fail to shadow indirect ctx\n");
3018                 return ret;
3019         }
3020
3021         combine_wa_ctx(wa_ctx);
3022
3023         ret = scan_wa_ctx(wa_ctx);
3024         if (ret) {
3025                 gvt_vgpu_err("scan wa ctx error\n");
3026                 return ret;
3027         }
3028
3029         return 0;
3030 }
3031
3032 static const struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
3033                 unsigned int opcode, unsigned long rings)
3034 {
3035         const struct cmd_info *info = NULL;
3036         unsigned int ring;
3037
3038         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
3039                 info = find_cmd_entry(gvt, opcode, ring);
3040                 if (info)
3041                         break;
3042         }
3043         return info;
3044 }
3045
3046 static int init_cmd_table(struct intel_gvt *gvt)
3047 {
3048         int i;
3049         struct cmd_entry *e;
3050         const struct cmd_info *info;
3051         unsigned int gen_type;
3052
3053         gen_type = intel_gvt_get_device_type(gvt);
3054
3055         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3056                 if (!(cmd_info[i].devices & gen_type))
3057                         continue;
3058
3059                 e = kzalloc(sizeof(*e), GFP_KERNEL);
3060                 if (!e)
3061                         return -ENOMEM;
3062
3063                 e->info = &cmd_info[i];
3064                 info = find_cmd_entry_any_ring(gvt,
3065                                 e->info->opcode, e->info->rings);
3066                 if (info) {
3067                         gvt_err("%s %s duplicated\n", e->info->name,
3068                                         info->name);
3069                         kfree(e);
3070                         return -EEXIST;
3071                 }
3072                 if (cmd_info[i].opcode == OP_MI_NOOP)
3073                         mi_noop_index = i;
3074
3075                 INIT_HLIST_NODE(&e->hlist);
3076                 add_cmd_entry(gvt, e);
3077                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3078                                 e->info->name, e->info->opcode, e->info->flag,
3079                                 e->info->devices, e->info->rings);
3080         }
3081         return 0;
3082 }
3083
3084 static void clean_cmd_table(struct intel_gvt *gvt)
3085 {
3086         struct hlist_node *tmp;
3087         struct cmd_entry *e;
3088         int i;
3089
3090         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3091                 kfree(e);
3092
3093         hash_init(gvt->cmd_table);
3094 }
3095
3096 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3097 {
3098         clean_cmd_table(gvt);
3099 }
3100
3101 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3102 {
3103         int ret;
3104
3105         ret = init_cmd_table(gvt);
3106         if (ret) {
3107                 intel_gvt_clean_cmd_parser(gvt);
3108                 return ret;
3109         }
3110         return 0;
3111 }