2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Kevin Tian <kevin.tian@intel.com>
28 * Pei Zhang <pei.zhang@intel.com>
29 * Min He <min.he@intel.com>
30 * Niu Bing <bing.niu@intel.com>
31 * Yulei Zhang <yulei.zhang@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
40 static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
42 struct intel_gvt *gvt = vgpu->gvt;
43 struct drm_i915_private *dev_priv = gvt->dev_priv;
46 struct drm_mm_node *node;
50 node = &vgpu->gm.high_gm_node;
51 size = vgpu_hidden_sz(vgpu);
52 start = ALIGN(gvt_hidden_gmadr_base(gvt), I915_GTT_PAGE_SIZE);
53 end = ALIGN(gvt_hidden_gmadr_end(gvt), I915_GTT_PAGE_SIZE);
56 node = &vgpu->gm.low_gm_node;
57 size = vgpu_aperture_sz(vgpu);
58 start = ALIGN(gvt_aperture_gmadr_base(gvt), I915_GTT_PAGE_SIZE);
59 end = ALIGN(gvt_aperture_gmadr_end(gvt), I915_GTT_PAGE_SIZE);
63 mutex_lock(&dev_priv->drm.struct_mutex);
64 ret = i915_gem_gtt_insert(&dev_priv->ggtt.base, node,
65 size, I915_GTT_PAGE_SIZE,
66 I915_COLOR_UNEVICTABLE,
68 mutex_unlock(&dev_priv->drm.struct_mutex);
70 gvt_err("fail to alloc %s gm space from host\n",
71 high_gm ? "high" : "low");
76 static int alloc_vgpu_gm(struct intel_vgpu *vgpu)
78 struct intel_gvt *gvt = vgpu->gvt;
79 struct drm_i915_private *dev_priv = gvt->dev_priv;
82 ret = alloc_gm(vgpu, false);
86 ret = alloc_gm(vgpu, true);
88 goto out_free_aperture;
90 gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,
91 vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu));
93 gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,
94 vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu));
98 mutex_lock(&dev_priv->drm.struct_mutex);
99 drm_mm_remove_node(&vgpu->gm.low_gm_node);
100 mutex_unlock(&dev_priv->drm.struct_mutex);
104 static void free_vgpu_gm(struct intel_vgpu *vgpu)
106 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
108 mutex_lock(&dev_priv->drm.struct_mutex);
109 drm_mm_remove_node(&vgpu->gm.low_gm_node);
110 drm_mm_remove_node(&vgpu->gm.high_gm_node);
111 mutex_unlock(&dev_priv->drm.struct_mutex);
115 * intel_vgpu_write_fence - write fence registers owned by a vGPU
116 * @vgpu: vGPU instance
117 * @fence: vGPU fence register number
118 * @value: Fence register value to be written
120 * This function is used to write fence registers owned by a vGPU. The vGPU
121 * fence register number will be translated into HW fence register number.
124 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
125 u32 fence, u64 value)
127 struct intel_gvt *gvt = vgpu->gvt;
128 struct drm_i915_private *dev_priv = gvt->dev_priv;
129 struct drm_i915_fence_reg *reg;
130 i915_reg_t fence_reg_lo, fence_reg_hi;
132 assert_rpm_wakelock_held(dev_priv);
134 if (WARN_ON(fence > vgpu_fence_sz(vgpu)))
137 reg = vgpu->fence.regs[fence];
141 fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
142 fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
144 I915_WRITE(fence_reg_lo, 0);
145 POSTING_READ(fence_reg_lo);
147 I915_WRITE(fence_reg_hi, upper_32_bits(value));
148 I915_WRITE(fence_reg_lo, lower_32_bits(value));
149 POSTING_READ(fence_reg_lo);
152 static void _clear_vgpu_fence(struct intel_vgpu *vgpu)
156 for (i = 0; i < vgpu_fence_sz(vgpu); i++)
157 intel_vgpu_write_fence(vgpu, i, 0);
160 static void free_vgpu_fence(struct intel_vgpu *vgpu)
162 struct intel_gvt *gvt = vgpu->gvt;
163 struct drm_i915_private *dev_priv = gvt->dev_priv;
164 struct drm_i915_fence_reg *reg;
167 if (WARN_ON(!vgpu_fence_sz(vgpu)))
170 intel_runtime_pm_get(dev_priv);
172 mutex_lock(&dev_priv->drm.struct_mutex);
173 _clear_vgpu_fence(vgpu);
174 for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
175 reg = vgpu->fence.regs[i];
176 list_add_tail(®->link,
177 &dev_priv->mm.fence_list);
179 mutex_unlock(&dev_priv->drm.struct_mutex);
181 intel_runtime_pm_put(dev_priv);
184 static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
186 struct intel_gvt *gvt = vgpu->gvt;
187 struct drm_i915_private *dev_priv = gvt->dev_priv;
188 struct drm_i915_fence_reg *reg;
190 struct list_head *pos, *q;
192 intel_runtime_pm_get(dev_priv);
194 /* Request fences from host */
195 mutex_lock(&dev_priv->drm.struct_mutex);
197 list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {
198 reg = list_entry(pos, struct drm_i915_fence_reg, link);
199 if (reg->pin_count || reg->vma)
202 vgpu->fence.regs[i] = reg;
203 if (++i == vgpu_fence_sz(vgpu))
206 if (i != vgpu_fence_sz(vgpu))
209 _clear_vgpu_fence(vgpu);
211 mutex_unlock(&dev_priv->drm.struct_mutex);
212 intel_runtime_pm_put(dev_priv);
215 /* Return fences to host, if fail */
216 for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
217 reg = vgpu->fence.regs[i];
220 list_add_tail(®->link,
221 &dev_priv->mm.fence_list);
223 mutex_unlock(&dev_priv->drm.struct_mutex);
224 intel_runtime_pm_put(dev_priv);
228 static void free_resource(struct intel_vgpu *vgpu)
230 struct intel_gvt *gvt = vgpu->gvt;
232 gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu);
233 gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu);
234 gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu);
237 static int alloc_resource(struct intel_vgpu *vgpu,
238 struct intel_vgpu_creation_params *param)
240 struct intel_gvt *gvt = vgpu->gvt;
241 unsigned long request, avail, max, taken;
244 if (!param->low_gm_sz || !param->high_gm_sz || !param->fence_sz) {
245 gvt_vgpu_err("Invalid vGPU creation params\n");
249 item = "low GM space";
250 max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
251 taken = gvt->gm.vgpu_allocated_low_gm_size;
253 request = MB_TO_BYTES(param->low_gm_sz);
256 goto no_enough_resource;
258 vgpu_aperture_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE);
260 item = "high GM space";
261 max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
262 taken = gvt->gm.vgpu_allocated_high_gm_size;
264 request = MB_TO_BYTES(param->high_gm_sz);
267 goto no_enough_resource;
269 vgpu_hidden_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE);
272 max = gvt_fence_sz(gvt) - HOST_FENCE;
273 taken = gvt->fence.vgpu_allocated_fence_num;
275 request = param->fence_sz;
278 goto no_enough_resource;
280 vgpu_fence_sz(vgpu) = request;
282 gvt->gm.vgpu_allocated_low_gm_size += MB_TO_BYTES(param->low_gm_sz);
283 gvt->gm.vgpu_allocated_high_gm_size += MB_TO_BYTES(param->high_gm_sz);
284 gvt->fence.vgpu_allocated_fence_num += param->fence_sz;
288 gvt_err("fail to allocate resource %s\n", item);
289 gvt_err("request %luMB avail %luMB max %luMB taken %luMB\n",
290 BYTES_TO_MB(request), BYTES_TO_MB(avail),
291 BYTES_TO_MB(max), BYTES_TO_MB(taken));
296 * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU
299 * This function is used to free the HW resource owned by a vGPU.
302 void intel_vgpu_free_resource(struct intel_vgpu *vgpu)
305 free_vgpu_fence(vgpu);
310 * intel_vgpu_reset_resource - reset resource state owned by a vGPU
313 * This function is used to reset resource state owned by a vGPU.
316 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu)
318 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
320 intel_runtime_pm_get(dev_priv);
321 _clear_vgpu_fence(vgpu);
322 intel_runtime_pm_put(dev_priv);
326 * intel_alloc_vgpu_resource - allocate HW resource for a vGPU
328 * @param: vGPU creation params
330 * This function is used to allocate HW resource for a vGPU. User specifies
331 * the resource configuration through the creation params.
334 * zero on success, negative error code if failed.
337 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
338 struct intel_vgpu_creation_params *param)
342 ret = alloc_resource(vgpu, param);
346 ret = alloc_vgpu_gm(vgpu);
348 goto out_free_resource;
350 ret = alloc_vgpu_fence(vgpu);
352 goto out_free_vgpu_gm;