drivers/gpu/drm/i915/gt/uc/intel_uc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2016-2019 Intel Corporation
   4  */
   5
   6 #include "gt/intel_gt.h"
   7 #include "gt/intel_reset.h"
   8 #include "intel_guc.h"
   9 #include "intel_guc_ads.h"
  10 #include "intel_guc_submission.h"
  11 #include "intel_uc.h"
  12
  13 #include "i915_drv.h"
  14
  15 static const struct intel_uc_ops uc_ops_off;
  16 static const struct intel_uc_ops uc_ops_on;
  17
  18 /* Reset GuC providing us with fresh state for both GuC and HuC.
  19  */
  20 static int __intel_uc_reset_hw(struct intel_uc *uc)
  21 {
  22         struct intel_gt *gt = uc_to_gt(uc);
  23         int ret;
  24         u32 guc_status;
  25
  26         ret = i915_inject_probe_error(gt->i915, -ENXIO);
  27         if (ret)
  28                 return ret;
  29
  30         ret = intel_reset_guc(gt);
  31         if (ret) {
  32                 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
  33                 return ret;
  34         }
  35
  36         guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
  37         WARN(!(guc_status & GS_MIA_IN_RESET),
  38              "GuC status: 0x%x, MIA core expected to be in reset\n",
  39              guc_status);
  40
  41         return ret;
  42 }
  43
  44 static void __confirm_options(struct intel_uc *uc)
  45 {
  46         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
  47
  48         DRM_DEV_DEBUG_DRIVER(i915->drm.dev,
  49                              "enable_guc=%d (guc:%s submission:%s huc:%s)\n",
  50                              i915_modparams.enable_guc,
  51                              yesno(intel_uc_uses_guc(uc)),
  52                              yesno(intel_uc_uses_guc_submission(uc)),
  53                              yesno(intel_uc_uses_huc(uc)));
  54
  55         if (i915_modparams.enable_guc == -1)
  56                 return;
  57
  58         if (i915_modparams.enable_guc == 0) {
  59                 GEM_BUG_ON(intel_uc_uses_guc(uc));
  60                 GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
  61                 GEM_BUG_ON(intel_uc_uses_huc(uc));
  62                 return;
  63         }
  64
  65         if (!intel_uc_supports_guc(uc))
  66                 dev_info(i915->drm.dev,
  67                          "Incompatible option enable_guc=%d - %s\n",
  68                          i915_modparams.enable_guc, "GuC is not supported!");
  69
  70         if (i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC &&
  71             !intel_uc_supports_huc(uc))
  72                 dev_info(i915->drm.dev,
  73                          "Incompatible option enable_guc=%d - %s\n",
  74                          i915_modparams.enable_guc, "HuC is not supported!");
  75
  76         if (i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION &&
  77             !intel_uc_supports_guc_submission(uc))
  78                 dev_info(i915->drm.dev,
  79                          "Incompatible option enable_guc=%d - %s\n",
  80                          i915_modparams.enable_guc, "GuC submission is N/A");
  81
  82         if (i915_modparams.enable_guc & ~(ENABLE_GUC_SUBMISSION |
  83                                           ENABLE_GUC_LOAD_HUC))
  84                 dev_info(i915->drm.dev,
  85                          "Incompatible option enable_guc=%d - %s\n",
  86                          i915_modparams.enable_guc, "undocumented flag");
  87 }
  88
  89 void intel_uc_init_early(struct intel_uc *uc)
  90 {
  91         intel_guc_init_early(&uc->guc);
  92         intel_huc_init_early(&uc->huc);
  93
  94         __confirm_options(uc);
  95
  96         if (intel_uc_uses_guc(uc))
  97                 uc->ops = &uc_ops_on;
  98         else
  99                 uc->ops = &uc_ops_off;
 100 }
 101
 102 void intel_uc_driver_late_release(struct intel_uc *uc)
 103 {
 104 }
 105
 106 /**
 107  * intel_uc_init_mmio - setup uC MMIO access
 108  * @uc: the intel_uc structure
 109  *
 110  * Setup minimal state necessary for MMIO accesses later in the
 111  * initialization sequence.
 112  */
 113 void intel_uc_init_mmio(struct intel_uc *uc)
 114 {
 115         intel_guc_init_send_regs(&uc->guc);
 116 }
 117
 118 static void __uc_capture_load_err_log(struct intel_uc *uc)
 119 {
 120         struct intel_guc *guc = &uc->guc;
 121
 122         if (guc->log.vma && !uc->load_err_log)
 123                 uc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
 124 }
 125
 126 static void __uc_free_load_err_log(struct intel_uc *uc)
 127 {
 128         struct drm_i915_gem_object *log = fetch_and_zero(&uc->load_err_log);
 129
 130         if (log)
 131                 i915_gem_object_put(log);
 132 }
 133
 134 static inline bool guc_communication_enabled(struct intel_guc *guc)
 135 {
 136         return intel_guc_ct_enabled(&guc->ct);
 137 }
 138
 139 /*
 140  * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
 141  * register using the same bits used in the CT message payload. Since our
 142  * communication channel with guc is turned off at this point, we can save the
 143  * message and handle it after we turn it back on.
 144  */
 145 static void guc_clear_mmio_msg(struct intel_guc *guc)
 146 {
 147         intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
 148 }
 149
 150 static void guc_get_mmio_msg(struct intel_guc *guc)
 151 {
 152         u32 val;
 153
 154         spin_lock_irq(&guc->irq_lock);
 155
 156         val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
 157         guc->mmio_msg |= val & guc->msg_enabled_mask;
 158
 159         /*
 160          * clear all events, including the ones we're not currently servicing,
 161          * to make sure we don't try to process a stale message if we enable
 162          * handling of more events later.
 163          */
 164         guc_clear_mmio_msg(guc);
 165
 166         spin_unlock_irq(&guc->irq_lock);
 167 }
 168
 169 static void guc_handle_mmio_msg(struct intel_guc *guc)
 170 {
 171         struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 172
 173         /* we need communication to be enabled to reply to GuC */
 174         GEM_BUG_ON(!guc_communication_enabled(guc));
 175
 176         if (!guc->mmio_msg)
 177                 return;
 178
 179         spin_lock_irq(&i915->irq_lock);
 180         intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
 181         spin_unlock_irq(&i915->irq_lock);
 182
 183         guc->mmio_msg = 0;
 184 }
 185
 186 static void guc_reset_interrupts(struct intel_guc *guc)
 187 {
 188         guc->interrupts.reset(guc);
 189 }
 190
 191 static void guc_enable_interrupts(struct intel_guc *guc)
 192 {
 193         guc->interrupts.enable(guc);
 194 }
 195
 196 static void guc_disable_interrupts(struct intel_guc *guc)
 197 {
 198         guc->interrupts.disable(guc);
 199 }
 200
 201 static int guc_enable_communication(struct intel_guc *guc)
 202 {
 203         struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 204         int ret;
 205
 206         GEM_BUG_ON(guc_communication_enabled(guc));
 207
 208         ret = i915_inject_probe_error(i915, -ENXIO);
 209         if (ret)
 210                 return ret;
 211
 212         ret = intel_guc_ct_enable(&guc->ct);
 213         if (ret)
 214                 return ret;
 215
 216         /* check for mmio messages received before/during the CT enable */
 217         guc_get_mmio_msg(guc);
 218         guc_handle_mmio_msg(guc);
 219
 220         guc_enable_interrupts(guc);
 221
 222         /* check for CT messages received before we enabled interrupts */
 223         spin_lock_irq(&i915->irq_lock);
 224         intel_guc_ct_event_handler(&guc->ct);
 225         spin_unlock_irq(&i915->irq_lock);
 226
 227         DRM_INFO("GuC communication enabled\n");
 228
 229         return 0;
 230 }
 231
 232 static void guc_disable_communication(struct intel_guc *guc)
 233 {
 234         /*
 235          * Events generated during or after CT disable are logged by guc in
 236          * via mmio. Make sure the register is clear before disabling CT since
 237          * all events we cared about have already been processed via CT.
 238          */
 239         guc_clear_mmio_msg(guc);
 240
 241         guc_disable_interrupts(guc);
 242
 243         intel_guc_ct_disable(&guc->ct);
 244
 245         /*
 246          * Check for messages received during/after the CT disable. We do not
 247          * expect any messages to have arrived via CT between the interrupt
 248          * disable and the CT disable because GuC should've been idle until we
 249          * triggered the CT disable protocol.
 250          */
 251         guc_get_mmio_msg(guc);
 252
 253         DRM_INFO("GuC communication disabled\n");
 254 }
 255
 256 void intel_uc_fetch_firmwares(struct intel_uc *uc)
 257 {
 258         int err;
 259
 260         if (!intel_uc_uses_guc(uc))
 261                 return;
 262
 263         err = intel_uc_fw_fetch(&uc->guc.fw);
 264         if (err)
 265                 return;
 266
 267         if (intel_uc_uses_huc(uc))
 268                 intel_uc_fw_fetch(&uc->huc.fw);
 269 }
 270
 271 void intel_uc_cleanup_firmwares(struct intel_uc *uc)
 272 {
 273         intel_uc_fw_cleanup_fetch(&uc->huc.fw);
 274         intel_uc_fw_cleanup_fetch(&uc->guc.fw);
 275 }
 276
 277 void intel_uc_init(struct intel_uc *uc)
 278 {
 279         struct intel_guc *guc = &uc->guc;
 280         struct intel_huc *huc = &uc->huc;
 281         int ret;
 282
 283         if (!intel_uc_uses_guc(uc))
 284                 return;
 285
 286         /* XXX: GuC submission is unavailable for now */
 287         GEM_BUG_ON(intel_uc_supports_guc_submission(uc));
 288
 289         ret = intel_guc_init(guc);
 290         if (ret) {
 291                 intel_uc_fw_cleanup_fetch(&huc->fw);
 292                 return;
 293         }
 294
 295         if (intel_uc_uses_huc(uc))
 296                 intel_huc_init(huc);
 297 }
 298
 299 void intel_uc_fini(struct intel_uc *uc)
 300 {
 301         intel_huc_fini(&uc->huc);
 302         intel_guc_fini(&uc->guc);
 303
 304         __uc_free_load_err_log(uc);
 305 }
 306
 307 static int __uc_sanitize(struct intel_uc *uc)
 308 {
 309         struct intel_guc *guc = &uc->guc;
 310         struct intel_huc *huc = &uc->huc;
 311
 312         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 313
 314         intel_huc_sanitize(huc);
 315         intel_guc_sanitize(guc);
 316
 317         return __intel_uc_reset_hw(uc);
 318 }
 319
 320 void intel_uc_sanitize(struct intel_uc *uc)
 321 {
 322         if (!intel_uc_supports_guc(uc))
 323                 return;
 324
 325         __uc_sanitize(uc);
 326 }
 327
 328 /* Initialize and verify the uC regs related to uC positioning in WOPCM */
 329 static int uc_init_wopcm(struct intel_uc *uc)
 330 {
 331         struct intel_gt *gt = uc_to_gt(uc);
 332         struct intel_uncore *uncore = gt->uncore;
 333         u32 base = intel_wopcm_guc_base(&gt->i915->wopcm);
 334         u32 size = intel_wopcm_guc_size(&gt->i915->wopcm);
 335         u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
 336         u32 mask;
 337         int err;
 338
 339         if (unlikely(!base || !size)) {
 340                 i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
 341                 return -E2BIG;
 342         }
 343
 344         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 345         GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
 346         GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
 347         GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
 348         GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
 349
 350         err = i915_inject_probe_error(gt->i915, -ENXIO);
 351         if (err)
 352                 return err;
 353
 354         mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
 355         err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
 356                                             size | GUC_WOPCM_SIZE_LOCKED);
 357         if (err)
 358                 goto err_out;
 359
 360         mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
 361         err = intel_uncore_write_and_verify(uncore, DMA_GUC_WOPCM_OFFSET,
 362                                             base | huc_agent, mask,
 363                                             base | huc_agent |
 364                                             GUC_WOPCM_OFFSET_VALID);
 365         if (err)
 366                 goto err_out;
 367
 368         return 0;
 369
 370 err_out:
 371         i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
 372         i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
 373                          i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
 374                          intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
 375         i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
 376                          i915_mmio_reg_offset(GUC_WOPCM_SIZE),
 377                          intel_uncore_read(uncore, GUC_WOPCM_SIZE));
 378
 379         return err;
 380 }
 381
 382 static bool uc_is_wopcm_locked(struct intel_uc *uc)
 383 {
 384         struct intel_gt *gt = uc_to_gt(uc);
 385         struct intel_uncore *uncore = gt->uncore;
 386
 387         return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) ||
 388                (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID);
 389 }
 390
 391 static int __uc_check_hw(struct intel_uc *uc)
 392 {
 393         if (!intel_uc_supports_guc(uc))
 394                 return 0;
 395
 396         /*
 397          * We can silently continue without GuC only if it was never enabled
 398          * before on this system after reboot, otherwise we risk GPU hangs.
 399          * To check if GuC was loaded before we look at WOPCM registers.
 400          */
 401         if (uc_is_wopcm_locked(uc))
 402                 return -EIO;
 403
 404         return 0;
 405 }
 406
 407 static int __uc_init_hw(struct intel_uc *uc)
 408 {
 409         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
 410         struct intel_guc *guc = &uc->guc;
 411         struct intel_huc *huc = &uc->huc;
 412         int ret, attempts;
 413
 414         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 415         GEM_BUG_ON(!intel_uc_uses_guc(uc));
 416
 417         if (!intel_uc_fw_is_available(&guc->fw)) {
 418                 ret = __uc_check_hw(uc) ||
 419                       intel_uc_fw_is_overridden(&guc->fw) ||
 420                       intel_uc_supports_guc_submission(uc) ?
 421                       intel_uc_fw_status_to_error(guc->fw.status) : 0;
 422                 goto err_out;
 423         }
 424
 425         ret = uc_init_wopcm(uc);
 426         if (ret)
 427                 goto err_out;
 428
 429         guc_reset_interrupts(guc);
 430
 431         /* WaEnableuKernelHeaderValidFix:skl */
 432         /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
 433         if (IS_GEN(i915, 9))
 434                 attempts = 3;
 435         else
 436                 attempts = 1;
 437
 438         while (attempts--) {
 439                 /*
 440                  * Always reset the GuC just before (re)loading, so
 441                  * that the state and timing are fairly predictable
 442                  */
 443                 ret = __uc_sanitize(uc);
 444                 if (ret)
 445                         goto err_out;
 446
 447                 intel_huc_fw_upload(huc);
 448                 intel_guc_ads_reset(guc);
 449                 intel_guc_write_params(guc);
 450                 ret = intel_guc_fw_upload(guc);
 451                 if (ret == 0)
 452                         break;
 453
 454                 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
 455                                  "retry %d more time(s)\n", ret, attempts);
 456         }
 457
 458         /* Did we succeded or run out of retries? */
 459         if (ret)
 460                 goto err_log_capture;
 461
 462         ret = guc_enable_communication(guc);
 463         if (ret)
 464                 goto err_log_capture;
 465
 466         intel_huc_auth(huc);
 467
 468         ret = intel_guc_sample_forcewake(guc);
 469         if (ret)
 470                 goto err_communication;
 471
 472         if (intel_uc_supports_guc_submission(uc))
 473                 intel_guc_submission_enable(guc);
 474
 475         dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n",
 476                  intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path,
 477                  guc->fw.major_ver_found, guc->fw.minor_ver_found,
 478                  "submission",
 479                  enableddisabled(intel_uc_supports_guc_submission(uc)));
 480
 481         if (intel_uc_uses_huc(uc)) {
 482                 dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n",
 483                          intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
 484                          huc->fw.path,
 485                          huc->fw.major_ver_found, huc->fw.minor_ver_found,
 486                          "authenticated",
 487                          yesno(intel_huc_is_authenticated(huc)));
 488         }
 489
 490         return 0;
 491
 492         /*
 493          * We've failed to load the firmware :(
 494          */
 495 err_communication:
 496         guc_disable_communication(guc);
 497 err_log_capture:
 498         __uc_capture_load_err_log(uc);
 499 err_out:
 500         __uc_sanitize(uc);
 501
 502         if (!ret) {
 503                 dev_notice(i915->drm.dev, "GuC is uninitialized\n");
 504                 /* We want to run without GuC submission */
 505                 return 0;
 506         }
 507
 508         i915_probe_error(i915, "GuC initialization failed %d\n", ret);
 509
 510         /* We want to keep KMS alive */
 511         return -EIO;
 512 }
 513
 514 static void __uc_fini_hw(struct intel_uc *uc)
 515 {
 516         struct intel_guc *guc = &uc->guc;
 517
 518         if (!intel_guc_is_running(guc))
 519                 return;
 520
 521         if (intel_uc_supports_guc_submission(uc))
 522                 intel_guc_submission_disable(guc);
 523
 524         if (guc_communication_enabled(guc))
 525                 guc_disable_communication(guc);
 526
 527         __uc_sanitize(uc);
 528 }
 529
 530 /**
 531  * intel_uc_reset_prepare - Prepare for reset
 532  * @uc: the intel_uc structure
 533  *
 534  * Preparing for full gpu reset.
 535  */
 536 void intel_uc_reset_prepare(struct intel_uc *uc)
 537 {
 538         struct intel_guc *guc = &uc->guc;
 539
 540         if (!intel_guc_is_running(guc))
 541                 return;
 542
 543         guc_disable_communication(guc);
 544         __uc_sanitize(uc);
 545 }
 546
 547 void intel_uc_runtime_suspend(struct intel_uc *uc)
 548 {
 549         struct intel_guc *guc = &uc->guc;
 550         int err;
 551
 552         if (!intel_guc_is_running(guc))
 553                 return;
 554
 555         err = intel_guc_suspend(guc);
 556         if (err)
 557                 DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
 558
 559         guc_disable_communication(guc);
 560 }
 561
 562 void intel_uc_suspend(struct intel_uc *uc)
 563 {
 564         struct intel_guc *guc = &uc->guc;
 565         intel_wakeref_t wakeref;
 566
 567         if (!intel_guc_is_running(guc))
 568                 return;
 569
 570         with_intel_runtime_pm(uc_to_gt(uc)->uncore->rpm, wakeref)
 571                 intel_uc_runtime_suspend(uc);
 572 }
 573
 574 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
 575 {
 576         struct intel_guc *guc = &uc->guc;
 577         int err;
 578
 579         if (!intel_guc_is_running(guc))
 580                 return 0;
 581
 582         /* Make sure we enable communication if and only if it's disabled */
 583         GEM_BUG_ON(enable_communication == guc_communication_enabled(guc));
 584
 585         if (enable_communication)
 586                 guc_enable_communication(guc);
 587
 588         err = intel_guc_resume(guc);
 589         if (err) {
 590                 DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
 591                 return err;
 592         }
 593
 594         return 0;
 595 }
 596
 597 int intel_uc_resume(struct intel_uc *uc)
 598 {
 599         /*
 600          * When coming out of S3/S4 we sanitize and re-init the HW, so
 601          * communication is already re-enabled at this point.
 602          */
 603         return __uc_resume(uc, false);
 604 }
 605
 606 int intel_uc_runtime_resume(struct intel_uc *uc)
 607 {
 608         /*
 609          * During runtime resume we don't sanitize, so we need to re-init
 610          * communication as well.
 611          */
 612         return __uc_resume(uc, true);
 613 }
 614
 615 static const struct intel_uc_ops uc_ops_off = {
 616         .init_hw = __uc_check_hw,
 617 };
 618
 619 static const struct intel_uc_ops uc_ops_on = {
 620         .init_hw = __uc_init_hw,
 621         .fini_hw = __uc_fini_hw,
 622 };