drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2016-2019 Intel Corporation
   4  */
   5
   6 #ifndef _INTEL_GUC_CT_H_
   7 #define _INTEL_GUC_CT_H_
   8
   9 #include <linux/spinlock.h>
  10 #include <linux/workqueue.h>
  11
  12 #include "intel_guc_fwif.h"
  13
  14 struct i915_vma;
  15 struct intel_guc;
  16
  17 /**
  18  * DOC: Command Transport (CT).
  19  *
  20  * Buffer based command transport is a replacement for MMIO based mechanism.
  21  * It can be used to perform both host-2-guc and guc-to-host communication.
  22  */
  23
  24 /** Represents single command transport buffer.
  25  *
  26  * A single command transport buffer consists of two parts, the header
  27  * record (command transport buffer descriptor) and the actual buffer which
  28  * holds the commands.
  29  *
  30  * @desc: pointer to the buffer descriptor
  31  * @cmds: pointer to the commands buffer
  32  */
  33 struct intel_guc_ct_buffer {
  34         struct guc_ct_buffer_desc *desc;
  35         u32 *cmds;
  36 };
  37
  38
  39 /** Top-level structure for Command Transport related data
  40  *
  41  * Includes a pair of CT buffers for bi-directional communication and tracking
  42  * for the H2G and G2H requests sent and received through the buffers.
  43  */
  44 struct intel_guc_ct {
  45         struct i915_vma *vma;
  46         bool enabled;
  47
  48         /* buffers for sending(0) and receiving(1) commands */
  49         struct intel_guc_ct_buffer ctbs[2];
  50
  51         struct {
  52                 u32 last_fence; /* last fence used to send request */
  53
  54                 spinlock_t lock; /* protects pending requests list */
  55                 struct list_head pending; /* requests waiting for response */
  56
  57                 struct list_head incoming; /* incoming requests */
  58                 struct work_struct worker; /* handler for incoming requests */
  59         } requests;
  60 };
  61
  62 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
  63 int intel_guc_ct_init(struct intel_guc_ct *ct);
  64 void intel_guc_ct_fini(struct intel_guc_ct *ct);
  65 int intel_guc_ct_enable(struct intel_guc_ct *ct);
  66 void intel_guc_ct_disable(struct intel_guc_ct *ct);
  67
  68 static inline void intel_guc_ct_sanitize(struct intel_guc_ct *ct)
  69 {
  70         ct->enabled = false;
  71 }
  72
  73 static inline bool intel_guc_ct_enabled(struct intel_guc_ct *ct)
  74 {
  75         return ct->enabled;
  76 }
  77
  78 int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
  79                       u32 *response_buf, u32 response_buf_size);
  80 void intel_guc_ct_event_handler(struct intel_guc_ct *ct);
  81
  82 #endif /* _INTEL_GUC_CT_H_ */