drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2014-2021 Intel Corporation
   4  */
   5
   6 #ifndef _ABI_GUC_ACTIONS_ABI_H
   7 #define _ABI_GUC_ACTIONS_ABI_H
   8
   9 /**
  10  * DOC: HOST2GUC_SELF_CFG
  11  *
  12  * This message is used by Host KMD to setup of the `GuC Self Config KLVs`_.
  13  *
  14  * This message must be sent as `MMIO HXG Message`_.
  15  *
  16  *  +---+-------+--------------------------------------------------------------+
  17  *  |   | Bits  | Description                                                  |
  18  *  +===+=======+==============================================================+
  19  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |
  20  *  |   +-------+--------------------------------------------------------------+
  21  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |
  22  *  |   +-------+--------------------------------------------------------------+
  23  *  |   | 27:16 | DATA0 = MBZ                                                  |
  24  *  |   +-------+--------------------------------------------------------------+
  25  *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508            |
  26  *  +---+-------+--------------------------------------------------------------+
  27  *  | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_           |
  28  *  |   +-------+--------------------------------------------------------------+
  29  *  |   |  15:0 | **KLV_LEN** - KLV length                                     |
  30  *  |   |       |                                                              |
  31  *  |   |       |   - 32 bit KLV = 1                                           |
  32  *  |   |       |   - 64 bit KLV = 2                                           |
  33  *  +---+-------+--------------------------------------------------------------+
  34  *  | 2 |  31:0 | **VALUE32** - Bits 31-0 of the KLV value                     |
  35  *  +---+-------+--------------------------------------------------------------+
  36  *  | 3 |  31:0 | **VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2)  |
  37  *  +---+-------+--------------------------------------------------------------+
  38  *
  39  *  +---+-------+--------------------------------------------------------------+
  40  *  |   | Bits  | Description                                                  |
  41  *  +===+=======+==============================================================+
  42  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |
  43  *  |   +-------+--------------------------------------------------------------+
  44  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |
  45  *  |   +-------+--------------------------------------------------------------+
  46  *  |   |  27:0 | DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognized   |
  47  *  +---+-------+--------------------------------------------------------------+
  48  */
  49 #define GUC_ACTION_HOST2GUC_SELF_CFG                    0x0508
  50
  51 #define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN               (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
  52 #define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ             GUC_HXG_REQUEST_MSG_0_DATA0
  53 #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY         (0xffffU << 16)
  54 #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN         (0xffff << 0)
  55 #define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32         GUC_HXG_REQUEST_MSG_n_DATAn
  56 #define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64         GUC_HXG_REQUEST_MSG_n_DATAn
  57
  58 #define HOST2GUC_SELF_CFG_RESPONSE_MSG_LEN              GUC_HXG_RESPONSE_MSG_MIN_LEN
  59 #define HOST2GUC_SELF_CFG_RESPONSE_MSG_0_NUM            GUC_HXG_RESPONSE_MSG_0_DATA0
  60
  61 /**
  62  * DOC: HOST2GUC_CONTROL_CTB
  63  *
  64  * This H2G action allows Vf Host to enable or disable H2G and G2H `CT Buffer`_.
  65  *
  66  * This message must be sent as `MMIO HXG Message`_.
  67  *
  68  *  +---+-------+--------------------------------------------------------------+
  69  *  |   | Bits  | Description                                                  |
  70  *  +===+=======+==============================================================+
  71  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |
  72  *  |   +-------+--------------------------------------------------------------+
  73  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |
  74  *  |   +-------+--------------------------------------------------------------+
  75  *  |   | 27:16 | DATA0 = MBZ                                                  |
  76  *  |   +-------+--------------------------------------------------------------+
  77  *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509         |
  78  *  +---+-------+--------------------------------------------------------------+
  79  *  | 1 |  31:0 | **CONTROL** - control `CTB based communication`_             |
  80  *  |   |       |                                                              |
  81  *  |   |       |   - _`GUC_CTB_CONTROL_DISABLE` = 0                           |
  82  *  |   |       |   - _`GUC_CTB_CONTROL_ENABLE` = 1                            |
  83  *  +---+-------+--------------------------------------------------------------+
  84  *
  85  *  +---+-------+--------------------------------------------------------------+
  86  *  |   | Bits  | Description                                                  |
  87  *  +===+=======+==============================================================+
  88  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |
  89  *  |   +-------+--------------------------------------------------------------+
  90  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |
  91  *  |   +-------+--------------------------------------------------------------+
  92  *  |   |  27:0 | DATA0 = MBZ                                                  |
  93  *  +---+-------+--------------------------------------------------------------+
  94  */
  95 #define GUC_ACTION_HOST2GUC_CONTROL_CTB                 0x4509
  96
  97 #define HOST2GUC_CONTROL_CTB_REQUEST_MSG_LEN            (GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)
  98 #define HOST2GUC_CONTROL_CTB_REQUEST_MSG_0_MBZ          GUC_HXG_REQUEST_MSG_0_DATA0
  99 #define HOST2GUC_CONTROL_CTB_REQUEST_MSG_1_CONTROL      GUC_HXG_REQUEST_MSG_n_DATAn
 100 #define   GUC_CTB_CONTROL_DISABLE                       0u
 101 #define   GUC_CTB_CONTROL_ENABLE                        1u
 102
 103 #define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_LEN           GUC_HXG_RESPONSE_MSG_MIN_LEN
 104 #define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_0_MBZ         GUC_HXG_RESPONSE_MSG_0_DATA0
 105
 106 /* legacy definitions */
 107
 108 enum intel_guc_action {
 109         INTEL_GUC_ACTION_DEFAULT = 0x0,
 110         INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
 111         INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
 112         INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
 113         INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
 114         INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
 115         INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,
 116         INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
 117         INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
 118         INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
 119         INTEL_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE = 0x506,
 120         INTEL_GUC_ACTION_SCHED_CONTEXT = 0x1000,
 121         INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET = 0x1001,
 122         INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002,
 123         INTEL_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003,
 124         INTEL_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004,
 125         INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
 126         INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
 127         INTEL_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 0x100B,
 128         INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
 129         INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
 130         INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100,
 131         INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
 132         INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
 133         INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
 134         INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
 135         INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
 136         INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
 137         INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
 138         INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
 139         INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
 140         INTEL_GUC_ACTION_NOTIFY_EXCEPTION = 0x8005,
 141         INTEL_GUC_ACTION_LIMIT
 142 };
 143
 144 enum intel_guc_rc_options {
 145         INTEL_GUCRC_HOST_CONTROL,
 146         INTEL_GUCRC_FIRMWARE_CONTROL,
 147 };
 148
 149 enum intel_guc_preempt_options {
 150         INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
 151         INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
 152 };
 153
 154 enum intel_guc_report_status {
 155         INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
 156         INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
 157         INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
 158         INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
 159 };
 160
 161 enum intel_guc_sleep_state_status {
 162         INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
 163         INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
 164         INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
 165 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
 166 };
 167
 168 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
 169 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
 170 #define GUC_LOG_CONTROL_VERBOSITY_MASK  (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
 171 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)
 172
 173 enum intel_guc_state_capture_event_status {
 174         INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0,
 175         INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1,
 176 };
 177
 178 #define INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK      0x000000FF
 179
 180 #endif /* _ABI_GUC_ACTIONS_ABI_H */