2 * SPDX-License-Identifier: MIT
4 * Copyright © 2018 Intel Corporation
7 #include "gem/i915_gem_pm.h"
8 #include "i915_selftest.h"
9 #include "intel_reset.h"
11 #include "selftests/igt_flush_test.h"
12 #include "selftests/igt_reset.h"
13 #include "selftests/igt_spinner.h"
14 #include "selftests/igt_wedge_me.h"
15 #include "selftests/mock_drm.h"
17 #include "gem/selftests/igt_gem_utils.h"
18 #include "gem/selftests/mock_context.h"
20 static const struct wo_register {
21 enum intel_platform platform;
24 { INTEL_GEMINILAKE, 0x731c }
27 #define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 8)
29 struct i915_wa_list gt_wa_list;
31 char name[REF_NAME_MAX];
32 struct i915_wa_list wa_list;
33 struct i915_wa_list ctx_wa_list;
34 } engine[I915_NUM_ENGINES];
38 reference_lists_init(struct drm_i915_private *i915, struct wa_lists *lists)
40 struct intel_engine_cs *engine;
41 enum intel_engine_id id;
43 memset(lists, 0, sizeof(*lists));
45 wa_init_start(&lists->gt_wa_list, "GT_REF");
46 gt_init_workarounds(i915, &lists->gt_wa_list);
47 wa_init_finish(&lists->gt_wa_list);
49 for_each_engine(engine, i915, id) {
50 struct i915_wa_list *wal = &lists->engine[id].wa_list;
51 char *name = lists->engine[id].name;
53 snprintf(name, REF_NAME_MAX, "%s_REF", engine->name);
55 wa_init_start(wal, name);
56 engine_init_workarounds(engine, wal);
59 snprintf(name, REF_NAME_MAX, "%s_CTX_REF", engine->name);
61 __intel_engine_init_ctx_wa(engine,
62 &lists->engine[id].ctx_wa_list,
68 reference_lists_fini(struct drm_i915_private *i915, struct wa_lists *lists)
70 struct intel_engine_cs *engine;
71 enum intel_engine_id id;
73 for_each_engine(engine, i915, id)
74 intel_wa_list_free(&lists->engine[id].wa_list);
76 intel_wa_list_free(&lists->gt_wa_list);
79 static struct drm_i915_gem_object *
80 read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
82 const u32 base = engine->mmio_base;
83 struct drm_i915_gem_object *result;
84 struct i915_request *rq;
90 result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
94 i915_gem_object_set_cache_coherency(result, I915_CACHE_LLC);
96 cs = i915_gem_object_pin_map(result, I915_MAP_WB);
101 memset(cs, 0xc5, PAGE_SIZE);
102 i915_gem_object_flush_map(result);
103 i915_gem_object_unpin_map(result);
105 vma = i915_vma_instance(result, &engine->i915->ggtt.vm, NULL);
111 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
115 rq = igt_request_alloc(ctx, engine);
122 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
123 i915_vma_unlock(vma);
127 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
128 if (INTEL_GEN(ctx->i915) >= 8)
131 cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
137 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
139 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
140 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
143 intel_ring_advance(rq, cs);
145 i915_request_add(rq);
151 i915_request_add(rq);
155 i915_gem_object_put(result);
160 get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)
162 i915_reg_t reg = i < engine->whitelist.count ?
163 engine->whitelist.list[i].reg :
164 RING_NOPID(engine->mmio_base);
166 return i915_mmio_reg_offset(reg);
170 print_results(const struct intel_engine_cs *engine, const u32 *results)
174 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
175 u32 expected = get_whitelist_reg(engine, i);
176 u32 actual = results[i];
178 pr_info("RING_NONPRIV[%d]: expected 0x%08x, found 0x%08x\n",
179 i, expected, actual);
183 static int check_whitelist(struct i915_gem_context *ctx,
184 struct intel_engine_cs *engine)
186 struct drm_i915_gem_object *results;
187 struct igt_wedge_me wedge;
192 results = read_nonprivs(ctx, engine);
194 return PTR_ERR(results);
197 i915_gem_object_lock(results);
198 igt_wedge_on_timeout(&wedge, ctx->i915, HZ / 5) /* a safety net! */
199 err = i915_gem_object_set_to_cpu_domain(results, false);
200 i915_gem_object_unlock(results);
201 if (i915_terminally_wedged(ctx->i915))
206 vaddr = i915_gem_object_pin_map(results, I915_MAP_WB);
208 err = PTR_ERR(vaddr);
212 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
213 u32 expected = get_whitelist_reg(engine, i);
214 u32 actual = vaddr[i];
216 if (expected != actual) {
217 print_results(engine, vaddr);
218 pr_err("Invalid RING_NONPRIV[%d], expected 0x%08x, found 0x%08x\n",
219 i, expected, actual);
226 i915_gem_object_unpin_map(results);
228 i915_gem_object_put(results);
232 static int do_device_reset(struct intel_engine_cs *engine)
234 i915_reset(engine->i915, engine->mask, "live_workarounds");
238 static int do_engine_reset(struct intel_engine_cs *engine)
240 return i915_reset_engine(engine, "live_workarounds");
244 switch_to_scratch_context(struct intel_engine_cs *engine,
245 struct igt_spinner *spin)
247 struct i915_gem_context *ctx;
248 struct i915_request *rq;
249 intel_wakeref_t wakeref;
252 ctx = kernel_context(engine->i915);
256 GEM_BUG_ON(i915_gem_context_is_bannable(ctx));
258 rq = ERR_PTR(-ENODEV);
259 with_intel_runtime_pm(&engine->i915->runtime_pm, wakeref)
260 rq = igt_spinner_create_request(spin, ctx, engine, MI_NOOP);
262 kernel_context_close(ctx);
270 i915_request_add(rq);
272 if (spin && !igt_wait_for_spinner(spin, rq)) {
273 pr_err("Spinner failed to start\n");
279 igt_spinner_end(spin);
284 static int check_whitelist_across_reset(struct intel_engine_cs *engine,
285 int (*reset)(struct intel_engine_cs *),
288 struct drm_i915_private *i915 = engine->i915;
289 struct i915_gem_context *ctx;
290 struct igt_spinner spin;
291 intel_wakeref_t wakeref;
294 pr_info("Checking %d whitelisted registers (RING_NONPRIV) [%s]\n",
295 engine->whitelist.count, name);
297 err = igt_spinner_init(&spin, i915);
301 ctx = kernel_context(i915);
305 err = check_whitelist(ctx, engine);
307 pr_err("Invalid whitelist *before* %s reset!\n", name);
311 err = switch_to_scratch_context(engine, &spin);
315 with_intel_runtime_pm(&i915->runtime_pm, wakeref)
318 igt_spinner_end(&spin);
319 igt_spinner_fini(&spin);
322 pr_err("%s reset failed\n", name);
326 err = check_whitelist(ctx, engine);
328 pr_err("Whitelist not preserved in context across %s reset!\n",
333 kernel_context_close(ctx);
335 ctx = kernel_context(i915);
339 err = check_whitelist(ctx, engine);
341 pr_err("Invalid whitelist *after* %s reset in fresh context!\n",
347 kernel_context_close(ctx);
351 static struct i915_vma *create_batch(struct i915_gem_context *ctx)
353 struct drm_i915_gem_object *obj;
354 struct i915_vma *vma;
357 obj = i915_gem_object_create_internal(ctx->i915, 16 * PAGE_SIZE);
359 return ERR_CAST(obj);
361 vma = i915_vma_instance(obj, ctx->vm, NULL);
367 err = i915_vma_pin(vma, 0, 0, PIN_USER);
374 i915_gem_object_put(obj);
378 static u32 reg_write(u32 old, u32 new, u32 rsvd)
380 if (rsvd == 0x0000ffff) {
382 old |= new & (new >> 16);
391 static bool wo_register(struct intel_engine_cs *engine, u32 reg)
393 enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
396 for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
397 if (wo_registers[i].platform == platform &&
398 wo_registers[i].reg == reg)
405 static bool ro_register(u32 reg)
407 if (reg & RING_FORCE_TO_NONPRIV_RD)
413 static int whitelist_writable_count(struct intel_engine_cs *engine)
415 int count = engine->whitelist.count;
418 for (i = 0; i < engine->whitelist.count; i++) {
419 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
421 if (ro_register(reg))
428 static int check_dirty_whitelist(struct i915_gem_context *ctx,
429 struct intel_engine_cs *engine)
431 const u32 values[] = {
457 struct i915_vma *scratch;
458 struct i915_vma *batch;
462 scratch = create_scratch(ctx->vm, 2 * ARRAY_SIZE(values) + 1);
464 return PTR_ERR(scratch);
466 batch = create_batch(ctx);
468 err = PTR_ERR(batch);
472 for (i = 0; i < engine->whitelist.count; i++) {
473 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
474 u64 addr = scratch->node.start;
475 struct i915_request *rq;
480 if (wo_register(engine, reg))
483 if (ro_register(reg))
486 srm = MI_STORE_REGISTER_MEM;
487 lrm = MI_LOAD_REGISTER_MEM;
488 if (INTEL_GEN(ctx->i915) >= 8)
491 pr_debug("%s: Writing garbage to %x\n",
494 cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
503 *cs++ = lower_32_bits(addr);
504 *cs++ = upper_32_bits(addr);
507 for (v = 0; v < ARRAY_SIZE(values); v++) {
509 *cs++ = MI_LOAD_REGISTER_IMM(1);
516 *cs++ = lower_32_bits(addr + sizeof(u32) * idx);
517 *cs++ = upper_32_bits(addr + sizeof(u32) * idx);
520 for (v = 0; v < ARRAY_SIZE(values); v++) {
522 *cs++ = MI_LOAD_REGISTER_IMM(1);
529 *cs++ = lower_32_bits(addr + sizeof(u32) * idx);
530 *cs++ = upper_32_bits(addr + sizeof(u32) * idx);
533 GEM_BUG_ON(idx * sizeof(u32) > scratch->size);
535 /* LRM original -- don't leave garbage in the context! */
538 *cs++ = lower_32_bits(addr);
539 *cs++ = upper_32_bits(addr);
541 *cs++ = MI_BATCH_BUFFER_END;
543 i915_gem_object_flush_map(batch->obj);
544 i915_gem_object_unpin_map(batch->obj);
545 i915_gem_chipset_flush(ctx->i915);
547 rq = igt_request_alloc(ctx, engine);
553 if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
554 err = engine->emit_init_breadcrumb(rq);
559 err = engine->emit_bb_start(rq,
560 batch->node.start, PAGE_SIZE,
566 i915_request_add(rq);
570 if (i915_request_wait(rq, 0, HZ / 5) < 0) {
571 pr_err("%s: Futzing %x timedout; cancelling test\n",
573 i915_gem_set_wedged(ctx->i915);
578 results = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
579 if (IS_ERR(results)) {
580 err = PTR_ERR(results);
584 GEM_BUG_ON(values[ARRAY_SIZE(values) - 1] != 0xffffffff);
585 rsvd = results[ARRAY_SIZE(values)]; /* detect write masking */
587 pr_err("%s: Unable to write to whitelisted register %x\n",
595 for (v = 0; v < ARRAY_SIZE(values); v++) {
596 expect = reg_write(expect, values[v], rsvd);
597 if (results[idx] != expect)
601 for (v = 0; v < ARRAY_SIZE(values); v++) {
602 expect = reg_write(expect, ~values[v], rsvd);
603 if (results[idx] != expect)
608 pr_err("%s: %d mismatch between values written to whitelisted register [%x], and values read back!\n",
609 engine->name, err, reg);
611 pr_info("%s: Whitelisted register: %x, original value %08x, rsvd %08x\n",
612 engine->name, reg, results[0], rsvd);
616 for (v = 0; v < ARRAY_SIZE(values); v++) {
619 expect = reg_write(expect, w, rsvd);
620 pr_info("Wrote %08x, read %08x, expect %08x\n",
621 w, results[idx], expect);
624 for (v = 0; v < ARRAY_SIZE(values); v++) {
627 expect = reg_write(expect, w, rsvd);
628 pr_info("Wrote %08x, read %08x, expect %08x\n",
629 w, results[idx], expect);
636 i915_gem_object_unpin_map(scratch->obj);
641 if (igt_flush_test(ctx->i915, I915_WAIT_LOCKED))
644 i915_vma_unpin_and_release(&batch, 0);
646 i915_vma_unpin_and_release(&scratch, 0);
650 static int live_dirty_whitelist(void *arg)
652 struct drm_i915_private *i915 = arg;
653 struct intel_engine_cs *engine;
654 struct i915_gem_context *ctx;
655 enum intel_engine_id id;
656 intel_wakeref_t wakeref;
657 struct drm_file *file;
660 /* Can the user write to the whitelisted registers? */
662 if (INTEL_GEN(i915) < 7) /* minimum requirement for LRI, SRM, LRM */
665 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
667 mutex_unlock(&i915->drm.struct_mutex);
668 file = mock_file(i915);
669 mutex_lock(&i915->drm.struct_mutex);
675 ctx = live_context(i915, file);
681 for_each_engine(engine, i915, id) {
682 if (engine->whitelist.count == 0)
685 err = check_dirty_whitelist(ctx, engine);
691 mutex_unlock(&i915->drm.struct_mutex);
692 mock_file_free(i915, file);
693 mutex_lock(&i915->drm.struct_mutex);
695 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
699 static int live_reset_whitelist(void *arg)
701 struct drm_i915_private *i915 = arg;
702 struct intel_engine_cs *engine = i915->engine[RCS0];
705 /* If we reset the gpu, we should not lose the RING_NONPRIV */
707 if (!engine || engine->whitelist.count == 0)
710 igt_global_reset_lock(i915);
712 if (intel_has_reset_engine(i915)) {
713 err = check_whitelist_across_reset(engine,
720 if (intel_has_gpu_reset(i915)) {
721 err = check_whitelist_across_reset(engine,
729 igt_global_reset_unlock(i915);
733 static int read_whitelisted_registers(struct i915_gem_context *ctx,
734 struct intel_engine_cs *engine,
735 struct i915_vma *results)
737 struct i915_request *rq;
741 rq = igt_request_alloc(ctx, engine);
745 srm = MI_STORE_REGISTER_MEM;
746 if (INTEL_GEN(ctx->i915) >= 8)
749 cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
755 for (i = 0; i < engine->whitelist.count; i++) {
756 u64 offset = results->node.start + sizeof(u32) * i;
757 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
759 /* Clear RD only and WR only flags */
760 reg &= ~(RING_FORCE_TO_NONPRIV_RD | RING_FORCE_TO_NONPRIV_WR);
764 *cs++ = lower_32_bits(offset);
765 *cs++ = upper_32_bits(offset);
767 intel_ring_advance(rq, cs);
770 i915_request_add(rq);
772 if (i915_request_wait(rq, 0, HZ / 5) < 0)
778 static int scrub_whitelisted_registers(struct i915_gem_context *ctx,
779 struct intel_engine_cs *engine)
781 struct i915_request *rq;
782 struct i915_vma *batch;
786 batch = create_batch(ctx);
788 return PTR_ERR(batch);
790 cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
796 *cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine));
797 for (i = 0; i < engine->whitelist.count; i++) {
798 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
800 if (ro_register(reg))
806 *cs++ = MI_BATCH_BUFFER_END;
808 i915_gem_object_flush_map(batch->obj);
809 i915_gem_chipset_flush(ctx->i915);
811 rq = igt_request_alloc(ctx, engine);
817 if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
818 err = engine->emit_init_breadcrumb(rq);
823 /* Perform the writes from an unprivileged "user" batch */
824 err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
827 i915_request_add(rq);
828 if (i915_request_wait(rq, 0, HZ / 5) < 0)
832 i915_gem_object_unpin_map(batch->obj);
834 i915_vma_unpin_and_release(&batch, 0);
840 unsigned long gen_mask;
843 static bool find_reg(struct drm_i915_private *i915,
845 const struct regmask *tbl,
848 u32 offset = i915_mmio_reg_offset(reg);
851 if (INTEL_INFO(i915)->gen_mask & tbl->gen_mask &&
852 i915_mmio_reg_offset(tbl->reg) == offset)
860 static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
862 /* Alas, we must pardon some whitelists. Mistakes already made */
863 static const struct regmask pardon[] = {
864 { GEN9_CTX_PREEMPT_REG, INTEL_GEN_MASK(9, 9) },
865 { GEN8_L3SQCREG4, INTEL_GEN_MASK(9, 9) },
868 return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
871 static bool result_eq(struct intel_engine_cs *engine,
872 u32 a, u32 b, i915_reg_t reg)
874 if (a != b && !pardon_reg(engine->i915, reg)) {
875 pr_err("Whitelisted register 0x%4x not context saved: A=%08x, B=%08x\n",
876 i915_mmio_reg_offset(reg), a, b);
883 static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
885 /* Some registers do not seem to behave and our writes unreadable */
886 static const struct regmask wo[] = {
887 { GEN9_SLICE_COMMON_ECO_CHICKEN1, INTEL_GEN_MASK(9, 9) },
890 return find_reg(i915, reg, wo, ARRAY_SIZE(wo));
893 static bool result_neq(struct intel_engine_cs *engine,
894 u32 a, u32 b, i915_reg_t reg)
896 if (a == b && !writeonly_reg(engine->i915, reg)) {
897 pr_err("Whitelist register 0x%4x:%08x was unwritable\n",
898 i915_mmio_reg_offset(reg), a);
906 check_whitelisted_registers(struct intel_engine_cs *engine,
909 bool (*fn)(struct intel_engine_cs *engine,
916 a = i915_gem_object_pin_map(A->obj, I915_MAP_WB);
920 b = i915_gem_object_pin_map(B->obj, I915_MAP_WB);
927 for (i = 0; i < engine->whitelist.count; i++) {
928 const struct i915_wa *wa = &engine->whitelist.list[i];
930 if (i915_mmio_reg_offset(wa->reg) & RING_FORCE_TO_NONPRIV_RD)
933 if (!fn(engine, a[i], b[i], wa->reg))
937 i915_gem_object_unpin_map(B->obj);
939 i915_gem_object_unpin_map(A->obj);
943 static int live_isolated_whitelist(void *arg)
945 struct drm_i915_private *i915 = arg;
947 struct i915_gem_context *ctx;
948 struct i915_vma *scratch[2];
950 struct intel_engine_cs *engine;
951 enum intel_engine_id id;
955 * Check that a write into a whitelist register works, but
956 * invisible to a second context.
959 if (!intel_engines_has_context_isolation(i915))
962 if (!i915->kernel_context->vm)
965 for (i = 0; i < ARRAY_SIZE(client); i++) {
966 struct i915_gem_context *c;
968 c = kernel_context(i915);
974 client[i].scratch[0] = create_scratch(c->vm, 1024);
975 if (IS_ERR(client[i].scratch[0])) {
976 err = PTR_ERR(client[i].scratch[0]);
977 kernel_context_close(c);
981 client[i].scratch[1] = create_scratch(c->vm, 1024);
982 if (IS_ERR(client[i].scratch[1])) {
983 err = PTR_ERR(client[i].scratch[1]);
984 i915_vma_unpin_and_release(&client[i].scratch[0], 0);
985 kernel_context_close(c);
992 for_each_engine(engine, i915, id) {
993 if (!whitelist_writable_count(engine))
996 /* Read default values */
997 err = read_whitelisted_registers(client[0].ctx, engine,
998 client[0].scratch[0]);
1002 /* Try to overwrite registers (should only affect ctx0) */
1003 err = scrub_whitelisted_registers(client[0].ctx, engine);
1007 /* Read values from ctx1, we expect these to be defaults */
1008 err = read_whitelisted_registers(client[1].ctx, engine,
1009 client[1].scratch[0]);
1013 /* Verify that both reads return the same default values */
1014 err = check_whitelisted_registers(engine,
1015 client[0].scratch[0],
1016 client[1].scratch[0],
1021 /* Read back the updated values in ctx0 */
1022 err = read_whitelisted_registers(client[0].ctx, engine,
1023 client[0].scratch[1]);
1027 /* User should be granted privilege to overwhite regs */
1028 err = check_whitelisted_registers(engine,
1029 client[0].scratch[0],
1030 client[0].scratch[1],
1037 for (i = 0; i < ARRAY_SIZE(client); i++) {
1041 i915_vma_unpin_and_release(&client[i].scratch[1], 0);
1042 i915_vma_unpin_and_release(&client[i].scratch[0], 0);
1043 kernel_context_close(client[i].ctx);
1046 if (igt_flush_test(i915, I915_WAIT_LOCKED))
1053 verify_wa_lists(struct i915_gem_context *ctx, struct wa_lists *lists,
1056 struct drm_i915_private *i915 = ctx->i915;
1057 struct i915_gem_engines_iter it;
1058 struct intel_context *ce;
1061 ok &= wa_list_verify(&i915->uncore, &lists->gt_wa_list, str);
1063 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1064 enum intel_engine_id id = ce->engine->id;
1066 ok &= engine_wa_list_verify(ce,
1067 &lists->engine[id].wa_list,
1070 ok &= engine_wa_list_verify(ce,
1071 &lists->engine[id].ctx_wa_list,
1074 i915_gem_context_unlock_engines(ctx);
1080 live_gpu_reset_workarounds(void *arg)
1082 struct drm_i915_private *i915 = arg;
1083 struct i915_gem_context *ctx;
1084 intel_wakeref_t wakeref;
1085 struct wa_lists lists;
1088 if (!intel_has_gpu_reset(i915))
1091 ctx = kernel_context(i915);
1093 return PTR_ERR(ctx);
1095 pr_info("Verifying after GPU reset...\n");
1097 igt_global_reset_lock(i915);
1098 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1100 reference_lists_init(i915, &lists);
1102 ok = verify_wa_lists(ctx, &lists, "before reset");
1106 i915_reset(i915, ALL_ENGINES, "live_workarounds");
1108 ok = verify_wa_lists(ctx, &lists, "after reset");
1111 kernel_context_close(ctx);
1112 reference_lists_fini(i915, &lists);
1113 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1114 igt_global_reset_unlock(i915);
1116 return ok ? 0 : -ESRCH;
1120 live_engine_reset_workarounds(void *arg)
1122 struct drm_i915_private *i915 = arg;
1123 struct intel_engine_cs *engine;
1124 struct i915_gem_context *ctx;
1125 struct igt_spinner spin;
1126 enum intel_engine_id id;
1127 struct i915_request *rq;
1128 intel_wakeref_t wakeref;
1129 struct wa_lists lists;
1132 if (!intel_has_reset_engine(i915))
1135 ctx = kernel_context(i915);
1137 return PTR_ERR(ctx);
1139 igt_global_reset_lock(i915);
1140 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1142 reference_lists_init(i915, &lists);
1144 for_each_engine(engine, i915, id) {
1147 pr_info("Verifying after %s reset...\n", engine->name);
1149 ok = verify_wa_lists(ctx, &lists, "before reset");
1155 i915_reset_engine(engine, "live_workarounds");
1157 ok = verify_wa_lists(ctx, &lists, "after idle reset");
1163 ret = igt_spinner_init(&spin, i915);
1167 rq = igt_spinner_create_request(&spin, ctx, engine, MI_NOOP);
1170 igt_spinner_fini(&spin);
1174 i915_request_add(rq);
1176 if (!igt_wait_for_spinner(&spin, rq)) {
1177 pr_err("Spinner failed to start\n");
1178 igt_spinner_fini(&spin);
1183 i915_reset_engine(engine, "live_workarounds");
1185 igt_spinner_end(&spin);
1186 igt_spinner_fini(&spin);
1188 ok = verify_wa_lists(ctx, &lists, "after busy reset");
1196 reference_lists_fini(i915, &lists);
1197 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1198 igt_global_reset_unlock(i915);
1199 kernel_context_close(ctx);
1201 igt_flush_test(i915, I915_WAIT_LOCKED);
1206 int intel_workarounds_live_selftests(struct drm_i915_private *i915)
1208 static const struct i915_subtest tests[] = {
1209 SUBTEST(live_dirty_whitelist),
1210 SUBTEST(live_reset_whitelist),
1211 SUBTEST(live_isolated_whitelist),
1212 SUBTEST(live_gpu_reset_workarounds),
1213 SUBTEST(live_engine_reset_workarounds),
1217 if (i915_terminally_wedged(i915))
1220 mutex_lock(&i915->drm.struct_mutex);
1221 err = i915_subtests(tests, i915);
1222 mutex_unlock(&i915->drm.struct_mutex);