drivers/gpu/drm/i915/gt/selftest_rc6.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2019 Intel Corporation
   5  */
   6
   7 #include "intel_context.h"
   8 #include "intel_engine_pm.h"
   9 #include "intel_gt_requests.h"
  10 #include "intel_ring.h"
  11 #include "selftest_rc6.h"
  12
  13 #include "selftests/i915_random.h"
  14
  15 static u64 energy_uJ(struct intel_rc6 *rc6)
  16 {
  17         unsigned long long power;
  18         u32 units;
  19
  20         if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power))
  21                 return 0;
  22
  23         units = (power & 0x1f00) >> 8;
  24
  25         if (rdmsrl_safe(MSR_PP1_ENERGY_STATUS, &power))
  26                 return 0;
  27
  28         return (1000000 * power) >> units; /* convert to uJ */
  29 }
  30
  31 static u64 rc6_residency(struct intel_rc6 *rc6)
  32 {
  33         u64 result;
  34
  35         /* XXX VLV_GT_MEDIA_RC6? */
  36
  37         result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
  38         if (HAS_RC6p(rc6_to_i915(rc6)))
  39                 result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p);
  40         if (HAS_RC6pp(rc6_to_i915(rc6)))
  41                 result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6pp);
  42
  43         return result;
  44 }
  45
  46 int live_rc6_manual(void *arg)
  47 {
  48         struct intel_gt *gt = arg;
  49         struct intel_rc6 *rc6 = &gt->rc6;
  50         u64 rc0_power, rc6_power;
  51         intel_wakeref_t wakeref;
  52         ktime_t dt;
  53         u64 res[2];
  54         int err = 0;
  55
  56         /*
  57          * Our claim is that we can "encourage" the GPU to enter rc6 at will.
  58          * Let's try it!
  59          */
  60
  61         if (!rc6->enabled)
  62                 return 0;
  63
  64         /* bsw/byt use a PCU and decouple RC6 from our manual control */
  65         if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
  66                 return 0;
  67
  68         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
  69
  70         /* Force RC6 off for starters */
  71         __intel_rc6_disable(rc6);
  72         msleep(1); /* wakeup is not immediate, takes about 100us on icl */
  73
  74         res[0] = rc6_residency(rc6);
  75
  76         dt = ktime_get();
  77         rc0_power = energy_uJ(rc6);
  78         msleep(250);
  79         rc0_power = energy_uJ(rc6) - rc0_power;
  80         dt = ktime_sub(ktime_get(), dt);
  81         res[1] = rc6_residency(rc6);
  82         if ((res[1] - res[0]) >> 10) {
  83                 pr_err("RC6 residency increased by %lldus while disabled for 250ms!\n",
  84                        (res[1] - res[0]) >> 10);
  85                 err = -EINVAL;
  86                 goto out_unlock;
  87         }
  88
  89         rc0_power = div64_u64(NSEC_PER_SEC * rc0_power, ktime_to_ns(dt));
  90         if (!rc0_power) {
  91                 pr_err("No power measured while in RC0\n");
  92                 err = -EINVAL;
  93                 goto out_unlock;
  94         }
  95
  96         /* Manually enter RC6 */
  97         intel_rc6_park(rc6);
  98
  99         res[0] = rc6_residency(rc6);
 100         intel_uncore_forcewake_flush(rc6_to_uncore(rc6), FORCEWAKE_ALL);
 101         dt = ktime_get();
 102         rc6_power = energy_uJ(rc6);
 103         msleep(100);
 104         rc6_power = energy_uJ(rc6) - rc6_power;
 105         dt = ktime_sub(ktime_get(), dt);
 106         res[1] = rc6_residency(rc6);
 107         if (res[1] == res[0]) {
 108                 pr_err("Did not enter RC6! RC6_STATE=%08x, RC6_CONTROL=%08x, residency=%lld\n",
 109                        intel_uncore_read_fw(gt->uncore, GEN6_RC_STATE),
 110                        intel_uncore_read_fw(gt->uncore, GEN6_RC_CONTROL),
 111                        res[0]);
 112                 err = -EINVAL;
 113         }
 114
 115         rc6_power = div64_u64(NSEC_PER_SEC * rc6_power, ktime_to_ns(dt));
 116         pr_info("GPU consumed %llduW in RC0 and %llduW in RC6\n",
 117                 rc0_power, rc6_power);
 118         if (2 * rc6_power > rc0_power) {
 119                 pr_err("GPU leaked energy while in RC6!\n");
 120                 err = -EINVAL;
 121                 goto out_unlock;
 122         }
 123
 124         /* Restore what should have been the original state! */
 125         intel_rc6_unpark(rc6);
 126
 127 out_unlock:
 128         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
 129         return err;
 130 }
 131
 132 static const u32 *__live_rc6_ctx(struct intel_context *ce)
 133 {
 134         struct i915_request *rq;
 135         const u32 *result;
 136         u32 cmd;
 137         u32 *cs;
 138
 139         rq = intel_context_create_request(ce);
 140         if (IS_ERR(rq))
 141                 return ERR_CAST(rq);
 142
 143         cs = intel_ring_begin(rq, 4);
 144         if (IS_ERR(cs)) {
 145                 i915_request_add(rq);
 146                 return cs;
 147         }
 148
 149         cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
 150         if (INTEL_GEN(rq->i915) >= 8)
 151                 cmd++;
 152
 153         *cs++ = cmd;
 154         *cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO);
 155         *cs++ = ce->timeline->hwsp_offset + 8;
 156         *cs++ = 0;
 157         intel_ring_advance(rq, cs);
 158
 159         result = rq->hwsp_seqno + 2;
 160         i915_request_add(rq);
 161
 162         return result;
 163 }
 164
 165 static struct intel_engine_cs **
 166 randomised_engines(struct intel_gt *gt,
 167                    struct rnd_state *prng,
 168                    unsigned int *count)
 169 {
 170         struct intel_engine_cs *engine, **engines;
 171         enum intel_engine_id id;
 172         int n;
 173
 174         n = 0;
 175         for_each_engine(engine, gt, id)
 176                 n++;
 177         if (!n)
 178                 return NULL;
 179
 180         engines = kmalloc_array(n, sizeof(*engines), GFP_KERNEL);
 181         if (!engines)
 182                 return NULL;
 183
 184         n = 0;
 185         for_each_engine(engine, gt, id)
 186                 engines[n++] = engine;
 187
 188         i915_prandom_shuffle(engines, sizeof(*engines), n, prng);
 189
 190         *count = n;
 191         return engines;
 192 }
 193
 194 int live_rc6_ctx_wa(void *arg)
 195 {
 196         struct intel_gt *gt = arg;
 197         struct intel_engine_cs **engines;
 198         unsigned int n, count;
 199         I915_RND_STATE(prng);
 200         int err = 0;
 201
 202         /* A read of CTX_INFO upsets rc6. Poke the bear! */
 203         if (INTEL_GEN(gt->i915) < 8)
 204                 return 0;
 205
 206         engines = randomised_engines(gt, &prng, &count);
 207         if (!engines)
 208                 return 0;
 209
 210         for (n = 0; n < count; n++) {
 211                 struct intel_engine_cs *engine = engines[n];
 212                 int pass;
 213
 214                 for (pass = 0; pass < 2; pass++) {
 215                         struct intel_context *ce;
 216                         unsigned int resets =
 217                                 i915_reset_engine_count(&gt->i915->gpu_error,
 218                                                         engine);
 219                         const u32 *res;
 220
 221                         /* Use a sacrifical context */
 222                         ce = intel_context_create(engine);
 223                         if (IS_ERR(ce)) {
 224                                 err = PTR_ERR(ce);
 225                                 goto out;
 226                         }
 227
 228                         intel_engine_pm_get(engine);
 229                         res = __live_rc6_ctx(ce);
 230                         intel_engine_pm_put(engine);
 231                         intel_context_put(ce);
 232                         if (IS_ERR(res)) {
 233                                 err = PTR_ERR(res);
 234                                 goto out;
 235                         }
 236
 237                         if (intel_gt_wait_for_idle(gt, HZ / 5) == -ETIME) {
 238                                 intel_gt_set_wedged(gt);
 239                                 err = -ETIME;
 240                                 goto out;
 241                         }
 242
 243                         intel_gt_pm_wait_for_idle(gt);
 244                         pr_debug("%s: CTX_INFO=%0x\n",
 245                                  engine->name, READ_ONCE(*res));
 246
 247                         if (resets !=
 248                             i915_reset_engine_count(&gt->i915->gpu_error,
 249                                                     engine)) {
 250                                 pr_err("%s: GPU reset required\n",
 251                                        engine->name);
 252                                 add_taint_for_CI(TAINT_WARN);
 253                                 err = -EIO;
 254                                 goto out;
 255                         }
 256                 }
 257         }
 258
 259 out:
 260         kfree(engines);
 261         return err;
 262 }