drivers/gpu/drm/i915/gt/intel_workarounds.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2014-2018 Intel Corporation
   5  */
   6
   7 #include "i915_drv.h"
   8 #include "intel_context.h"
   9 #include "intel_engine_pm.h"
  10 #include "intel_gt.h"
  11 #include "intel_ring.h"
  12 #include "intel_workarounds.h"
  13
  14 /**
  15  * DOC: Hardware workarounds
  16  *
  17  * This file is intended as a central place to implement most [1]_ of the
  18  * required workarounds for hardware to work as originally intended. They fall
  19  * in five basic categories depending on how/when they are applied:
  20  *
  21  * - Workarounds that touch registers that are saved/restored to/from the HW
  22  *   context image. The list is emitted (via Load Register Immediate commands)
  23  *   everytime a new context is created.
  24  * - GT workarounds. The list of these WAs is applied whenever these registers
  25  *   revert to default values (on GPU reset, suspend/resume [2]_, etc..).
  26  * - Display workarounds. The list is applied during display clock-gating
  27  *   initialization.
  28  * - Workarounds that whitelist a privileged register, so that UMDs can manage
  29  *   them directly. This is just a special case of a MMMIO workaround (as we
  30  *   write the list of these to/be-whitelisted registers to some special HW
  31  *   registers).
  32  * - Workaround batchbuffers, that get executed automatically by the hardware
  33  *   on every HW context restore.
  34  *
  35  * .. [1] Please notice that there are other WAs that, due to their nature,
  36  *    cannot be applied from a central place. Those are peppered around the rest
  37  *    of the code, as needed.
  38  *
  39  * .. [2] Technically, some registers are powercontext saved & restored, so they
  40  *    survive a suspend/resume. In practice, writing them again is not too
  41  *    costly and simplifies things. We can revisit this in the future.
  42  *
  43  * Layout
  44  * ~~~~~~
  45  *
  46  * Keep things in this file ordered by WA type, as per the above (context, GT,
  47  * display, register whitelist, batchbuffer). Then, inside each type, keep the
  48  * following order:
  49  *
  50  * - Infrastructure functions and macros
  51  * - WAs per platform in standard gen/chrono order
  52  * - Public functions to init or apply the given workaround type.
  53  */
  54
  55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
  56 {
  57         wal->name = name;
  58         wal->engine_name = engine_name;
  59 }
  60
  61 #define WA_LIST_CHUNK (1 << 4)
  62
  63 static void wa_init_finish(struct i915_wa_list *wal)
  64 {
  65         /* Trim unused entries. */
  66         if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) {
  67                 struct i915_wa *list = kmemdup(wal->list,
  68                                                wal->count * sizeof(*list),
  69                                                GFP_KERNEL);
  70
  71                 if (list) {
  72                         kfree(wal->list);
  73                         wal->list = list;
  74                 }
  75         }
  76
  77         if (!wal->count)
  78                 return;
  79
  80         DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n",
  81                          wal->wa_count, wal->name, wal->engine_name);
  82 }
  83
  84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
  85 {
  86         unsigned int addr = i915_mmio_reg_offset(wa->reg);
  87         unsigned int start = 0, end = wal->count;
  88         const unsigned int grow = WA_LIST_CHUNK;
  89         struct i915_wa *wa_;
  90
  91         GEM_BUG_ON(!is_power_of_2(grow));
  92
  93         if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
  94                 struct i915_wa *list;
  95
  96                 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
  97                                      GFP_KERNEL);
  98                 if (!list) {
  99                         DRM_ERROR("No space for workaround init!\n");
 100                         return;
 101                 }
 102
 103                 if (wal->list)
 104                         memcpy(list, wal->list, sizeof(*wa) * wal->count);
 105
 106                 wal->list = list;
 107         }
 108
 109         while (start < end) {
 110                 unsigned int mid = start + (end - start) / 2;
 111
 112                 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
 113                         start = mid + 1;
 114                 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
 115                         end = mid;
 116                 } else {
 117                         wa_ = &wal->list[mid];
 118
 119                         if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
 120                                 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",
 121                                           i915_mmio_reg_offset(wa_->reg),
 122                                           wa_->clr, wa_->set);
 123
 124                                 wa_->set &= ~wa->clr;
 125                         }
 126
 127                         wal->wa_count++;
 128                         wa_->set |= wa->set;
 129                         wa_->clr |= wa->clr;
 130                         wa_->read |= wa->read;
 131                         return;
 132                 }
 133         }
 134
 135         wal->wa_count++;
 136         wa_ = &wal->list[wal->count++];
 137         *wa_ = *wa;
 138
 139         while (wa_-- > wal->list) {
 140                 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
 141                            i915_mmio_reg_offset(wa_[1].reg));
 142                 if (i915_mmio_reg_offset(wa_[1].reg) >
 143                     i915_mmio_reg_offset(wa_[0].reg))
 144                         break;
 145
 146                 swap(wa_[1], wa_[0]);
 147         }
 148 }
 149
 150 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
 151                    u32 clear, u32 set, u32 read_mask)
 152 {
 153         struct i915_wa wa = {
 154                 .reg  = reg,
 155                 .clr  = clear,
 156                 .set  = set,
 157                 .read = read_mask,
 158         };
 159
 160         _wa_add(wal, &wa);
 161 }
 162
 163 static void
 164 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
 165 {
 166         wa_add(wal, reg, clear, set, clear);
 167 }
 168
 169 static void
 170 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 171 {
 172         wa_write_masked_or(wal, reg, ~0, set);
 173 }
 174
 175 static void
 176 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 177 {
 178         wa_write_masked_or(wal, reg, set, set);
 179 }
 180
 181 static void
 182 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
 183 {
 184         wa_write_masked_or(wal, reg, clr, 0);
 185 }
 186
 187 static void
 188 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 189 {
 190         wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
 191 }
 192
 193 static void
 194 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 195 {
 196         wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
 197 }
 198
 199 #define WA_SET_BIT_MASKED(addr, mask) \
 200         wa_masked_en(wal, (addr), (mask))
 201
 202 #define WA_CLR_BIT_MASKED(addr, mask) \
 203         wa_masked_dis(wal, (addr), (mask))
 204
 205 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 206         wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value)))
 207
 208 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
 209                                       struct i915_wa_list *wal)
 210 {
 211         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 212
 213         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 214         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 215
 216         /* WaDisablePartialInstShootdown:bdw,chv */
 217         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 218                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 219
 220         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 221          * workaround for for a possible hang in the unlikely event a TLB
 222          * invalidation occurs during a PSD flush.
 223          */
 224         /* WaForceEnableNonCoherent:bdw,chv */
 225         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 226         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 227                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 228                           HDC_FORCE_NON_COHERENT);
 229
 230         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 231          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 232          *  polygons in the same 8x4 pixel/sample area to be processed without
 233          *  stalling waiting for the earlier ones to write to Hierarchical Z
 234          *  buffer."
 235          *
 236          * This optimization is off by default for BDW and CHV; turn it on.
 237          */
 238         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 239
 240         /* Wa4x4STCOptimizationDisable:bdw,chv */
 241         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 242
 243         /*
 244          * BSpec recommends 8x4 when MSAA is used,
 245          * however in practice 16x4 seems fastest.
 246          *
 247          * Note that PS/WM thread counts depend on the WIZ hashing
 248          * disable bit, which we don't touch here, but it's good
 249          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 250          */
 251         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 252                             GEN6_WIZ_HASHING_MASK,
 253                             GEN6_WIZ_HASHING_16x4);
 254 }
 255
 256 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
 257                                      struct i915_wa_list *wal)
 258 {
 259         struct drm_i915_private *i915 = engine->i915;
 260
 261         gen8_ctx_workarounds_init(engine, wal);
 262
 263         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 264         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 265
 266         /* WaDisableDopClockGating:bdw
 267          *
 268          * Also see the related UCGTCL1 write in bdw_init_clock_gating()
 269          * to disable EUTC clock gating.
 270          */
 271         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 272                           DOP_CLOCK_GATING_DISABLE);
 273
 274         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 275                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 276
 277         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 278                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 279                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 280                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 281                           (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 282 }
 283
 284 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
 285                                      struct i915_wa_list *wal)
 286 {
 287         gen8_ctx_workarounds_init(engine, wal);
 288
 289         /* WaDisableThreadStallDopClockGating:chv */
 290         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 291
 292         /* Improve HiZ throughput on CHV. */
 293         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 294 }
 295
 296 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
 297                                       struct i915_wa_list *wal)
 298 {
 299         struct drm_i915_private *i915 = engine->i915;
 300
 301         if (HAS_LLC(i915)) {
 302                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
 303                  *
 304                  * Must match Display Engine. See
 305                  * WaCompressedResourceDisplayNewHashMode.
 306                  */
 307                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 308                                   GEN9_PBE_COMPRESSED_HASH_SELECTION);
 309                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 310                                   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
 311         }
 312
 313         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
 314         /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
 315         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 316                           FLOW_CONTROL_ENABLE |
 317                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 318
 319         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
 320         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
 321         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 322                           GEN9_ENABLE_YV12_BUGFIX |
 323                           GEN9_ENABLE_GPGPU_PREEMPTION);
 324
 325         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
 326         /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
 327         WA_SET_BIT_MASKED(CACHE_MODE_1,
 328                           GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 329                           GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 330
 331         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
 332         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 333                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 334
 335         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
 336         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 337                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 338                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 339
 340         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 341          * both tied to WaForceContextSaveRestoreNonCoherent
 342          * in some hsds for skl. We keep the tie for all gen9. The
 343          * documentation is a bit hazy and so we want to get common behaviour,
 344          * even though there is no clear evidence we would need both on kbl/bxt.
 345          * This area has been source of system hangs so we play it safe
 346          * and mimic the skl regardless of what bspec says.
 347          *
 348          * Use Force Non-Coherent whenever executing a 3D context. This
 349          * is a workaround for a possible hang in the unlikely event
 350          * a TLB invalidation occurs during a PSD flush.
 351          */
 352
 353         /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
 354         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 355                           HDC_FORCE_NON_COHERENT);
 356
 357         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
 358         if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915))
 359                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 360                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 361
 362         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
 363         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 364
 365         /*
 366          * Supporting preemption with fine-granularity requires changes in the
 367          * batch buffer programming. Since we can't break old userspace, we
 368          * need to set our default preemption level to safe value. Userspace is
 369          * still able to use more fine-grained preemption levels, since in
 370          * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
 371          * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
 372          * not real HW workarounds, but merely a way to start using preemption
 373          * while maintaining old contract with userspace.
 374          */
 375
 376         /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
 377         WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
 378
 379         /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
 380         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 381                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 382                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 383
 384         /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
 385         if (IS_GEN9_LP(i915))
 386                 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
 387 }
 388
 389 static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
 390                                 struct i915_wa_list *wal)
 391 {
 392         struct drm_i915_private *i915 = engine->i915;
 393         u8 vals[3] = { 0, 0, 0 };
 394         unsigned int i;
 395
 396         for (i = 0; i < 3; i++) {
 397                 u8 ss;
 398
 399                 /*
 400                  * Only consider slices where one, and only one, subslice has 7
 401                  * EUs
 402                  */
 403                 if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]))
 404                         continue;
 405
 406                 /*
 407                  * subslice_7eu[i] != 0 (because of the check above) and
 408                  * ss_max == 4 (maximum number of subslices possible per slice)
 409                  *
 410                  * ->    0 <= ss <= 3;
 411                  */
 412                 ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1;
 413                 vals[i] = 3 - ss;
 414         }
 415
 416         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
 417                 return;
 418
 419         /* Tune IZ hashing. See intel_device_info_runtime_init() */
 420         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 421                             GEN9_IZ_HASHING_MASK(2) |
 422                             GEN9_IZ_HASHING_MASK(1) |
 423                             GEN9_IZ_HASHING_MASK(0),
 424                             GEN9_IZ_HASHING(2, vals[2]) |
 425                             GEN9_IZ_HASHING(1, vals[1]) |
 426                             GEN9_IZ_HASHING(0, vals[0]));
 427 }
 428
 429 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
 430                                      struct i915_wa_list *wal)
 431 {
 432         gen9_ctx_workarounds_init(engine, wal);
 433         skl_tune_iz_hashing(engine, wal);
 434 }
 435
 436 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
 437                                      struct i915_wa_list *wal)
 438 {
 439         gen9_ctx_workarounds_init(engine, wal);
 440
 441         /* WaDisableThreadStallDopClockGating:bxt */
 442         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 443                           STALL_DOP_GATING_DISABLE);
 444
 445         /* WaToEnableHwFixForPushConstHWBug:bxt */
 446         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 447                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 448 }
 449
 450 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
 451                                      struct i915_wa_list *wal)
 452 {
 453         struct drm_i915_private *i915 = engine->i915;
 454
 455         gen9_ctx_workarounds_init(engine, wal);
 456
 457         /* WaToEnableHwFixForPushConstHWBug:kbl */
 458         if (IS_KBL_REVID(i915, KBL_REVID_C0, REVID_FOREVER))
 459                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 460                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 461
 462         /* WaDisableSbeCacheDispatchPortSharing:kbl */
 463         WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 464                           GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 465 }
 466
 467 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
 468                                      struct i915_wa_list *wal)
 469 {
 470         gen9_ctx_workarounds_init(engine, wal);
 471
 472         /* WaToEnableHwFixForPushConstHWBug:glk */
 473         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 474                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 475 }
 476
 477 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
 478                                      struct i915_wa_list *wal)
 479 {
 480         gen9_ctx_workarounds_init(engine, wal);
 481
 482         /* WaToEnableHwFixForPushConstHWBug:cfl */
 483         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 484                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 485
 486         /* WaDisableSbeCacheDispatchPortSharing:cfl */
 487         WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 488                           GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 489 }
 490
 491 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
 492                                      struct i915_wa_list *wal)
 493 {
 494         /* WaForceContextSaveRestoreNonCoherent:cnl */
 495         WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
 496                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
 497
 498         /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
 499         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 500                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 501
 502         /* WaPushConstantDereferenceHoldDisable:cnl */
 503         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
 504
 505         /* FtrEnableFastAnisoL1BankingFix:cnl */
 506         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
 507
 508         /* WaDisable3DMidCmdPreemption:cnl */
 509         WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
 510
 511         /* WaDisableGPGPUMidCmdPreemption:cnl */
 512         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 513                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 514                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 515
 516         /* WaDisableEarlyEOT:cnl */
 517         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
 518 }
 519
 520 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 521                                      struct i915_wa_list *wal)
 522 {
 523         struct drm_i915_private *i915 = engine->i915;
 524
 525         /* WaDisableBankHangMode:icl */
 526         wa_write(wal,
 527                  GEN8_L3CNTLREG,
 528                  intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
 529                  GEN8_ERRDETBCTRL);
 530
 531         /* Wa_1604370585:icl (pre-prod)
 532          * Formerly known as WaPushConstantDereferenceHoldDisable
 533          */
 534         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
 535                 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 536                                   PUSH_CONSTANT_DEREF_DISABLE);
 537
 538         /* WaForceEnableNonCoherent:icl
 539          * This is not the same workaround as in early Gen9 platforms, where
 540          * lacking this could cause system hangs, but coherency performance
 541          * overhead is high and only a few compute workloads really need it
 542          * (the register is whitelisted in hardware now, so UMDs can opt in
 543          * for coherency if they have a good reason).
 544          */
 545         WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
 546
 547         /* Wa_2006611047:icl (pre-prod)
 548          * Formerly known as WaDisableImprovedTdlClkGating
 549          */
 550         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
 551                 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 552                                   GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 553
 554         /* Wa_2006665173:icl (pre-prod) */
 555         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
 556                 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 557                                   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 558
 559         /* WaEnableFloatBlendOptimization:icl */
 560         wa_write_masked_or(wal,
 561                            GEN10_CACHE_MODE_SS,
 562                            0, /* write-only, so skip validation */
 563                            _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
 564
 565         /* WaDisableGPGPUMidThreadPreemption:icl */
 566         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 567                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 568                             GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 569
 570         /* allow headerless messages for preemptible GPGPU context */
 571         WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
 572                           GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
 573
 574         /* Wa_1604278689:icl,ehl */
 575         wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
 576         wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
 577                            0, /* write-only register; skip validation */
 578                            0xFFFFFFFF);
 579
 580         /* Wa_1406306137:icl,ehl */
 581         wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
 582 }
 583
 584 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 585                                      struct i915_wa_list *wal)
 586 {
 587         /*
 588          * Wa_1409142259:tgl
 589          * Wa_1409347922:tgl
 590          * Wa_1409252684:tgl
 591          * Wa_1409217633:tgl
 592          * Wa_1409207793:tgl
 593          * Wa_1409178076:tgl
 594          * Wa_1408979724:tgl
 595          */
 596         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 597                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 598
 599         /*
 600          * Wa_1604555607:gen12 and Wa_1608008084:gen12
 601          * FF_MODE2 register will return the wrong value when read. The default
 602          * value for this register is zero for all fields and there are no bit
 603          * masks. So instead of doing a RMW we should just write the TDS timer
 604          * value for Wa_1604555607.
 605          */
 606         wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
 607                FF_MODE2_TDS_TIMER_128, 0);
 608
 609         /* WaDisableGPGPUMidThreadPreemption:tgl */
 610         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 611                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 612                             GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 613 }
 614
 615 static void
 616 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 617                            struct i915_wa_list *wal,
 618                            const char *name)
 619 {
 620         struct drm_i915_private *i915 = engine->i915;
 621
 622         if (engine->class != RENDER_CLASS)
 623                 return;
 624
 625         wa_init_start(wal, name, engine->name);
 626
 627         if (IS_GEN(i915, 12))
 628                 tgl_ctx_workarounds_init(engine, wal);
 629         else if (IS_GEN(i915, 11))
 630                 icl_ctx_workarounds_init(engine, wal);
 631         else if (IS_CANNONLAKE(i915))
 632                 cnl_ctx_workarounds_init(engine, wal);
 633         else if (IS_COFFEELAKE(i915))
 634                 cfl_ctx_workarounds_init(engine, wal);
 635         else if (IS_GEMINILAKE(i915))
 636                 glk_ctx_workarounds_init(engine, wal);
 637         else if (IS_KABYLAKE(i915))
 638                 kbl_ctx_workarounds_init(engine, wal);
 639         else if (IS_BROXTON(i915))
 640                 bxt_ctx_workarounds_init(engine, wal);
 641         else if (IS_SKYLAKE(i915))
 642                 skl_ctx_workarounds_init(engine, wal);
 643         else if (IS_CHERRYVIEW(i915))
 644                 chv_ctx_workarounds_init(engine, wal);
 645         else if (IS_BROADWELL(i915))
 646                 bdw_ctx_workarounds_init(engine, wal);
 647         else if (INTEL_GEN(i915) < 8)
 648                 return;
 649         else
 650                 MISSING_CASE(INTEL_GEN(i915));
 651
 652         wa_init_finish(wal);
 653 }
 654
 655 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
 656 {
 657         __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
 658 }
 659
 660 int intel_engine_emit_ctx_wa(struct i915_request *rq)
 661 {
 662         struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
 663         struct i915_wa *wa;
 664         unsigned int i;
 665         u32 *cs;
 666         int ret;
 667
 668         if (wal->count == 0)
 669                 return 0;
 670
 671         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
 672         if (ret)
 673                 return ret;
 674
 675         cs = intel_ring_begin(rq, (wal->count * 2 + 2));
 676         if (IS_ERR(cs))
 677                 return PTR_ERR(cs);
 678
 679         *cs++ = MI_LOAD_REGISTER_IMM(wal->count);
 680         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
 681                 *cs++ = i915_mmio_reg_offset(wa->reg);
 682                 *cs++ = wa->set;
 683         }
 684         *cs++ = MI_NOOP;
 685
 686         intel_ring_advance(rq, cs);
 687
 688         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
 689         if (ret)
 690                 return ret;
 691
 692         return 0;
 693 }
 694
 695 static void
 696 hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 697 {
 698         /* L3 caching of data atomics doesn't work -- disable it. */
 699         wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
 700
 701         wa_add(wal,
 702                HSW_ROW_CHICKEN3, 0,
 703                _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
 704                 0 /* XXX does this reg exist? */);
 705
 706         /* WaVSRefCountFullforceMissDisable:hsw */
 707         wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
 708
 709         wa_masked_dis(wal,
 710                       CACHE_MODE_0_GEN7,
 711                       /* WaDisable_RenderCache_OperationalFlush:hsw */
 712                       RC_OP_FLUSH_ENABLE |
 713                       /* enable HiZ Raw Stall Optimization */
 714                       HIZ_RAW_STALL_OPT_DISABLE);
 715
 716         /* WaDisable4x2SubspanOptimization:hsw */
 717         wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
 718
 719         /*
 720          * BSpec recommends 8x4 when MSAA is used,
 721          * however in practice 16x4 seems fastest.
 722          *
 723          * Note that PS/WM thread counts depend on the WIZ hashing
 724          * disable bit, which we don't touch here, but it's good
 725          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 726          */
 727         wa_add(wal, GEN7_GT_MODE, 0,
 728                _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
 729                GEN6_WIZ_HASHING_16x4);
 730
 731         /* WaSampleCChickenBitEnable:hsw */
 732         wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
 733 }
 734
 735 static void
 736 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 737 {
 738         /* WaDisableKillLogic:bxt,skl,kbl */
 739         if (!IS_COFFEELAKE(i915))
 740                 wa_write_or(wal,
 741                             GAM_ECOCHK,
 742                             ECOCHK_DIS_TLB);
 743
 744         if (HAS_LLC(i915)) {
 745                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
 746                  *
 747                  * Must match Display Engine. See
 748                  * WaCompressedResourceDisplayNewHashMode.
 749                  */
 750                 wa_write_or(wal,
 751                             MMCD_MISC_CTRL,
 752                             MMCD_PCLA | MMCD_HOTSPOT_EN);
 753         }
 754
 755         /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
 756         wa_write_or(wal,
 757                     GAM_ECOCHK,
 758                     BDW_DISABLE_HDC_INVALIDATION);
 759 }
 760
 761 static void
 762 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 763 {
 764         gen9_gt_workarounds_init(i915, wal);
 765
 766         /* WaDisableGafsUnitClkGating:skl */
 767         wa_write_or(wal,
 768                     GEN7_UCGCTL4,
 769                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 770
 771         /* WaInPlaceDecompressionHang:skl */
 772         if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
 773                 wa_write_or(wal,
 774                             GEN9_GAMT_ECO_REG_RW_IA,
 775                             GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 776 }
 777
 778 static void
 779 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 780 {
 781         gen9_gt_workarounds_init(i915, wal);
 782
 783         /* WaInPlaceDecompressionHang:bxt */
 784         wa_write_or(wal,
 785                     GEN9_GAMT_ECO_REG_RW_IA,
 786                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 787 }
 788
 789 static void
 790 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 791 {
 792         gen9_gt_workarounds_init(i915, wal);
 793
 794         /* WaDisableDynamicCreditSharing:kbl */
 795         if (IS_KBL_REVID(i915, 0, KBL_REVID_B0))
 796                 wa_write_or(wal,
 797                             GAMT_CHKN_BIT_REG,
 798                             GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
 799
 800         /* WaDisableGafsUnitClkGating:kbl */
 801         wa_write_or(wal,
 802                     GEN7_UCGCTL4,
 803                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 804
 805         /* WaInPlaceDecompressionHang:kbl */
 806         wa_write_or(wal,
 807                     GEN9_GAMT_ECO_REG_RW_IA,
 808                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 809 }
 810
 811 static void
 812 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 813 {
 814         gen9_gt_workarounds_init(i915, wal);
 815 }
 816
 817 static void
 818 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 819 {
 820         gen9_gt_workarounds_init(i915, wal);
 821
 822         /* WaDisableGafsUnitClkGating:cfl */
 823         wa_write_or(wal,
 824                     GEN7_UCGCTL4,
 825                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 826
 827         /* WaInPlaceDecompressionHang:cfl */
 828         wa_write_or(wal,
 829                     GEN9_GAMT_ECO_REG_RW_IA,
 830                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 831 }
 832
 833 static void
 834 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 835 {
 836         const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
 837         unsigned int slice, subslice;
 838         u32 l3_en, mcr, mcr_mask;
 839
 840         GEM_BUG_ON(INTEL_GEN(i915) < 10);
 841
 842         /*
 843          * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
 844          * L3Banks could be fused off in single slice scenario. If that is
 845          * the case, we might need to program MCR select to a valid L3Bank
 846          * by default, to make sure we correctly read certain registers
 847          * later on (in the range 0xB100 - 0xB3FF).
 848          *
 849          * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
 850          * Before any MMIO read into slice/subslice specific registers, MCR
 851          * packet control register needs to be programmed to point to any
 852          * enabled s/ss pair. Otherwise, incorrect values will be returned.
 853          * This means each subsequent MMIO read will be forwarded to an
 854          * specific s/ss combination, but this is OK since these registers
 855          * are consistent across s/ss in almost all cases. In the rare
 856          * occasions, such as INSTDONE, where this value is dependent
 857          * on s/ss combo, the read should be done with read_subslice_reg.
 858          *
 859          * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both
 860          * to which subslice, or to which L3 bank, the respective mmio reads
 861          * will go, we have to find a common index which works for both
 862          * accesses.
 863          *
 864          * Case where we cannot find a common index fortunately should not
 865          * happen in production hardware, so we only emit a warning instead of
 866          * implementing something more complex that requires checking the range
 867          * of every MMIO read.
 868          */
 869
 870         if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
 871                 u32 l3_fuse =
 872                         intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
 873                         GEN10_L3BANK_MASK;
 874
 875                 drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse);
 876                 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse);
 877         } else {
 878                 l3_en = ~0;
 879         }
 880
 881         slice = fls(sseu->slice_mask) - 1;
 882         subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
 883         if (!subslice) {
 884                 drm_warn(&i915->drm,
 885                          "No common index found between subslice mask %x and L3 bank mask %x!\n",
 886                          intel_sseu_get_subslices(sseu, slice), l3_en);
 887                 subslice = fls(l3_en);
 888                 drm_WARN_ON(&i915->drm, !subslice);
 889         }
 890         subslice--;
 891
 892         if (INTEL_GEN(i915) >= 11) {
 893                 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
 894                 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
 895         } else {
 896                 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
 897                 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
 898         }
 899
 900         drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr);
 901
 902         wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
 903 }
 904
 905 static void
 906 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 907 {
 908         wa_init_mcr(i915, wal);
 909
 910         /* WaInPlaceDecompressionHang:cnl */
 911         wa_write_or(wal,
 912                     GEN9_GAMT_ECO_REG_RW_IA,
 913                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 914 }
 915
 916 static void
 917 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 918 {
 919         wa_init_mcr(i915, wal);
 920
 921         /* WaInPlaceDecompressionHang:icl */
 922         wa_write_or(wal,
 923                     GEN9_GAMT_ECO_REG_RW_IA,
 924                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 925
 926         /* WaModifyGamTlbPartitioning:icl */
 927         wa_write_masked_or(wal,
 928                            GEN11_GACB_PERF_CTRL,
 929                            GEN11_HASH_CTRL_MASK,
 930                            GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
 931
 932         /* Wa_1405766107:icl
 933          * Formerly known as WaCL2SFHalfMaxAlloc
 934          */
 935         wa_write_or(wal,
 936                     GEN11_LSN_UNSLCVC,
 937                     GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
 938                     GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
 939
 940         /* Wa_220166154:icl
 941          * Formerly known as WaDisCtxReload
 942          */
 943         wa_write_or(wal,
 944                     GEN8_GAMW_ECO_DEV_RW_IA,
 945                     GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
 946
 947         /* Wa_1405779004:icl (pre-prod) */
 948         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
 949                 wa_write_or(wal,
 950                             SLICE_UNIT_LEVEL_CLKGATE,
 951                             MSCUNIT_CLKGATE_DIS);
 952
 953         /* Wa_1406838659:icl (pre-prod) */
 954         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
 955                 wa_write_or(wal,
 956                             INF_UNIT_LEVEL_CLKGATE,
 957                             CGPSF_CLKGATE_DIS);
 958
 959         /* Wa_1406463099:icl
 960          * Formerly known as WaGamTlbPendError
 961          */
 962         wa_write_or(wal,
 963                     GAMT_CHKN_BIT_REG,
 964                     GAMT_CHKN_DISABLE_L3_COH_PIPE);
 965
 966         /* Wa_1607087056:icl,ehl,jsl */
 967         if (IS_ICELAKE(i915) ||
 968             IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) {
 969                 wa_write_or(wal,
 970                             SLICE_UNIT_LEVEL_CLKGATE,
 971                             L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 972         }
 973 }
 974
 975 static void
 976 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 977 {
 978         wa_init_mcr(i915, wal);
 979
 980         /* Wa_1409420604:tgl */
 981         if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
 982                 wa_write_or(wal,
 983                             SUBSLICE_UNIT_LEVEL_CLKGATE2,
 984                             CPSSUNIT_CLKGATE_DIS);
 985
 986         /* Wa_1607087056:tgl also know as BUG:1409180338 */
 987         if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
 988                 wa_write_or(wal,
 989                             SLICE_UNIT_LEVEL_CLKGATE,
 990                             L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 991 }
 992
 993 static void
 994 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 995 {
 996         if (IS_GEN(i915, 12))
 997                 tgl_gt_workarounds_init(i915, wal);
 998         else if (IS_GEN(i915, 11))
 999                 icl_gt_workarounds_init(i915, wal);
1000         else if (IS_CANNONLAKE(i915))
1001                 cnl_gt_workarounds_init(i915, wal);
1002         else if (IS_COFFEELAKE(i915))
1003                 cfl_gt_workarounds_init(i915, wal);
1004         else if (IS_GEMINILAKE(i915))
1005                 glk_gt_workarounds_init(i915, wal);
1006         else if (IS_KABYLAKE(i915))
1007                 kbl_gt_workarounds_init(i915, wal);
1008         else if (IS_BROXTON(i915))
1009                 bxt_gt_workarounds_init(i915, wal);
1010         else if (IS_SKYLAKE(i915))
1011                 skl_gt_workarounds_init(i915, wal);
1012         else if (IS_HASWELL(i915))
1013                 hsw_gt_workarounds_init(i915, wal);
1014         else if (INTEL_GEN(i915) <= 8)
1015                 return;
1016         else
1017                 MISSING_CASE(INTEL_GEN(i915));
1018 }
1019
1020 void intel_gt_init_workarounds(struct drm_i915_private *i915)
1021 {
1022         struct i915_wa_list *wal = &i915->gt_wa_list;
1023
1024         wa_init_start(wal, "GT", "global");
1025         gt_init_workarounds(i915, wal);
1026         wa_init_finish(wal);
1027 }
1028
1029 static enum forcewake_domains
1030 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
1031 {
1032         enum forcewake_domains fw = 0;
1033         struct i915_wa *wa;
1034         unsigned int i;
1035
1036         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1037                 fw |= intel_uncore_forcewake_for_reg(uncore,
1038                                                      wa->reg,
1039                                                      FW_REG_READ |
1040                                                      FW_REG_WRITE);
1041
1042         return fw;
1043 }
1044
1045 static bool
1046 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
1047 {
1048         if ((cur ^ wa->set) & wa->read) {
1049                 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n",
1050                           name, from, i915_mmio_reg_offset(wa->reg),
1051                           cur, cur & wa->read, wa->set);
1052
1053                 return false;
1054         }
1055
1056         return true;
1057 }
1058
1059 static void
1060 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
1061 {
1062         enum forcewake_domains fw;
1063         unsigned long flags;
1064         struct i915_wa *wa;
1065         unsigned int i;
1066
1067         if (!wal->count)
1068                 return;
1069
1070         fw = wal_get_fw_for_rmw(uncore, wal);
1071
1072         spin_lock_irqsave(&uncore->lock, flags);
1073         intel_uncore_forcewake_get__locked(uncore, fw);
1074
1075         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1076                 if (wa->clr)
1077                         intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set);
1078                 else
1079                         intel_uncore_write_fw(uncore, wa->reg, wa->set);
1080                 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1081                         wa_verify(wa,
1082                                   intel_uncore_read_fw(uncore, wa->reg),
1083                                   wal->name, "application");
1084         }
1085
1086         intel_uncore_forcewake_put__locked(uncore, fw);
1087         spin_unlock_irqrestore(&uncore->lock, flags);
1088 }
1089
1090 void intel_gt_apply_workarounds(struct intel_gt *gt)
1091 {
1092         wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
1093 }
1094
1095 static bool wa_list_verify(struct intel_uncore *uncore,
1096                            const struct i915_wa_list *wal,
1097                            const char *from)
1098 {
1099         struct i915_wa *wa;
1100         unsigned int i;
1101         bool ok = true;
1102
1103         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1104                 ok &= wa_verify(wa,
1105                                 intel_uncore_read(uncore, wa->reg),
1106                                 wal->name, from);
1107
1108         return ok;
1109 }
1110
1111 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
1112 {
1113         return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
1114 }
1115
1116 static inline bool is_nonpriv_flags_valid(u32 flags)
1117 {
1118         /* Check only valid flag bits are set */
1119         if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
1120                 return false;
1121
1122         /* NB: Only 3 out of 4 enum values are valid for access field */
1123         if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
1124             RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
1125                 return false;
1126
1127         return true;
1128 }
1129
1130 static void
1131 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1132 {
1133         struct i915_wa wa = {
1134                 .reg = reg
1135         };
1136
1137         if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1138                 return;
1139
1140         if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1141                 return;
1142
1143         wa.reg.reg |= flags;
1144         _wa_add(wal, &wa);
1145 }
1146
1147 static void
1148 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1149 {
1150         whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1151 }
1152
1153 static void gen9_whitelist_build(struct i915_wa_list *w)
1154 {
1155         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1156         whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
1157
1158         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1159         whitelist_reg(w, GEN8_CS_CHICKEN1);
1160
1161         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1162         whitelist_reg(w, GEN8_HDC_CHICKEN1);
1163
1164         /* WaSendPushConstantsFromMMIO:skl,bxt */
1165         whitelist_reg(w, COMMON_SLICE_CHICKEN2);
1166 }
1167
1168 static void skl_whitelist_build(struct intel_engine_cs *engine)
1169 {
1170         struct i915_wa_list *w = &engine->whitelist;
1171
1172         if (engine->class != RENDER_CLASS)
1173                 return;
1174
1175         gen9_whitelist_build(w);
1176
1177         /* WaDisableLSQCROPERFforOCL:skl */
1178         whitelist_reg(w, GEN8_L3SQCREG4);
1179 }
1180
1181 static void bxt_whitelist_build(struct intel_engine_cs *engine)
1182 {
1183         if (engine->class != RENDER_CLASS)
1184                 return;
1185
1186         gen9_whitelist_build(&engine->whitelist);
1187 }
1188
1189 static void kbl_whitelist_build(struct intel_engine_cs *engine)
1190 {
1191         struct i915_wa_list *w = &engine->whitelist;
1192
1193         if (engine->class != RENDER_CLASS)
1194                 return;
1195
1196         gen9_whitelist_build(w);
1197
1198         /* WaDisableLSQCROPERFforOCL:kbl */
1199         whitelist_reg(w, GEN8_L3SQCREG4);
1200 }
1201
1202 static void glk_whitelist_build(struct intel_engine_cs *engine)
1203 {
1204         struct i915_wa_list *w = &engine->whitelist;
1205
1206         if (engine->class != RENDER_CLASS)
1207                 return;
1208
1209         gen9_whitelist_build(w);
1210
1211         /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
1212         whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1213 }
1214
1215 static void cfl_whitelist_build(struct intel_engine_cs *engine)
1216 {
1217         struct i915_wa_list *w = &engine->whitelist;
1218
1219         if (engine->class != RENDER_CLASS)
1220                 return;
1221
1222         gen9_whitelist_build(w);
1223
1224         /*
1225          * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
1226          *
1227          * This covers 4 register which are next to one another :
1228          *   - PS_INVOCATION_COUNT
1229          *   - PS_INVOCATION_COUNT_UDW
1230          *   - PS_DEPTH_COUNT
1231          *   - PS_DEPTH_COUNT_UDW
1232          */
1233         whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1234                           RING_FORCE_TO_NONPRIV_ACCESS_RD |
1235                           RING_FORCE_TO_NONPRIV_RANGE_4);
1236 }
1237
1238 static void cnl_whitelist_build(struct intel_engine_cs *engine)
1239 {
1240         struct i915_wa_list *w = &engine->whitelist;
1241
1242         if (engine->class != RENDER_CLASS)
1243                 return;
1244
1245         /* WaEnablePreemptionGranularityControlByUMD:cnl */
1246         whitelist_reg(w, GEN8_CS_CHICKEN1);
1247 }
1248
1249 static void icl_whitelist_build(struct intel_engine_cs *engine)
1250 {
1251         struct i915_wa_list *w = &engine->whitelist;
1252
1253         switch (engine->class) {
1254         case RENDER_CLASS:
1255                 /* WaAllowUMDToModifyHalfSliceChicken7:icl */
1256                 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
1257
1258                 /* WaAllowUMDToModifySamplerMode:icl */
1259                 whitelist_reg(w, GEN10_SAMPLER_MODE);
1260
1261                 /* WaEnableStateCacheRedirectToCS:icl */
1262                 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1263
1264                 /*
1265                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
1266                  *
1267                  * This covers 4 register which are next to one another :
1268                  *   - PS_INVOCATION_COUNT
1269                  *   - PS_INVOCATION_COUNT_UDW
1270                  *   - PS_DEPTH_COUNT
1271                  *   - PS_DEPTH_COUNT_UDW
1272                  */
1273                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1274                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
1275                                   RING_FORCE_TO_NONPRIV_RANGE_4);
1276                 break;
1277
1278         case VIDEO_DECODE_CLASS:
1279                 /* hucStatusRegOffset */
1280                 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
1281                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
1282                 /* hucUKernelHdrInfoRegOffset */
1283                 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
1284                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
1285                 /* hucStatus2RegOffset */
1286                 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
1287                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
1288                 break;
1289
1290         default:
1291                 break;
1292         }
1293 }
1294
1295 static void tgl_whitelist_build(struct intel_engine_cs *engine)
1296 {
1297         struct i915_wa_list *w = &engine->whitelist;
1298
1299         switch (engine->class) {
1300         case RENDER_CLASS:
1301                 /*
1302                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
1303                  * Wa_1408556865:tgl
1304                  *
1305                  * This covers 4 registers which are next to one another :
1306                  *   - PS_INVOCATION_COUNT
1307                  *   - PS_INVOCATION_COUNT_UDW
1308                  *   - PS_DEPTH_COUNT
1309                  *   - PS_DEPTH_COUNT_UDW
1310                  */
1311                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1312                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
1313                                   RING_FORCE_TO_NONPRIV_RANGE_4);
1314
1315                 /* Wa_1808121037:tgl */
1316                 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
1317
1318                 /* Wa_1806527549:tgl */
1319                 whitelist_reg(w, HIZ_CHICKEN);
1320                 break;
1321         default:
1322                 break;
1323         }
1324 }
1325
1326 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
1327 {
1328         struct drm_i915_private *i915 = engine->i915;
1329         struct i915_wa_list *w = &engine->whitelist;
1330
1331         wa_init_start(w, "whitelist", engine->name);
1332
1333         if (IS_GEN(i915, 12))
1334                 tgl_whitelist_build(engine);
1335         else if (IS_GEN(i915, 11))
1336                 icl_whitelist_build(engine);
1337         else if (IS_CANNONLAKE(i915))
1338                 cnl_whitelist_build(engine);
1339         else if (IS_COFFEELAKE(i915))
1340                 cfl_whitelist_build(engine);
1341         else if (IS_GEMINILAKE(i915))
1342                 glk_whitelist_build(engine);
1343         else if (IS_KABYLAKE(i915))
1344                 kbl_whitelist_build(engine);
1345         else if (IS_BROXTON(i915))
1346                 bxt_whitelist_build(engine);
1347         else if (IS_SKYLAKE(i915))
1348                 skl_whitelist_build(engine);
1349         else if (INTEL_GEN(i915) <= 8)
1350                 return;
1351         else
1352                 MISSING_CASE(INTEL_GEN(i915));
1353
1354         wa_init_finish(w);
1355 }
1356
1357 void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
1358 {
1359         const struct i915_wa_list *wal = &engine->whitelist;
1360         struct intel_uncore *uncore = engine->uncore;
1361         const u32 base = engine->mmio_base;
1362         struct i915_wa *wa;
1363         unsigned int i;
1364
1365         if (!wal->count)
1366                 return;
1367
1368         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1369                 intel_uncore_write(uncore,
1370                                    RING_FORCE_TO_NONPRIV(base, i),
1371                                    i915_mmio_reg_offset(wa->reg));
1372
1373         /* And clear the rest just in case of garbage */
1374         for (; i < RING_MAX_NONPRIV_SLOTS; i++)
1375                 intel_uncore_write(uncore,
1376                                    RING_FORCE_TO_NONPRIV(base, i),
1377                                    i915_mmio_reg_offset(RING_NOPID(base)));
1378 }
1379
1380 static void
1381 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1382 {
1383         struct drm_i915_private *i915 = engine->i915;
1384
1385         if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
1386                 /*
1387                  * Wa_1607138336:tgl
1388                  * Wa_1607063988:tgl
1389                  */
1390                 wa_write_or(wal,
1391                             GEN9_CTX_PREEMPT_REG,
1392                             GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
1393
1394                 /*
1395                  * Wa_1607030317:tgl
1396                  * Wa_1607186500:tgl
1397                  * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
1398                  * of then says it is fixed on B0 the other one says it is
1399                  * permanent
1400                  */
1401                 wa_masked_en(wal,
1402                              GEN6_RC_SLEEP_PSMI_CONTROL,
1403                              GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
1404                              GEN8_RC_SEMA_IDLE_MSG_DISABLE);
1405
1406                 /*
1407                  * Wa_1606679103:tgl
1408                  * (see also Wa_1606682166:icl)
1409                  */
1410                 wa_write_or(wal,
1411                             GEN7_SARCHKMD,
1412                             GEN7_DISABLE_SAMPLER_PREFETCH);
1413
1414                 /* Wa_1407928979:tgl */
1415                 wa_write_or(wal,
1416                             GEN7_FF_THREAD_MODE,
1417                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
1418
1419                 /* Wa_1408615072:tgl */
1420                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
1421                             VSUNIT_CLKGATE_DIS_TGL);
1422         }
1423
1424         if (IS_TIGERLAKE(i915)) {
1425                 /* Wa_1606931601:tgl */
1426                 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
1427
1428                 /* Wa_1409804808:tgl */
1429                 wa_masked_en(wal, GEN7_ROW_CHICKEN2,
1430                              GEN12_PUSH_CONST_DEREF_HOLD_DIS);
1431
1432                 /* Wa_1606700617:tgl */
1433                 wa_masked_en(wal,
1434                              GEN9_CS_DEBUG_MODE1,
1435                              FF_DOP_CLOCK_GATE_DISABLE);
1436
1437                 /*
1438                  * Wa_1409085225:tgl
1439                  * Wa_14010229206:tgl
1440                  */
1441                 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
1442         }
1443
1444         if (IS_GEN(i915, 11)) {
1445                 /* This is not an Wa. Enable for better image quality */
1446                 wa_masked_en(wal,
1447                              _3D_CHICKEN3,
1448                              _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
1449
1450                 /* WaPipelineFlushCoherentLines:icl */
1451                 wa_write_or(wal,
1452                             GEN8_L3SQCREG4,
1453                             GEN8_LQSC_FLUSH_COHERENT_LINES);
1454
1455                 /*
1456                  * Wa_1405543622:icl
1457                  * Formerly known as WaGAPZPriorityScheme
1458                  */
1459                 wa_write_or(wal,
1460                             GEN8_GARBCNTL,
1461                             GEN11_ARBITRATION_PRIO_ORDER_MASK);
1462
1463                 /*
1464                  * Wa_1604223664:icl
1465                  * Formerly known as WaL3BankAddressHashing
1466                  */
1467                 wa_write_masked_or(wal,
1468                                    GEN8_GARBCNTL,
1469                                    GEN11_HASH_CTRL_EXCL_MASK,
1470                                    GEN11_HASH_CTRL_EXCL_BIT0);
1471                 wa_write_masked_or(wal,
1472                                    GEN11_GLBLINVL,
1473                                    GEN11_BANK_HASH_ADDR_EXCL_MASK,
1474                                    GEN11_BANK_HASH_ADDR_EXCL_BIT0);
1475
1476                 /*
1477                  * Wa_1405733216:icl
1478                  * Formerly known as WaDisableCleanEvicts
1479                  */
1480                 wa_write_or(wal,
1481                             GEN8_L3SQCREG4,
1482                             GEN11_LQSC_CLEAN_EVICT_DISABLE);
1483
1484                 /* WaForwardProgressSoftReset:icl */
1485                 wa_write_or(wal,
1486                             GEN10_SCRATCH_LNCF2,
1487                             PMFLUSHDONE_LNICRSDROP |
1488                             PMFLUSH_GAPL3UNBLOCK |
1489                             PMFLUSHDONE_LNEBLK);
1490
1491                 /* Wa_1406609255:icl (pre-prod) */
1492                 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
1493                         wa_write_or(wal,
1494                                     GEN7_SARCHKMD,
1495                                     GEN7_DISABLE_DEMAND_PREFETCH);
1496
1497                 /* Wa_1606682166:icl */
1498                 wa_write_or(wal,
1499                             GEN7_SARCHKMD,
1500                             GEN7_DISABLE_SAMPLER_PREFETCH);
1501
1502                 /* Wa_1409178092:icl */
1503                 wa_write_masked_or(wal,
1504                                    GEN11_SCRATCH2,
1505                                    GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
1506                                    0);
1507
1508                 /* WaEnable32PlaneMode:icl */
1509                 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
1510                              GEN11_ENABLE_32_PLANE_MODE);
1511
1512                 /*
1513                  * Wa_1408615072:icl,ehl  (vsunit)
1514                  * Wa_1407596294:icl,ehl  (hsunit)
1515                  */
1516                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1517                             VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
1518
1519                 /* Wa_1407352427:icl,ehl */
1520                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
1521                             PSDUNIT_CLKGATE_DIS);
1522
1523                 /* Wa_1406680159:icl,ehl */
1524                 wa_write_or(wal,
1525                             SUBSLICE_UNIT_LEVEL_CLKGATE,
1526                             GWUNIT_CLKGATE_DIS);
1527
1528                 /*
1529                  * Wa_1408767742:icl[a2..forever],ehl[all]
1530                  * Wa_1605460711:icl[a0..c0]
1531                  */
1532                 wa_write_or(wal,
1533                             GEN7_FF_THREAD_MODE,
1534                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
1535         }
1536
1537         if (IS_GEN_RANGE(i915, 9, 12)) {
1538                 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
1539                 wa_masked_en(wal,
1540                              GEN7_FF_SLICE_CS_CHICKEN1,
1541                              GEN9_FFSC_PERCTX_PREEMPT_CTRL);
1542         }
1543
1544         if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
1545                 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
1546                 wa_write_or(wal,
1547                             GEN8_GARBCNTL,
1548                             GEN9_GAPS_TSV_CREDIT_DISABLE);
1549         }
1550
1551         if (IS_BROXTON(i915)) {
1552                 /* WaDisablePooledEuLoadBalancingFix:bxt */
1553                 wa_masked_en(wal,
1554                              FF_SLICE_CS_CHICKEN2,
1555                              GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1556         }
1557
1558         if (IS_GEN(i915, 9)) {
1559                 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
1560                 wa_masked_en(wal,
1561                              GEN9_CSFE_CHICKEN1_RCS,
1562                              GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
1563
1564                 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
1565                 wa_write_or(wal,
1566                             BDW_SCRATCH1,
1567                             GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
1568
1569                 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
1570                 if (IS_GEN9_LP(i915))
1571                         wa_write_masked_or(wal,
1572                                            GEN8_L3SQCREG1,
1573                                            L3_PRIO_CREDITS_MASK,
1574                                            L3_GENERAL_PRIO_CREDITS(62) |
1575                                            L3_HIGH_PRIO_CREDITS(2));
1576
1577                 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
1578                 wa_write_or(wal,
1579                             GEN8_L3SQCREG4,
1580                             GEN8_LQSC_FLUSH_COHERENT_LINES);
1581         }
1582
1583         if (IS_GEN(i915, 7))
1584                 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1585                 wa_masked_en(wal,
1586                              GFX_MODE_GEN7,
1587                              GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
1588
1589         if (IS_GEN_RANGE(i915, 6, 7))
1590                 /*
1591                  * We need to disable the AsyncFlip performance optimisations in
1592                  * order to use MI_WAIT_FOR_EVENT within the CS. It should
1593                  * already be programmed to '1' on all products.
1594                  *
1595                  * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1596                  */
1597                 wa_masked_en(wal,
1598                              MI_MODE,
1599                              ASYNC_FLIP_PERF_DISABLE);
1600
1601         if (IS_GEN(i915, 6)) {
1602                 /*
1603                  * Required for the hardware to program scanline values for
1604                  * waiting
1605                  * WaEnableFlushTlbInvalidationMode:snb
1606                  */
1607                 wa_masked_en(wal,
1608                              GFX_MODE,
1609                              GFX_TLB_INVALIDATE_EXPLICIT);
1610
1611                 /*
1612                  * From the Sandybridge PRM, volume 1 part 3, page 24:
1613                  * "If this bit is set, STCunit will have LRA as replacement
1614                  *  policy. [...] This bit must be reset. LRA replacement
1615                  *  policy is not supported."
1616                  */
1617                 wa_masked_dis(wal,
1618                               CACHE_MODE_0,
1619                               CM0_STC_EVICT_DISABLE_LRA_SNB);
1620         }
1621
1622         if (IS_GEN_RANGE(i915, 4, 6))
1623                 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1624                 wa_add(wal, MI_MODE,
1625                        0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
1626                        /* XXX bit doesn't stick on Broadwater */
1627                        IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
1628 }
1629
1630 static void
1631 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1632 {
1633         struct drm_i915_private *i915 = engine->i915;
1634
1635         /* WaKBLVECSSemaphoreWaitPoll:kbl */
1636         if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
1637                 wa_write(wal,
1638                          RING_SEMA_WAIT_POLL(engine->mmio_base),
1639                          1);
1640         }
1641 }
1642
1643 static void
1644 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1645 {
1646         if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
1647                 return;
1648
1649         if (engine->class == RENDER_CLASS)
1650                 rcs_engine_wa_init(engine, wal);
1651         else
1652                 xcs_engine_wa_init(engine, wal);
1653 }
1654
1655 void intel_engine_init_workarounds(struct intel_engine_cs *engine)
1656 {
1657         struct i915_wa_list *wal = &engine->wa_list;
1658
1659         if (INTEL_GEN(engine->i915) < 4)
1660                 return;
1661
1662         wa_init_start(wal, "engine", engine->name);
1663         engine_init_workarounds(engine, wal);
1664         wa_init_finish(wal);
1665 }
1666
1667 void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
1668 {
1669         wa_list_apply(engine->uncore, &engine->wa_list);
1670 }
1671
1672 static struct i915_vma *
1673 create_scratch(struct i915_address_space *vm, int count)
1674 {
1675         struct drm_i915_gem_object *obj;
1676         struct i915_vma *vma;
1677         unsigned int size;
1678         int err;
1679
1680         size = round_up(count * sizeof(u32), PAGE_SIZE);
1681         obj = i915_gem_object_create_internal(vm->i915, size);
1682         if (IS_ERR(obj))
1683                 return ERR_CAST(obj);
1684
1685         i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1686
1687         vma = i915_vma_instance(obj, vm, NULL);
1688         if (IS_ERR(vma)) {
1689                 err = PTR_ERR(vma);
1690                 goto err_obj;
1691         }
1692
1693         err = i915_vma_pin(vma, 0, 0,
1694                            i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
1695         if (err)
1696                 goto err_obj;
1697
1698         return vma;
1699
1700 err_obj:
1701         i915_gem_object_put(obj);
1702         return ERR_PTR(err);
1703 }
1704
1705 static const struct {
1706         u32 start;
1707         u32 end;
1708 } mcr_ranges_gen8[] = {
1709         { .start = 0x5500, .end = 0x55ff },
1710         { .start = 0x7000, .end = 0x7fff },
1711         { .start = 0x9400, .end = 0x97ff },
1712         { .start = 0xb000, .end = 0xb3ff },
1713         { .start = 0xe000, .end = 0xe7ff },
1714         {},
1715 };
1716
1717 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
1718 {
1719         int i;
1720
1721         if (INTEL_GEN(i915) < 8)
1722                 return false;
1723
1724         /*
1725          * Registers in these ranges are affected by the MCR selector
1726          * which only controls CPU initiated MMIO. Routing does not
1727          * work for CS access so we cannot verify them on this path.
1728          */
1729         for (i = 0; mcr_ranges_gen8[i].start; i++)
1730                 if (offset >= mcr_ranges_gen8[i].start &&
1731                     offset <= mcr_ranges_gen8[i].end)
1732                         return true;
1733
1734         return false;
1735 }
1736
1737 static int
1738 wa_list_srm(struct i915_request *rq,
1739             const struct i915_wa_list *wal,
1740             struct i915_vma *vma)
1741 {
1742         struct drm_i915_private *i915 = rq->i915;
1743         unsigned int i, count = 0;
1744         const struct i915_wa *wa;
1745         u32 srm, *cs;
1746
1747         srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1748         if (INTEL_GEN(i915) >= 8)
1749                 srm++;
1750
1751         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1752                 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
1753                         count++;
1754         }
1755
1756         cs = intel_ring_begin(rq, 4 * count);
1757         if (IS_ERR(cs))
1758                 return PTR_ERR(cs);
1759
1760         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1761                 u32 offset = i915_mmio_reg_offset(wa->reg);
1762
1763                 if (mcr_range(i915, offset))
1764                         continue;
1765
1766                 *cs++ = srm;
1767                 *cs++ = offset;
1768                 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
1769                 *cs++ = 0;
1770         }
1771         intel_ring_advance(rq, cs);
1772
1773         return 0;
1774 }
1775
1776 static int engine_wa_list_verify(struct intel_context *ce,
1777                                  const struct i915_wa_list * const wal,
1778                                  const char *from)
1779 {
1780         const struct i915_wa *wa;
1781         struct i915_request *rq;
1782         struct i915_vma *vma;
1783         unsigned int i;
1784         u32 *results;
1785         int err;
1786
1787         if (!wal->count)
1788                 return 0;
1789
1790         vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
1791         if (IS_ERR(vma))
1792                 return PTR_ERR(vma);
1793
1794         intel_engine_pm_get(ce->engine);
1795         rq = intel_context_create_request(ce);
1796         intel_engine_pm_put(ce->engine);
1797         if (IS_ERR(rq)) {
1798                 err = PTR_ERR(rq);
1799                 goto err_vma;
1800         }
1801
1802         i915_vma_lock(vma);
1803         err = i915_request_await_object(rq, vma->obj, true);
1804         if (err == 0)
1805                 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1806         i915_vma_unlock(vma);
1807         if (err) {
1808                 i915_request_add(rq);
1809                 goto err_vma;
1810         }
1811
1812         err = wa_list_srm(rq, wal, vma);
1813         if (err)
1814                 goto err_vma;
1815
1816         i915_request_get(rq);
1817         i915_request_add(rq);
1818         if (i915_request_wait(rq, 0, HZ / 5) < 0) {
1819                 err = -ETIME;
1820                 goto err_rq;
1821         }
1822
1823         results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1824         if (IS_ERR(results)) {
1825                 err = PTR_ERR(results);
1826                 goto err_rq;
1827         }
1828
1829         err = 0;
1830         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1831                 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
1832                         continue;
1833
1834                 if (!wa_verify(wa, results[i], wal->name, from))
1835                         err = -ENXIO;
1836         }
1837
1838         i915_gem_object_unpin_map(vma->obj);
1839
1840 err_rq:
1841         i915_request_put(rq);
1842 err_vma:
1843         i915_vma_unpin(vma);
1844         i915_vma_put(vma);
1845         return err;
1846 }
1847
1848 int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
1849                                     const char *from)
1850 {
1851         return engine_wa_list_verify(engine->kernel_context,
1852                                      &engine->wa_list,
1853                                      from);
1854 }
1855
1856 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1857 #include "selftest_workarounds.c"
1858 #endif