drivers/gpu/drm/i915/gt/intel_workarounds.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2014-2018 Intel Corporation
   5  */
   6
   7 #include "i915_drv.h"
   8 #include "intel_context.h"
   9 #include "intel_engine_pm.h"
  10 #include "intel_gt.h"
  11 #include "intel_ring.h"
  12 #include "intel_workarounds.h"
  13
  14 /**
  15  * DOC: Hardware workarounds
  16  *
  17  * This file is intended as a central place to implement most [1]_ of the
  18  * required workarounds for hardware to work as originally intended. They fall
  19  * in five basic categories depending on how/when they are applied:
  20  *
  21  * - Workarounds that touch registers that are saved/restored to/from the HW
  22  *   context image. The list is emitted (via Load Register Immediate commands)
  23  *   everytime a new context is created.
  24  * - GT workarounds. The list of these WAs is applied whenever these registers
  25  *   revert to default values (on GPU reset, suspend/resume [2]_, etc..).
  26  * - Display workarounds. The list is applied during display clock-gating
  27  *   initialization.
  28  * - Workarounds that whitelist a privileged register, so that UMDs can manage
  29  *   them directly. This is just a special case of a MMMIO workaround (as we
  30  *   write the list of these to/be-whitelisted registers to some special HW
  31  *   registers).
  32  * - Workaround batchbuffers, that get executed automatically by the hardware
  33  *   on every HW context restore.
  34  *
  35  * .. [1] Please notice that there are other WAs that, due to their nature,
  36  *    cannot be applied from a central place. Those are peppered around the rest
  37  *    of the code, as needed.
  38  *
  39  * .. [2] Technically, some registers are powercontext saved & restored, so they
  40  *    survive a suspend/resume. In practice, writing them again is not too
  41  *    costly and simplifies things. We can revisit this in the future.
  42  *
  43  * Layout
  44  * ~~~~~~
  45  *
  46  * Keep things in this file ordered by WA type, as per the above (context, GT,
  47  * display, register whitelist, batchbuffer). Then, inside each type, keep the
  48  * following order:
  49  *
  50  * - Infrastructure functions and macros
  51  * - WAs per platform in standard gen/chrono order
  52  * - Public functions to init or apply the given workaround type.
  53  */
  54
  55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
  56 {
  57         wal->name = name;
  58         wal->engine_name = engine_name;
  59 }
  60
  61 #define WA_LIST_CHUNK (1 << 4)
  62
  63 static void wa_init_finish(struct i915_wa_list *wal)
  64 {
  65         /* Trim unused entries. */
  66         if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) {
  67                 struct i915_wa *list = kmemdup(wal->list,
  68                                                wal->count * sizeof(*list),
  69                                                GFP_KERNEL);
  70
  71                 if (list) {
  72                         kfree(wal->list);
  73                         wal->list = list;
  74                 }
  75         }
  76
  77         if (!wal->count)
  78                 return;
  79
  80         DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n",
  81                          wal->wa_count, wal->name, wal->engine_name);
  82 }
  83
  84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
  85 {
  86         unsigned int addr = i915_mmio_reg_offset(wa->reg);
  87         unsigned int start = 0, end = wal->count;
  88         const unsigned int grow = WA_LIST_CHUNK;
  89         struct i915_wa *wa_;
  90
  91         GEM_BUG_ON(!is_power_of_2(grow));
  92
  93         if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
  94                 struct i915_wa *list;
  95
  96                 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
  97                                      GFP_KERNEL);
  98                 if (!list) {
  99                         DRM_ERROR("No space for workaround init!\n");
 100                         return;
 101                 }
 102
 103                 if (wal->list)
 104                         memcpy(list, wal->list, sizeof(*wa) * wal->count);
 105
 106                 wal->list = list;
 107         }
 108
 109         while (start < end) {
 110                 unsigned int mid = start + (end - start) / 2;
 111
 112                 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
 113                         start = mid + 1;
 114                 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
 115                         end = mid;
 116                 } else {
 117                         wa_ = &wal->list[mid];
 118
 119                         if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
 120                                 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",
 121                                           i915_mmio_reg_offset(wa_->reg),
 122                                           wa_->clr, wa_->set);
 123
 124                                 wa_->set &= ~wa->clr;
 125                         }
 126
 127                         wal->wa_count++;
 128                         wa_->set |= wa->set;
 129                         wa_->clr |= wa->clr;
 130                         wa_->read |= wa->read;
 131                         return;
 132                 }
 133         }
 134
 135         wal->wa_count++;
 136         wa_ = &wal->list[wal->count++];
 137         *wa_ = *wa;
 138
 139         while (wa_-- > wal->list) {
 140                 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
 141                            i915_mmio_reg_offset(wa_[1].reg));
 142                 if (i915_mmio_reg_offset(wa_[1].reg) >
 143                     i915_mmio_reg_offset(wa_[0].reg))
 144                         break;
 145
 146                 swap(wa_[1], wa_[0]);
 147         }
 148 }
 149
 150 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
 151                    u32 clear, u32 set, u32 read_mask)
 152 {
 153         struct i915_wa wa = {
 154                 .reg  = reg,
 155                 .clr  = clear,
 156                 .set  = set,
 157                 .read = read_mask,
 158         };
 159
 160         _wa_add(wal, &wa);
 161 }
 162
 163 static void
 164 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
 165 {
 166         wa_add(wal, reg, clear, set, clear);
 167 }
 168
 169 static void
 170 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 171 {
 172         wa_write_masked_or(wal, reg, ~0, set);
 173 }
 174
 175 static void
 176 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 177 {
 178         wa_write_masked_or(wal, reg, set, set);
 179 }
 180
 181 static void
 182 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 183 {
 184         wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
 185 }
 186
 187 static void
 188 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 189 {
 190         wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
 191 }
 192
 193 #define WA_SET_BIT_MASKED(addr, mask) \
 194         wa_masked_en(wal, (addr), (mask))
 195
 196 #define WA_CLR_BIT_MASKED(addr, mask) \
 197         wa_masked_dis(wal, (addr), (mask))
 198
 199 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 200         wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value)))
 201
 202 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
 203                                       struct i915_wa_list *wal)
 204 {
 205         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 206
 207         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 208         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 209
 210         /* WaDisablePartialInstShootdown:bdw,chv */
 211         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 212                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 213
 214         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 215          * workaround for for a possible hang in the unlikely event a TLB
 216          * invalidation occurs during a PSD flush.
 217          */
 218         /* WaForceEnableNonCoherent:bdw,chv */
 219         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 220         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 221                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 222                           HDC_FORCE_NON_COHERENT);
 223
 224         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 225          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 226          *  polygons in the same 8x4 pixel/sample area to be processed without
 227          *  stalling waiting for the earlier ones to write to Hierarchical Z
 228          *  buffer."
 229          *
 230          * This optimization is off by default for BDW and CHV; turn it on.
 231          */
 232         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 233
 234         /* Wa4x4STCOptimizationDisable:bdw,chv */
 235         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 236
 237         /*
 238          * BSpec recommends 8x4 when MSAA is used,
 239          * however in practice 16x4 seems fastest.
 240          *
 241          * Note that PS/WM thread counts depend on the WIZ hashing
 242          * disable bit, which we don't touch here, but it's good
 243          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 244          */
 245         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 246                             GEN6_WIZ_HASHING_MASK,
 247                             GEN6_WIZ_HASHING_16x4);
 248 }
 249
 250 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
 251                                      struct i915_wa_list *wal)
 252 {
 253         struct drm_i915_private *i915 = engine->i915;
 254
 255         gen8_ctx_workarounds_init(engine, wal);
 256
 257         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 258         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 259
 260         /* WaDisableDopClockGating:bdw
 261          *
 262          * Also see the related UCGTCL1 write in bdw_init_clock_gating()
 263          * to disable EUTC clock gating.
 264          */
 265         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 266                           DOP_CLOCK_GATING_DISABLE);
 267
 268         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 269                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 270
 271         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 272                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 273                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 274                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 275                           (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 276 }
 277
 278 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
 279                                      struct i915_wa_list *wal)
 280 {
 281         gen8_ctx_workarounds_init(engine, wal);
 282
 283         /* WaDisableThreadStallDopClockGating:chv */
 284         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 285
 286         /* Improve HiZ throughput on CHV. */
 287         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 288 }
 289
 290 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
 291                                       struct i915_wa_list *wal)
 292 {
 293         struct drm_i915_private *i915 = engine->i915;
 294
 295         if (HAS_LLC(i915)) {
 296                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
 297                  *
 298                  * Must match Display Engine. See
 299                  * WaCompressedResourceDisplayNewHashMode.
 300                  */
 301                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 302                                   GEN9_PBE_COMPRESSED_HASH_SELECTION);
 303                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 304                                   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
 305         }
 306
 307         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
 308         /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
 309         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 310                           FLOW_CONTROL_ENABLE |
 311                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 312
 313         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
 314         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
 315         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 316                           GEN9_ENABLE_YV12_BUGFIX |
 317                           GEN9_ENABLE_GPGPU_PREEMPTION);
 318
 319         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
 320         /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
 321         WA_SET_BIT_MASKED(CACHE_MODE_1,
 322                           GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 323                           GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 324
 325         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
 326         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 327                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 328
 329         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
 330         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 331                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 332                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 333
 334         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 335          * both tied to WaForceContextSaveRestoreNonCoherent
 336          * in some hsds for skl. We keep the tie for all gen9. The
 337          * documentation is a bit hazy and so we want to get common behaviour,
 338          * even though there is no clear evidence we would need both on kbl/bxt.
 339          * This area has been source of system hangs so we play it safe
 340          * and mimic the skl regardless of what bspec says.
 341          *
 342          * Use Force Non-Coherent whenever executing a 3D context. This
 343          * is a workaround for a possible hang in the unlikely event
 344          * a TLB invalidation occurs during a PSD flush.
 345          */
 346
 347         /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
 348         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 349                           HDC_FORCE_NON_COHERENT);
 350
 351         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
 352         if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915))
 353                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 354                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 355
 356         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
 357         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 358
 359         /*
 360          * Supporting preemption with fine-granularity requires changes in the
 361          * batch buffer programming. Since we can't break old userspace, we
 362          * need to set our default preemption level to safe value. Userspace is
 363          * still able to use more fine-grained preemption levels, since in
 364          * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
 365          * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
 366          * not real HW workarounds, but merely a way to start using preemption
 367          * while maintaining old contract with userspace.
 368          */
 369
 370         /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
 371         WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
 372
 373         /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
 374         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 375                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 376                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 377
 378         /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
 379         if (IS_GEN9_LP(i915))
 380                 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
 381 }
 382
 383 static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
 384                                 struct i915_wa_list *wal)
 385 {
 386         struct drm_i915_private *i915 = engine->i915;
 387         u8 vals[3] = { 0, 0, 0 };
 388         unsigned int i;
 389
 390         for (i = 0; i < 3; i++) {
 391                 u8 ss;
 392
 393                 /*
 394                  * Only consider slices where one, and only one, subslice has 7
 395                  * EUs
 396                  */
 397                 if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]))
 398                         continue;
 399
 400                 /*
 401                  * subslice_7eu[i] != 0 (because of the check above) and
 402                  * ss_max == 4 (maximum number of subslices possible per slice)
 403                  *
 404                  * ->    0 <= ss <= 3;
 405                  */
 406                 ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1;
 407                 vals[i] = 3 - ss;
 408         }
 409
 410         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
 411                 return;
 412
 413         /* Tune IZ hashing. See intel_device_info_runtime_init() */
 414         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 415                             GEN9_IZ_HASHING_MASK(2) |
 416                             GEN9_IZ_HASHING_MASK(1) |
 417                             GEN9_IZ_HASHING_MASK(0),
 418                             GEN9_IZ_HASHING(2, vals[2]) |
 419                             GEN9_IZ_HASHING(1, vals[1]) |
 420                             GEN9_IZ_HASHING(0, vals[0]));
 421 }
 422
 423 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
 424                                      struct i915_wa_list *wal)
 425 {
 426         gen9_ctx_workarounds_init(engine, wal);
 427         skl_tune_iz_hashing(engine, wal);
 428 }
 429
 430 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
 431                                      struct i915_wa_list *wal)
 432 {
 433         gen9_ctx_workarounds_init(engine, wal);
 434
 435         /* WaDisableThreadStallDopClockGating:bxt */
 436         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 437                           STALL_DOP_GATING_DISABLE);
 438
 439         /* WaToEnableHwFixForPushConstHWBug:bxt */
 440         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 441                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 442 }
 443
 444 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
 445                                      struct i915_wa_list *wal)
 446 {
 447         struct drm_i915_private *i915 = engine->i915;
 448
 449         gen9_ctx_workarounds_init(engine, wal);
 450
 451         /* WaToEnableHwFixForPushConstHWBug:kbl */
 452         if (IS_KBL_REVID(i915, KBL_REVID_C0, REVID_FOREVER))
 453                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 454                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 455
 456         /* WaDisableSbeCacheDispatchPortSharing:kbl */
 457         WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 458                           GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 459 }
 460
 461 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
 462                                      struct i915_wa_list *wal)
 463 {
 464         gen9_ctx_workarounds_init(engine, wal);
 465
 466         /* WaToEnableHwFixForPushConstHWBug:glk */
 467         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 468                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 469 }
 470
 471 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
 472                                      struct i915_wa_list *wal)
 473 {
 474         gen9_ctx_workarounds_init(engine, wal);
 475
 476         /* WaToEnableHwFixForPushConstHWBug:cfl */
 477         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 478                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 479
 480         /* WaDisableSbeCacheDispatchPortSharing:cfl */
 481         WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 482                           GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 483 }
 484
 485 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
 486                                      struct i915_wa_list *wal)
 487 {
 488         struct drm_i915_private *i915 = engine->i915;
 489
 490         /* WaForceContextSaveRestoreNonCoherent:cnl */
 491         WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
 492                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
 493
 494         /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
 495         if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0))
 496                 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
 497
 498         /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
 499         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 500                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 501
 502         /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
 503         if (IS_CNL_REVID(i915, 0, CNL_REVID_B0))
 504                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 505                                   GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
 506
 507         /* WaPushConstantDereferenceHoldDisable:cnl */
 508         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
 509
 510         /* FtrEnableFastAnisoL1BankingFix:cnl */
 511         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
 512
 513         /* WaDisable3DMidCmdPreemption:cnl */
 514         WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
 515
 516         /* WaDisableGPGPUMidCmdPreemption:cnl */
 517         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 518                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 519                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 520
 521         /* WaDisableEarlyEOT:cnl */
 522         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
 523 }
 524
 525 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 526                                      struct i915_wa_list *wal)
 527 {
 528         struct drm_i915_private *i915 = engine->i915;
 529
 530         /* WaDisableBankHangMode:icl */
 531         wa_write(wal,
 532                  GEN8_L3CNTLREG,
 533                  intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
 534                  GEN8_ERRDETBCTRL);
 535
 536         /* Wa_1604370585:icl (pre-prod)
 537          * Formerly known as WaPushConstantDereferenceHoldDisable
 538          */
 539         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
 540                 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 541                                   PUSH_CONSTANT_DEREF_DISABLE);
 542
 543         /* WaForceEnableNonCoherent:icl
 544          * This is not the same workaround as in early Gen9 platforms, where
 545          * lacking this could cause system hangs, but coherency performance
 546          * overhead is high and only a few compute workloads really need it
 547          * (the register is whitelisted in hardware now, so UMDs can opt in
 548          * for coherency if they have a good reason).
 549          */
 550         WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
 551
 552         /* Wa_2006611047:icl (pre-prod)
 553          * Formerly known as WaDisableImprovedTdlClkGating
 554          */
 555         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
 556                 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 557                                   GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 558
 559         /* Wa_2006665173:icl (pre-prod) */
 560         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
 561                 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 562                                   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 563
 564         /* WaEnableFloatBlendOptimization:icl */
 565         wa_write_masked_or(wal,
 566                            GEN10_CACHE_MODE_SS,
 567                            0, /* write-only, so skip validation */
 568                            _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
 569
 570         /* WaDisableGPGPUMidThreadPreemption:icl */
 571         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
 572                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 573                             GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 574
 575         /* allow headerless messages for preemptible GPGPU context */
 576         WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
 577                           GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
 578 }
 579
 580 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 581                                      struct i915_wa_list *wal)
 582 {
 583         /* Wa_1409142259:tgl */
 584         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 585                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 586
 587         /*
 588          * Wa_1604555607:gen12 and Wa_1608008084:gen12
 589          * FF_MODE2 register will return the wrong value when read. The default
 590          * value for this register is zero for all fields and there are no bit
 591          * masks. So instead of doing a RMW we should just write the TDS timer
 592          * value for Wa_1604555607.
 593          */
 594         wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
 595                FF_MODE2_TDS_TIMER_128, 0);
 596 }
 597
 598 static void
 599 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 600                            struct i915_wa_list *wal,
 601                            const char *name)
 602 {
 603         struct drm_i915_private *i915 = engine->i915;
 604
 605         if (engine->class != RENDER_CLASS)
 606                 return;
 607
 608         wa_init_start(wal, name, engine->name);
 609
 610         if (IS_GEN(i915, 12))
 611                 tgl_ctx_workarounds_init(engine, wal);
 612         else if (IS_GEN(i915, 11))
 613                 icl_ctx_workarounds_init(engine, wal);
 614         else if (IS_CANNONLAKE(i915))
 615                 cnl_ctx_workarounds_init(engine, wal);
 616         else if (IS_COFFEELAKE(i915))
 617                 cfl_ctx_workarounds_init(engine, wal);
 618         else if (IS_GEMINILAKE(i915))
 619                 glk_ctx_workarounds_init(engine, wal);
 620         else if (IS_KABYLAKE(i915))
 621                 kbl_ctx_workarounds_init(engine, wal);
 622         else if (IS_BROXTON(i915))
 623                 bxt_ctx_workarounds_init(engine, wal);
 624         else if (IS_SKYLAKE(i915))
 625                 skl_ctx_workarounds_init(engine, wal);
 626         else if (IS_CHERRYVIEW(i915))
 627                 chv_ctx_workarounds_init(engine, wal);
 628         else if (IS_BROADWELL(i915))
 629                 bdw_ctx_workarounds_init(engine, wal);
 630         else if (INTEL_GEN(i915) < 8)
 631                 return;
 632         else
 633                 MISSING_CASE(INTEL_GEN(i915));
 634
 635         wa_init_finish(wal);
 636 }
 637
 638 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
 639 {
 640         __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
 641 }
 642
 643 int intel_engine_emit_ctx_wa(struct i915_request *rq)
 644 {
 645         struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
 646         struct i915_wa *wa;
 647         unsigned int i;
 648         u32 *cs;
 649         int ret;
 650
 651         if (wal->count == 0)
 652                 return 0;
 653
 654         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
 655         if (ret)
 656                 return ret;
 657
 658         cs = intel_ring_begin(rq, (wal->count * 2 + 2));
 659         if (IS_ERR(cs))
 660                 return PTR_ERR(cs);
 661
 662         *cs++ = MI_LOAD_REGISTER_IMM(wal->count);
 663         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
 664                 *cs++ = i915_mmio_reg_offset(wa->reg);
 665                 *cs++ = wa->set;
 666         }
 667         *cs++ = MI_NOOP;
 668
 669         intel_ring_advance(rq, cs);
 670
 671         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
 672         if (ret)
 673                 return ret;
 674
 675         return 0;
 676 }
 677
 678 static void
 679 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 680 {
 681         /* WaDisableKillLogic:bxt,skl,kbl */
 682         if (!IS_COFFEELAKE(i915))
 683                 wa_write_or(wal,
 684                             GAM_ECOCHK,
 685                             ECOCHK_DIS_TLB);
 686
 687         if (HAS_LLC(i915)) {
 688                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
 689                  *
 690                  * Must match Display Engine. See
 691                  * WaCompressedResourceDisplayNewHashMode.
 692                  */
 693                 wa_write_or(wal,
 694                             MMCD_MISC_CTRL,
 695                             MMCD_PCLA | MMCD_HOTSPOT_EN);
 696         }
 697
 698         /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
 699         wa_write_or(wal,
 700                     GAM_ECOCHK,
 701                     BDW_DISABLE_HDC_INVALIDATION);
 702 }
 703
 704 static void
 705 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 706 {
 707         gen9_gt_workarounds_init(i915, wal);
 708
 709         /* WaDisableGafsUnitClkGating:skl */
 710         wa_write_or(wal,
 711                     GEN7_UCGCTL4,
 712                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 713
 714         /* WaInPlaceDecompressionHang:skl */
 715         if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
 716                 wa_write_or(wal,
 717                             GEN9_GAMT_ECO_REG_RW_IA,
 718                             GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 719 }
 720
 721 static void
 722 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 723 {
 724         gen9_gt_workarounds_init(i915, wal);
 725
 726         /* WaInPlaceDecompressionHang:bxt */
 727         wa_write_or(wal,
 728                     GEN9_GAMT_ECO_REG_RW_IA,
 729                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 730 }
 731
 732 static void
 733 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 734 {
 735         gen9_gt_workarounds_init(i915, wal);
 736
 737         /* WaDisableDynamicCreditSharing:kbl */
 738         if (IS_KBL_REVID(i915, 0, KBL_REVID_B0))
 739                 wa_write_or(wal,
 740                             GAMT_CHKN_BIT_REG,
 741                             GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
 742
 743         /* WaDisableGafsUnitClkGating:kbl */
 744         wa_write_or(wal,
 745                     GEN7_UCGCTL4,
 746                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 747
 748         /* WaInPlaceDecompressionHang:kbl */
 749         wa_write_or(wal,
 750                     GEN9_GAMT_ECO_REG_RW_IA,
 751                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 752 }
 753
 754 static void
 755 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 756 {
 757         gen9_gt_workarounds_init(i915, wal);
 758 }
 759
 760 static void
 761 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 762 {
 763         gen9_gt_workarounds_init(i915, wal);
 764
 765         /* WaDisableGafsUnitClkGating:cfl */
 766         wa_write_or(wal,
 767                     GEN7_UCGCTL4,
 768                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 769
 770         /* WaInPlaceDecompressionHang:cfl */
 771         wa_write_or(wal,
 772                     GEN9_GAMT_ECO_REG_RW_IA,
 773                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 774 }
 775
 776 static void
 777 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 778 {
 779         const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
 780         unsigned int slice, subslice;
 781         u32 l3_en, mcr, mcr_mask;
 782
 783         GEM_BUG_ON(INTEL_GEN(i915) < 10);
 784
 785         /*
 786          * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
 787          * L3Banks could be fused off in single slice scenario. If that is
 788          * the case, we might need to program MCR select to a valid L3Bank
 789          * by default, to make sure we correctly read certain registers
 790          * later on (in the range 0xB100 - 0xB3FF).
 791          *
 792          * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
 793          * Before any MMIO read into slice/subslice specific registers, MCR
 794          * packet control register needs to be programmed to point to any
 795          * enabled s/ss pair. Otherwise, incorrect values will be returned.
 796          * This means each subsequent MMIO read will be forwarded to an
 797          * specific s/ss combination, but this is OK since these registers
 798          * are consistent across s/ss in almost all cases. In the rare
 799          * occasions, such as INSTDONE, where this value is dependent
 800          * on s/ss combo, the read should be done with read_subslice_reg.
 801          *
 802          * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both
 803          * to which subslice, or to which L3 bank, the respective mmio reads
 804          * will go, we have to find a common index which works for both
 805          * accesses.
 806          *
 807          * Case where we cannot find a common index fortunately should not
 808          * happen in production hardware, so we only emit a warning instead of
 809          * implementing something more complex that requires checking the range
 810          * of every MMIO read.
 811          */
 812
 813         if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
 814                 u32 l3_fuse =
 815                         intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
 816                         GEN10_L3BANK_MASK;
 817
 818                 DRM_DEBUG_DRIVER("L3 fuse = %x\n", l3_fuse);
 819                 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse);
 820         } else {
 821                 l3_en = ~0;
 822         }
 823
 824         slice = fls(sseu->slice_mask) - 1;
 825         subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
 826         if (!subslice) {
 827                 DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
 828                          intel_sseu_get_subslices(sseu, slice), l3_en);
 829                 subslice = fls(l3_en);
 830                 drm_WARN_ON(&i915->drm, !subslice);
 831         }
 832         subslice--;
 833
 834         if (INTEL_GEN(i915) >= 11) {
 835                 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
 836                 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
 837         } else {
 838                 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
 839                 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
 840         }
 841
 842         DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr);
 843
 844         wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
 845 }
 846
 847 static void
 848 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 849 {
 850         wa_init_mcr(i915, wal);
 851
 852         /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
 853         if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0))
 854                 wa_write_or(wal,
 855                             GAMT_CHKN_BIT_REG,
 856                             GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
 857
 858         /* WaInPlaceDecompressionHang:cnl */
 859         wa_write_or(wal,
 860                     GEN9_GAMT_ECO_REG_RW_IA,
 861                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 862 }
 863
 864 static void
 865 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 866 {
 867         wa_init_mcr(i915, wal);
 868
 869         /* WaInPlaceDecompressionHang:icl */
 870         wa_write_or(wal,
 871                     GEN9_GAMT_ECO_REG_RW_IA,
 872                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 873
 874         /* WaModifyGamTlbPartitioning:icl */
 875         wa_write_masked_or(wal,
 876                            GEN11_GACB_PERF_CTRL,
 877                            GEN11_HASH_CTRL_MASK,
 878                            GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
 879
 880         /* Wa_1405766107:icl
 881          * Formerly known as WaCL2SFHalfMaxAlloc
 882          */
 883         wa_write_or(wal,
 884                     GEN11_LSN_UNSLCVC,
 885                     GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
 886                     GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
 887
 888         /* Wa_220166154:icl
 889          * Formerly known as WaDisCtxReload
 890          */
 891         wa_write_or(wal,
 892                     GEN8_GAMW_ECO_DEV_RW_IA,
 893                     GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
 894
 895         /* Wa_1405779004:icl (pre-prod) */
 896         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
 897                 wa_write_or(wal,
 898                             SLICE_UNIT_LEVEL_CLKGATE,
 899                             MSCUNIT_CLKGATE_DIS);
 900
 901         /* Wa_1406680159:icl */
 902         wa_write_or(wal,
 903                     SUBSLICE_UNIT_LEVEL_CLKGATE,
 904                     GWUNIT_CLKGATE_DIS);
 905
 906         /* Wa_1406838659:icl (pre-prod) */
 907         if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
 908                 wa_write_or(wal,
 909                             INF_UNIT_LEVEL_CLKGATE,
 910                             CGPSF_CLKGATE_DIS);
 911
 912         /* Wa_1406463099:icl
 913          * Formerly known as WaGamTlbPendError
 914          */
 915         wa_write_or(wal,
 916                     GAMT_CHKN_BIT_REG,
 917                     GAMT_CHKN_DISABLE_L3_COH_PIPE);
 918
 919         /* Wa_1607087056:icl */
 920         wa_write_or(wal,
 921                     SLICE_UNIT_LEVEL_CLKGATE,
 922                     L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 923 }
 924
 925 static void
 926 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 927 {
 928         /* Wa_1409420604:tgl */
 929         if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
 930                 wa_write_or(wal,
 931                             SUBSLICE_UNIT_LEVEL_CLKGATE2,
 932                             CPSSUNIT_CLKGATE_DIS);
 933
 934         /* Wa_1409180338:tgl */
 935         if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
 936                 wa_write_or(wal,
 937                             SLICE_UNIT_LEVEL_CLKGATE,
 938                             L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 939 }
 940
 941 static void
 942 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 943 {
 944         if (IS_GEN(i915, 12))
 945                 tgl_gt_workarounds_init(i915, wal);
 946         else if (IS_GEN(i915, 11))
 947                 icl_gt_workarounds_init(i915, wal);
 948         else if (IS_CANNONLAKE(i915))
 949                 cnl_gt_workarounds_init(i915, wal);
 950         else if (IS_COFFEELAKE(i915))
 951                 cfl_gt_workarounds_init(i915, wal);
 952         else if (IS_GEMINILAKE(i915))
 953                 glk_gt_workarounds_init(i915, wal);
 954         else if (IS_KABYLAKE(i915))
 955                 kbl_gt_workarounds_init(i915, wal);
 956         else if (IS_BROXTON(i915))
 957                 bxt_gt_workarounds_init(i915, wal);
 958         else if (IS_SKYLAKE(i915))
 959                 skl_gt_workarounds_init(i915, wal);
 960         else if (INTEL_GEN(i915) <= 8)
 961                 return;
 962         else
 963                 MISSING_CASE(INTEL_GEN(i915));
 964 }
 965
 966 void intel_gt_init_workarounds(struct drm_i915_private *i915)
 967 {
 968         struct i915_wa_list *wal = &i915->gt_wa_list;
 969
 970         wa_init_start(wal, "GT", "global");
 971         gt_init_workarounds(i915, wal);
 972         wa_init_finish(wal);
 973 }
 974
 975 static enum forcewake_domains
 976 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
 977 {
 978         enum forcewake_domains fw = 0;
 979         struct i915_wa *wa;
 980         unsigned int i;
 981
 982         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
 983                 fw |= intel_uncore_forcewake_for_reg(uncore,
 984                                                      wa->reg,
 985                                                      FW_REG_READ |
 986                                                      FW_REG_WRITE);
 987
 988         return fw;
 989 }
 990
 991 static bool
 992 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
 993 {
 994         if ((cur ^ wa->set) & wa->read) {
 995                 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n",
 996                           name, from, i915_mmio_reg_offset(wa->reg),
 997                           cur, cur & wa->read, wa->set);
 998
 999                 return false;
1000         }
1001
1002         return true;
1003 }
1004
1005 static void
1006 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
1007 {
1008         enum forcewake_domains fw;
1009         unsigned long flags;
1010         struct i915_wa *wa;
1011         unsigned int i;
1012
1013         if (!wal->count)
1014                 return;
1015
1016         fw = wal_get_fw_for_rmw(uncore, wal);
1017
1018         spin_lock_irqsave(&uncore->lock, flags);
1019         intel_uncore_forcewake_get__locked(uncore, fw);
1020
1021         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1022                 if (wa->clr)
1023                         intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set);
1024                 else
1025                         intel_uncore_write_fw(uncore, wa->reg, wa->set);
1026                 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1027                         wa_verify(wa,
1028                                   intel_uncore_read_fw(uncore, wa->reg),
1029                                   wal->name, "application");
1030         }
1031
1032         intel_uncore_forcewake_put__locked(uncore, fw);
1033         spin_unlock_irqrestore(&uncore->lock, flags);
1034 }
1035
1036 void intel_gt_apply_workarounds(struct intel_gt *gt)
1037 {
1038         wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
1039 }
1040
1041 static bool wa_list_verify(struct intel_uncore *uncore,
1042                            const struct i915_wa_list *wal,
1043                            const char *from)
1044 {
1045         struct i915_wa *wa;
1046         unsigned int i;
1047         bool ok = true;
1048
1049         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1050                 ok &= wa_verify(wa,
1051                                 intel_uncore_read(uncore, wa->reg),
1052                                 wal->name, from);
1053
1054         return ok;
1055 }
1056
1057 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
1058 {
1059         return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
1060 }
1061
1062 static inline bool is_nonpriv_flags_valid(u32 flags)
1063 {
1064         /* Check only valid flag bits are set */
1065         if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
1066                 return false;
1067
1068         /* NB: Only 3 out of 4 enum values are valid for access field */
1069         if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
1070             RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
1071                 return false;
1072
1073         return true;
1074 }
1075
1076 static void
1077 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1078 {
1079         struct i915_wa wa = {
1080                 .reg = reg
1081         };
1082
1083         if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1084                 return;
1085
1086         if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1087                 return;
1088
1089         wa.reg.reg |= flags;
1090         _wa_add(wal, &wa);
1091 }
1092
1093 static void
1094 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1095 {
1096         whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1097 }
1098
1099 static void gen9_whitelist_build(struct i915_wa_list *w)
1100 {
1101         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1102         whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
1103
1104         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1105         whitelist_reg(w, GEN8_CS_CHICKEN1);
1106
1107         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1108         whitelist_reg(w, GEN8_HDC_CHICKEN1);
1109
1110         /* WaSendPushConstantsFromMMIO:skl,bxt */
1111         whitelist_reg(w, COMMON_SLICE_CHICKEN2);
1112 }
1113
1114 static void skl_whitelist_build(struct intel_engine_cs *engine)
1115 {
1116         struct i915_wa_list *w = &engine->whitelist;
1117
1118         if (engine->class != RENDER_CLASS)
1119                 return;
1120
1121         gen9_whitelist_build(w);
1122
1123         /* WaDisableLSQCROPERFforOCL:skl */
1124         whitelist_reg(w, GEN8_L3SQCREG4);
1125 }
1126
1127 static void bxt_whitelist_build(struct intel_engine_cs *engine)
1128 {
1129         if (engine->class != RENDER_CLASS)
1130                 return;
1131
1132         gen9_whitelist_build(&engine->whitelist);
1133 }
1134
1135 static void kbl_whitelist_build(struct intel_engine_cs *engine)
1136 {
1137         struct i915_wa_list *w = &engine->whitelist;
1138
1139         if (engine->class != RENDER_CLASS)
1140                 return;
1141
1142         gen9_whitelist_build(w);
1143
1144         /* WaDisableLSQCROPERFforOCL:kbl */
1145         whitelist_reg(w, GEN8_L3SQCREG4);
1146 }
1147
1148 static void glk_whitelist_build(struct intel_engine_cs *engine)
1149 {
1150         struct i915_wa_list *w = &engine->whitelist;
1151
1152         if (engine->class != RENDER_CLASS)
1153                 return;
1154
1155         gen9_whitelist_build(w);
1156
1157         /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
1158         whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1159 }
1160
1161 static void cfl_whitelist_build(struct intel_engine_cs *engine)
1162 {
1163         struct i915_wa_list *w = &engine->whitelist;
1164
1165         if (engine->class != RENDER_CLASS)
1166                 return;
1167
1168         gen9_whitelist_build(w);
1169
1170         /*
1171          * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
1172          *
1173          * This covers 4 register which are next to one another :
1174          *   - PS_INVOCATION_COUNT
1175          *   - PS_INVOCATION_COUNT_UDW
1176          *   - PS_DEPTH_COUNT
1177          *   - PS_DEPTH_COUNT_UDW
1178          */
1179         whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1180                           RING_FORCE_TO_NONPRIV_ACCESS_RD |
1181                           RING_FORCE_TO_NONPRIV_RANGE_4);
1182 }
1183
1184 static void cnl_whitelist_build(struct intel_engine_cs *engine)
1185 {
1186         struct i915_wa_list *w = &engine->whitelist;
1187
1188         if (engine->class != RENDER_CLASS)
1189                 return;
1190
1191         /* WaEnablePreemptionGranularityControlByUMD:cnl */
1192         whitelist_reg(w, GEN8_CS_CHICKEN1);
1193 }
1194
1195 static void icl_whitelist_build(struct intel_engine_cs *engine)
1196 {
1197         struct i915_wa_list *w = &engine->whitelist;
1198
1199         switch (engine->class) {
1200         case RENDER_CLASS:
1201                 /* WaAllowUMDToModifyHalfSliceChicken7:icl */
1202                 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
1203
1204                 /* WaAllowUMDToModifySamplerMode:icl */
1205                 whitelist_reg(w, GEN10_SAMPLER_MODE);
1206
1207                 /* WaEnableStateCacheRedirectToCS:icl */
1208                 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1209
1210                 /*
1211                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
1212                  *
1213                  * This covers 4 register which are next to one another :
1214                  *   - PS_INVOCATION_COUNT
1215                  *   - PS_INVOCATION_COUNT_UDW
1216                  *   - PS_DEPTH_COUNT
1217                  *   - PS_DEPTH_COUNT_UDW
1218                  */
1219                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1220                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
1221                                   RING_FORCE_TO_NONPRIV_RANGE_4);
1222                 break;
1223
1224         case VIDEO_DECODE_CLASS:
1225                 /* hucStatusRegOffset */
1226                 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
1227                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
1228                 /* hucUKernelHdrInfoRegOffset */
1229                 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
1230                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
1231                 /* hucStatus2RegOffset */
1232                 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
1233                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
1234                 break;
1235
1236         default:
1237                 break;
1238         }
1239 }
1240
1241 static void tgl_whitelist_build(struct intel_engine_cs *engine)
1242 {
1243         struct i915_wa_list *w = &engine->whitelist;
1244
1245         switch (engine->class) {
1246         case RENDER_CLASS:
1247                 /*
1248                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
1249                  *
1250                  * This covers 4 registers which are next to one another :
1251                  *   - PS_INVOCATION_COUNT
1252                  *   - PS_INVOCATION_COUNT_UDW
1253                  *   - PS_DEPTH_COUNT
1254                  *   - PS_DEPTH_COUNT_UDW
1255                  */
1256                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1257                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
1258                                   RING_FORCE_TO_NONPRIV_RANGE_4);
1259
1260                 /* Wa_1808121037:tgl */
1261                 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
1262
1263                 /* Wa_1806527549:tgl */
1264                 whitelist_reg(w, HIZ_CHICKEN);
1265                 break;
1266         default:
1267                 break;
1268         }
1269 }
1270
1271 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
1272 {
1273         struct drm_i915_private *i915 = engine->i915;
1274         struct i915_wa_list *w = &engine->whitelist;
1275
1276         wa_init_start(w, "whitelist", engine->name);
1277
1278         if (IS_GEN(i915, 12))
1279                 tgl_whitelist_build(engine);
1280         else if (IS_GEN(i915, 11))
1281                 icl_whitelist_build(engine);
1282         else if (IS_CANNONLAKE(i915))
1283                 cnl_whitelist_build(engine);
1284         else if (IS_COFFEELAKE(i915))
1285                 cfl_whitelist_build(engine);
1286         else if (IS_GEMINILAKE(i915))
1287                 glk_whitelist_build(engine);
1288         else if (IS_KABYLAKE(i915))
1289                 kbl_whitelist_build(engine);
1290         else if (IS_BROXTON(i915))
1291                 bxt_whitelist_build(engine);
1292         else if (IS_SKYLAKE(i915))
1293                 skl_whitelist_build(engine);
1294         else if (INTEL_GEN(i915) <= 8)
1295                 return;
1296         else
1297                 MISSING_CASE(INTEL_GEN(i915));
1298
1299         wa_init_finish(w);
1300 }
1301
1302 void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
1303 {
1304         const struct i915_wa_list *wal = &engine->whitelist;
1305         struct intel_uncore *uncore = engine->uncore;
1306         const u32 base = engine->mmio_base;
1307         struct i915_wa *wa;
1308         unsigned int i;
1309
1310         if (!wal->count)
1311                 return;
1312
1313         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1314                 intel_uncore_write(uncore,
1315                                    RING_FORCE_TO_NONPRIV(base, i),
1316                                    i915_mmio_reg_offset(wa->reg));
1317
1318         /* And clear the rest just in case of garbage */
1319         for (; i < RING_MAX_NONPRIV_SLOTS; i++)
1320                 intel_uncore_write(uncore,
1321                                    RING_FORCE_TO_NONPRIV(base, i),
1322                                    i915_mmio_reg_offset(RING_NOPID(base)));
1323 }
1324
1325 static void
1326 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1327 {
1328         struct drm_i915_private *i915 = engine->i915;
1329
1330         if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
1331                 /* Wa_1606700617:tgl */
1332                 wa_masked_en(wal,
1333                              GEN9_CS_DEBUG_MODE1,
1334                              FF_DOP_CLOCK_GATE_DISABLE);
1335
1336                 /*
1337                  * Wa_1607138336:tgl
1338                  * Wa_1607063988:tgl
1339                  */
1340                 wa_write_or(wal,
1341                             GEN9_CTX_PREEMPT_REG,
1342                             GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
1343
1344                 /*
1345                  * Wa_1607030317:tgl
1346                  * Wa_1607186500:tgl
1347                  * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
1348                  * of then says it is fixed on B0 the other one says it is
1349                  * permanent
1350                  */
1351                 wa_masked_en(wal,
1352                              GEN6_RC_SLEEP_PSMI_CONTROL,
1353                              GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
1354                              GEN8_RC_SEMA_IDLE_MSG_DISABLE);
1355
1356                 /*
1357                  * Wa_1606679103:tgl
1358                  * (see also Wa_1606682166:icl)
1359                  */
1360                 wa_write_or(wal,
1361                             GEN7_SARCHKMD,
1362                             GEN7_DISABLE_SAMPLER_PREFETCH);
1363
1364                 /* Wa_1407928979:tgl */
1365                 wa_write_or(wal,
1366                             GEN7_FF_THREAD_MODE,
1367                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
1368
1369                 /*
1370                  * Wa_1409085225:tgl
1371                  * Wa_14010229206:tgl
1372                  */
1373                 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
1374         }
1375
1376         if (IS_TIGERLAKE(i915)) {
1377                 /* Wa_1606931601:tgl */
1378                 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
1379
1380                 /* Wa_1409804808:tgl */
1381                 wa_masked_en(wal, GEN7_ROW_CHICKEN2,
1382                              GEN12_PUSH_CONST_DEREF_HOLD_DIS);
1383         }
1384
1385         if (IS_GEN(i915, 11)) {
1386                 /* This is not an Wa. Enable for better image quality */
1387                 wa_masked_en(wal,
1388                              _3D_CHICKEN3,
1389                              _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
1390
1391                 /* WaPipelineFlushCoherentLines:icl */
1392                 wa_write_or(wal,
1393                             GEN8_L3SQCREG4,
1394                             GEN8_LQSC_FLUSH_COHERENT_LINES);
1395
1396                 /*
1397                  * Wa_1405543622:icl
1398                  * Formerly known as WaGAPZPriorityScheme
1399                  */
1400                 wa_write_or(wal,
1401                             GEN8_GARBCNTL,
1402                             GEN11_ARBITRATION_PRIO_ORDER_MASK);
1403
1404                 /*
1405                  * Wa_1604223664:icl
1406                  * Formerly known as WaL3BankAddressHashing
1407                  */
1408                 wa_write_masked_or(wal,
1409                                    GEN8_GARBCNTL,
1410                                    GEN11_HASH_CTRL_EXCL_MASK,
1411                                    GEN11_HASH_CTRL_EXCL_BIT0);
1412                 wa_write_masked_or(wal,
1413                                    GEN11_GLBLINVL,
1414                                    GEN11_BANK_HASH_ADDR_EXCL_MASK,
1415                                    GEN11_BANK_HASH_ADDR_EXCL_BIT0);
1416
1417                 /*
1418                  * Wa_1405733216:icl
1419                  * Formerly known as WaDisableCleanEvicts
1420                  */
1421                 wa_write_or(wal,
1422                             GEN8_L3SQCREG4,
1423                             GEN11_LQSC_CLEAN_EVICT_DISABLE);
1424
1425                 /* WaForwardProgressSoftReset:icl */
1426                 wa_write_or(wal,
1427                             GEN10_SCRATCH_LNCF2,
1428                             PMFLUSHDONE_LNICRSDROP |
1429                             PMFLUSH_GAPL3UNBLOCK |
1430                             PMFLUSHDONE_LNEBLK);
1431
1432                 /* Wa_1406609255:icl (pre-prod) */
1433                 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
1434                         wa_write_or(wal,
1435                                     GEN7_SARCHKMD,
1436                                     GEN7_DISABLE_DEMAND_PREFETCH);
1437
1438                 /* Wa_1606682166:icl */
1439                 wa_write_or(wal,
1440                             GEN7_SARCHKMD,
1441                             GEN7_DISABLE_SAMPLER_PREFETCH);
1442
1443                 /* Wa_1409178092:icl */
1444                 wa_write_masked_or(wal,
1445                                    GEN11_SCRATCH2,
1446                                    GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
1447                                    0);
1448         }
1449
1450         if (IS_GEN_RANGE(i915, 9, 11)) {
1451                 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
1452                 wa_masked_en(wal,
1453                              GEN7_FF_SLICE_CS_CHICKEN1,
1454                              GEN9_FFSC_PERCTX_PREEMPT_CTRL);
1455         }
1456
1457         if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
1458                 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
1459                 wa_write_or(wal,
1460                             GEN8_GARBCNTL,
1461                             GEN9_GAPS_TSV_CREDIT_DISABLE);
1462         }
1463
1464         if (IS_BROXTON(i915)) {
1465                 /* WaDisablePooledEuLoadBalancingFix:bxt */
1466                 wa_masked_en(wal,
1467                              FF_SLICE_CS_CHICKEN2,
1468                              GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1469         }
1470
1471         if (IS_GEN(i915, 9)) {
1472                 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
1473                 wa_masked_en(wal,
1474                              GEN9_CSFE_CHICKEN1_RCS,
1475                              GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
1476
1477                 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
1478                 wa_write_or(wal,
1479                             BDW_SCRATCH1,
1480                             GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
1481
1482                 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
1483                 if (IS_GEN9_LP(i915))
1484                         wa_write_masked_or(wal,
1485                                            GEN8_L3SQCREG1,
1486                                            L3_PRIO_CREDITS_MASK,
1487                                            L3_GENERAL_PRIO_CREDITS(62) |
1488                                            L3_HIGH_PRIO_CREDITS(2));
1489
1490                 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
1491                 wa_write_or(wal,
1492                             GEN8_L3SQCREG4,
1493                             GEN8_LQSC_FLUSH_COHERENT_LINES);
1494         }
1495
1496         if (IS_GEN(i915, 7))
1497                 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1498                 wa_masked_en(wal,
1499                              GFX_MODE_GEN7,
1500                              GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
1501
1502         if (IS_GEN_RANGE(i915, 6, 7))
1503                 /*
1504                  * We need to disable the AsyncFlip performance optimisations in
1505                  * order to use MI_WAIT_FOR_EVENT within the CS. It should
1506                  * already be programmed to '1' on all products.
1507                  *
1508                  * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1509                  */
1510                 wa_masked_en(wal,
1511                              MI_MODE,
1512                              ASYNC_FLIP_PERF_DISABLE);
1513
1514         if (IS_GEN(i915, 6)) {
1515                 /*
1516                  * Required for the hardware to program scanline values for
1517                  * waiting
1518                  * WaEnableFlushTlbInvalidationMode:snb
1519                  */
1520                 wa_masked_en(wal,
1521                              GFX_MODE,
1522                              GFX_TLB_INVALIDATE_EXPLICIT);
1523
1524                 /*
1525                  * From the Sandybridge PRM, volume 1 part 3, page 24:
1526                  * "If this bit is set, STCunit will have LRA as replacement
1527                  *  policy. [...] This bit must be reset. LRA replacement
1528                  *  policy is not supported."
1529                  */
1530                 wa_masked_dis(wal,
1531                               CACHE_MODE_0,
1532                               CM0_STC_EVICT_DISABLE_LRA_SNB);
1533         }
1534
1535         if (IS_GEN_RANGE(i915, 4, 6))
1536                 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1537                 wa_add(wal, MI_MODE,
1538                        0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
1539                        /* XXX bit doesn't stick on Broadwater */
1540                        IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
1541 }
1542
1543 static void
1544 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1545 {
1546         struct drm_i915_private *i915 = engine->i915;
1547
1548         /* WaKBLVECSSemaphoreWaitPoll:kbl */
1549         if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
1550                 wa_write(wal,
1551                          RING_SEMA_WAIT_POLL(engine->mmio_base),
1552                          1);
1553         }
1554 }
1555
1556 static void
1557 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1558 {
1559         if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
1560                 return;
1561
1562         if (engine->class == RENDER_CLASS)
1563                 rcs_engine_wa_init(engine, wal);
1564         else
1565                 xcs_engine_wa_init(engine, wal);
1566 }
1567
1568 void intel_engine_init_workarounds(struct intel_engine_cs *engine)
1569 {
1570         struct i915_wa_list *wal = &engine->wa_list;
1571
1572         if (INTEL_GEN(engine->i915) < 4)
1573                 return;
1574
1575         wa_init_start(wal, "engine", engine->name);
1576         engine_init_workarounds(engine, wal);
1577         wa_init_finish(wal);
1578 }
1579
1580 void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
1581 {
1582         wa_list_apply(engine->uncore, &engine->wa_list);
1583 }
1584
1585 static struct i915_vma *
1586 create_scratch(struct i915_address_space *vm, int count)
1587 {
1588         struct drm_i915_gem_object *obj;
1589         struct i915_vma *vma;
1590         unsigned int size;
1591         int err;
1592
1593         size = round_up(count * sizeof(u32), PAGE_SIZE);
1594         obj = i915_gem_object_create_internal(vm->i915, size);
1595         if (IS_ERR(obj))
1596                 return ERR_CAST(obj);
1597
1598         i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1599
1600         vma = i915_vma_instance(obj, vm, NULL);
1601         if (IS_ERR(vma)) {
1602                 err = PTR_ERR(vma);
1603                 goto err_obj;
1604         }
1605
1606         err = i915_vma_pin(vma, 0, 0,
1607                            i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
1608         if (err)
1609                 goto err_obj;
1610
1611         return vma;
1612
1613 err_obj:
1614         i915_gem_object_put(obj);
1615         return ERR_PTR(err);
1616 }
1617
1618 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
1619 {
1620         /*
1621          * Registers in this range are affected by the MCR selector
1622          * which only controls CPU initiated MMIO. Routing does not
1623          * work for CS access so we cannot verify them on this path.
1624          */
1625         if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))
1626                 return true;
1627
1628         return false;
1629 }
1630
1631 static int
1632 wa_list_srm(struct i915_request *rq,
1633             const struct i915_wa_list *wal,
1634             struct i915_vma *vma)
1635 {
1636         struct drm_i915_private *i915 = rq->i915;
1637         unsigned int i, count = 0;
1638         const struct i915_wa *wa;
1639         u32 srm, *cs;
1640
1641         srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1642         if (INTEL_GEN(i915) >= 8)
1643                 srm++;
1644
1645         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1646                 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
1647                         count++;
1648         }
1649
1650         cs = intel_ring_begin(rq, 4 * count);
1651         if (IS_ERR(cs))
1652                 return PTR_ERR(cs);
1653
1654         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1655                 u32 offset = i915_mmio_reg_offset(wa->reg);
1656
1657                 if (mcr_range(i915, offset))
1658                         continue;
1659
1660                 *cs++ = srm;
1661                 *cs++ = offset;
1662                 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
1663                 *cs++ = 0;
1664         }
1665         intel_ring_advance(rq, cs);
1666
1667         return 0;
1668 }
1669
1670 static int engine_wa_list_verify(struct intel_context *ce,
1671                                  const struct i915_wa_list * const wal,
1672                                  const char *from)
1673 {
1674         const struct i915_wa *wa;
1675         struct i915_request *rq;
1676         struct i915_vma *vma;
1677         unsigned int i;
1678         u32 *results;
1679         int err;
1680
1681         if (!wal->count)
1682                 return 0;
1683
1684         vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
1685         if (IS_ERR(vma))
1686                 return PTR_ERR(vma);
1687
1688         intel_engine_pm_get(ce->engine);
1689         rq = intel_context_create_request(ce);
1690         intel_engine_pm_put(ce->engine);
1691         if (IS_ERR(rq)) {
1692                 err = PTR_ERR(rq);
1693                 goto err_vma;
1694         }
1695
1696         i915_vma_lock(vma);
1697         err = i915_request_await_object(rq, vma->obj, true);
1698         if (err == 0)
1699                 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1700         i915_vma_unlock(vma);
1701         if (err) {
1702                 i915_request_add(rq);
1703                 goto err_vma;
1704         }
1705
1706         err = wa_list_srm(rq, wal, vma);
1707         if (err)
1708                 goto err_vma;
1709
1710         i915_request_get(rq);
1711         i915_request_add(rq);
1712         if (i915_request_wait(rq, 0, HZ / 5) < 0) {
1713                 err = -ETIME;
1714                 goto err_rq;
1715         }
1716
1717         results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1718         if (IS_ERR(results)) {
1719                 err = PTR_ERR(results);
1720                 goto err_rq;
1721         }
1722
1723         err = 0;
1724         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1725                 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
1726                         continue;
1727
1728                 if (!wa_verify(wa, results[i], wal->name, from))
1729                         err = -ENXIO;
1730         }
1731
1732         i915_gem_object_unpin_map(vma->obj);
1733
1734 err_rq:
1735         i915_request_put(rq);
1736 err_vma:
1737         i915_vma_unpin(vma);
1738         i915_vma_put(vma);
1739         return err;
1740 }
1741
1742 int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
1743                                     const char *from)
1744 {
1745         return engine_wa_list_verify(engine->kernel_context,
1746                                      &engine->wa_list,
1747                                      from);
1748 }
1749
1750 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1751 #include "selftest_workarounds.c"
1752 #endif