drivers/gpu/drm/i915/gt/intel_rps.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2019 Intel Corporation
   5  */
   6
   7 #include <drm/i915_drm.h>
   8
   9 #include "i915_drv.h"
  10 #include "intel_breadcrumbs.h"
  11 #include "intel_gt.h"
  12 #include "intel_gt_clock_utils.h"
  13 #include "intel_gt_irq.h"
  14 #include "intel_gt_pm_irq.h"
  15 #include "intel_rps.h"
  16 #include "intel_sideband.h"
  17 #include "../../../platform/x86/intel_ips.h"
  18
  19 #define BUSY_MAX_EI     20u /* ms */
  20
  21 /*
  22  * Lock protecting IPS related data structures
  23  */
  24 static DEFINE_SPINLOCK(mchdev_lock);
  25
  26 static struct intel_gt *rps_to_gt(struct intel_rps *rps)
  27 {
  28         return container_of(rps, struct intel_gt, rps);
  29 }
  30
  31 static struct drm_i915_private *rps_to_i915(struct intel_rps *rps)
  32 {
  33         return rps_to_gt(rps)->i915;
  34 }
  35
  36 static struct intel_uncore *rps_to_uncore(struct intel_rps *rps)
  37 {
  38         return rps_to_gt(rps)->uncore;
  39 }
  40
  41 static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask)
  42 {
  43         return mask & ~rps->pm_intrmsk_mbz;
  44 }
  45
  46 static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
  47 {
  48         intel_uncore_write_fw(uncore, reg, val);
  49 }
  50
  51 static void rps_timer(struct timer_list *t)
  52 {
  53         struct intel_rps *rps = from_timer(rps, t, timer);
  54         struct intel_engine_cs *engine;
  55         ktime_t dt, last, timestamp;
  56         enum intel_engine_id id;
  57         s64 max_busy[3] = {};
  58
  59         timestamp = 0;
  60         for_each_engine(engine, rps_to_gt(rps), id) {
  61                 s64 busy;
  62                 int i;
  63
  64                 dt = intel_engine_get_busy_time(engine, &timestamp);
  65                 last = engine->stats.rps;
  66                 engine->stats.rps = dt;
  67
  68                 busy = ktime_to_ns(ktime_sub(dt, last));
  69                 for (i = 0; i < ARRAY_SIZE(max_busy); i++) {
  70                         if (busy > max_busy[i])
  71                                 swap(busy, max_busy[i]);
  72                 }
  73         }
  74         last = rps->pm_timestamp;
  75         rps->pm_timestamp = timestamp;
  76
  77         if (intel_rps_is_active(rps)) {
  78                 s64 busy;
  79                 int i;
  80
  81                 dt = ktime_sub(timestamp, last);
  82
  83                 /*
  84                  * Our goal is to evaluate each engine independently, so we run
  85                  * at the lowest clocks required to sustain the heaviest
  86                  * workload. However, a task may be split into sequential
  87                  * dependent operations across a set of engines, such that
  88                  * the independent contributions do not account for high load,
  89                  * but overall the task is GPU bound. For example, consider
  90                  * video decode on vcs followed by colour post-processing
  91                  * on vecs, followed by general post-processing on rcs.
  92                  * Since multi-engines being active does imply a single
  93                  * continuous workload across all engines, we hedge our
  94                  * bets by only contributing a factor of the distributed
  95                  * load into our busyness calculation.
  96                  */
  97                 busy = max_busy[0];
  98                 for (i = 1; i < ARRAY_SIZE(max_busy); i++) {
  99                         if (!max_busy[i])
 100                                 break;
 101
 102                         busy += div_u64(max_busy[i], 1 << i);
 103                 }
 104                 GT_TRACE(rps_to_gt(rps),
 105                          "busy:%lld [%d%%], max:[%lld, %lld, %lld], interval:%d\n",
 106                          busy, (int)div64_u64(100 * busy, dt),
 107                          max_busy[0], max_busy[1], max_busy[2],
 108                          rps->pm_interval);
 109
 110                 if (100 * busy > rps->power.up_threshold * dt &&
 111                     rps->cur_freq < rps->max_freq_softlimit) {
 112                         rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD;
 113                         rps->pm_interval = 1;
 114                         schedule_work(&rps->work);
 115                 } else if (100 * busy < rps->power.down_threshold * dt &&
 116                            rps->cur_freq > rps->min_freq_softlimit) {
 117                         rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD;
 118                         rps->pm_interval = 1;
 119                         schedule_work(&rps->work);
 120                 } else {
 121                         rps->last_adj = 0;
 122                 }
 123
 124                 mod_timer(&rps->timer,
 125                           jiffies + msecs_to_jiffies(rps->pm_interval));
 126                 rps->pm_interval = min(rps->pm_interval * 2, BUSY_MAX_EI);
 127         }
 128 }
 129
 130 static void rps_start_timer(struct intel_rps *rps)
 131 {
 132         rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp);
 133         rps->pm_interval = 1;
 134         mod_timer(&rps->timer, jiffies + 1);
 135 }
 136
 137 static void rps_stop_timer(struct intel_rps *rps)
 138 {
 139         del_timer_sync(&rps->timer);
 140         rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp);
 141         cancel_work_sync(&rps->work);
 142 }
 143
 144 static u32 rps_pm_mask(struct intel_rps *rps, u8 val)
 145 {
 146         u32 mask = 0;
 147
 148         /* We use UP_EI_EXPIRED interrupts for both up/down in manual mode */
 149         if (val > rps->min_freq_softlimit)
 150                 mask |= (GEN6_PM_RP_UP_EI_EXPIRED |
 151                          GEN6_PM_RP_DOWN_THRESHOLD |
 152                          GEN6_PM_RP_DOWN_TIMEOUT);
 153
 154         if (val < rps->max_freq_softlimit)
 155                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
 156
 157         mask &= rps->pm_events;
 158
 159         return rps_pm_sanitize_mask(rps, ~mask);
 160 }
 161
 162 static void rps_reset_ei(struct intel_rps *rps)
 163 {
 164         memset(&rps->ei, 0, sizeof(rps->ei));
 165 }
 166
 167 static void rps_enable_interrupts(struct intel_rps *rps)
 168 {
 169         struct intel_gt *gt = rps_to_gt(rps);
 170
 171         GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",
 172                  rps->pm_events, rps_pm_mask(rps, rps->last_freq));
 173
 174         rps_reset_ei(rps);
 175
 176         spin_lock_irq(&gt->irq_lock);
 177         gen6_gt_pm_enable_irq(gt, rps->pm_events);
 178         spin_unlock_irq(&gt->irq_lock);
 179
 180         intel_uncore_write(gt->uncore,
 181                            GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
 182 }
 183
 184 static void gen6_rps_reset_interrupts(struct intel_rps *rps)
 185 {
 186         gen6_gt_pm_reset_iir(rps_to_gt(rps), GEN6_PM_RPS_EVENTS);
 187 }
 188
 189 static void gen11_rps_reset_interrupts(struct intel_rps *rps)
 190 {
 191         while (gen11_gt_reset_one_iir(rps_to_gt(rps), 0, GEN11_GTPM))
 192                 ;
 193 }
 194
 195 static void rps_reset_interrupts(struct intel_rps *rps)
 196 {
 197         struct intel_gt *gt = rps_to_gt(rps);
 198
 199         spin_lock_irq(&gt->irq_lock);
 200         if (INTEL_GEN(gt->i915) >= 11)
 201                 gen11_rps_reset_interrupts(rps);
 202         else
 203                 gen6_rps_reset_interrupts(rps);
 204
 205         rps->pm_iir = 0;
 206         spin_unlock_irq(&gt->irq_lock);
 207 }
 208
 209 static void rps_disable_interrupts(struct intel_rps *rps)
 210 {
 211         struct intel_gt *gt = rps_to_gt(rps);
 212
 213         intel_uncore_write(gt->uncore,
 214                            GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
 215
 216         spin_lock_irq(&gt->irq_lock);
 217         gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
 218         spin_unlock_irq(&gt->irq_lock);
 219
 220         intel_synchronize_irq(gt->i915);
 221
 222         /*
 223          * Now that we will not be generating any more work, flush any
 224          * outstanding tasks. As we are called on the RPS idle path,
 225          * we will reset the GPU to minimum frequencies, so the current
 226          * state of the worker can be discarded.
 227          */
 228         cancel_work_sync(&rps->work);
 229
 230         rps_reset_interrupts(rps);
 231         GT_TRACE(gt, "interrupts:off\n");
 232 }
 233
 234 static const struct cparams {
 235         u16 i;
 236         u16 t;
 237         u16 m;
 238         u16 c;
 239 } cparams[] = {
 240         { 1, 1333, 301, 28664 },
 241         { 1, 1066, 294, 24460 },
 242         { 1, 800, 294, 25192 },
 243         { 0, 1333, 276, 27605 },
 244         { 0, 1066, 276, 27605 },
 245         { 0, 800, 231, 23784 },
 246 };
 247
 248 static void gen5_rps_init(struct intel_rps *rps)
 249 {
 250         struct drm_i915_private *i915 = rps_to_i915(rps);
 251         struct intel_uncore *uncore = rps_to_uncore(rps);
 252         u8 fmax, fmin, fstart;
 253         u32 rgvmodectl;
 254         int c_m, i;
 255
 256         if (i915->fsb_freq <= 3200)
 257                 c_m = 0;
 258         else if (i915->fsb_freq <= 4800)
 259                 c_m = 1;
 260         else
 261                 c_m = 2;
 262
 263         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
 264                 if (cparams[i].i == c_m && cparams[i].t == i915->mem_freq) {
 265                         rps->ips.m = cparams[i].m;
 266                         rps->ips.c = cparams[i].c;
 267                         break;
 268                 }
 269         }
 270
 271         rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
 272
 273         /* Set up min, max, and cur for interrupt handling */
 274         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
 275         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
 276         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
 277                 MEMMODE_FSTART_SHIFT;
 278         drm_dbg(&i915->drm, "fmax: %d, fmin: %d, fstart: %d\n",
 279                 fmax, fmin, fstart);
 280
 281         rps->min_freq = fmax;
 282         rps->efficient_freq = fstart;
 283         rps->max_freq = fmin;
 284 }
 285
 286 static unsigned long
 287 __ips_chipset_val(struct intel_ips *ips)
 288 {
 289         struct intel_uncore *uncore =
 290                 rps_to_uncore(container_of(ips, struct intel_rps, ips));
 291         unsigned long now = jiffies_to_msecs(jiffies), dt;
 292         unsigned long result;
 293         u64 total, delta;
 294
 295         lockdep_assert_held(&mchdev_lock);
 296
 297         /*
 298          * Prevent division-by-zero if we are asking too fast.
 299          * Also, we don't get interesting results if we are polling
 300          * faster than once in 10ms, so just return the saved value
 301          * in such cases.
 302          */
 303         dt = now - ips->last_time1;
 304         if (dt <= 10)
 305                 return ips->chipset_power;
 306
 307         /* FIXME: handle per-counter overflow */
 308         total = intel_uncore_read(uncore, DMIEC);
 309         total += intel_uncore_read(uncore, DDREC);
 310         total += intel_uncore_read(uncore, CSIEC);
 311
 312         delta = total - ips->last_count1;
 313
 314         result = div_u64(div_u64(ips->m * delta, dt) + ips->c, 10);
 315
 316         ips->last_count1 = total;
 317         ips->last_time1 = now;
 318
 319         ips->chipset_power = result;
 320
 321         return result;
 322 }
 323
 324 static unsigned long ips_mch_val(struct intel_uncore *uncore)
 325 {
 326         unsigned int m, x, b;
 327         u32 tsfs;
 328
 329         tsfs = intel_uncore_read(uncore, TSFS);
 330         x = intel_uncore_read8(uncore, TR1);
 331
 332         b = tsfs & TSFS_INTR_MASK;
 333         m = (tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT;
 334
 335         return m * x / 127 - b;
 336 }
 337
 338 static int _pxvid_to_vd(u8 pxvid)
 339 {
 340         if (pxvid == 0)
 341                 return 0;
 342
 343         if (pxvid >= 8 && pxvid < 31)
 344                 pxvid = 31;
 345
 346         return (pxvid + 2) * 125;
 347 }
 348
 349 static u32 pvid_to_extvid(struct drm_i915_private *i915, u8 pxvid)
 350 {
 351         const int vd = _pxvid_to_vd(pxvid);
 352
 353         if (INTEL_INFO(i915)->is_mobile)
 354                 return max(vd - 1125, 0);
 355
 356         return vd;
 357 }
 358
 359 static void __gen5_ips_update(struct intel_ips *ips)
 360 {
 361         struct intel_uncore *uncore =
 362                 rps_to_uncore(container_of(ips, struct intel_rps, ips));
 363         u64 now, delta, dt;
 364         u32 count;
 365
 366         lockdep_assert_held(&mchdev_lock);
 367
 368         now = ktime_get_raw_ns();
 369         dt = now - ips->last_time2;
 370         do_div(dt, NSEC_PER_MSEC);
 371
 372         /* Don't divide by 0 */
 373         if (dt <= 10)
 374                 return;
 375
 376         count = intel_uncore_read(uncore, GFXEC);
 377         delta = count - ips->last_count2;
 378
 379         ips->last_count2 = count;
 380         ips->last_time2 = now;
 381
 382         /* More magic constants... */
 383         ips->gfx_power = div_u64(delta * 1181, dt * 10);
 384 }
 385
 386 static void gen5_rps_update(struct intel_rps *rps)
 387 {
 388         spin_lock_irq(&mchdev_lock);
 389         __gen5_ips_update(&rps->ips);
 390         spin_unlock_irq(&mchdev_lock);
 391 }
 392
 393 static bool gen5_rps_set(struct intel_rps *rps, u8 val)
 394 {
 395         struct intel_uncore *uncore = rps_to_uncore(rps);
 396         u16 rgvswctl;
 397
 398         lockdep_assert_held(&mchdev_lock);
 399
 400         rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
 401         if (rgvswctl & MEMCTL_CMD_STS) {
 402                 DRM_DEBUG("gpu busy, RCS change rejected\n");
 403                 return false; /* still busy with another command */
 404         }
 405
 406         /* Invert the frequency bin into an ips delay */
 407         val = rps->max_freq - val;
 408         val = rps->min_freq + val;
 409
 410         rgvswctl =
 411                 (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
 412                 (val << MEMCTL_FREQ_SHIFT) |
 413                 MEMCTL_SFCAVM;
 414         intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
 415         intel_uncore_posting_read16(uncore, MEMSWCTL);
 416
 417         rgvswctl |= MEMCTL_CMD_STS;
 418         intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
 419
 420         return true;
 421 }
 422
 423 static unsigned long intel_pxfreq(u32 vidfreq)
 424 {
 425         int div = (vidfreq & 0x3f0000) >> 16;
 426         int post = (vidfreq & 0x3000) >> 12;
 427         int pre = (vidfreq & 0x7);
 428
 429         if (!pre)
 430                 return 0;
 431
 432         return div * 133333 / (pre << post);
 433 }
 434
 435 static unsigned int init_emon(struct intel_uncore *uncore)
 436 {
 437         u8 pxw[16];
 438         int i;
 439
 440         /* Disable to program */
 441         intel_uncore_write(uncore, ECR, 0);
 442         intel_uncore_posting_read(uncore, ECR);
 443
 444         /* Program energy weights for various events */
 445         intel_uncore_write(uncore, SDEW, 0x15040d00);
 446         intel_uncore_write(uncore, CSIEW0, 0x007f0000);
 447         intel_uncore_write(uncore, CSIEW1, 0x1e220004);
 448         intel_uncore_write(uncore, CSIEW2, 0x04000004);
 449
 450         for (i = 0; i < 5; i++)
 451                 intel_uncore_write(uncore, PEW(i), 0);
 452         for (i = 0; i < 3; i++)
 453                 intel_uncore_write(uncore, DEW(i), 0);
 454
 455         /* Program P-state weights to account for frequency power adjustment */
 456         for (i = 0; i < 16; i++) {
 457                 u32 pxvidfreq = intel_uncore_read(uncore, PXVFREQ(i));
 458                 unsigned int freq = intel_pxfreq(pxvidfreq);
 459                 unsigned int vid =
 460                         (pxvidfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT;
 461                 unsigned int val;
 462
 463                 val = vid * vid * freq / 1000 * 255;
 464                 val /= 127 * 127 * 900;
 465
 466                 pxw[i] = val;
 467         }
 468         /* Render standby states get 0 weight */
 469         pxw[14] = 0;
 470         pxw[15] = 0;
 471
 472         for (i = 0; i < 4; i++) {
 473                 intel_uncore_write(uncore, PXW(i),
 474                                    pxw[i * 4 + 0] << 24 |
 475                                    pxw[i * 4 + 1] << 16 |
 476                                    pxw[i * 4 + 2] <<  8 |
 477                                    pxw[i * 4 + 3] <<  0);
 478         }
 479
 480         /* Adjust magic regs to magic values (more experimental results) */
 481         intel_uncore_write(uncore, OGW0, 0);
 482         intel_uncore_write(uncore, OGW1, 0);
 483         intel_uncore_write(uncore, EG0, 0x00007f00);
 484         intel_uncore_write(uncore, EG1, 0x0000000e);
 485         intel_uncore_write(uncore, EG2, 0x000e0000);
 486         intel_uncore_write(uncore, EG3, 0x68000300);
 487         intel_uncore_write(uncore, EG4, 0x42000000);
 488         intel_uncore_write(uncore, EG5, 0x00140031);
 489         intel_uncore_write(uncore, EG6, 0);
 490         intel_uncore_write(uncore, EG7, 0);
 491
 492         for (i = 0; i < 8; i++)
 493                 intel_uncore_write(uncore, PXWL(i), 0);
 494
 495         /* Enable PMON + select events */
 496         intel_uncore_write(uncore, ECR, 0x80000019);
 497
 498         return intel_uncore_read(uncore, LCFUSE02) & LCFUSE_HIV_MASK;
 499 }
 500
 501 static bool gen5_rps_enable(struct intel_rps *rps)
 502 {
 503         struct intel_uncore *uncore = rps_to_uncore(rps);
 504         u8 fstart, vstart;
 505         u32 rgvmodectl;
 506
 507         spin_lock_irq(&mchdev_lock);
 508
 509         rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
 510
 511         /* Enable temp reporting */
 512         intel_uncore_write16(uncore, PMMISC,
 513                              intel_uncore_read16(uncore, PMMISC) | MCPPCE_EN);
 514         intel_uncore_write16(uncore, TSC1,
 515                              intel_uncore_read16(uncore, TSC1) | TSE);
 516
 517         /* 100ms RC evaluation intervals */
 518         intel_uncore_write(uncore, RCUPEI, 100000);
 519         intel_uncore_write(uncore, RCDNEI, 100000);
 520
 521         /* Set max/min thresholds to 90ms and 80ms respectively */
 522         intel_uncore_write(uncore, RCBMAXAVG, 90000);
 523         intel_uncore_write(uncore, RCBMINAVG, 80000);
 524
 525         intel_uncore_write(uncore, MEMIHYST, 1);
 526
 527         /* Set up min, max, and cur for interrupt handling */
 528         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
 529                 MEMMODE_FSTART_SHIFT;
 530
 531         vstart = (intel_uncore_read(uncore, PXVFREQ(fstart)) &
 532                   PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT;
 533
 534         intel_uncore_write(uncore,
 535                            MEMINTREN,
 536                            MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
 537
 538         intel_uncore_write(uncore, VIDSTART, vstart);
 539         intel_uncore_posting_read(uncore, VIDSTART);
 540
 541         rgvmodectl |= MEMMODE_SWMODE_EN;
 542         intel_uncore_write(uncore, MEMMODECTL, rgvmodectl);
 543
 544         if (wait_for_atomic((intel_uncore_read(uncore, MEMSWCTL) &
 545                              MEMCTL_CMD_STS) == 0, 10))
 546                 drm_err(&uncore->i915->drm,
 547                         "stuck trying to change perf mode\n");
 548         mdelay(1);
 549
 550         gen5_rps_set(rps, rps->cur_freq);
 551
 552         rps->ips.last_count1 = intel_uncore_read(uncore, DMIEC);
 553         rps->ips.last_count1 += intel_uncore_read(uncore, DDREC);
 554         rps->ips.last_count1 += intel_uncore_read(uncore, CSIEC);
 555         rps->ips.last_time1 = jiffies_to_msecs(jiffies);
 556
 557         rps->ips.last_count2 = intel_uncore_read(uncore, GFXEC);
 558         rps->ips.last_time2 = ktime_get_raw_ns();
 559
 560         spin_unlock_irq(&mchdev_lock);
 561
 562         rps->ips.corr = init_emon(uncore);
 563
 564         return true;
 565 }
 566
 567 static void gen5_rps_disable(struct intel_rps *rps)
 568 {
 569         struct intel_uncore *uncore = rps_to_uncore(rps);
 570         u16 rgvswctl;
 571
 572         spin_lock_irq(&mchdev_lock);
 573
 574         rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
 575
 576         /* Ack interrupts, disable EFC interrupt */
 577         intel_uncore_write(uncore, MEMINTREN,
 578                            intel_uncore_read(uncore, MEMINTREN) &
 579                            ~MEMINT_EVAL_CHG_EN);
 580         intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
 581         intel_uncore_write(uncore, DEIER,
 582                            intel_uncore_read(uncore, DEIER) & ~DE_PCU_EVENT);
 583         intel_uncore_write(uncore, DEIIR, DE_PCU_EVENT);
 584         intel_uncore_write(uncore, DEIMR,
 585                            intel_uncore_read(uncore, DEIMR) | DE_PCU_EVENT);
 586
 587         /* Go back to the starting frequency */
 588         gen5_rps_set(rps, rps->idle_freq);
 589         mdelay(1);
 590         rgvswctl |= MEMCTL_CMD_STS;
 591         intel_uncore_write(uncore, MEMSWCTL, rgvswctl);
 592         mdelay(1);
 593
 594         spin_unlock_irq(&mchdev_lock);
 595 }
 596
 597 static u32 rps_limits(struct intel_rps *rps, u8 val)
 598 {
 599         u32 limits;
 600
 601         /*
 602          * Only set the down limit when we've reached the lowest level to avoid
 603          * getting more interrupts, otherwise leave this clear. This prevents a
 604          * race in the hw when coming out of rc6: There's a tiny window where
 605          * the hw runs at the minimal clock before selecting the desired
 606          * frequency, if the down threshold expires in that window we will not
 607          * receive a down interrupt.
 608          */
 609         if (INTEL_GEN(rps_to_i915(rps)) >= 9) {
 610                 limits = rps->max_freq_softlimit << 23;
 611                 if (val <= rps->min_freq_softlimit)
 612                         limits |= rps->min_freq_softlimit << 14;
 613         } else {
 614                 limits = rps->max_freq_softlimit << 24;
 615                 if (val <= rps->min_freq_softlimit)
 616                         limits |= rps->min_freq_softlimit << 16;
 617         }
 618
 619         return limits;
 620 }
 621
 622 static void rps_set_power(struct intel_rps *rps, int new_power)
 623 {
 624         struct intel_gt *gt = rps_to_gt(rps);
 625         struct intel_uncore *uncore = gt->uncore;
 626         u32 threshold_up = 0, threshold_down = 0; /* in % */
 627         u32 ei_up = 0, ei_down = 0;
 628
 629         lockdep_assert_held(&rps->power.mutex);
 630
 631         if (new_power == rps->power.mode)
 632                 return;
 633
 634         threshold_up = 95;
 635         threshold_down = 85;
 636
 637         /* Note the units here are not exactly 1us, but 1280ns. */
 638         switch (new_power) {
 639         case LOW_POWER:
 640                 ei_up = 16000;
 641                 ei_down = 32000;
 642                 break;
 643
 644         case BETWEEN:
 645                 ei_up = 13000;
 646                 ei_down = 32000;
 647                 break;
 648
 649         case HIGH_POWER:
 650                 ei_up = 10000;
 651                 ei_down = 32000;
 652                 break;
 653         }
 654
 655         /* When byt can survive without system hang with dynamic
 656          * sw freq adjustments, this restriction can be lifted.
 657          */
 658         if (IS_VALLEYVIEW(gt->i915))
 659                 goto skip_hw_write;
 660
 661         GT_TRACE(gt,
 662                  "changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n",
 663                  new_power, threshold_up, ei_up, threshold_down, ei_down);
 664
 665         set(uncore, GEN6_RP_UP_EI,
 666             intel_gt_ns_to_pm_interval(gt, ei_up * 1000));
 667         set(uncore, GEN6_RP_UP_THRESHOLD,
 668             intel_gt_ns_to_pm_interval(gt, ei_up * threshold_up * 10));
 669
 670         set(uncore, GEN6_RP_DOWN_EI,
 671             intel_gt_ns_to_pm_interval(gt, ei_down * 1000));
 672         set(uncore, GEN6_RP_DOWN_THRESHOLD,
 673             intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
 674
 675         set(uncore, GEN6_RP_CONTROL,
 676             (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
 677             GEN6_RP_MEDIA_HW_NORMAL_MODE |
 678             GEN6_RP_MEDIA_IS_GFX |
 679             GEN6_RP_ENABLE |
 680             GEN6_RP_UP_BUSY_AVG |
 681             GEN6_RP_DOWN_IDLE_AVG);
 682
 683 skip_hw_write:
 684         rps->power.mode = new_power;
 685         rps->power.up_threshold = threshold_up;
 686         rps->power.down_threshold = threshold_down;
 687 }
 688
 689 static void gen6_rps_set_thresholds(struct intel_rps *rps, u8 val)
 690 {
 691         int new_power;
 692
 693         new_power = rps->power.mode;
 694         switch (rps->power.mode) {
 695         case LOW_POWER:
 696                 if (val > rps->efficient_freq + 1 &&
 697                     val > rps->cur_freq)
 698                         new_power = BETWEEN;
 699                 break;
 700
 701         case BETWEEN:
 702                 if (val <= rps->efficient_freq &&
 703                     val < rps->cur_freq)
 704                         new_power = LOW_POWER;
 705                 else if (val >= rps->rp0_freq &&
 706                          val > rps->cur_freq)
 707                         new_power = HIGH_POWER;
 708                 break;
 709
 710         case HIGH_POWER:
 711                 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
 712                     val < rps->cur_freq)
 713                         new_power = BETWEEN;
 714                 break;
 715         }
 716         /* Max/min bins are special */
 717         if (val <= rps->min_freq_softlimit)
 718                 new_power = LOW_POWER;
 719         if (val >= rps->max_freq_softlimit)
 720                 new_power = HIGH_POWER;
 721
 722         mutex_lock(&rps->power.mutex);
 723         if (rps->power.interactive)
 724                 new_power = HIGH_POWER;
 725         rps_set_power(rps, new_power);
 726         mutex_unlock(&rps->power.mutex);
 727 }
 728
 729 void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive)
 730 {
 731         GT_TRACE(rps_to_gt(rps), "mark interactive: %s\n", yesno(interactive));
 732
 733         mutex_lock(&rps->power.mutex);
 734         if (interactive) {
 735                 if (!rps->power.interactive++ && intel_rps_is_active(rps))
 736                         rps_set_power(rps, HIGH_POWER);
 737         } else {
 738                 GEM_BUG_ON(!rps->power.interactive);
 739                 rps->power.interactive--;
 740         }
 741         mutex_unlock(&rps->power.mutex);
 742 }
 743
 744 static int gen6_rps_set(struct intel_rps *rps, u8 val)
 745 {
 746         struct intel_uncore *uncore = rps_to_uncore(rps);
 747         struct drm_i915_private *i915 = rps_to_i915(rps);
 748         u32 swreq;
 749
 750         if (INTEL_GEN(i915) >= 9)
 751                 swreq = GEN9_FREQUENCY(val);
 752         else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
 753                 swreq = HSW_FREQUENCY(val);
 754         else
 755                 swreq = (GEN6_FREQUENCY(val) |
 756                          GEN6_OFFSET(0) |
 757                          GEN6_AGGRESSIVE_TURBO);
 758         set(uncore, GEN6_RPNSWREQ, swreq);
 759
 760         GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d, swreq:%x\n",
 761                  val, intel_gpu_freq(rps, val), swreq);
 762
 763         return 0;
 764 }
 765
 766 static int vlv_rps_set(struct intel_rps *rps, u8 val)
 767 {
 768         struct drm_i915_private *i915 = rps_to_i915(rps);
 769         int err;
 770
 771         vlv_punit_get(i915);
 772         err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val);
 773         vlv_punit_put(i915);
 774
 775         GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n",
 776                  val, intel_gpu_freq(rps, val));
 777
 778         return err;
 779 }
 780
 781 static int rps_set(struct intel_rps *rps, u8 val, bool update)
 782 {
 783         struct drm_i915_private *i915 = rps_to_i915(rps);
 784         int err;
 785
 786         if (INTEL_GEN(i915) < 6)
 787                 return 0;
 788
 789         if (val == rps->last_freq)
 790                 return 0;
 791
 792         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
 793                 err = vlv_rps_set(rps, val);
 794         else
 795                 err = gen6_rps_set(rps, val);
 796         if (err)
 797                 return err;
 798
 799         if (update)
 800                 gen6_rps_set_thresholds(rps, val);
 801         rps->last_freq = val;
 802
 803         return 0;
 804 }
 805
 806 void intel_rps_unpark(struct intel_rps *rps)
 807 {
 808         if (!intel_rps_is_enabled(rps))
 809                 return;
 810
 811         GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq);
 812
 813         /*
 814          * Use the user's desired frequency as a guide, but for better
 815          * performance, jump directly to RPe as our starting frequency.
 816          */
 817         mutex_lock(&rps->lock);
 818
 819         intel_rps_set_active(rps);
 820         intel_rps_set(rps,
 821                       clamp(rps->cur_freq,
 822                             rps->min_freq_softlimit,
 823                             rps->max_freq_softlimit));
 824
 825         mutex_unlock(&rps->lock);
 826
 827         rps->pm_iir = 0;
 828         if (intel_rps_has_interrupts(rps))
 829                 rps_enable_interrupts(rps);
 830         if (intel_rps_uses_timer(rps))
 831                 rps_start_timer(rps);
 832
 833         if (IS_GEN(rps_to_i915(rps), 5))
 834                 gen5_rps_update(rps);
 835 }
 836
 837 void intel_rps_park(struct intel_rps *rps)
 838 {
 839         int adj;
 840
 841         if (!intel_rps_clear_active(rps))
 842                 return;
 843
 844         if (intel_rps_uses_timer(rps))
 845                 rps_stop_timer(rps);
 846         if (intel_rps_has_interrupts(rps))
 847                 rps_disable_interrupts(rps);
 848
 849         if (rps->last_freq <= rps->idle_freq)
 850                 return;
 851
 852         /*
 853          * The punit delays the write of the frequency and voltage until it
 854          * determines the GPU is awake. During normal usage we don't want to
 855          * waste power changing the frequency if the GPU is sleeping (rc6).
 856          * However, the GPU and driver is now idle and we do not want to delay
 857          * switching to minimum voltage (reducing power whilst idle) as we do
 858          * not expect to be woken in the near future and so must flush the
 859          * change by waking the device.
 860          *
 861          * We choose to take the media powerwell (either would do to trick the
 862          * punit into committing the voltage change) as that takes a lot less
 863          * power than the render powerwell.
 864          */
 865         intel_uncore_forcewake_get(rps_to_uncore(rps), FORCEWAKE_MEDIA);
 866         rps_set(rps, rps->idle_freq, false);
 867         intel_uncore_forcewake_put(rps_to_uncore(rps), FORCEWAKE_MEDIA);
 868
 869         /*
 870          * Since we will try and restart from the previously requested
 871          * frequency on unparking, treat this idle point as a downclock
 872          * interrupt and reduce the frequency for resume. If we park/unpark
 873          * more frequently than the rps worker can run, we will not respond
 874          * to any EI and never see a change in frequency.
 875          *
 876          * (Note we accommodate Cherryview's limitation of only using an
 877          * even bin by applying it to all.)
 878          */
 879         adj = rps->last_adj;
 880         if (adj < 0)
 881                 adj *= 2;
 882         else /* CHV needs even encode values */
 883                 adj = -2;
 884         rps->last_adj = adj;
 885         rps->cur_freq = max_t(int, rps->cur_freq + adj, rps->min_freq);
 886
 887         GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq);
 888 }
 889
 890 void intel_rps_boost(struct i915_request *rq)
 891 {
 892         struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps;
 893         unsigned long flags;
 894
 895         if (i915_request_signaled(rq) || !intel_rps_is_active(rps))
 896                 return;
 897
 898         /* Serializes with i915_request_retire() */
 899         spin_lock_irqsave(&rq->lock, flags);
 900         if (!i915_request_has_waitboost(rq) &&
 901             !dma_fence_is_signaled_locked(&rq->fence)) {
 902                 set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags);
 903
 904                 GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n",
 905                          rq->fence.context, rq->fence.seqno);
 906
 907                 if (!atomic_fetch_inc(&rps->num_waiters) &&
 908                     READ_ONCE(rps->cur_freq) < rps->boost_freq)
 909                         schedule_work(&rps->work);
 910
 911                 atomic_inc(&rps->boosts);
 912         }
 913         spin_unlock_irqrestore(&rq->lock, flags);
 914 }
 915
 916 int intel_rps_set(struct intel_rps *rps, u8 val)
 917 {
 918         int err;
 919
 920         lockdep_assert_held(&rps->lock);
 921         GEM_BUG_ON(val > rps->max_freq);
 922         GEM_BUG_ON(val < rps->min_freq);
 923
 924         if (intel_rps_is_active(rps)) {
 925                 err = rps_set(rps, val, true);
 926                 if (err)
 927                         return err;
 928
 929                 /*
 930                  * Make sure we continue to get interrupts
 931                  * until we hit the minimum or maximum frequencies.
 932                  */
 933                 if (intel_rps_has_interrupts(rps)) {
 934                         struct intel_uncore *uncore = rps_to_uncore(rps);
 935
 936                         set(uncore,
 937                             GEN6_RP_INTERRUPT_LIMITS, rps_limits(rps, val));
 938
 939                         set(uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, val));
 940                 }
 941         }
 942
 943         rps->cur_freq = val;
 944         return 0;
 945 }
 946
 947 static void gen6_rps_init(struct intel_rps *rps)
 948 {
 949         struct drm_i915_private *i915 = rps_to_i915(rps);
 950         struct intel_uncore *uncore = rps_to_uncore(rps);
 951
 952         /* All of these values are in units of 50MHz */
 953
 954         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
 955         if (IS_GEN9_LP(i915)) {
 956                 u32 rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
 957
 958                 rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
 959                 rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
 960                 rps->min_freq = (rp_state_cap >>  0) & 0xff;
 961         } else {
 962                 u32 rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
 963
 964                 rps->rp0_freq = (rp_state_cap >>  0) & 0xff;
 965                 rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
 966                 rps->min_freq = (rp_state_cap >> 16) & 0xff;
 967         }
 968
 969         /* hw_max = RP0 until we check for overclocking */
 970         rps->max_freq = rps->rp0_freq;
 971
 972         rps->efficient_freq = rps->rp1_freq;
 973         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
 974             IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
 975                 u32 ddcc_status = 0;
 976
 977                 if (sandybridge_pcode_read(i915,
 978                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
 979                                            &ddcc_status, NULL) == 0)
 980                         rps->efficient_freq =
 981                                 clamp_t(u8,
 982                                         (ddcc_status >> 8) & 0xff,
 983                                         rps->min_freq,
 984                                         rps->max_freq);
 985         }
 986
 987         if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
 988                 /* Store the frequency values in 16.66 MHZ units, which is
 989                  * the natural hardware unit for SKL
 990                  */
 991                 rps->rp0_freq *= GEN9_FREQ_SCALER;
 992                 rps->rp1_freq *= GEN9_FREQ_SCALER;
 993                 rps->min_freq *= GEN9_FREQ_SCALER;
 994                 rps->max_freq *= GEN9_FREQ_SCALER;
 995                 rps->efficient_freq *= GEN9_FREQ_SCALER;
 996         }
 997 }
 998
 999 static bool rps_reset(struct intel_rps *rps)
1000 {
1001         struct drm_i915_private *i915 = rps_to_i915(rps);
1002
1003         /* force a reset */
1004         rps->power.mode = -1;
1005         rps->last_freq = -1;
1006
1007         if (rps_set(rps, rps->min_freq, true)) {
1008                 drm_err(&i915->drm, "Failed to reset RPS to initial values\n");
1009                 return false;
1010         }
1011
1012         rps->cur_freq = rps->min_freq;
1013         return true;
1014 }
1015
1016 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
1017 static bool gen9_rps_enable(struct intel_rps *rps)
1018 {
1019         struct intel_gt *gt = rps_to_gt(rps);
1020         struct intel_uncore *uncore = gt->uncore;
1021
1022         /* Program defaults and thresholds for RPS */
1023         if (IS_GEN(gt->i915, 9))
1024                 intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
1025                                       GEN9_FREQUENCY(rps->rp1_freq));
1026
1027         intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 0xa);
1028
1029         rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD;
1030
1031         return rps_reset(rps);
1032 }
1033
1034 static bool gen8_rps_enable(struct intel_rps *rps)
1035 {
1036         struct intel_uncore *uncore = rps_to_uncore(rps);
1037
1038         intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
1039                               HSW_FREQUENCY(rps->rp1_freq));
1040
1041         intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10);
1042
1043         rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD;
1044
1045         return rps_reset(rps);
1046 }
1047
1048 static bool gen6_rps_enable(struct intel_rps *rps)
1049 {
1050         struct intel_uncore *uncore = rps_to_uncore(rps);
1051
1052         /* Power down if completely idle for over 50ms */
1053         intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 50000);
1054         intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10);
1055
1056         rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD |
1057                           GEN6_PM_RP_DOWN_THRESHOLD |
1058                           GEN6_PM_RP_DOWN_TIMEOUT);
1059
1060         return rps_reset(rps);
1061 }
1062
1063 static int chv_rps_max_freq(struct intel_rps *rps)
1064 {
1065         struct drm_i915_private *i915 = rps_to_i915(rps);
1066         struct intel_gt *gt = rps_to_gt(rps);
1067         u32 val;
1068
1069         val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
1070
1071         switch (gt->info.sseu.eu_total) {
1072         case 8:
1073                 /* (2 * 4) config */
1074                 val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT;
1075                 break;
1076         case 12:
1077                 /* (2 * 6) config */
1078                 val >>= FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT;
1079                 break;
1080         case 16:
1081                 /* (2 * 8) config */
1082         default:
1083                 /* Setting (2 * 8) Min RP0 for any other combination */
1084                 val >>= FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT;
1085                 break;
1086         }
1087
1088         return val & FB_GFX_FREQ_FUSE_MASK;
1089 }
1090
1091 static int chv_rps_rpe_freq(struct intel_rps *rps)
1092 {
1093         struct drm_i915_private *i915 = rps_to_i915(rps);
1094         u32 val;
1095
1096         val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG);
1097         val >>= PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT;
1098
1099         return val & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
1100 }
1101
1102 static int chv_rps_guar_freq(struct intel_rps *rps)
1103 {
1104         struct drm_i915_private *i915 = rps_to_i915(rps);
1105         u32 val;
1106
1107         val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
1108
1109         return val & FB_GFX_FREQ_FUSE_MASK;
1110 }
1111
1112 static u32 chv_rps_min_freq(struct intel_rps *rps)
1113 {
1114         struct drm_i915_private *i915 = rps_to_i915(rps);
1115         u32 val;
1116
1117         val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE);
1118         val >>= FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT;
1119
1120         return val & FB_GFX_FREQ_FUSE_MASK;
1121 }
1122
1123 static bool chv_rps_enable(struct intel_rps *rps)
1124 {
1125         struct intel_uncore *uncore = rps_to_uncore(rps);
1126         struct drm_i915_private *i915 = rps_to_i915(rps);
1127         u32 val;
1128
1129         /* 1: Program defaults and thresholds for RPS*/
1130         intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000);
1131         intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400);
1132         intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000);
1133         intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000);
1134         intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000);
1135
1136         intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10);
1137
1138         /* 2: Enable RPS */
1139         intel_uncore_write_fw(uncore, GEN6_RP_CONTROL,
1140                               GEN6_RP_MEDIA_HW_NORMAL_MODE |
1141                               GEN6_RP_MEDIA_IS_GFX |
1142                               GEN6_RP_ENABLE |
1143                               GEN6_RP_UP_BUSY_AVG |
1144                               GEN6_RP_DOWN_IDLE_AVG);
1145
1146         rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD |
1147                           GEN6_PM_RP_DOWN_THRESHOLD |
1148                           GEN6_PM_RP_DOWN_TIMEOUT);
1149
1150         /* Setting Fixed Bias */
1151         vlv_punit_get(i915);
1152
1153         val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50;
1154         vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val);
1155
1156         val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
1157
1158         vlv_punit_put(i915);
1159
1160         /* RPS code assumes GPLL is used */
1161         drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
1162                       "GPLL not enabled\n");
1163
1164         drm_dbg(&i915->drm, "GPLL enabled? %s\n", yesno(val & GPLLENABLE));
1165         drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val);
1166
1167         return rps_reset(rps);
1168 }
1169
1170 static int vlv_rps_guar_freq(struct intel_rps *rps)
1171 {
1172         struct drm_i915_private *i915 = rps_to_i915(rps);
1173         u32 val, rp1;
1174
1175         val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE);
1176
1177         rp1 = val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK;
1178         rp1 >>= FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
1179
1180         return rp1;
1181 }
1182
1183 static int vlv_rps_max_freq(struct intel_rps *rps)
1184 {
1185         struct drm_i915_private *i915 = rps_to_i915(rps);
1186         u32 val, rp0;
1187
1188         val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE);
1189
1190         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
1191         /* Clamp to max */
1192         rp0 = min_t(u32, rp0, 0xea);
1193
1194         return rp0;
1195 }
1196
1197 static int vlv_rps_rpe_freq(struct intel_rps *rps)
1198 {
1199         struct drm_i915_private *i915 = rps_to_i915(rps);
1200         u32 val, rpe;
1201
1202         val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
1203         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
1204         val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
1205         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
1206
1207         return rpe;
1208 }
1209
1210 static int vlv_rps_min_freq(struct intel_rps *rps)
1211 {
1212         struct drm_i915_private *i915 = rps_to_i915(rps);
1213         u32 val;
1214
1215         val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff;
1216         /*
1217          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
1218          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
1219          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
1220          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
1221          * to make sure it matches what Punit accepts.
1222          */
1223         return max_t(u32, val, 0xc0);
1224 }
1225
1226 static bool vlv_rps_enable(struct intel_rps *rps)
1227 {
1228         struct intel_uncore *uncore = rps_to_uncore(rps);
1229         struct drm_i915_private *i915 = rps_to_i915(rps);
1230         u32 val;
1231
1232         intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000);
1233         intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400);
1234         intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000);
1235         intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000);
1236         intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000);
1237
1238         intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10);
1239
1240         intel_uncore_write_fw(uncore, GEN6_RP_CONTROL,
1241                               GEN6_RP_MEDIA_TURBO |
1242                               GEN6_RP_MEDIA_HW_NORMAL_MODE |
1243                               GEN6_RP_MEDIA_IS_GFX |
1244                               GEN6_RP_ENABLE |
1245                               GEN6_RP_UP_BUSY_AVG |
1246                               GEN6_RP_DOWN_IDLE_CONT);
1247
1248         /* WaGsvRC0ResidencyMethod:vlv */
1249         rps->pm_events = GEN6_PM_RP_UP_EI_EXPIRED;
1250
1251         vlv_punit_get(i915);
1252
1253         /* Setting Fixed Bias */
1254         val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875;
1255         vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val);
1256
1257         val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
1258
1259         vlv_punit_put(i915);
1260
1261         /* RPS code assumes GPLL is used */
1262         drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
1263                       "GPLL not enabled\n");
1264
1265         drm_dbg(&i915->drm, "GPLL enabled? %s\n", yesno(val & GPLLENABLE));
1266         drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val);
1267
1268         return rps_reset(rps);
1269 }
1270
1271 static unsigned long __ips_gfx_val(struct intel_ips *ips)
1272 {
1273         struct intel_rps *rps = container_of(ips, typeof(*rps), ips);
1274         struct intel_uncore *uncore = rps_to_uncore(rps);
1275         unsigned long t, corr, state1, corr2, state2;
1276         u32 pxvid, ext_v;
1277
1278         lockdep_assert_held(&mchdev_lock);
1279
1280         pxvid = intel_uncore_read(uncore, PXVFREQ(rps->cur_freq));
1281         pxvid = (pxvid >> 24) & 0x7f;
1282         ext_v = pvid_to_extvid(rps_to_i915(rps), pxvid);
1283
1284         state1 = ext_v;
1285
1286         /* Revel in the empirically derived constants */
1287
1288         /* Correction factor in 1/100000 units */
1289         t = ips_mch_val(uncore);
1290         if (t > 80)
1291                 corr = t * 2349 + 135940;
1292         else if (t >= 50)
1293                 corr = t * 964 + 29317;
1294         else /* < 50 */
1295                 corr = t * 301 + 1004;
1296
1297         corr = corr * 150142 * state1 / 10000 - 78642;
1298         corr /= 100000;
1299         corr2 = corr * ips->corr;
1300
1301         state2 = corr2 * state1 / 10000;
1302         state2 /= 100; /* convert to mW */
1303
1304         __gen5_ips_update(ips);
1305
1306         return ips->gfx_power + state2;
1307 }
1308
1309 static bool has_busy_stats(struct intel_rps *rps)
1310 {
1311         struct intel_engine_cs *engine;
1312         enum intel_engine_id id;
1313
1314         for_each_engine(engine, rps_to_gt(rps), id) {
1315                 if (!intel_engine_supports_stats(engine))
1316                         return false;
1317         }
1318
1319         return true;
1320 }
1321
1322 void intel_rps_enable(struct intel_rps *rps)
1323 {
1324         struct drm_i915_private *i915 = rps_to_i915(rps);
1325         struct intel_uncore *uncore = rps_to_uncore(rps);
1326         bool enabled = false;
1327
1328         if (!HAS_RPS(i915))
1329                 return;
1330
1331         intel_gt_check_clock_frequency(rps_to_gt(rps));
1332
1333         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1334         if (rps->max_freq <= rps->min_freq)
1335                 /* leave disabled, no room for dynamic reclocking */;
1336         else if (IS_CHERRYVIEW(i915))
1337                 enabled = chv_rps_enable(rps);
1338         else if (IS_VALLEYVIEW(i915))
1339                 enabled = vlv_rps_enable(rps);
1340         else if (INTEL_GEN(i915) >= 9)
1341                 enabled = gen9_rps_enable(rps);
1342         else if (INTEL_GEN(i915) >= 8)
1343                 enabled = gen8_rps_enable(rps);
1344         else if (INTEL_GEN(i915) >= 6)
1345                 enabled = gen6_rps_enable(rps);
1346         else if (IS_IRONLAKE_M(i915))
1347                 enabled = gen5_rps_enable(rps);
1348         else
1349                 MISSING_CASE(INTEL_GEN(i915));
1350         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1351         if (!enabled)
1352                 return;
1353
1354         GT_TRACE(rps_to_gt(rps),
1355                  "min:%x, max:%x, freq:[%d, %d]\n",
1356                  rps->min_freq, rps->max_freq,
1357                  intel_gpu_freq(rps, rps->min_freq),
1358                  intel_gpu_freq(rps, rps->max_freq));
1359
1360         GEM_BUG_ON(rps->max_freq < rps->min_freq);
1361         GEM_BUG_ON(rps->idle_freq > rps->max_freq);
1362
1363         GEM_BUG_ON(rps->efficient_freq < rps->min_freq);
1364         GEM_BUG_ON(rps->efficient_freq > rps->max_freq);
1365
1366         if (has_busy_stats(rps))
1367                 intel_rps_set_timer(rps);
1368         else if (INTEL_GEN(i915) >= 6)
1369                 intel_rps_set_interrupts(rps);
1370         else
1371                 /* Ironlake currently uses intel_ips.ko */ {}
1372
1373         intel_rps_set_enabled(rps);
1374 }
1375
1376 static void gen6_rps_disable(struct intel_rps *rps)
1377 {
1378         set(rps_to_uncore(rps), GEN6_RP_CONTROL, 0);
1379 }
1380
1381 void intel_rps_disable(struct intel_rps *rps)
1382 {
1383         struct drm_i915_private *i915 = rps_to_i915(rps);
1384
1385         intel_rps_clear_enabled(rps);
1386         intel_rps_clear_interrupts(rps);
1387         intel_rps_clear_timer(rps);
1388
1389         if (INTEL_GEN(i915) >= 6)
1390                 gen6_rps_disable(rps);
1391         else if (IS_IRONLAKE_M(i915))
1392                 gen5_rps_disable(rps);
1393 }
1394
1395 static int byt_gpu_freq(struct intel_rps *rps, int val)
1396 {
1397         /*
1398          * N = val - 0xb7
1399          * Slow = Fast = GPLL ref * N
1400          */
1401         return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000);
1402 }
1403
1404 static int byt_freq_opcode(struct intel_rps *rps, int val)
1405 {
1406         return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
1407 }
1408
1409 static int chv_gpu_freq(struct intel_rps *rps, int val)
1410 {
1411         /*
1412          * N = val / 2
1413          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
1414          */
1415         return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000);
1416 }
1417
1418 static int chv_freq_opcode(struct intel_rps *rps, int val)
1419 {
1420         /* CHV needs even values */
1421         return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
1422 }
1423
1424 int intel_gpu_freq(struct intel_rps *rps, int val)
1425 {
1426         struct drm_i915_private *i915 = rps_to_i915(rps);
1427
1428         if (INTEL_GEN(i915) >= 9)
1429                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
1430                                          GEN9_FREQ_SCALER);
1431         else if (IS_CHERRYVIEW(i915))
1432                 return chv_gpu_freq(rps, val);
1433         else if (IS_VALLEYVIEW(i915))
1434                 return byt_gpu_freq(rps, val);
1435         else
1436                 return val * GT_FREQUENCY_MULTIPLIER;
1437 }
1438
1439 int intel_freq_opcode(struct intel_rps *rps, int val)
1440 {
1441         struct drm_i915_private *i915 = rps_to_i915(rps);
1442
1443         if (INTEL_GEN(i915) >= 9)
1444                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
1445                                          GT_FREQUENCY_MULTIPLIER);
1446         else if (IS_CHERRYVIEW(i915))
1447                 return chv_freq_opcode(rps, val);
1448         else if (IS_VALLEYVIEW(i915))
1449                 return byt_freq_opcode(rps, val);
1450         else
1451                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
1452 }
1453
1454 static void vlv_init_gpll_ref_freq(struct intel_rps *rps)
1455 {
1456         struct drm_i915_private *i915 = rps_to_i915(rps);
1457
1458         rps->gpll_ref_freq =
1459                 vlv_get_cck_clock(i915, "GPLL ref",
1460                                   CCK_GPLL_CLOCK_CONTROL,
1461                                   i915->czclk_freq);
1462
1463         drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n",
1464                 rps->gpll_ref_freq);
1465 }
1466
1467 static void vlv_rps_init(struct intel_rps *rps)
1468 {
1469         struct drm_i915_private *i915 = rps_to_i915(rps);
1470         u32 val;
1471
1472         vlv_iosf_sb_get(i915,
1473                         BIT(VLV_IOSF_SB_PUNIT) |
1474                         BIT(VLV_IOSF_SB_NC) |
1475                         BIT(VLV_IOSF_SB_CCK));
1476
1477         vlv_init_gpll_ref_freq(rps);
1478
1479         val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
1480         switch ((val >> 6) & 3) {
1481         case 0:
1482         case 1:
1483                 i915->mem_freq = 800;
1484                 break;
1485         case 2:
1486                 i915->mem_freq = 1066;
1487                 break;
1488         case 3:
1489                 i915->mem_freq = 1333;
1490                 break;
1491         }
1492         drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
1493
1494         rps->max_freq = vlv_rps_max_freq(rps);
1495         rps->rp0_freq = rps->max_freq;
1496         drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",
1497                 intel_gpu_freq(rps, rps->max_freq), rps->max_freq);
1498
1499         rps->efficient_freq = vlv_rps_rpe_freq(rps);
1500         drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n",
1501                 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq);
1502
1503         rps->rp1_freq = vlv_rps_guar_freq(rps);
1504         drm_dbg(&i915->drm, "RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
1505                 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq);
1506
1507         rps->min_freq = vlv_rps_min_freq(rps);
1508         drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n",
1509                 intel_gpu_freq(rps, rps->min_freq), rps->min_freq);
1510
1511         vlv_iosf_sb_put(i915,
1512                         BIT(VLV_IOSF_SB_PUNIT) |
1513                         BIT(VLV_IOSF_SB_NC) |
1514                         BIT(VLV_IOSF_SB_CCK));
1515 }
1516
1517 static void chv_rps_init(struct intel_rps *rps)
1518 {
1519         struct drm_i915_private *i915 = rps_to_i915(rps);
1520         u32 val;
1521
1522         vlv_iosf_sb_get(i915,
1523                         BIT(VLV_IOSF_SB_PUNIT) |
1524                         BIT(VLV_IOSF_SB_NC) |
1525                         BIT(VLV_IOSF_SB_CCK));
1526
1527         vlv_init_gpll_ref_freq(rps);
1528
1529         val = vlv_cck_read(i915, CCK_FUSE_REG);
1530
1531         switch ((val >> 2) & 0x7) {
1532         case 3:
1533                 i915->mem_freq = 2000;
1534                 break;
1535         default:
1536                 i915->mem_freq = 1600;
1537                 break;
1538         }
1539         drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
1540
1541         rps->max_freq = chv_rps_max_freq(rps);
1542         rps->rp0_freq = rps->max_freq;
1543         drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",
1544                 intel_gpu_freq(rps, rps->max_freq), rps->max_freq);
1545
1546         rps->efficient_freq = chv_rps_rpe_freq(rps);
1547         drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n",
1548                 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq);
1549
1550         rps->rp1_freq = chv_rps_guar_freq(rps);
1551         drm_dbg(&i915->drm, "RP1(Guar) GPU freq: %d MHz (%u)\n",
1552                 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq);
1553
1554         rps->min_freq = chv_rps_min_freq(rps);
1555         drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n",
1556                 intel_gpu_freq(rps, rps->min_freq), rps->min_freq);
1557
1558         vlv_iosf_sb_put(i915,
1559                         BIT(VLV_IOSF_SB_PUNIT) |
1560                         BIT(VLV_IOSF_SB_NC) |
1561                         BIT(VLV_IOSF_SB_CCK));
1562
1563         drm_WARN_ONCE(&i915->drm, (rps->max_freq | rps->efficient_freq |
1564                                    rps->rp1_freq | rps->min_freq) & 1,
1565                       "Odd GPU freq values\n");
1566 }
1567
1568 static void vlv_c0_read(struct intel_uncore *uncore, struct intel_rps_ei *ei)
1569 {
1570         ei->ktime = ktime_get_raw();
1571         ei->render_c0 = intel_uncore_read(uncore, VLV_RENDER_C0_COUNT);
1572         ei->media_c0 = intel_uncore_read(uncore, VLV_MEDIA_C0_COUNT);
1573 }
1574
1575 static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir)
1576 {
1577         struct intel_uncore *uncore = rps_to_uncore(rps);
1578         const struct intel_rps_ei *prev = &rps->ei;
1579         struct intel_rps_ei now;
1580         u32 events = 0;
1581
1582         if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1583                 return 0;
1584
1585         vlv_c0_read(uncore, &now);
1586
1587         if (prev->ktime) {
1588                 u64 time, c0;
1589                 u32 render, media;
1590
1591                 time = ktime_us_delta(now.ktime, prev->ktime);
1592
1593                 time *= rps_to_i915(rps)->czclk_freq;
1594
1595                 /* Workload can be split between render + media,
1596                  * e.g. SwapBuffers being blitted in X after being rendered in
1597                  * mesa. To account for this we need to combine both engines
1598                  * into our activity counter.
1599                  */
1600                 render = now.render_c0 - prev->render_c0;
1601                 media = now.media_c0 - prev->media_c0;
1602                 c0 = max(render, media);
1603                 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1604
1605                 if (c0 > time * rps->power.up_threshold)
1606                         events = GEN6_PM_RP_UP_THRESHOLD;
1607                 else if (c0 < time * rps->power.down_threshold)
1608                         events = GEN6_PM_RP_DOWN_THRESHOLD;
1609         }
1610
1611         rps->ei = now;
1612         return events;
1613 }
1614
1615 static void rps_work(struct work_struct *work)
1616 {
1617         struct intel_rps *rps = container_of(work, typeof(*rps), work);
1618         struct intel_gt *gt = rps_to_gt(rps);
1619         struct drm_i915_private *i915 = rps_to_i915(rps);
1620         bool client_boost = false;
1621         int new_freq, adj, min, max;
1622         u32 pm_iir = 0;
1623
1624         spin_lock_irq(&gt->irq_lock);
1625         pm_iir = fetch_and_zero(&rps->pm_iir) & rps->pm_events;
1626         client_boost = atomic_read(&rps->num_waiters);
1627         spin_unlock_irq(&gt->irq_lock);
1628
1629         /* Make sure we didn't queue anything we're not going to process. */
1630         if (!pm_iir && !client_boost)
1631                 goto out;
1632
1633         mutex_lock(&rps->lock);
1634         if (!intel_rps_is_active(rps)) {
1635                 mutex_unlock(&rps->lock);
1636                 return;
1637         }
1638
1639         pm_iir |= vlv_wa_c0_ei(rps, pm_iir);
1640
1641         adj = rps->last_adj;
1642         new_freq = rps->cur_freq;
1643         min = rps->min_freq_softlimit;
1644         max = rps->max_freq_softlimit;
1645         if (client_boost)
1646                 max = rps->max_freq;
1647
1648         GT_TRACE(gt,
1649                  "pm_iir:%x, client_boost:%s, last:%d, cur:%x, min:%x, max:%x\n",
1650                  pm_iir, yesno(client_boost),
1651                  adj, new_freq, min, max);
1652
1653         if (client_boost && new_freq < rps->boost_freq) {
1654                 new_freq = rps->boost_freq;
1655                 adj = 0;
1656         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1657                 if (adj > 0)
1658                         adj *= 2;
1659                 else /* CHV needs even encode values */
1660                         adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1;
1661
1662                 if (new_freq >= rps->max_freq_softlimit)
1663                         adj = 0;
1664         } else if (client_boost) {
1665                 adj = 0;
1666         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1667                 if (rps->cur_freq > rps->efficient_freq)
1668                         new_freq = rps->efficient_freq;
1669                 else if (rps->cur_freq > rps->min_freq_softlimit)
1670                         new_freq = rps->min_freq_softlimit;
1671                 adj = 0;
1672         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1673                 if (adj < 0)
1674                         adj *= 2;
1675                 else /* CHV needs even encode values */
1676                         adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1;
1677
1678                 if (new_freq <= rps->min_freq_softlimit)
1679                         adj = 0;
1680         } else { /* unknown event */
1681                 adj = 0;
1682         }
1683
1684         /*
1685          * sysfs frequency limits may have snuck in while
1686          * servicing the interrupt
1687          */
1688         new_freq += adj;
1689         new_freq = clamp_t(int, new_freq, min, max);
1690
1691         if (intel_rps_set(rps, new_freq)) {
1692                 drm_dbg(&i915->drm, "Failed to set new GPU frequency\n");
1693                 adj = 0;
1694         }
1695         rps->last_adj = adj;
1696
1697         mutex_unlock(&rps->lock);
1698
1699 out:
1700         spin_lock_irq(&gt->irq_lock);
1701         gen6_gt_pm_unmask_irq(gt, rps->pm_events);
1702         spin_unlock_irq(&gt->irq_lock);
1703 }
1704
1705 void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
1706 {
1707         struct intel_gt *gt = rps_to_gt(rps);
1708         const u32 events = rps->pm_events & pm_iir;
1709
1710         lockdep_assert_held(&gt->irq_lock);
1711
1712         if (unlikely(!events))
1713                 return;
1714
1715         GT_TRACE(gt, "irq events:%x\n", events);
1716
1717         gen6_gt_pm_mask_irq(gt, events);
1718
1719         rps->pm_iir |= events;
1720         schedule_work(&rps->work);
1721 }
1722
1723 void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
1724 {
1725         struct intel_gt *gt = rps_to_gt(rps);
1726         u32 events;
1727
1728         events = pm_iir & rps->pm_events;
1729         if (events) {
1730                 spin_lock(&gt->irq_lock);
1731
1732                 GT_TRACE(gt, "irq events:%x\n", events);
1733
1734                 gen6_gt_pm_mask_irq(gt, events);
1735                 rps->pm_iir |= events;
1736
1737                 schedule_work(&rps->work);
1738                 spin_unlock(&gt->irq_lock);
1739         }
1740
1741         if (INTEL_GEN(gt->i915) >= 8)
1742                 return;
1743
1744         if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1745                 intel_engine_signal_breadcrumbs(gt->engine[VECS0]);
1746
1747         if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1748                 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1749 }
1750
1751 void gen5_rps_irq_handler(struct intel_rps *rps)
1752 {
1753         struct intel_uncore *uncore = rps_to_uncore(rps);
1754         u32 busy_up, busy_down, max_avg, min_avg;
1755         u8 new_freq;
1756
1757         spin_lock(&mchdev_lock);
1758
1759         intel_uncore_write16(uncore,
1760                              MEMINTRSTS,
1761                              intel_uncore_read(uncore, MEMINTRSTS));
1762
1763         intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
1764         busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG);
1765         busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG);
1766         max_avg = intel_uncore_read(uncore, RCBMAXAVG);
1767         min_avg = intel_uncore_read(uncore, RCBMINAVG);
1768
1769         /* Handle RCS change request from hw */
1770         new_freq = rps->cur_freq;
1771         if (busy_up > max_avg)
1772                 new_freq++;
1773         else if (busy_down < min_avg)
1774                 new_freq--;
1775         new_freq = clamp(new_freq,
1776                          rps->min_freq_softlimit,
1777                          rps->max_freq_softlimit);
1778
1779         if (new_freq != rps->cur_freq && gen5_rps_set(rps, new_freq))
1780                 rps->cur_freq = new_freq;
1781
1782         spin_unlock(&mchdev_lock);
1783 }
1784
1785 void intel_rps_init_early(struct intel_rps *rps)
1786 {
1787         mutex_init(&rps->lock);
1788         mutex_init(&rps->power.mutex);
1789
1790         INIT_WORK(&rps->work, rps_work);
1791         timer_setup(&rps->timer, rps_timer, 0);
1792
1793         atomic_set(&rps->num_waiters, 0);
1794 }
1795
1796 void intel_rps_init(struct intel_rps *rps)
1797 {
1798         struct drm_i915_private *i915 = rps_to_i915(rps);
1799
1800         if (IS_CHERRYVIEW(i915))
1801                 chv_rps_init(rps);
1802         else if (IS_VALLEYVIEW(i915))
1803                 vlv_rps_init(rps);
1804         else if (INTEL_GEN(i915) >= 6)
1805                 gen6_rps_init(rps);
1806         else if (IS_IRONLAKE_M(i915))
1807                 gen5_rps_init(rps);
1808
1809         /* Derive initial user preferences/limits from the hardware limits */
1810         rps->max_freq_softlimit = rps->max_freq;
1811         rps->min_freq_softlimit = rps->min_freq;
1812
1813         /* After setting max-softlimit, find the overclock max freq */
1814         if (IS_GEN(i915, 6) || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
1815                 u32 params = 0;
1816
1817                 sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
1818                                        &params, NULL);
1819                 if (params & BIT(31)) { /* OC supported */
1820                         drm_dbg(&i915->drm,
1821                                 "Overclocking supported, max: %dMHz, overclock: %dMHz\n",
1822                                 (rps->max_freq & 0xff) * 50,
1823                                 (params & 0xff) * 50);
1824                         rps->max_freq = params & 0xff;
1825                 }
1826         }
1827
1828         /* Finally allow us to boost to max by default */
1829         rps->boost_freq = rps->max_freq;
1830         rps->idle_freq = rps->min_freq;
1831
1832         /* Start in the middle, from here we will autotune based on workload */
1833         rps->cur_freq = rps->efficient_freq;
1834
1835         rps->pm_intrmsk_mbz = 0;
1836
1837         /*
1838          * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
1839          * if GEN6_PM_UP_EI_EXPIRED is masked.
1840          *
1841          * TODO: verify if this can be reproduced on VLV,CHV.
1842          */
1843         if (INTEL_GEN(i915) <= 7)
1844                 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
1845
1846         if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
1847                 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
1848 }
1849
1850 void intel_rps_sanitize(struct intel_rps *rps)
1851 {
1852         if (INTEL_GEN(rps_to_i915(rps)) >= 6)
1853                 rps_disable_interrupts(rps);
1854 }
1855
1856 u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
1857 {
1858         struct drm_i915_private *i915 = rps_to_i915(rps);
1859         u32 cagf;
1860
1861         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1862                 cagf = (rpstat >> 8) & 0xff;
1863         else if (INTEL_GEN(i915) >= 9)
1864                 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1865         else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
1866                 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1867         else
1868                 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1869
1870         return cagf;
1871 }
1872
1873 static u32 read_cagf(struct intel_rps *rps)
1874 {
1875         struct drm_i915_private *i915 = rps_to_i915(rps);
1876         u32 freq;
1877
1878         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1879                 vlv_punit_get(i915);
1880                 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
1881                 vlv_punit_put(i915);
1882         } else {
1883                 freq = intel_uncore_read(rps_to_uncore(rps), GEN6_RPSTAT1);
1884         }
1885
1886         return intel_rps_get_cagf(rps, freq);
1887 }
1888
1889 u32 intel_rps_read_actual_frequency(struct intel_rps *rps)
1890 {
1891         struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm;
1892         intel_wakeref_t wakeref;
1893         u32 freq = 0;
1894
1895         with_intel_runtime_pm_if_in_use(rpm, wakeref)
1896                 freq = intel_gpu_freq(rps, read_cagf(rps));
1897
1898         return freq;
1899 }
1900
1901 /* External interface for intel_ips.ko */
1902
1903 static struct drm_i915_private __rcu *ips_mchdev;
1904
1905 /**
1906  * Tells the intel_ips driver that the i915 driver is now loaded, if
1907  * IPS got loaded first.
1908  *
1909  * This awkward dance is so that neither module has to depend on the
1910  * other in order for IPS to do the appropriate communication of
1911  * GPU turbo limits to i915.
1912  */
1913 static void
1914 ips_ping_for_i915_load(void)
1915 {
1916         void (*link)(void);
1917
1918         link = symbol_get(ips_link_to_i915_driver);
1919         if (link) {
1920                 link();
1921                 symbol_put(ips_link_to_i915_driver);
1922         }
1923 }
1924
1925 void intel_rps_driver_register(struct intel_rps *rps)
1926 {
1927         struct intel_gt *gt = rps_to_gt(rps);
1928
1929         /*
1930          * We only register the i915 ips part with intel-ips once everything is
1931          * set up, to avoid intel-ips sneaking in and reading bogus values.
1932          */
1933         if (IS_GEN(gt->i915, 5)) {
1934                 GEM_BUG_ON(ips_mchdev);
1935                 rcu_assign_pointer(ips_mchdev, gt->i915);
1936                 ips_ping_for_i915_load();
1937         }
1938 }
1939
1940 void intel_rps_driver_unregister(struct intel_rps *rps)
1941 {
1942         if (rcu_access_pointer(ips_mchdev) == rps_to_i915(rps))
1943                 rcu_assign_pointer(ips_mchdev, NULL);
1944 }
1945
1946 static struct drm_i915_private *mchdev_get(void)
1947 {
1948         struct drm_i915_private *i915;
1949
1950         rcu_read_lock();
1951         i915 = rcu_dereference(ips_mchdev);
1952         if (!kref_get_unless_zero(&i915->drm.ref))
1953                 i915 = NULL;
1954         rcu_read_unlock();
1955
1956         return i915;
1957 }
1958
1959 /**
1960  * i915_read_mch_val - return value for IPS use
1961  *
1962  * Calculate and return a value for the IPS driver to use when deciding whether
1963  * we have thermal and power headroom to increase CPU or GPU power budget.
1964  */
1965 unsigned long i915_read_mch_val(void)
1966 {
1967         struct drm_i915_private *i915;
1968         unsigned long chipset_val = 0;
1969         unsigned long graphics_val = 0;
1970         intel_wakeref_t wakeref;
1971
1972         i915 = mchdev_get();
1973         if (!i915)
1974                 return 0;
1975
1976         with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
1977                 struct intel_ips *ips = &i915->gt.rps.ips;
1978
1979                 spin_lock_irq(&mchdev_lock);
1980                 chipset_val = __ips_chipset_val(ips);
1981                 graphics_val = __ips_gfx_val(ips);
1982                 spin_unlock_irq(&mchdev_lock);
1983         }
1984
1985         drm_dev_put(&i915->drm);
1986         return chipset_val + graphics_val;
1987 }
1988 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1989
1990 /**
1991  * i915_gpu_raise - raise GPU frequency limit
1992  *
1993  * Raise the limit; IPS indicates we have thermal headroom.
1994  */
1995 bool i915_gpu_raise(void)
1996 {
1997         struct drm_i915_private *i915;
1998         struct intel_rps *rps;
1999
2000         i915 = mchdev_get();
2001         if (!i915)
2002                 return false;
2003
2004         rps = &i915->gt.rps;
2005
2006         spin_lock_irq(&mchdev_lock);
2007         if (rps->max_freq_softlimit < rps->max_freq)
2008                 rps->max_freq_softlimit++;
2009         spin_unlock_irq(&mchdev_lock);
2010
2011         drm_dev_put(&i915->drm);
2012         return true;
2013 }
2014 EXPORT_SYMBOL_GPL(i915_gpu_raise);
2015
2016 /**
2017  * i915_gpu_lower - lower GPU frequency limit
2018  *
2019  * IPS indicates we're close to a thermal limit, so throttle back the GPU
2020  * frequency maximum.
2021  */
2022 bool i915_gpu_lower(void)
2023 {
2024         struct drm_i915_private *i915;
2025         struct intel_rps *rps;
2026
2027         i915 = mchdev_get();
2028         if (!i915)
2029                 return false;
2030
2031         rps = &i915->gt.rps;
2032
2033         spin_lock_irq(&mchdev_lock);
2034         if (rps->max_freq_softlimit > rps->min_freq)
2035                 rps->max_freq_softlimit--;
2036         spin_unlock_irq(&mchdev_lock);
2037
2038         drm_dev_put(&i915->drm);
2039         return true;
2040 }
2041 EXPORT_SYMBOL_GPL(i915_gpu_lower);
2042
2043 /**
2044  * i915_gpu_busy - indicate GPU business to IPS
2045  *
2046  * Tell the IPS driver whether or not the GPU is busy.
2047  */
2048 bool i915_gpu_busy(void)
2049 {
2050         struct drm_i915_private *i915;
2051         bool ret;
2052
2053         i915 = mchdev_get();
2054         if (!i915)
2055                 return false;
2056
2057         ret = i915->gt.awake;
2058
2059         drm_dev_put(&i915->drm);
2060         return ret;
2061 }
2062 EXPORT_SYMBOL_GPL(i915_gpu_busy);
2063
2064 /**
2065  * i915_gpu_turbo_disable - disable graphics turbo
2066  *
2067  * Disable graphics turbo by resetting the max frequency and setting the
2068  * current frequency to the default.
2069  */
2070 bool i915_gpu_turbo_disable(void)
2071 {
2072         struct drm_i915_private *i915;
2073         struct intel_rps *rps;
2074         bool ret;
2075
2076         i915 = mchdev_get();
2077         if (!i915)
2078                 return false;
2079
2080         rps = &i915->gt.rps;
2081
2082         spin_lock_irq(&mchdev_lock);
2083         rps->max_freq_softlimit = rps->min_freq;
2084         ret = gen5_rps_set(&i915->gt.rps, rps->min_freq);
2085         spin_unlock_irq(&mchdev_lock);
2086
2087         drm_dev_put(&i915->drm);
2088         return ret;
2089 }
2090 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2091
2092 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2093 #include "selftest_rps.c"
2094 #endif