drivers/gpu/drm/i915/gt/intel_reset.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2008-2018 Intel Corporation
   4  */
   5
   6 #include <linux/sched/mm.h>
   7 #include <linux/stop_machine.h>
   8
   9 #include "display/intel_display_types.h"
  10 #include "display/intel_overlay.h"
  11
  12 #include "gem/i915_gem_context.h"
  13
  14 #include "i915_drv.h"
  15 #include "i915_gpu_error.h"
  16 #include "i915_irq.h"
  17 #include "intel_breadcrumbs.h"
  18 #include "intel_engine_pm.h"
  19 #include "intel_gt.h"
  20 #include "intel_gt_pm.h"
  21 #include "intel_gt_requests.h"
  22 #include "intel_reset.h"
  23
  24 #include "uc/intel_guc.h"
  25
  26 #define RESET_MAX_RETRIES 3
  27
  28 /* XXX How to handle concurrent GGTT updates using tiling registers? */
  29 #define RESET_UNDER_STOP_MACHINE 0
  30
  31 static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
  32 {
  33         intel_uncore_rmw_fw(uncore, reg, 0, set);
  34 }
  35
  36 static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
  37 {
  38         intel_uncore_rmw_fw(uncore, reg, clr, 0);
  39 }
  40
  41 static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
  42 {
  43         struct drm_i915_file_private *file_priv = ctx->file_priv;
  44         unsigned long prev_hang;
  45         unsigned int score;
  46
  47         if (IS_ERR_OR_NULL(file_priv))
  48                 return;
  49
  50         score = 0;
  51         if (banned)
  52                 score = I915_CLIENT_SCORE_CONTEXT_BAN;
  53
  54         prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
  55         if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
  56                 score += I915_CLIENT_SCORE_HANG_FAST;
  57
  58         if (score) {
  59                 atomic_add(score, &file_priv->ban_score);
  60
  61                 drm_dbg(&ctx->i915->drm,
  62                         "client %s: gained %u ban score, now %u\n",
  63                         ctx->name, score,
  64                         atomic_read(&file_priv->ban_score));
  65         }
  66 }
  67
  68 static bool mark_guilty(struct i915_request *rq)
  69 {
  70         struct i915_gem_context *ctx;
  71         unsigned long prev_hang;
  72         bool banned;
  73         int i;
  74
  75         if (intel_context_is_closed(rq->context))
  76                 return true;
  77
  78         rcu_read_lock();
  79         ctx = rcu_dereference(rq->context->gem_context);
  80         if (ctx && !kref_get_unless_zero(&ctx->ref))
  81                 ctx = NULL;
  82         rcu_read_unlock();
  83         if (!ctx)
  84                 return intel_context_is_banned(rq->context);
  85
  86         atomic_inc(&ctx->guilty_count);
  87
  88         /* Cool contexts are too cool to be banned! (Used for reset testing.) */
  89         if (!i915_gem_context_is_bannable(ctx)) {
  90                 banned = false;
  91                 goto out;
  92         }
  93
  94         drm_notice(&ctx->i915->drm,
  95                    "%s context reset due to GPU hang\n",
  96                    ctx->name);
  97
  98         /* Record the timestamp for the last N hangs */
  99         prev_hang = ctx->hang_timestamp[0];
 100         for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
 101                 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
 102         ctx->hang_timestamp[i] = jiffies;
 103
 104         /* If we have hung N+1 times in rapid succession, we ban the context! */
 105         banned = !i915_gem_context_is_recoverable(ctx);
 106         if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
 107                 banned = true;
 108         if (banned)
 109                 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
 110                         ctx->name, atomic_read(&ctx->guilty_count));
 111
 112         client_mark_guilty(ctx, banned);
 113
 114 out:
 115         i915_gem_context_put(ctx);
 116         return banned;
 117 }
 118
 119 static void mark_innocent(struct i915_request *rq)
 120 {
 121         struct i915_gem_context *ctx;
 122
 123         rcu_read_lock();
 124         ctx = rcu_dereference(rq->context->gem_context);
 125         if (ctx)
 126                 atomic_inc(&ctx->active_count);
 127         rcu_read_unlock();
 128 }
 129
 130 void __i915_request_reset(struct i915_request *rq, bool guilty)
 131 {
 132         bool banned = false;
 133
 134         RQ_TRACE(rq, "guilty? %s\n", yesno(guilty));
 135         GEM_BUG_ON(__i915_request_is_complete(rq));
 136
 137         rcu_read_lock(); /* protect the GEM context */
 138         if (guilty) {
 139                 i915_request_set_error_once(rq, -EIO);
 140                 __i915_request_skip(rq);
 141                 banned = mark_guilty(rq);
 142         } else {
 143                 i915_request_set_error_once(rq, -EAGAIN);
 144                 mark_innocent(rq);
 145         }
 146         rcu_read_unlock();
 147
 148         if (banned)
 149                 intel_context_ban(rq->context, rq);
 150 }
 151
 152 static bool i915_in_reset(struct pci_dev *pdev)
 153 {
 154         u8 gdrst;
 155
 156         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 157         return gdrst & GRDOM_RESET_STATUS;
 158 }
 159
 160 static int i915_do_reset(struct intel_gt *gt,
 161                          intel_engine_mask_t engine_mask,
 162                          unsigned int retry)
 163 {
 164         struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
 165         int err;
 166
 167         /* Assert reset for at least 20 usec, and wait for acknowledgement. */
 168         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 169         udelay(50);
 170         err = wait_for_atomic(i915_in_reset(pdev), 50);
 171
 172         /* Clear the reset request. */
 173         pci_write_config_byte(pdev, I915_GDRST, 0);
 174         udelay(50);
 175         if (!err)
 176                 err = wait_for_atomic(!i915_in_reset(pdev), 50);
 177
 178         return err;
 179 }
 180
 181 static bool g4x_reset_complete(struct pci_dev *pdev)
 182 {
 183         u8 gdrst;
 184
 185         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 186         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 187 }
 188
 189 static int g33_do_reset(struct intel_gt *gt,
 190                         intel_engine_mask_t engine_mask,
 191                         unsigned int retry)
 192 {
 193         struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
 194
 195         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 196         return wait_for_atomic(g4x_reset_complete(pdev), 50);
 197 }
 198
 199 static int g4x_do_reset(struct intel_gt *gt,
 200                         intel_engine_mask_t engine_mask,
 201                         unsigned int retry)
 202 {
 203         struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
 204         struct intel_uncore *uncore = gt->uncore;
 205         int ret;
 206
 207         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
 208         rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
 209         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 210
 211         pci_write_config_byte(pdev, I915_GDRST,
 212                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 213         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 214         if (ret) {
 215                 GT_TRACE(gt, "Wait for media reset failed\n");
 216                 goto out;
 217         }
 218
 219         pci_write_config_byte(pdev, I915_GDRST,
 220                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
 221         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 222         if (ret) {
 223                 GT_TRACE(gt, "Wait for render reset failed\n");
 224                 goto out;
 225         }
 226
 227 out:
 228         pci_write_config_byte(pdev, I915_GDRST, 0);
 229
 230         rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
 231         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 232
 233         return ret;
 234 }
 235
 236 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
 237                         unsigned int retry)
 238 {
 239         struct intel_uncore *uncore = gt->uncore;
 240         int ret;
 241
 242         intel_uncore_write_fw(uncore, ILK_GDSR,
 243                               ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
 244         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 245                                            ILK_GRDOM_RESET_ENABLE, 0,
 246                                            5000, 0,
 247                                            NULL);
 248         if (ret) {
 249                 GT_TRACE(gt, "Wait for render reset failed\n");
 250                 goto out;
 251         }
 252
 253         intel_uncore_write_fw(uncore, ILK_GDSR,
 254                               ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
 255         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 256                                            ILK_GRDOM_RESET_ENABLE, 0,
 257                                            5000, 0,
 258                                            NULL);
 259         if (ret) {
 260                 GT_TRACE(gt, "Wait for media reset failed\n");
 261                 goto out;
 262         }
 263
 264 out:
 265         intel_uncore_write_fw(uncore, ILK_GDSR, 0);
 266         intel_uncore_posting_read_fw(uncore, ILK_GDSR);
 267         return ret;
 268 }
 269
 270 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
 271 static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
 272 {
 273         struct intel_uncore *uncore = gt->uncore;
 274         int err;
 275
 276         /*
 277          * GEN6_GDRST is not in the gt power well, no need to check
 278          * for fifo space for the write or forcewake the chip for
 279          * the read
 280          */
 281         intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
 282
 283         /* Wait for the device to ack the reset requests */
 284         err = __intel_wait_for_register_fw(uncore,
 285                                            GEN6_GDRST, hw_domain_mask, 0,
 286                                            500, 0,
 287                                            NULL);
 288         if (err)
 289                 GT_TRACE(gt,
 290                          "Wait for 0x%08x engines reset failed\n",
 291                          hw_domain_mask);
 292
 293         return err;
 294 }
 295
 296 static int gen6_reset_engines(struct intel_gt *gt,
 297                               intel_engine_mask_t engine_mask,
 298                               unsigned int retry)
 299 {
 300         static const u32 hw_engine_mask[] = {
 301                 [RCS0]  = GEN6_GRDOM_RENDER,
 302                 [BCS0]  = GEN6_GRDOM_BLT,
 303                 [VCS0]  = GEN6_GRDOM_MEDIA,
 304                 [VCS1]  = GEN8_GRDOM_MEDIA2,
 305                 [VECS0] = GEN6_GRDOM_VECS,
 306         };
 307         struct intel_engine_cs *engine;
 308         u32 hw_mask;
 309
 310         if (engine_mask == ALL_ENGINES) {
 311                 hw_mask = GEN6_GRDOM_FULL;
 312         } else {
 313                 intel_engine_mask_t tmp;
 314
 315                 hw_mask = 0;
 316                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 317                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 318                         hw_mask |= hw_engine_mask[engine->id];
 319                 }
 320         }
 321
 322         return gen6_hw_domain_reset(gt, hw_mask);
 323 }
 324
 325 static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)
 326 {
 327         int vecs_id;
 328
 329         GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);
 330
 331         vecs_id = _VECS((engine->instance) / 2);
 332
 333         return engine->gt->engine[vecs_id];
 334 }
 335
 336 struct sfc_lock_data {
 337         i915_reg_t lock_reg;
 338         i915_reg_t ack_reg;
 339         i915_reg_t usage_reg;
 340         u32 lock_bit;
 341         u32 ack_bit;
 342         u32 usage_bit;
 343         u32 reset_bit;
 344 };
 345
 346 static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,
 347                                      struct sfc_lock_data *sfc_lock)
 348 {
 349         switch (engine->class) {
 350         default:
 351                 MISSING_CASE(engine->class);
 352                 fallthrough;
 353         case VIDEO_DECODE_CLASS:
 354                 sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine);
 355                 sfc_lock->lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 356
 357                 sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
 358                 sfc_lock->ack_bit  = GEN11_VCS_SFC_LOCK_ACK_BIT;
 359
 360                 sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
 361                 sfc_lock->usage_bit = GEN11_VCS_SFC_USAGE_BIT;
 362                 sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
 363
 364                 break;
 365         case VIDEO_ENHANCEMENT_CLASS:
 366                 sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine);
 367                 sfc_lock->lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 368
 369                 sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine);
 370                 sfc_lock->ack_bit  = GEN11_VECS_SFC_LOCK_ACK_BIT;
 371
 372                 sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine);
 373                 sfc_lock->usage_bit = GEN11_VECS_SFC_USAGE_BIT;
 374                 sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
 375
 376                 break;
 377         }
 378 }
 379
 380 static int gen11_lock_sfc(struct intel_engine_cs *engine,
 381                           u32 *reset_mask,
 382                           u32 *unlock_mask)
 383 {
 384         struct intel_uncore *uncore = engine->uncore;
 385         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 386         struct sfc_lock_data sfc_lock;
 387         bool lock_obtained, lock_to_other = false;
 388         int ret;
 389
 390         switch (engine->class) {
 391         case VIDEO_DECODE_CLASS:
 392                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 393                         return 0;
 394
 395                 fallthrough;
 396         case VIDEO_ENHANCEMENT_CLASS:
 397                 get_sfc_forced_lock_data(engine, &sfc_lock);
 398
 399                 break;
 400         default:
 401                 return 0;
 402         }
 403
 404         if (!(intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & sfc_lock.usage_bit)) {
 405                 struct intel_engine_cs *paired_vecs;
 406
 407                 if (engine->class != VIDEO_DECODE_CLASS ||
 408                     GRAPHICS_VER(engine->i915) != 12)
 409                         return 0;
 410
 411                 /*
 412                  * Wa_14010733141
 413                  *
 414                  * If the VCS-MFX isn't using the SFC, we also need to check
 415                  * whether VCS-HCP is using it.  If so, we need to issue a *VE*
 416                  * forced lock on the VE engine that shares the same SFC.
 417                  */
 418                 if (!(intel_uncore_read_fw(uncore,
 419                                            GEN12_HCP_SFC_LOCK_STATUS(engine)) &
 420                       GEN12_HCP_SFC_USAGE_BIT))
 421                         return 0;
 422
 423                 paired_vecs = find_sfc_paired_vecs_engine(engine);
 424                 get_sfc_forced_lock_data(paired_vecs, &sfc_lock);
 425                 lock_to_other = true;
 426                 *unlock_mask |= paired_vecs->mask;
 427         } else {
 428                 *unlock_mask |= engine->mask;
 429         }
 430
 431         /*
 432          * If the engine is using an SFC, tell the engine that a software reset
 433          * is going to happen. The engine will then try to force lock the SFC.
 434          * If SFC ends up being locked to the engine we want to reset, we have
 435          * to reset it as well (we will unlock it once the reset sequence is
 436          * completed).
 437          */
 438         rmw_set_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
 439
 440         ret = __intel_wait_for_register_fw(uncore,
 441                                            sfc_lock.ack_reg,
 442                                            sfc_lock.ack_bit,
 443                                            sfc_lock.ack_bit,
 444                                            1000, 0, NULL);
 445
 446         /*
 447          * Was the SFC released while we were trying to lock it?
 448          *
 449          * We should reset both the engine and the SFC if:
 450          *  - We were locking the SFC to this engine and the lock succeeded
 451          *       OR
 452          *  - We were locking the SFC to a different engine (Wa_14010733141)
 453          *    but the SFC was released before the lock was obtained.
 454          *
 455          * Otherwise we need only reset the engine by itself and we can
 456          * leave the SFC alone.
 457          */
 458         lock_obtained = (intel_uncore_read_fw(uncore, sfc_lock.usage_reg) &
 459                         sfc_lock.usage_bit) != 0;
 460         if (lock_obtained == lock_to_other)
 461                 return 0;
 462
 463         if (ret) {
 464                 ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
 465                 return ret;
 466         }
 467
 468         *reset_mask |= sfc_lock.reset_bit;
 469         return 0;
 470 }
 471
 472 static void gen11_unlock_sfc(struct intel_engine_cs *engine)
 473 {
 474         struct intel_uncore *uncore = engine->uncore;
 475         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 476         struct sfc_lock_data sfc_lock = {};
 477
 478         if (engine->class != VIDEO_DECODE_CLASS &&
 479             engine->class != VIDEO_ENHANCEMENT_CLASS)
 480                 return;
 481
 482         if (engine->class == VIDEO_DECODE_CLASS &&
 483             (BIT(engine->instance) & vdbox_sfc_access) == 0)
 484                 return;
 485
 486         get_sfc_forced_lock_data(engine, &sfc_lock);
 487
 488         rmw_clear_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
 489 }
 490
 491 static int gen11_reset_engines(struct intel_gt *gt,
 492                                intel_engine_mask_t engine_mask,
 493                                unsigned int retry)
 494 {
 495         static const u32 hw_engine_mask[] = {
 496                 [RCS0]  = GEN11_GRDOM_RENDER,
 497                 [BCS0]  = GEN11_GRDOM_BLT,
 498                 [VCS0]  = GEN11_GRDOM_MEDIA,
 499                 [VCS1]  = GEN11_GRDOM_MEDIA2,
 500                 [VCS2]  = GEN11_GRDOM_MEDIA3,
 501                 [VCS3]  = GEN11_GRDOM_MEDIA4,
 502                 [VCS4]  = GEN11_GRDOM_MEDIA5,
 503                 [VCS5]  = GEN11_GRDOM_MEDIA6,
 504                 [VCS6]  = GEN11_GRDOM_MEDIA7,
 505                 [VCS7]  = GEN11_GRDOM_MEDIA8,
 506                 [VECS0] = GEN11_GRDOM_VECS,
 507                 [VECS1] = GEN11_GRDOM_VECS2,
 508                 [VECS2] = GEN11_GRDOM_VECS3,
 509                 [VECS3] = GEN11_GRDOM_VECS4,
 510         };
 511         struct intel_engine_cs *engine;
 512         intel_engine_mask_t tmp;
 513         u32 reset_mask, unlock_mask = 0;
 514         int ret;
 515
 516         if (engine_mask == ALL_ENGINES) {
 517                 reset_mask = GEN11_GRDOM_FULL;
 518         } else {
 519                 reset_mask = 0;
 520                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 521                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 522                         reset_mask |= hw_engine_mask[engine->id];
 523                         ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);
 524                         if (ret)
 525                                 goto sfc_unlock;
 526                 }
 527         }
 528
 529         ret = gen6_hw_domain_reset(gt, reset_mask);
 530
 531 sfc_unlock:
 532         /*
 533          * We unlock the SFC based on the lock status and not the result of
 534          * gen11_lock_sfc to make sure that we clean properly if something
 535          * wrong happened during the lock (e.g. lock acquired after timeout
 536          * expiration).
 537          *
 538          * Due to Wa_14010733141, we may have locked an SFC to an engine that
 539          * wasn't being reset.  So instead of calling gen11_unlock_sfc()
 540          * on engine_mask, we instead call it on the mask of engines that our
 541          * gen11_lock_sfc() calls told us actually had locks attempted.
 542          */
 543         for_each_engine_masked(engine, gt, unlock_mask, tmp)
 544                 gen11_unlock_sfc(engine);
 545
 546         return ret;
 547 }
 548
 549 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 550 {
 551         struct intel_uncore *uncore = engine->uncore;
 552         const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
 553         u32 request, mask, ack;
 554         int ret;
 555
 556         if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))
 557                 return -ETIMEDOUT;
 558
 559         ack = intel_uncore_read_fw(uncore, reg);
 560         if (ack & RESET_CTL_CAT_ERROR) {
 561                 /*
 562                  * For catastrophic errors, ready-for-reset sequence
 563                  * needs to be bypassed: HAS#396813
 564                  */
 565                 request = RESET_CTL_CAT_ERROR;
 566                 mask = RESET_CTL_CAT_ERROR;
 567
 568                 /* Catastrophic errors need to be cleared by HW */
 569                 ack = 0;
 570         } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
 571                 request = RESET_CTL_REQUEST_RESET;
 572                 mask = RESET_CTL_READY_TO_RESET;
 573                 ack = RESET_CTL_READY_TO_RESET;
 574         } else {
 575                 return 0;
 576         }
 577
 578         intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
 579         ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
 580                                            700, 0, NULL);
 581         if (ret)
 582                 drm_err(&engine->i915->drm,
 583                         "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
 584                         engine->name, request,
 585                         intel_uncore_read_fw(uncore, reg));
 586
 587         return ret;
 588 }
 589
 590 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
 591 {
 592         intel_uncore_write_fw(engine->uncore,
 593                               RING_RESET_CTL(engine->mmio_base),
 594                               _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
 595 }
 596
 597 static int gen8_reset_engines(struct intel_gt *gt,
 598                               intel_engine_mask_t engine_mask,
 599                               unsigned int retry)
 600 {
 601         struct intel_engine_cs *engine;
 602         const bool reset_non_ready = retry >= 1;
 603         intel_engine_mask_t tmp;
 604         int ret;
 605
 606         for_each_engine_masked(engine, gt, engine_mask, tmp) {
 607                 ret = gen8_engine_reset_prepare(engine);
 608                 if (ret && !reset_non_ready)
 609                         goto skip_reset;
 610
 611                 /*
 612                  * If this is not the first failed attempt to prepare,
 613                  * we decide to proceed anyway.
 614                  *
 615                  * By doing so we risk context corruption and with
 616                  * some gens (kbl), possible system hang if reset
 617                  * happens during active bb execution.
 618                  *
 619                  * We rather take context corruption instead of
 620                  * failed reset with a wedged driver/gpu. And
 621                  * active bb execution case should be covered by
 622                  * stop_engines() we have before the reset.
 623                  */
 624         }
 625
 626         if (GRAPHICS_VER(gt->i915) >= 11)
 627                 ret = gen11_reset_engines(gt, engine_mask, retry);
 628         else
 629                 ret = gen6_reset_engines(gt, engine_mask, retry);
 630
 631 skip_reset:
 632         for_each_engine_masked(engine, gt, engine_mask, tmp)
 633                 gen8_engine_reset_cancel(engine);
 634
 635         return ret;
 636 }
 637
 638 static int mock_reset(struct intel_gt *gt,
 639                       intel_engine_mask_t mask,
 640                       unsigned int retry)
 641 {
 642         return 0;
 643 }
 644
 645 typedef int (*reset_func)(struct intel_gt *,
 646                           intel_engine_mask_t engine_mask,
 647                           unsigned int retry);
 648
 649 static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
 650 {
 651         struct drm_i915_private *i915 = gt->i915;
 652
 653         if (is_mock_gt(gt))
 654                 return mock_reset;
 655         else if (GRAPHICS_VER(i915) >= 8)
 656                 return gen8_reset_engines;
 657         else if (GRAPHICS_VER(i915) >= 6)
 658                 return gen6_reset_engines;
 659         else if (GRAPHICS_VER(i915) >= 5)
 660                 return ilk_do_reset;
 661         else if (IS_G4X(i915))
 662                 return g4x_do_reset;
 663         else if (IS_G33(i915) || IS_PINEVIEW(i915))
 664                 return g33_do_reset;
 665         else if (GRAPHICS_VER(i915) >= 3)
 666                 return i915_do_reset;
 667         else
 668                 return NULL;
 669 }
 670
 671 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 672 {
 673         const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
 674         reset_func reset;
 675         int ret = -ETIMEDOUT;
 676         int retry;
 677
 678         reset = intel_get_gpu_reset(gt);
 679         if (!reset)
 680                 return -ENODEV;
 681
 682         /*
 683          * If the power well sleeps during the reset, the reset
 684          * request may be dropped and never completes (causing -EIO).
 685          */
 686         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 687         for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
 688                 GT_TRACE(gt, "engine_mask=%x\n", engine_mask);
 689                 preempt_disable();
 690                 ret = reset(gt, engine_mask, retry);
 691                 preempt_enable();
 692         }
 693         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 694
 695         return ret;
 696 }
 697
 698 bool intel_has_gpu_reset(const struct intel_gt *gt)
 699 {
 700         if (!gt->i915->params.reset)
 701                 return NULL;
 702
 703         return intel_get_gpu_reset(gt);
 704 }
 705
 706 bool intel_has_reset_engine(const struct intel_gt *gt)
 707 {
 708         if (gt->i915->params.reset < 2)
 709                 return false;
 710
 711         return INTEL_INFO(gt->i915)->has_reset_engine;
 712 }
 713
 714 int intel_reset_guc(struct intel_gt *gt)
 715 {
 716         u32 guc_domain =
 717                 GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
 718         int ret;
 719
 720         GEM_BUG_ON(!HAS_GT_UC(gt->i915));
 721
 722         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 723         ret = gen6_hw_domain_reset(gt, guc_domain);
 724         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 725
 726         return ret;
 727 }
 728
 729 /*
 730  * Ensure irq handler finishes, and not run again.
 731  * Also return the active request so that we only search for it once.
 732  */
 733 static void reset_prepare_engine(struct intel_engine_cs *engine)
 734 {
 735         /*
 736          * During the reset sequence, we must prevent the engine from
 737          * entering RC6. As the context state is undefined until we restart
 738          * the engine, if it does enter RC6 during the reset, the state
 739          * written to the powercontext is undefined and so we may lose
 740          * GPU state upon resume, i.e. fail to restart after a reset.
 741          */
 742         intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
 743         if (engine->reset.prepare)
 744                 engine->reset.prepare(engine);
 745 }
 746
 747 static void revoke_mmaps(struct intel_gt *gt)
 748 {
 749         int i;
 750
 751         for (i = 0; i < gt->ggtt->num_fences; i++) {
 752                 struct drm_vma_offset_node *node;
 753                 struct i915_vma *vma;
 754                 u64 vma_offset;
 755
 756                 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
 757                 if (!vma)
 758                         continue;
 759
 760                 if (!i915_vma_has_userfault(vma))
 761                         continue;
 762
 763                 GEM_BUG_ON(vma->fence != &gt->ggtt->fence_regs[i]);
 764
 765                 if (!vma->mmo)
 766                         continue;
 767
 768                 node = &vma->mmo->vma_node;
 769                 vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
 770
 771                 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
 772                                     drm_vma_node_offset_addr(node) + vma_offset,
 773                                     vma->size,
 774                                     1);
 775         }
 776 }
 777
 778 static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
 779 {
 780         struct intel_engine_cs *engine;
 781         intel_engine_mask_t awake = 0;
 782         enum intel_engine_id id;
 783
 784         for_each_engine(engine, gt, id) {
 785                 if (intel_engine_pm_get_if_awake(engine))
 786                         awake |= engine->mask;
 787                 reset_prepare_engine(engine);
 788         }
 789
 790         intel_uc_reset_prepare(&gt->uc);
 791
 792         return awake;
 793 }
 794
 795 static void gt_revoke(struct intel_gt *gt)
 796 {
 797         revoke_mmaps(gt);
 798 }
 799
 800 static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 801 {
 802         struct intel_engine_cs *engine;
 803         enum intel_engine_id id;
 804         int err;
 805
 806         /*
 807          * Everything depends on having the GTT running, so we need to start
 808          * there.
 809          */
 810         err = i915_ggtt_enable_hw(gt->i915);
 811         if (err)
 812                 return err;
 813
 814         local_bh_disable();
 815         for_each_engine(engine, gt, id)
 816                 __intel_engine_reset(engine, stalled_mask & engine->mask);
 817         local_bh_enable();
 818
 819         intel_uc_reset(&gt->uc, true);
 820
 821         intel_ggtt_restore_fences(gt->ggtt);
 822
 823         return err;
 824 }
 825
 826 static void reset_finish_engine(struct intel_engine_cs *engine)
 827 {
 828         if (engine->reset.finish)
 829                 engine->reset.finish(engine);
 830         intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
 831
 832         intel_engine_signal_breadcrumbs(engine);
 833 }
 834
 835 static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
 836 {
 837         struct intel_engine_cs *engine;
 838         enum intel_engine_id id;
 839
 840         for_each_engine(engine, gt, id) {
 841                 reset_finish_engine(engine);
 842                 if (awake & engine->mask)
 843                         intel_engine_pm_put(engine);
 844         }
 845
 846         intel_uc_reset_finish(&gt->uc);
 847 }
 848
 849 static void nop_submit_request(struct i915_request *request)
 850 {
 851         RQ_TRACE(request, "-EIO\n");
 852
 853         request = i915_request_mark_eio(request);
 854         if (request) {
 855                 i915_request_submit(request);
 856                 intel_engine_signal_breadcrumbs(request->engine);
 857
 858                 i915_request_put(request);
 859         }
 860 }
 861
 862 static void __intel_gt_set_wedged(struct intel_gt *gt)
 863 {
 864         struct intel_engine_cs *engine;
 865         intel_engine_mask_t awake;
 866         enum intel_engine_id id;
 867
 868         if (test_bit(I915_WEDGED, &gt->reset.flags))
 869                 return;
 870
 871         GT_TRACE(gt, "start\n");
 872
 873         /*
 874          * First, stop submission to hw, but do not yet complete requests by
 875          * rolling the global seqno forward (since this would complete requests
 876          * for which we haven't set the fence error to EIO yet).
 877          */
 878         awake = reset_prepare(gt);
 879
 880         /* Even if the GPU reset fails, it should still stop the engines */
 881         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 882                 __intel_gt_reset(gt, ALL_ENGINES);
 883
 884         for_each_engine(engine, gt, id)
 885                 engine->submit_request = nop_submit_request;
 886
 887         /*
 888          * Make sure no request can slip through without getting completed by
 889          * either this call here to intel_engine_write_global_seqno, or the one
 890          * in nop_submit_request.
 891          */
 892         synchronize_rcu_expedited();
 893         set_bit(I915_WEDGED, &gt->reset.flags);
 894
 895         /* Mark all executing requests as skipped */
 896         local_bh_disable();
 897         for_each_engine(engine, gt, id)
 898                 if (engine->reset.cancel)
 899                         engine->reset.cancel(engine);
 900         intel_uc_cancel_requests(&gt->uc);
 901         local_bh_enable();
 902
 903         reset_finish(gt, awake);
 904
 905         GT_TRACE(gt, "end\n");
 906 }
 907
 908 void intel_gt_set_wedged(struct intel_gt *gt)
 909 {
 910         intel_wakeref_t wakeref;
 911
 912         if (test_bit(I915_WEDGED, &gt->reset.flags))
 913                 return;
 914
 915         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
 916         mutex_lock(&gt->reset.mutex);
 917
 918         if (GEM_SHOW_DEBUG()) {
 919                 struct drm_printer p = drm_debug_printer(__func__);
 920                 struct intel_engine_cs *engine;
 921                 enum intel_engine_id id;
 922
 923                 drm_printf(&p, "called from %pS\n", (void *)_RET_IP_);
 924                 for_each_engine(engine, gt, id) {
 925                         if (intel_engine_is_idle(engine))
 926                                 continue;
 927
 928                         intel_engine_dump(engine, &p, "%s\n", engine->name);
 929                 }
 930         }
 931
 932         __intel_gt_set_wedged(gt);
 933
 934         mutex_unlock(&gt->reset.mutex);
 935         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
 936 }
 937
 938 static bool __intel_gt_unset_wedged(struct intel_gt *gt)
 939 {
 940         struct intel_gt_timelines *timelines = &gt->timelines;
 941         struct intel_timeline *tl;
 942         bool ok;
 943
 944         if (!test_bit(I915_WEDGED, &gt->reset.flags))
 945                 return true;
 946
 947         /* Never fully initialised, recovery impossible */
 948         if (intel_gt_has_unrecoverable_error(gt))
 949                 return false;
 950
 951         GT_TRACE(gt, "start\n");
 952
 953         /*
 954          * Before unwedging, make sure that all pending operations
 955          * are flushed and errored out - we may have requests waiting upon
 956          * third party fences. We marked all inflight requests as EIO, and
 957          * every execbuf since returned EIO, for consistency we want all
 958          * the currently pending requests to also be marked as EIO, which
 959          * is done inside our nop_submit_request - and so we must wait.
 960          *
 961          * No more can be submitted until we reset the wedged bit.
 962          */
 963         spin_lock(&timelines->lock);
 964         list_for_each_entry(tl, &timelines->active_list, link) {
 965                 struct dma_fence *fence;
 966
 967                 fence = i915_active_fence_get(&tl->last_request);
 968                 if (!fence)
 969                         continue;
 970
 971                 spin_unlock(&timelines->lock);
 972
 973                 /*
 974                  * All internal dependencies (i915_requests) will have
 975                  * been flushed by the set-wedge, but we may be stuck waiting
 976                  * for external fences. These should all be capped to 10s
 977                  * (I915_FENCE_TIMEOUT) so this wait should not be unbounded
 978                  * in the worst case.
 979                  */
 980                 dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
 981                 dma_fence_put(fence);
 982
 983                 /* Restart iteration after droping lock */
 984                 spin_lock(&timelines->lock);
 985                 tl = list_entry(&timelines->active_list, typeof(*tl), link);
 986         }
 987         spin_unlock(&timelines->lock);
 988
 989         /* We must reset pending GPU events before restoring our submission */
 990         ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
 991         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 992                 ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
 993         if (!ok) {
 994                 /*
 995                  * Warn CI about the unrecoverable wedged condition.
 996                  * Time for a reboot.
 997                  */
 998                 add_taint_for_CI(gt->i915, TAINT_WARN);
 999                 return false;
1000         }
1001
1002         /*
1003          * Undo nop_submit_request. We prevent all new i915 requests from
1004          * being queued (by disallowing execbuf whilst wedged) so having
1005          * waited for all active requests above, we know the system is idle
1006          * and do not have to worry about a thread being inside
1007          * engine->submit_request() as we swap over. So unlike installing
1008          * the nop_submit_request on reset, we can do this from normal
1009          * context and do not require stop_machine().
1010          */
1011         intel_engines_reset_default_submission(gt);
1012
1013         GT_TRACE(gt, "end\n");
1014
1015         smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
1016         clear_bit(I915_WEDGED, &gt->reset.flags);
1017
1018         return true;
1019 }
1020
1021 bool intel_gt_unset_wedged(struct intel_gt *gt)
1022 {
1023         bool result;
1024
1025         mutex_lock(&gt->reset.mutex);
1026         result = __intel_gt_unset_wedged(gt);
1027         mutex_unlock(&gt->reset.mutex);
1028
1029         return result;
1030 }
1031
1032 static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
1033 {
1034         int err, i;
1035
1036         err = __intel_gt_reset(gt, ALL_ENGINES);
1037         for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
1038                 msleep(10 * (i + 1));
1039                 err = __intel_gt_reset(gt, ALL_ENGINES);
1040         }
1041         if (err)
1042                 return err;
1043
1044         return gt_reset(gt, stalled_mask);
1045 }
1046
1047 static int resume(struct intel_gt *gt)
1048 {
1049         struct intel_engine_cs *engine;
1050         enum intel_engine_id id;
1051         int ret;
1052
1053         for_each_engine(engine, gt, id) {
1054                 ret = intel_engine_resume(engine);
1055                 if (ret)
1056                         return ret;
1057         }
1058
1059         return 0;
1060 }
1061
1062 /**
1063  * intel_gt_reset - reset chip after a hang
1064  * @gt: #intel_gt to reset
1065  * @stalled_mask: mask of the stalled engines with the guilty requests
1066  * @reason: user error message for why we are resetting
1067  *
1068  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1069  * on failure.
1070  *
1071  * Procedure is fairly simple:
1072  *   - reset the chip using the reset reg
1073  *   - re-init context state
1074  *   - re-init hardware status page
1075  *   - re-init ring buffer
1076  *   - re-init interrupt state
1077  *   - re-init display
1078  */
1079 void intel_gt_reset(struct intel_gt *gt,
1080                     intel_engine_mask_t stalled_mask,
1081                     const char *reason)
1082 {
1083         intel_engine_mask_t awake;
1084         int ret;
1085
1086         GT_TRACE(gt, "flags=%lx\n", gt->reset.flags);
1087
1088         might_sleep();
1089         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1090
1091         /*
1092          * FIXME: Revoking cpu mmap ptes cannot be done from a dma_fence
1093          * critical section like gpu reset.
1094          */
1095         gt_revoke(gt);
1096
1097         mutex_lock(&gt->reset.mutex);
1098
1099         /* Clear any previous failed attempts at recovery. Time to try again. */
1100         if (!__intel_gt_unset_wedged(gt))
1101                 goto unlock;
1102
1103         if (reason)
1104                 drm_notice(&gt->i915->drm,
1105                            "Resetting chip for %s\n", reason);
1106         atomic_inc(&gt->i915->gpu_error.reset_count);
1107
1108         awake = reset_prepare(gt);
1109
1110         if (!intel_has_gpu_reset(gt)) {
1111                 if (gt->i915->params.reset)
1112                         drm_err(&gt->i915->drm, "GPU reset not supported\n");
1113                 else
1114                         drm_dbg(&gt->i915->drm, "GPU reset disabled\n");
1115                 goto error;
1116         }
1117
1118         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1119                 intel_runtime_pm_disable_interrupts(gt->i915);
1120
1121         if (do_reset(gt, stalled_mask)) {
1122                 drm_err(&gt->i915->drm, "Failed to reset chip\n");
1123                 goto taint;
1124         }
1125
1126         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1127                 intel_runtime_pm_enable_interrupts(gt->i915);
1128
1129         intel_overlay_reset(gt->i915);
1130
1131         /*
1132          * Next we need to restore the context, but we don't use those
1133          * yet either...
1134          *
1135          * Ring buffer needs to be re-initialized in the KMS case, or if X
1136          * was running at the time of the reset (i.e. we weren't VT
1137          * switched away).
1138          */
1139         ret = intel_gt_init_hw(gt);
1140         if (ret) {
1141                 drm_err(&gt->i915->drm,
1142                         "Failed to initialise HW following reset (%d)\n",
1143                         ret);
1144                 goto taint;
1145         }
1146
1147         ret = resume(gt);
1148         if (ret)
1149                 goto taint;
1150
1151 finish:
1152         reset_finish(gt, awake);
1153 unlock:
1154         mutex_unlock(&gt->reset.mutex);
1155         return;
1156
1157 taint:
1158         /*
1159          * History tells us that if we cannot reset the GPU now, we
1160          * never will. This then impacts everything that is run
1161          * subsequently. On failing the reset, we mark the driver
1162          * as wedged, preventing further execution on the GPU.
1163          * We also want to go one step further and add a taint to the
1164          * kernel so that any subsequent faults can be traced back to
1165          * this failure. This is important for CI, where if the
1166          * GPU/driver fails we would like to reboot and restart testing
1167          * rather than continue on into oblivion. For everyone else,
1168          * the system should still plod along, but they have been warned!
1169          */
1170         add_taint_for_CI(gt->i915, TAINT_WARN);
1171 error:
1172         __intel_gt_set_wedged(gt);
1173         goto finish;
1174 }
1175
1176 static int intel_gt_reset_engine(struct intel_engine_cs *engine)
1177 {
1178         return __intel_gt_reset(engine->gt, engine->mask);
1179 }
1180
1181 int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
1182 {
1183         struct intel_gt *gt = engine->gt;
1184         int ret;
1185
1186         ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1187         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));
1188
1189         if (intel_engine_uses_guc(engine))
1190                 return -ENODEV;
1191
1192         if (!intel_engine_pm_get_if_awake(engine))
1193                 return 0;
1194
1195         reset_prepare_engine(engine);
1196
1197         if (msg)
1198                 drm_notice(&engine->i915->drm,
1199                            "Resetting %s for %s\n", engine->name, msg);
1200         atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1201
1202         ret = intel_gt_reset_engine(engine);
1203         if (ret) {
1204                 /* If we fail here, we expect to fallback to a global reset */
1205                 ENGINE_TRACE(engine, "Failed to reset %s, err: %d\n", engine->name, ret);
1206                 goto out;
1207         }
1208
1209         /*
1210          * The request that caused the hang is stuck on elsp, we know the
1211          * active request and can drop it, adjust head to skip the offending
1212          * request to resume executing remaining requests in the queue.
1213          */
1214         __intel_engine_reset(engine, true);
1215
1216         /*
1217          * The engine and its registers (and workarounds in case of render)
1218          * have been reset to their default values. Follow the init_ring
1219          * process to program RING_MODE, HWSP and re-enable submission.
1220          */
1221         ret = intel_engine_resume(engine);
1222
1223 out:
1224         intel_engine_cancel_stop_cs(engine);
1225         reset_finish_engine(engine);
1226         intel_engine_pm_put_async(engine);
1227         return ret;
1228 }
1229
1230 /**
1231  * intel_engine_reset - reset GPU engine to recover from a hang
1232  * @engine: engine to reset
1233  * @msg: reason for GPU reset; or NULL for no drm_notice()
1234  *
1235  * Reset a specific GPU engine. Useful if a hang is detected.
1236  * Returns zero on successful reset or otherwise an error code.
1237  *
1238  * Procedure is:
1239  *  - identifies the request that caused the hang and it is dropped
1240  *  - reset engine (which will force the engine to idle)
1241  *  - re-init/configure engine
1242  */
1243 int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1244 {
1245         int err;
1246
1247         local_bh_disable();
1248         err = __intel_engine_reset_bh(engine, msg);
1249         local_bh_enable();
1250
1251         return err;
1252 }
1253
1254 static void intel_gt_reset_global(struct intel_gt *gt,
1255                                   u32 engine_mask,
1256                                   const char *reason)
1257 {
1258         struct kobject *kobj = &gt->i915->drm.primary->kdev->kobj;
1259         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1260         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1261         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1262         struct intel_wedge_me w;
1263
1264         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1265
1266         GT_TRACE(gt, "resetting chip, engines=%x\n", engine_mask);
1267         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1268
1269         /* Use a watchdog to ensure that our reset completes */
1270         intel_wedge_on_timeout(&w, gt, 5 * HZ) {
1271                 intel_display_prepare_reset(gt->i915);
1272
1273                 /* Flush everyone using a resource about to be clobbered */
1274                 synchronize_srcu_expedited(&gt->reset.backoff_srcu);
1275
1276                 intel_gt_reset(gt, engine_mask, reason);
1277
1278                 intel_display_finish_reset(gt->i915);
1279         }
1280
1281         if (!test_bit(I915_WEDGED, &gt->reset.flags))
1282                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1283 }
1284
1285 /**
1286  * intel_gt_handle_error - handle a gpu error
1287  * @gt: the intel_gt
1288  * @engine_mask: mask representing engines that are hung
1289  * @flags: control flags
1290  * @fmt: Error message format string
1291  *
1292  * Do some basic checking of register state at error time and
1293  * dump it to the syslog.  Also call i915_capture_error_state() to make
1294  * sure we get a record and make it available in debugfs.  Fire a uevent
1295  * so userspace knows something bad happened (should trigger collection
1296  * of a ring dump etc.).
1297  */
1298 void intel_gt_handle_error(struct intel_gt *gt,
1299                            intel_engine_mask_t engine_mask,
1300                            unsigned long flags,
1301                            const char *fmt, ...)
1302 {
1303         struct intel_engine_cs *engine;
1304         intel_wakeref_t wakeref;
1305         intel_engine_mask_t tmp;
1306         char error_msg[80];
1307         char *msg = NULL;
1308
1309         if (fmt) {
1310                 va_list args;
1311
1312                 va_start(args, fmt);
1313                 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1314                 va_end(args);
1315
1316                 msg = error_msg;
1317         }
1318
1319         /*
1320          * In most cases it's guaranteed that we get here with an RPM
1321          * reference held, for example because there is a pending GPU
1322          * request that won't finish until the reset is done. This
1323          * isn't the case at least when we get here by doing a
1324          * simulated reset via debugfs, so get an RPM reference.
1325          */
1326         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1327
1328         engine_mask &= gt->info.engine_mask;
1329
1330         if (flags & I915_ERROR_CAPTURE) {
1331                 i915_capture_error_state(gt, engine_mask);
1332                 intel_gt_clear_error_registers(gt, engine_mask);
1333         }
1334
1335         /*
1336          * Try engine reset when available. We fall back to full reset if
1337          * single reset fails.
1338          */
1339         if (!intel_uc_uses_guc_submission(&gt->uc) &&
1340             intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
1341                 local_bh_disable();
1342                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
1343                         BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1344                         if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1345                                              &gt->reset.flags))
1346                                 continue;
1347
1348                         if (__intel_engine_reset_bh(engine, msg) == 0)
1349                                 engine_mask &= ~engine->mask;
1350
1351                         clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1352                                               &gt->reset.flags);
1353                 }
1354                 local_bh_enable();
1355         }
1356
1357         if (!engine_mask)
1358                 goto out;
1359
1360         /* Full reset needs the mutex, stop any other user trying to do so. */
1361         if (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1362                 wait_event(gt->reset.queue,
1363                            !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1364                 goto out; /* piggy-back on the other reset */
1365         }
1366
1367         /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
1368         synchronize_rcu_expedited();
1369
1370         /* Prevent any other reset-engine attempt. */
1371         for_each_engine(engine, gt, tmp) {
1372                 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1373                                         &gt->reset.flags))
1374                         wait_on_bit(&gt->reset.flags,
1375                                     I915_RESET_ENGINE + engine->id,
1376                                     TASK_UNINTERRUPTIBLE);
1377         }
1378
1379         intel_gt_reset_global(gt, engine_mask, msg);
1380
1381         for_each_engine(engine, gt, tmp)
1382                 clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1383                                  &gt->reset.flags);
1384         clear_bit_unlock(I915_RESET_BACKOFF, &gt->reset.flags);
1385         smp_mb__after_atomic();
1386         wake_up_all(&gt->reset.queue);
1387
1388 out:
1389         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1390 }
1391
1392 int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
1393 {
1394         might_lock(&gt->reset.backoff_srcu);
1395         might_sleep();
1396
1397         rcu_read_lock();
1398         while (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1399                 rcu_read_unlock();
1400
1401                 if (wait_event_interruptible(gt->reset.queue,
1402                                              !test_bit(I915_RESET_BACKOFF,
1403                                                        &gt->reset.flags)))
1404                         return -EINTR;
1405
1406                 rcu_read_lock();
1407         }
1408         *srcu = srcu_read_lock(&gt->reset.backoff_srcu);
1409         rcu_read_unlock();
1410
1411         return 0;
1412 }
1413
1414 void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1415 __releases(&gt->reset.backoff_srcu)
1416 {
1417         srcu_read_unlock(&gt->reset.backoff_srcu, tag);
1418 }
1419
1420 int intel_gt_terminally_wedged(struct intel_gt *gt)
1421 {
1422         might_sleep();
1423
1424         if (!intel_gt_is_wedged(gt))
1425                 return 0;
1426
1427         if (intel_gt_has_unrecoverable_error(gt))
1428                 return -EIO;
1429
1430         /* Reset still in progress? Maybe we will recover? */
1431         if (wait_event_interruptible(gt->reset.queue,
1432                                      !test_bit(I915_RESET_BACKOFF,
1433                                                &gt->reset.flags)))
1434                 return -EINTR;
1435
1436         return intel_gt_is_wedged(gt) ? -EIO : 0;
1437 }
1438
1439 void intel_gt_set_wedged_on_init(struct intel_gt *gt)
1440 {
1441         BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
1442                      I915_WEDGED_ON_INIT);
1443         intel_gt_set_wedged(gt);
1444         set_bit(I915_WEDGED_ON_INIT, &gt->reset.flags);
1445
1446         /* Wedged on init is non-recoverable */
1447         add_taint_for_CI(gt->i915, TAINT_WARN);
1448 }
1449
1450 void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
1451 {
1452         intel_gt_set_wedged(gt);
1453         set_bit(I915_WEDGED_ON_FINI, &gt->reset.flags);
1454         intel_gt_retire_requests(gt); /* cleanup any wedged requests */
1455 }
1456
1457 void intel_gt_init_reset(struct intel_gt *gt)
1458 {
1459         init_waitqueue_head(&gt->reset.queue);
1460         mutex_init(&gt->reset.mutex);
1461         init_srcu_struct(&gt->reset.backoff_srcu);
1462
1463         /*
1464          * While undesirable to wait inside the shrinker, complain anyway.
1465          *
1466          * If we have to wait during shrinking, we guarantee forward progress
1467          * by forcing the reset. Therefore during the reset we must not
1468          * re-enter the shrinker. By declaring that we take the reset mutex
1469          * within the shrinker, we forbid ourselves from performing any
1470          * fs-reclaim or taking related locks during reset.
1471          */
1472         i915_gem_shrinker_taints_mutex(gt->i915, &gt->reset.mutex);
1473
1474         /* no GPU until we are ready! */
1475         __set_bit(I915_WEDGED, &gt->reset.flags);
1476 }
1477
1478 void intel_gt_fini_reset(struct intel_gt *gt)
1479 {
1480         cleanup_srcu_struct(&gt->reset.backoff_srcu);
1481 }
1482
1483 static void intel_wedge_me(struct work_struct *work)
1484 {
1485         struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1486
1487         drm_err(&w->gt->i915->drm,
1488                 "%s timed out, cancelling all in-flight rendering.\n",
1489                 w->name);
1490         intel_gt_set_wedged(w->gt);
1491 }
1492
1493 void __intel_init_wedge(struct intel_wedge_me *w,
1494                         struct intel_gt *gt,
1495                         long timeout,
1496                         const char *name)
1497 {
1498         w->gt = gt;
1499         w->name = name;
1500
1501         INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1502         schedule_delayed_work(&w->work, timeout);
1503 }
1504
1505 void __intel_fini_wedge(struct intel_wedge_me *w)
1506 {
1507         cancel_delayed_work_sync(&w->work);
1508         destroy_delayed_work_on_stack(&w->work);
1509         w->gt = NULL;
1510 }
1511
1512 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1513 #include "selftest_reset.c"
1514 #include "selftest_hangcheck.c"
1515 #endif