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25 #include "intel_engine.h"
27 #include "intel_mocs.h"
28 #include "intel_lrc.h"
30 /* structures required */
31 struct drm_i915_mocs_entry {
37 struct drm_i915_mocs_table {
39 unsigned int n_entries;
40 const struct drm_i915_mocs_entry *table;
43 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
44 #define _LE_CACHEABILITY(value) ((value) << 0)
45 #define _LE_TGT_CACHE(value) ((value) << 2)
46 #define LE_LRUM(value) ((value) << 4)
47 #define LE_AOM(value) ((value) << 6)
48 #define LE_RSC(value) ((value) << 7)
49 #define LE_SCC(value) ((value) << 8)
50 #define LE_PFM(value) ((value) << 11)
51 #define LE_SCF(value) ((value) << 14)
52 #define LE_COS(value) ((value) << 15)
53 #define LE_SSE(value) ((value) << 17)
55 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
56 #define L3_ESC(value) ((value) << 0)
57 #define L3_SCC(value) ((value) << 1)
58 #define _L3_CACHEABILITY(value) ((value) << 4)
61 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
62 #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
64 /* (e)LLC caching options */
66 * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
69 #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
70 #define LE_1_UC _LE_CACHEABILITY(1)
71 #define LE_2_WT _LE_CACHEABILITY(2)
72 #define LE_3_WB _LE_CACHEABILITY(3)
75 #define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
76 #define LE_TC_1_LLC _LE_TGT_CACHE(1)
77 #define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
78 #define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
80 /* L3 caching options */
81 #define L3_0_DIRECT _L3_CACHEABILITY(0)
82 #define L3_1_UC _L3_CACHEABILITY(1)
83 #define L3_2_RESERVED _L3_CACHEABILITY(2)
84 #define L3_3_WB _L3_CACHEABILITY(3)
86 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
88 .control_value = __control_value, \
89 .l3cc_value = __l3cc_value, \
96 * These are the MOCS tables that are programmed across all the rings.
97 * The control value is programmed to all the rings that support the
98 * MOCS registers. While the l3cc_values are only programmed to the
99 * LNCFCMOCS0 - LNCFCMOCS32 registers.
101 * These tables are intended to be kept reasonably consistent across
102 * HW platforms, and for ICL+, be identical across OSes. To achieve
103 * that, for Icelake and above, list of entries is published as part
106 * Entries not part of the following tables are undefined as far as
107 * userspace is concerned and shouldn't be relied upon. For Gen < 12
108 * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
109 * PTE and will be initialized to an invalid value.
111 * The last two entries are reserved by the hardware. For ICL+ they
112 * should be initialized according to bspec and never used, for older
113 * platforms they should never be written to.
115 * NOTE: These tables are part of bspec and defined as part of hardware
116 * interface for ICL+. For older platforms, they are part of kernel
117 * ABI. It is expected that, for specific hardware platform, existing
118 * entries will remain constant and the table will only be updated by
119 * adding new entries, filling unused positions.
121 #define GEN9_MOCS_ENTRIES \
122 MOCS_ENTRY(I915_MOCS_UNCACHED, \
123 LE_1_UC | LE_TC_2_LLC_ELLC, \
125 MOCS_ENTRY(I915_MOCS_PTE, \
126 LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
129 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
131 MOCS_ENTRY(I915_MOCS_CACHED,
132 LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
136 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
137 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
139 MOCS_ENTRY(I915_MOCS_CACHED,
140 LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
144 #define GEN11_MOCS_ENTRIES \
145 /* Entries 0 and 1 are defined per-platform */ \
146 /* Base - L3 + LLC */ \
148 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
150 /* Base - Uncached */ \
152 LE_1_UC | LE_TC_1_LLC, \
156 LE_1_UC | LE_TC_1_LLC, \
160 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
164 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
166 /* Age 0 - L3 + LLC */ \
168 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
170 /* Age: Don't Chg. - LLC */ \
172 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
174 /* Age: Don't Chg. - L3 + LLC */ \
176 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
180 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
182 /* No AOM - L3 + LLC */ \
184 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
186 /* No AOM; Age 0 - LLC */ \
188 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
190 /* No AOM; Age 0 - L3 + LLC */ \
192 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
194 /* No AOM; Age:DC - LLC */ \
196 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
198 /* No AOM; Age:DC - L3 + LLC */ \
200 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
202 /* Self-Snoop - L3 + LLC */ \
204 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
206 /* Skip Caching - L3 + LLC(12.5%) */ \
208 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
210 /* Skip Caching - L3 + LLC(25%) */ \
212 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
214 /* Skip Caching - L3 + LLC(50%) */ \
216 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
218 /* Skip Caching - L3 + LLC(75%) */ \
220 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
222 /* Skip Caching - L3 + LLC(87.5%) */ \
224 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
226 /* HW Reserved - SW program but never use */ \
228 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
230 /* HW Reserved - SW program but never use */ \
232 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
235 static const struct drm_i915_mocs_entry tigerlake_mocs_table[] = {
236 /* Base - Error (Reserved for Non-Use) */
237 MOCS_ENTRY(0, 0x0, 0x0),
238 /* Base - Reserved */
239 MOCS_ENTRY(1, 0x0, 0x0),
243 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
245 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
247 /* Implicitly enable L1 - HDC:L1 + L3 */
249 LE_1_UC | LE_TC_1_LLC,
251 /* Implicitly enable L1 - HDC:L1 + LLC */
253 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
255 /* Implicitly enable L1 - HDC:L1 */
257 LE_1_UC | LE_TC_1_LLC,
259 /* HW Special Case (CCS) */
261 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
263 /* HW Special Case (Displayable) */
265 LE_1_UC | LE_TC_1_LLC,
269 static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
270 /* Base - Uncached (Deprecated) */
271 MOCS_ENTRY(I915_MOCS_UNCACHED,
272 LE_1_UC | LE_TC_1_LLC,
274 /* Base - L3 + LeCC:PAT (Deprecated) */
275 MOCS_ENTRY(I915_MOCS_PTE,
276 LE_0_PAGETABLE | LE_TC_1_LLC,
282 static bool get_mocs_settings(struct intel_gt *gt,
283 struct drm_i915_mocs_table *table)
285 struct drm_i915_private *i915 = gt->i915;
288 if (INTEL_GEN(i915) >= 12) {
289 table->size = ARRAY_SIZE(tigerlake_mocs_table);
290 table->table = tigerlake_mocs_table;
291 table->n_entries = GEN11_NUM_MOCS_ENTRIES;
293 } else if (IS_GEN(i915, 11)) {
294 table->size = ARRAY_SIZE(icelake_mocs_table);
295 table->table = icelake_mocs_table;
296 table->n_entries = GEN11_NUM_MOCS_ENTRIES;
298 } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
299 table->size = ARRAY_SIZE(skylake_mocs_table);
300 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
301 table->table = skylake_mocs_table;
303 } else if (IS_GEN9_LP(i915)) {
304 table->size = ARRAY_SIZE(broxton_mocs_table);
305 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
306 table->table = broxton_mocs_table;
309 WARN_ONCE(INTEL_GEN(i915) >= 9,
310 "Platform that should have a MOCS table does not.\n");
313 /* WaDisableSkipCaching:skl,bxt,kbl,glk */
314 if (IS_GEN(i915, 9)) {
317 for (i = 0; i < table->size; i++)
318 if (WARN_ON(table->table[i].l3cc_value &
319 (L3_ESC(1) | L3_SCC(0x7))))
326 static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
330 return GEN9_GFX_MOCS(index);
332 return GEN9_MFX0_MOCS(index);
334 return GEN9_BLT_MOCS(index);
336 return GEN9_VEBOX_MOCS(index);
338 return GEN9_MFX1_MOCS(index);
340 return GEN11_MFX2_MOCS(index);
342 MISSING_CASE(engine_id);
343 return INVALID_MMIO_REG;
348 * Get control_value from MOCS entry taking into account when it's not used:
349 * I915_MOCS_PTE's value is returned in this case.
351 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
354 if (table->table[index].used)
355 return table->table[index].control_value;
357 return table->table[I915_MOCS_PTE].control_value;
361 * intel_mocs_init_engine() - emit the mocs control table
362 * @engine: The engine for whom to emit the registers.
364 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
365 * given table starting at the given address.
367 void intel_mocs_init_engine(struct intel_engine_cs *engine)
369 struct intel_gt *gt = engine->gt;
370 struct intel_uncore *uncore = gt->uncore;
371 struct drm_i915_mocs_table table;
375 /* Platforms with global MOCS do not need per-engine initialization. */
376 if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
379 /* Called under a blanket forcewake */
380 assert_forcewakes_active(uncore, FORCEWAKE_ALL);
382 if (!get_mocs_settings(gt, &table))
385 /* Set unused values to PTE */
386 unused_value = table.table[I915_MOCS_PTE].control_value;
388 for (index = 0; index < table.size; index++) {
389 u32 value = get_entry_control(&table, index);
391 intel_uncore_write_fw(uncore,
392 mocs_register(engine->id, index),
396 /* All remaining entries are also unused */
397 for (; index < table.n_entries; index++)
398 intel_uncore_write_fw(uncore,
399 mocs_register(engine->id, index),
403 static void intel_mocs_init_global(struct intel_gt *gt)
405 struct intel_uncore *uncore = gt->uncore;
406 struct drm_i915_mocs_table table;
409 GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
411 if (!get_mocs_settings(gt, &table))
414 if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
417 for (index = 0; index < table.size; index++)
418 intel_uncore_write(uncore,
419 GEN12_GLOBAL_MOCS(index),
420 table.table[index].control_value);
423 * Ok, now set the unused entries to the invalid entry (index 0). These
424 * entries are officially undefined and no contract for the contents and
425 * settings is given for these entries.
427 for (; index < table.n_entries; index++)
428 intel_uncore_write(uncore,
429 GEN12_GLOBAL_MOCS(index),
430 table.table[0].control_value);
433 static int emit_mocs_control_table(struct i915_request *rq,
434 const struct drm_i915_mocs_table *table)
436 enum intel_engine_id engine = rq->engine->id;
441 if (GEM_WARN_ON(table->size > table->n_entries))
444 /* Set unused values to PTE */
445 unused_value = table->table[I915_MOCS_PTE].control_value;
447 cs = intel_ring_begin(rq, 2 + 2 * table->n_entries);
451 *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries);
453 for (index = 0; index < table->size; index++) {
454 u32 value = get_entry_control(table, index);
456 *cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
460 /* All remaining entries are also unused */
461 for (; index < table->n_entries; index++) {
462 *cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
463 *cs++ = unused_value;
467 intel_ring_advance(rq, cs);
473 * Get l3cc_value from MOCS entry taking into account when it's not used:
474 * I915_MOCS_PTE's value is returned in this case.
476 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
479 if (table->table[index].used)
480 return table->table[index].l3cc_value;
482 return table->table[I915_MOCS_PTE].l3cc_value;
485 static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
489 return low | high << 16;
492 static int emit_mocs_l3cc_table(struct i915_request *rq,
493 const struct drm_i915_mocs_table *table)
499 if (GEM_WARN_ON(table->size > table->n_entries))
502 /* Set unused values to PTE */
503 unused_value = table->table[I915_MOCS_PTE].l3cc_value;
505 cs = intel_ring_begin(rq, 2 + table->n_entries);
509 *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries / 2);
511 for (i = 0; i < table->size / 2; i++) {
512 u16 low = get_entry_l3cc(table, 2 * i);
513 u16 high = get_entry_l3cc(table, 2 * i + 1);
515 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
516 *cs++ = l3cc_combine(table, low, high);
519 /* Odd table size - 1 left over */
520 if (table->size & 0x01) {
521 u16 low = get_entry_l3cc(table, 2 * i);
523 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
524 *cs++ = l3cc_combine(table, low, unused_value);
528 /* All remaining entries are also unused */
529 for (; i < table->n_entries / 2; i++) {
530 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
531 *cs++ = l3cc_combine(table, unused_value, unused_value);
535 intel_ring_advance(rq, cs);
540 static void intel_mocs_init_l3cc_table(struct intel_gt *gt)
542 struct intel_uncore *uncore = gt->uncore;
543 struct drm_i915_mocs_table table;
547 if (!get_mocs_settings(gt, &table))
550 /* Set unused values to PTE */
551 unused_value = table.table[I915_MOCS_PTE].l3cc_value;
553 for (i = 0; i < table.size / 2; i++) {
554 u16 low = get_entry_l3cc(&table, 2 * i);
555 u16 high = get_entry_l3cc(&table, 2 * i + 1);
557 intel_uncore_write(uncore,
559 l3cc_combine(&table, low, high));
562 /* Odd table size - 1 left over */
563 if (table.size & 0x01) {
564 u16 low = get_entry_l3cc(&table, 2 * i);
566 intel_uncore_write(uncore,
568 l3cc_combine(&table, low, unused_value));
572 /* All remaining entries are also unused */
573 for (; i < table.n_entries / 2; i++)
574 intel_uncore_write(uncore,
576 l3cc_combine(&table, unused_value,
581 * intel_mocs_emit() - program the MOCS register.
582 * @rq: Request to use to set up the MOCS tables.
584 * This function will emit a batch buffer with the values required for
585 * programming the MOCS register values for all the currently supported
588 * These registers are partially stored in the RCS context, so they are
589 * emitted at the same time so that when a context is created these registers
590 * are set up. These registers have to be emitted into the start of the
591 * context as setting the ELSP will re-init some of these registers back
594 * Return: 0 on success, otherwise the error status.
596 int intel_mocs_emit(struct i915_request *rq)
598 struct drm_i915_mocs_table t;
601 if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915) ||
602 rq->engine->class != RENDER_CLASS)
605 if (get_mocs_settings(rq->engine->gt, &t)) {
606 /* Program the RCS control registers */
607 ret = emit_mocs_control_table(rq, &t);
611 /* Now program the l3cc registers */
612 ret = emit_mocs_l3cc_table(rq, &t);
620 void intel_mocs_init(struct intel_gt *gt)
622 intel_mocs_init_l3cc_table(gt);
624 if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
625 intel_mocs_init_global(gt);