2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 * DEALINGS IN THE SOFTWARE.
27 #include "intel_engine.h"
30 #define RING_ELSP(base) _MMIO((base) + 0x230)
31 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
32 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
33 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
34 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
35 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
36 #define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
37 #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
38 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
39 #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
40 #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
42 #define EL_CTRL_LOAD (1 << 0)
44 /* The docs specify that the write pointer wraps around after 5h, "After status
45 * is written out to the last available status QW at offset 5h, this pointer
48 * Therefore, one must infer than even though there are 3 bits available, 6 and
49 * 7 appear to be * reserved.
51 #define GEN8_CSB_ENTRIES 6
52 #define GEN8_CSB_PTR_MASK 0x7
53 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
54 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
56 #define GEN11_CSB_ENTRIES 12
57 #define GEN11_CSB_PTR_MASK 0xf
58 #define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
59 #define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
62 INTEL_CONTEXT_SCHEDULE_IN = 0,
63 INTEL_CONTEXT_SCHEDULE_OUT,
64 INTEL_CONTEXT_SCHEDULE_PREEMPTED,
68 void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
70 int intel_execlists_submission_setup(struct intel_engine_cs *engine);
71 int intel_execlists_submission_init(struct intel_engine_cs *engine);
73 /* Logical Ring Contexts */
76 * We allocate a header at the start of the context image for our own
77 * use, therefore the actual location of the logical state is offset
78 * from the start of the VMA. The layout is
80 * | [guc] | [hwsp] [logical state] |
81 * |<- our header ->|<- context image ->|
84 /* The first page is used for sharing data with the GuC */
85 #define LRC_GUCSHR_PN (0)
86 #define LRC_GUCSHR_SZ (1)
87 /* At the start of the context image is its per-process HWS page */
88 #define LRC_PPHWSP_PN (LRC_GUCSHR_PN + LRC_GUCSHR_SZ)
89 #define LRC_PPHWSP_SZ (1)
90 /* Finally we have the logical state for the context */
91 #define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
94 * Currently we include the PPHWSP in __intel_engine_context_size() so
95 * the size of the header is synonymous with the start of the PPHWSP.
97 #define LRC_HEADER_PAGES LRC_PPHWSP_PN
101 struct drm_i915_private;
103 void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
105 void intel_lr_context_reset(struct intel_engine_cs *engine,
106 struct intel_context *ce,
110 void intel_execlists_show_requests(struct intel_engine_cs *engine,
111 struct drm_printer *m,
112 void (*show_request)(struct drm_printer *m,
113 struct i915_request *rq,
117 struct intel_context *
118 intel_execlists_create_virtual(struct i915_gem_context *ctx,
119 struct intel_engine_cs **siblings,
122 struct intel_context *
123 intel_execlists_clone_virtual(struct i915_gem_context *ctx,
124 struct intel_engine_cs *src);
126 int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
127 const struct intel_engine_cs *master,
128 const struct intel_engine_cs *sibling);
130 #endif /* _INTEL_LRC_H_ */