2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include "i915_drv.h"
137 #include "i915_perf.h"
138 #include "i915_trace.h"
139 #include "i915_vgpu.h"
140 #include "intel_context.h"
141 #include "intel_engine_pm.h"
142 #include "intel_gt.h"
143 #include "intel_gt_pm.h"
144 #include "intel_gt_requests.h"
145 #include "intel_lrc_reg.h"
146 #include "intel_mocs.h"
147 #include "intel_reset.h"
148 #include "intel_ring.h"
149 #include "intel_workarounds.h"
151 #define RING_EXECLIST_QFULL (1 << 0x2)
152 #define RING_EXECLIST1_VALID (1 << 0x3)
153 #define RING_EXECLIST0_VALID (1 << 0x4)
154 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
155 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
156 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
158 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
159 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
160 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
161 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
162 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
163 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
165 #define GEN8_CTX_STATUS_COMPLETED_MASK \
166 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
168 #define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
170 #define GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE (0x1) /* lower csb dword */
171 #define GEN12_CTX_SWITCH_DETAIL(csb_dw) ((csb_dw) & 0xF) /* upper csb dword */
172 #define GEN12_CSB_SW_CTX_ID_MASK GENMASK(25, 15)
173 #define GEN12_IDLE_CTX_ID 0x7FF
174 #define GEN12_CSB_CTX_VALID(csb_dw) \
175 (FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID)
177 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
178 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
180 struct virtual_engine {
181 struct intel_engine_cs base;
182 struct intel_context context;
185 * We allow only a single request through the virtual engine at a time
186 * (each request in the timeline waits for the completion fence of
187 * the previous before being submitted). By restricting ourselves to
188 * only submitting a single request, each request is placed on to a
189 * physical to maximise load spreading (by virtue of the late greedy
190 * scheduling -- each real engine takes the next available request
193 struct i915_request *request;
196 * We keep a rbtree of available virtual engines inside each physical
197 * engine, sorted by priority. Here we preallocate the nodes we need
198 * for the virtual engine, indexed by physical_engine->id.
203 } nodes[I915_NUM_ENGINES];
206 * Keep track of bonded pairs -- restrictions upon on our selection
207 * of physical engines any particular request may be submitted to.
208 * If we receive a submit-fence from a master engine, we will only
209 * use one of sibling_mask physical engines.
212 const struct intel_engine_cs *master;
213 intel_engine_mask_t sibling_mask;
215 unsigned int num_bonds;
217 /* And finally, which physical engines this virtual engine maps onto. */
218 unsigned int num_siblings;
219 struct intel_engine_cs *siblings[0];
222 static struct virtual_engine *to_virtual_engine(struct intel_engine_cs *engine)
224 GEM_BUG_ON(!intel_engine_is_virtual(engine));
225 return container_of(engine, struct virtual_engine, base);
228 static int __execlists_context_alloc(struct intel_context *ce,
229 struct intel_engine_cs *engine);
231 static void execlists_init_reg_state(u32 *reg_state,
232 const struct intel_context *ce,
233 const struct intel_engine_cs *engine,
234 const struct intel_ring *ring,
237 __execlists_update_reg_state(const struct intel_context *ce,
238 const struct intel_engine_cs *engine,
241 static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
243 if (INTEL_GEN(engine->i915) >= 12)
245 else if (INTEL_GEN(engine->i915) >= 9)
247 else if (engine->class == RENDER_CLASS)
253 static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
255 if (INTEL_GEN(engine->i915) >= 12)
257 else if (INTEL_GEN(engine->i915) >= 9)
259 else if (engine->class == RENDER_CLASS)
265 static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
267 if (INTEL_GEN(engine->i915) >= 12)
269 else if (INTEL_GEN(engine->i915) >= 9 || engine->class == RENDER_CLASS)
275 static int lrc_ring_indirect_ptr(const struct intel_engine_cs *engine)
279 x = lrc_ring_wa_bb_per_ctx(engine);
286 static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)
290 x = lrc_ring_indirect_ptr(engine);
298 lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
300 switch (INTEL_GEN(engine->i915)) {
302 MISSING_CASE(INTEL_GEN(engine->i915));
305 return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
307 return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
309 return GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
311 return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
313 return GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
317 static u32 intel_context_get_runtime(const struct intel_context *ce)
320 * We can use either ppHWSP[16] which is recorded before the context
321 * switch (and so excludes the cost of context switches) or use the
322 * value from the context image itself, which is saved/restored earlier
323 * and so includes the cost of the save.
325 return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
328 static void mark_eio(struct i915_request *rq)
330 if (i915_request_completed(rq))
333 GEM_BUG_ON(i915_request_signaled(rq));
335 i915_request_set_error_once(rq, -EIO);
336 i915_request_mark_complete(rq);
339 static struct i915_request *
340 active_request(const struct intel_timeline * const tl, struct i915_request *rq)
342 struct i915_request *active = rq;
345 list_for_each_entry_continue_reverse(rq, &tl->requests, link) {
346 if (i915_request_completed(rq))
356 static inline u32 intel_hws_preempt_address(struct intel_engine_cs *engine)
358 return (i915_ggtt_offset(engine->status_page.vma) +
359 I915_GEM_HWS_PREEMPT_ADDR);
363 ring_set_paused(const struct intel_engine_cs *engine, int state)
366 * We inspect HWS_PREEMPT with a semaphore inside
367 * engine->emit_fini_breadcrumb. If the dword is true,
368 * the ring is paused as the semaphore will busywait
369 * until the dword is false.
371 engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;
376 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
378 return rb_entry(rb, struct i915_priolist, node);
381 static inline int rq_prio(const struct i915_request *rq)
383 return READ_ONCE(rq->sched.attr.priority);
386 static int effective_prio(const struct i915_request *rq)
388 int prio = rq_prio(rq);
391 * If this request is special and must not be interrupted at any
392 * cost, so be it. Note we are only checking the most recent request
393 * in the context and so may be masking an earlier vip request. It
394 * is hoped that under the conditions where nopreempt is used, this
395 * will not matter (i.e. all requests to that context will be
396 * nopreempt for as long as desired).
398 if (i915_request_has_nopreempt(rq))
399 prio = I915_PRIORITY_UNPREEMPTABLE;
402 * On unwinding the active request, we give it a priority bump
403 * if it has completed waiting on any semaphore. If we know that
404 * the request has already started, we can prevent an unwanted
405 * preempt-to-idle cycle by taking that into account now.
407 if (__i915_request_has_started(rq))
408 prio |= I915_PRIORITY_NOSEMAPHORE;
410 /* Restrict mere WAIT boosts from triggering preemption */
411 BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */
412 return prio | __NO_PREEMPTION;
415 static int queue_prio(const struct intel_engine_execlists *execlists)
417 struct i915_priolist *p;
420 rb = rb_first_cached(&execlists->queue);
425 * As the priolist[] are inverted, with the highest priority in [0],
426 * we have to flip the index value to become priority.
429 return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
432 static inline bool need_preempt(const struct intel_engine_cs *engine,
433 const struct i915_request *rq,
438 if (!intel_engine_has_semaphores(engine))
442 * Check if the current priority hint merits a preemption attempt.
444 * We record the highest value priority we saw during rescheduling
445 * prior to this dequeue, therefore we know that if it is strictly
446 * less than the current tail of ESLP[0], we do not need to force
447 * a preempt-to-idle cycle.
449 * However, the priority hint is a mere hint that we may need to
450 * preempt. If that hint is stale or we may be trying to preempt
451 * ourselves, ignore the request.
453 * More naturally we would write
454 * prio >= max(0, last);
455 * except that we wish to prevent triggering preemption at the same
456 * priority level: the task that is running should remain running
457 * to preserve FIFO ordering of dependencies.
459 last_prio = max(effective_prio(rq), I915_PRIORITY_NORMAL - 1);
460 if (engine->execlists.queue_priority_hint <= last_prio)
464 * Check against the first request in ELSP[1], it will, thanks to the
465 * power of PI, be the highest priority of that context.
467 if (!list_is_last(&rq->sched.link, &engine->active.requests) &&
468 rq_prio(list_next_entry(rq, sched.link)) > last_prio)
472 struct virtual_engine *ve =
473 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
474 bool preempt = false;
476 if (engine == ve->siblings[0]) { /* only preempt one sibling */
477 struct i915_request *next;
480 next = READ_ONCE(ve->request);
482 preempt = rq_prio(next) > last_prio;
491 * If the inflight context did not trigger the preemption, then maybe
492 * it was the set of queued requests? Pick the highest priority in
493 * the queue (the first active priolist) and see if it deserves to be
494 * running instead of ELSP[0].
496 * The highest priority request in the queue can not be either
497 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same
498 * context, it's priority would not exceed ELSP[0] aka last_prio.
500 return queue_prio(&engine->execlists) > last_prio;
503 __maybe_unused static inline bool
504 assert_priority_queue(const struct i915_request *prev,
505 const struct i915_request *next)
508 * Without preemption, the prev may refer to the still active element
509 * which we refuse to let go.
511 * Even with preemption, there are times when we think it is better not
512 * to preempt and leave an ostensibly lower priority request in flight.
514 if (i915_request_is_active(prev))
517 return rq_prio(prev) >= rq_prio(next);
521 * The context descriptor encodes various attributes of a context,
522 * including its GTT address and some flags. Because it's fairly
523 * expensive to calculate, we'll just do it once and cache the result,
524 * which remains valid until the context is unpinned.
526 * This is what a descriptor looks like, from LSB to MSB::
528 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
529 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
530 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
531 * bits 53-54: mbz, reserved for use by hardware
532 * bits 55-63: group ID, currently unused and set to 0
534 * Starting from Gen11, the upper dword of the descriptor has a new format:
536 * bits 32-36: reserved
537 * bits 37-47: SW context ID
538 * bits 48:53: engine instance
539 * bit 54: mbz, reserved for use by hardware
540 * bits 55-60: SW counter
541 * bits 61-63: engine class
543 * engine info, SW context ID and SW counter need to form a unique number
544 * (Context ID) per lrc.
547 lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
551 desc = INTEL_LEGACY_32B_CONTEXT;
552 if (i915_vm_is_4lvl(ce->vm))
553 desc = INTEL_LEGACY_64B_CONTEXT;
554 desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
556 desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
557 if (IS_GEN(engine->i915, 8))
558 desc |= GEN8_CTX_L3LLC_COHERENT;
560 desc |= i915_ggtt_offset(ce->state); /* bits 12-31 */
562 * The following 32bits are copied into the OA reports (dword 2).
563 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
566 if (INTEL_GEN(engine->i915) >= 11) {
567 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
570 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
577 static inline unsigned int dword_in_page(void *addr)
579 return offset_in_page(addr) / sizeof(u32);
582 static void set_offsets(u32 *regs,
584 const struct intel_engine_cs *engine,
586 #define NOP(x) (BIT(7) | (x))
587 #define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6)))
588 #define POSTED BIT(0)
589 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))
591 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \
593 #define END(x) 0, (x)
595 const u32 base = engine->mmio_base;
600 if (*data & BIT(7)) { /* skip */
601 count = *data++ & ~BIT(7);
603 memset32(regs, MI_NOOP, count);
608 count = *data & 0x3f;
612 *regs = MI_LOAD_REGISTER_IMM(count);
614 *regs |= MI_LRI_FORCE_POSTED;
615 if (INTEL_GEN(engine->i915) >= 11)
616 *regs |= MI_LRI_CS_MMIO;
627 offset |= v & ~BIT(7);
628 } while (v & BIT(7));
630 regs[0] = base + (offset << 2);
640 /* Clear past the tail for HW access */
641 GEM_BUG_ON(dword_in_page(regs) > count);
642 memset32(regs, MI_NOOP, count - dword_in_page(regs));
644 /* Close the batch; used mainly by live_lrc_layout() */
645 *regs = MI_BATCH_BUFFER_END;
646 if (INTEL_GEN(engine->i915) >= 10)
651 static const u8 gen8_xcs_offsets[] = {
686 static const u8 gen9_xcs_offsets[] = {
770 static const u8 gen12_xcs_offsets[] = {
802 static const u8 gen8_rcs_offsets[] = {
839 static const u8 gen9_rcs_offsets[] = {
923 static const u8 gen11_rcs_offsets[] = {
964 static const u8 gen12_rcs_offsets[] = {
1011 static const u8 *reg_offsets(const struct intel_engine_cs *engine)
1014 * The gen12+ lists only have the registers we program in the basic
1015 * default state. We rely on the context image using relative
1016 * addressing to automatic fixup the register state between the
1017 * physical engines for virtual engine.
1019 GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
1020 !intel_engine_has_relative_mmio(engine));
1022 if (engine->class == RENDER_CLASS) {
1023 if (INTEL_GEN(engine->i915) >= 12)
1024 return gen12_rcs_offsets;
1025 else if (INTEL_GEN(engine->i915) >= 11)
1026 return gen11_rcs_offsets;
1027 else if (INTEL_GEN(engine->i915) >= 9)
1028 return gen9_rcs_offsets;
1030 return gen8_rcs_offsets;
1032 if (INTEL_GEN(engine->i915) >= 12)
1033 return gen12_xcs_offsets;
1034 else if (INTEL_GEN(engine->i915) >= 9)
1035 return gen9_xcs_offsets;
1037 return gen8_xcs_offsets;
1041 static struct i915_request *
1042 __unwind_incomplete_requests(struct intel_engine_cs *engine)
1044 struct i915_request *rq, *rn, *active = NULL;
1045 struct list_head *uninitialized_var(pl);
1046 int prio = I915_PRIORITY_INVALID;
1048 lockdep_assert_held(&engine->active.lock);
1050 list_for_each_entry_safe_reverse(rq, rn,
1051 &engine->active.requests,
1053 if (i915_request_completed(rq))
1056 __i915_request_unsubmit(rq);
1059 * Push the request back into the queue for later resubmission.
1060 * If this request is not native to this physical engine (i.e.
1061 * it came from a virtual source), push it back onto the virtual
1062 * engine so that it can be moved across onto another physical
1063 * engine as load dictates.
1065 if (likely(rq->execution_mask == engine->mask)) {
1066 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
1067 if (rq_prio(rq) != prio) {
1069 pl = i915_sched_lookup_priolist(engine, prio);
1071 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1073 list_move(&rq->sched.link, pl);
1074 set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
1078 struct intel_engine_cs *owner = rq->context->engine;
1081 * Decouple the virtual breadcrumb before moving it
1082 * back to the virtual engine -- we don't want the
1083 * request to complete in the background and try
1084 * and cancel the breadcrumb on the virtual engine
1085 * (instead of the old engine where it is linked)!
1087 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
1088 &rq->fence.flags)) {
1089 spin_lock_nested(&rq->lock,
1090 SINGLE_DEPTH_NESTING);
1091 i915_request_cancel_breadcrumb(rq);
1092 spin_unlock(&rq->lock);
1094 WRITE_ONCE(rq->engine, owner);
1095 owner->submit_request(rq);
1103 struct i915_request *
1104 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
1106 struct intel_engine_cs *engine =
1107 container_of(execlists, typeof(*engine), execlists);
1109 return __unwind_incomplete_requests(engine);
1113 execlists_context_status_change(struct i915_request *rq, unsigned long status)
1116 * Only used when GVT-g is enabled now. When GVT-g is disabled,
1117 * The compiler should eliminate this function as dead-code.
1119 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
1122 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
1126 static void intel_engine_context_in(struct intel_engine_cs *engine)
1128 unsigned long flags;
1130 if (READ_ONCE(engine->stats.enabled) == 0)
1133 write_seqlock_irqsave(&engine->stats.lock, flags);
1135 if (engine->stats.enabled > 0) {
1136 if (engine->stats.active++ == 0)
1137 engine->stats.start = ktime_get();
1138 GEM_BUG_ON(engine->stats.active == 0);
1141 write_sequnlock_irqrestore(&engine->stats.lock, flags);
1144 static void intel_engine_context_out(struct intel_engine_cs *engine)
1146 unsigned long flags;
1148 if (READ_ONCE(engine->stats.enabled) == 0)
1151 write_seqlock_irqsave(&engine->stats.lock, flags);
1153 if (engine->stats.enabled > 0) {
1156 if (engine->stats.active && --engine->stats.active == 0) {
1158 * Decrement the active context count and in case GPU
1159 * is now idle add up to the running total.
1161 last = ktime_sub(ktime_get(), engine->stats.start);
1163 engine->stats.total = ktime_add(engine->stats.total,
1165 } else if (engine->stats.active == 0) {
1167 * After turning on engine stats, context out might be
1168 * the first event in which case we account from the
1169 * time stats gathering was turned on.
1171 last = ktime_sub(ktime_get(), engine->stats.enabled_at);
1173 engine->stats.total = ktime_add(engine->stats.total,
1178 write_sequnlock_irqrestore(&engine->stats.lock, flags);
1182 execlists_check_context(const struct intel_context *ce,
1183 const struct intel_engine_cs *engine)
1185 const struct intel_ring *ring = ce->ring;
1186 u32 *regs = ce->lrc_reg_state;
1190 if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {
1191 pr_err("%s: context submitted with incorrect RING_START [%08x], expected %08x\n",
1193 regs[CTX_RING_START],
1194 i915_ggtt_offset(ring->vma));
1195 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
1199 if ((regs[CTX_RING_CTL] & ~(RING_WAIT | RING_WAIT_SEMAPHORE)) !=
1200 (RING_CTL_SIZE(ring->size) | RING_VALID)) {
1201 pr_err("%s: context submitted with incorrect RING_CTL [%08x], expected %08x\n",
1204 (u32)(RING_CTL_SIZE(ring->size) | RING_VALID));
1205 regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
1209 x = lrc_ring_mi_mode(engine);
1210 if (x != -1 && regs[x + 1] & (regs[x + 1] >> 16) & STOP_RING) {
1211 pr_err("%s: context submitted with STOP_RING [%08x] in RING_MI_MODE\n",
1212 engine->name, regs[x + 1]);
1213 regs[x + 1] &= ~STOP_RING;
1214 regs[x + 1] |= STOP_RING << 16;
1218 WARN_ONCE(!valid, "Invalid lrc state found before submission\n");
1221 static void restore_default_state(struct intel_context *ce,
1222 struct intel_engine_cs *engine)
1224 u32 *regs = ce->lrc_reg_state;
1226 if (engine->pinned_default_state)
1227 memcpy(regs, /* skip restoring the vanilla PPHWSP */
1228 engine->pinned_default_state + LRC_STATE_OFFSET,
1229 engine->context_size - PAGE_SIZE);
1231 execlists_init_reg_state(regs, ce, engine, ce->ring, false);
1232 ce->runtime.last = intel_context_get_runtime(ce);
1235 static void reset_active(struct i915_request *rq,
1236 struct intel_engine_cs *engine)
1238 struct intel_context * const ce = rq->context;
1242 * The executing context has been cancelled. We want to prevent
1243 * further execution along this context and propagate the error on
1244 * to anything depending on its results.
1246 * In __i915_request_submit(), we apply the -EIO and remove the
1247 * requests' payloads for any banned requests. But first, we must
1248 * rewind the context back to the start of the incomplete request so
1249 * that we do not jump back into the middle of the batch.
1251 * We preserve the breadcrumbs and semaphores of the incomplete
1252 * requests so that inter-timeline dependencies (i.e other timelines)
1253 * remain correctly ordered. And we defer to __i915_request_submit()
1254 * so that all asynchronous waits are correctly handled.
1256 ENGINE_TRACE(engine, "{ rq=%llx:%lld }\n",
1257 rq->fence.context, rq->fence.seqno);
1259 /* On resubmission of the active request, payload will be scrubbed */
1260 if (i915_request_completed(rq))
1263 head = active_request(ce->timeline, rq)->head;
1264 head = intel_ring_wrap(ce->ring, head);
1266 /* Scrub the context image to prevent replaying the previous batch */
1267 restore_default_state(ce, engine);
1268 __execlists_update_reg_state(ce, engine, head);
1270 /* We've switched away, so this should be a no-op, but intent matters */
1271 ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
1274 static void st_update_runtime_underflow(struct intel_context *ce, s32 dt)
1276 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1277 ce->runtime.num_underflow += dt < 0;
1278 ce->runtime.max_underflow = max_t(u32, ce->runtime.max_underflow, -dt);
1282 static void intel_context_update_runtime(struct intel_context *ce)
1287 if (intel_context_is_barrier(ce))
1290 old = ce->runtime.last;
1291 ce->runtime.last = intel_context_get_runtime(ce);
1292 dt = ce->runtime.last - old;
1294 if (unlikely(dt <= 0)) {
1295 CE_TRACE(ce, "runtime underflow: last=%u, new=%u, delta=%d\n",
1296 old, ce->runtime.last, dt);
1297 st_update_runtime_underflow(ce, dt);
1301 ewma_runtime_add(&ce->runtime.avg, dt);
1302 ce->runtime.total += dt;
1305 static inline struct intel_engine_cs *
1306 __execlists_schedule_in(struct i915_request *rq)
1308 struct intel_engine_cs * const engine = rq->engine;
1309 struct intel_context * const ce = rq->context;
1311 intel_context_get(ce);
1313 if (unlikely(intel_context_is_banned(ce)))
1314 reset_active(rq, engine);
1316 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1317 execlists_check_context(ce, engine);
1319 ce->lrc_desc &= ~GENMASK_ULL(47, 37);
1321 /* Use a fixed tag for OA and friends */
1322 ce->lrc_desc |= (u64)ce->tag << 32;
1324 /* We don't need a strict matching tag, just different values */
1326 (u64)(++engine->context_tag % NUM_CONTEXT_TAG) <<
1327 GEN11_SW_CTX_ID_SHIFT;
1328 BUILD_BUG_ON(NUM_CONTEXT_TAG > GEN12_MAX_CONTEXT_HW_ID);
1331 __intel_gt_pm_get(engine->gt);
1332 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
1333 intel_engine_context_in(engine);
1338 static inline struct i915_request *
1339 execlists_schedule_in(struct i915_request *rq, int idx)
1341 struct intel_context * const ce = rq->context;
1342 struct intel_engine_cs *old;
1344 GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
1345 trace_i915_request_in(rq, idx);
1347 old = READ_ONCE(ce->inflight);
1350 WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq));
1353 } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old)));
1355 GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
1356 return i915_request_get(rq);
1359 static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
1361 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
1362 struct i915_request *next = READ_ONCE(ve->request);
1364 if (next && next->execution_mask & ~rq->execution_mask)
1365 tasklet_schedule(&ve->base.execlists.tasklet);
1369 __execlists_schedule_out(struct i915_request *rq,
1370 struct intel_engine_cs * const engine)
1372 struct intel_context * const ce = rq->context;
1375 * NB process_csb() is not under the engine->active.lock and hence
1376 * schedule_out can race with schedule_in meaning that we should
1377 * refrain from doing non-trivial work here.
1381 * If we have just completed this context, the engine may now be
1382 * idle and we want to re-enter powersaving.
1384 if (list_is_last_rcu(&rq->link, &ce->timeline->requests) &&
1385 i915_request_completed(rq))
1386 intel_engine_add_retire(engine, ce->timeline);
1388 intel_context_update_runtime(ce);
1389 intel_engine_context_out(engine);
1390 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
1391 intel_gt_pm_put_async(engine->gt);
1394 * If this is part of a virtual engine, its next request may
1395 * have been blocked waiting for access to the active context.
1396 * We have to kick all the siblings again in case we need to
1397 * switch (e.g. the next request is not runnable on this
1398 * engine). Hopefully, we will already have submitted the next
1399 * request before the tasklet runs and do not need to rebuild
1400 * each virtual tree and kick everyone again.
1402 if (ce->engine != engine)
1403 kick_siblings(rq, ce);
1405 intel_context_put(ce);
1409 execlists_schedule_out(struct i915_request *rq)
1411 struct intel_context * const ce = rq->context;
1412 struct intel_engine_cs *cur, *old;
1414 trace_i915_request_out(rq);
1416 old = READ_ONCE(ce->inflight);
1418 cur = ptr_unmask_bits(old, 2) ? ptr_dec(old) : NULL;
1419 while (!try_cmpxchg(&ce->inflight, &old, cur));
1421 __execlists_schedule_out(rq, old);
1423 i915_request_put(rq);
1426 static u64 execlists_update_context(struct i915_request *rq)
1428 struct intel_context *ce = rq->context;
1429 u64 desc = ce->lrc_desc;
1433 * WaIdleLiteRestore:bdw,skl
1435 * We should never submit the context with the same RING_TAIL twice
1436 * just in case we submit an empty ring, which confuses the HW.
1438 * We append a couple of NOOPs (gen8_emit_wa_tail) after the end of
1439 * the normal request to be able to always advance the RING_TAIL on
1440 * subsequent resubmissions (for lite restore). Should that fail us,
1441 * and we try and submit the same tail again, force the context
1444 * If we need to return to a preempted context, we need to skip the
1445 * lite-restore and force it to reload the RING_TAIL. Otherwise, the
1446 * HW has a tendency to ignore us rewinding the TAIL to the end of
1447 * an earlier request.
1449 tail = intel_ring_set_tail(rq->ring, rq->tail);
1450 prev = ce->lrc_reg_state[CTX_RING_TAIL];
1451 if (unlikely(intel_ring_direction(rq->ring, tail, prev) <= 0))
1452 desc |= CTX_DESC_FORCE_RESTORE;
1453 ce->lrc_reg_state[CTX_RING_TAIL] = tail;
1454 rq->tail = rq->wa_tail;
1457 * Make sure the context image is complete before we submit it to HW.
1459 * Ostensibly, writes (including the WCB) should be flushed prior to
1460 * an uncached write such as our mmio register access, the empirical
1461 * evidence (esp. on Braswell) suggests that the WC write into memory
1462 * may not be visible to the HW prior to the completion of the UC
1463 * register write and that we may begin execution from the context
1464 * before its image is complete leading to invalid PD chasing.
1468 ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;
1472 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
1474 if (execlists->ctrl_reg) {
1475 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
1476 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
1478 writel(upper_32_bits(desc), execlists->submit_reg);
1479 writel(lower_32_bits(desc), execlists->submit_reg);
1483 static __maybe_unused char *
1484 dump_port(char *buf, int buflen, const char *prefix, struct i915_request *rq)
1489 snprintf(buf, buflen, "%s%llx:%lld%s prio %d",
1491 rq->fence.context, rq->fence.seqno,
1492 i915_request_completed(rq) ? "!" :
1493 i915_request_started(rq) ? "*" :
1500 static __maybe_unused void
1501 trace_ports(const struct intel_engine_execlists *execlists,
1503 struct i915_request * const *ports)
1505 const struct intel_engine_cs *engine =
1506 container_of(execlists, typeof(*engine), execlists);
1507 char __maybe_unused p0[40], p1[40];
1512 ENGINE_TRACE(engine, "%s { %s%s }\n", msg,
1513 dump_port(p0, sizeof(p0), "", ports[0]),
1514 dump_port(p1, sizeof(p1), ", ", ports[1]));
1518 reset_in_progress(const struct intel_engine_execlists *execlists)
1520 return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
1523 static __maybe_unused bool
1524 assert_pending_valid(const struct intel_engine_execlists *execlists,
1527 struct i915_request * const *port, *rq;
1528 struct intel_context *ce = NULL;
1529 bool sentinel = false;
1531 trace_ports(execlists, msg, execlists->pending);
1533 /* We may be messing around with the lists during reset, lalala */
1534 if (reset_in_progress(execlists))
1537 if (!execlists->pending[0]) {
1538 GEM_TRACE_ERR("Nothing pending for promotion!\n");
1542 if (execlists->pending[execlists_num_ports(execlists)]) {
1543 GEM_TRACE_ERR("Excess pending[%d] for promotion!\n",
1544 execlists_num_ports(execlists));
1548 for (port = execlists->pending; (rq = *port); port++) {
1549 unsigned long flags;
1552 GEM_BUG_ON(!kref_read(&rq->fence.refcount));
1553 GEM_BUG_ON(!i915_request_is_active(rq));
1555 if (ce == rq->context) {
1556 GEM_TRACE_ERR("Dup context:%llx in pending[%zd]\n",
1557 ce->timeline->fence_context,
1558 port - execlists->pending);
1564 * Sentinels are supposed to be lonely so they flush the
1565 * current exection off the HW. Check that they are the
1566 * only request in the pending submission.
1569 GEM_TRACE_ERR("context:%llx after sentinel in pending[%zd]\n",
1570 ce->timeline->fence_context,
1571 port - execlists->pending);
1575 sentinel = i915_request_has_sentinel(rq);
1576 if (sentinel && port != execlists->pending) {
1577 GEM_TRACE_ERR("sentinel context:%llx not in prime position[%zd]\n",
1578 ce->timeline->fence_context,
1579 port - execlists->pending);
1583 /* Hold tightly onto the lock to prevent concurrent retires! */
1584 if (!spin_trylock_irqsave(&rq->lock, flags))
1587 if (i915_request_completed(rq))
1590 if (i915_active_is_idle(&ce->active) &&
1591 !intel_context_is_barrier(ce)) {
1592 GEM_TRACE_ERR("Inactive context:%llx in pending[%zd]\n",
1593 ce->timeline->fence_context,
1594 port - execlists->pending);
1599 if (!i915_vma_is_pinned(ce->state)) {
1600 GEM_TRACE_ERR("Unpinned context:%llx in pending[%zd]\n",
1601 ce->timeline->fence_context,
1602 port - execlists->pending);
1607 if (!i915_vma_is_pinned(ce->ring->vma)) {
1608 GEM_TRACE_ERR("Unpinned ring:%llx in pending[%zd]\n",
1609 ce->timeline->fence_context,
1610 port - execlists->pending);
1616 spin_unlock_irqrestore(&rq->lock, flags);
1624 static void execlists_submit_ports(struct intel_engine_cs *engine)
1626 struct intel_engine_execlists *execlists = &engine->execlists;
1629 GEM_BUG_ON(!assert_pending_valid(execlists, "submit"));
1632 * We can skip acquiring intel_runtime_pm_get() here as it was taken
1633 * on our behalf by the request (see i915_gem_mark_busy()) and it will
1634 * not be relinquished until the device is idle (see
1635 * i915_gem_idle_work_handler()). As a precaution, we make sure
1636 * that all ELSP are drained i.e. we have processed the CSB,
1637 * before allowing ourselves to idle and calling intel_runtime_pm_put().
1639 GEM_BUG_ON(!intel_engine_pm_is_awake(engine));
1642 * ELSQ note: the submit queue is not cleared after being submitted
1643 * to the HW so we need to make sure we always clean it up. This is
1644 * currently ensured by the fact that we always write the same number
1645 * of elsq entries, keep this in mind before changing the loop below.
1647 for (n = execlists_num_ports(execlists); n--; ) {
1648 struct i915_request *rq = execlists->pending[n];
1650 write_desc(execlists,
1651 rq ? execlists_update_context(rq) : 0,
1655 /* we need to manually load the submit queue */
1656 if (execlists->ctrl_reg)
1657 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
1660 static bool ctx_single_port_submission(const struct intel_context *ce)
1662 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
1663 intel_context_force_single_submission(ce));
1666 static bool can_merge_ctx(const struct intel_context *prev,
1667 const struct intel_context *next)
1672 if (ctx_single_port_submission(prev))
1678 static unsigned long i915_request_flags(const struct i915_request *rq)
1680 return READ_ONCE(rq->fence.flags);
1683 static bool can_merge_rq(const struct i915_request *prev,
1684 const struct i915_request *next)
1686 GEM_BUG_ON(prev == next);
1687 GEM_BUG_ON(!assert_priority_queue(prev, next));
1690 * We do not submit known completed requests. Therefore if the next
1691 * request is already completed, we can pretend to merge it in
1692 * with the previous context (and we will skip updating the ELSP
1693 * and tracking). Thus hopefully keeping the ELSP full with active
1694 * contexts, despite the best efforts of preempt-to-busy to confuse
1697 if (i915_request_completed(next))
1700 if (unlikely((i915_request_flags(prev) ^ i915_request_flags(next)) &
1701 (BIT(I915_FENCE_FLAG_NOPREEMPT) |
1702 BIT(I915_FENCE_FLAG_SENTINEL))))
1705 if (!can_merge_ctx(prev->context, next->context))
1708 GEM_BUG_ON(i915_seqno_passed(prev->fence.seqno, next->fence.seqno));
1712 static void virtual_update_register_offsets(u32 *regs,
1713 struct intel_engine_cs *engine)
1715 set_offsets(regs, reg_offsets(engine), engine, false);
1718 static bool virtual_matches(const struct virtual_engine *ve,
1719 const struct i915_request *rq,
1720 const struct intel_engine_cs *engine)
1722 const struct intel_engine_cs *inflight;
1724 if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */
1728 * We track when the HW has completed saving the context image
1729 * (i.e. when we have seen the final CS event switching out of
1730 * the context) and must not overwrite the context image before
1731 * then. This restricts us to only using the active engine
1732 * while the previous virtualized request is inflight (so
1733 * we reuse the register offsets). This is a very small
1734 * hystersis on the greedy seelction algorithm.
1736 inflight = intel_context_inflight(&ve->context);
1737 if (inflight && inflight != engine)
1743 static void virtual_xfer_breadcrumbs(struct virtual_engine *ve,
1744 struct i915_request *rq)
1746 struct intel_engine_cs *old = ve->siblings[0];
1748 /* All unattached (rq->engine == old) must already be completed */
1750 spin_lock(&old->breadcrumbs.irq_lock);
1751 if (!list_empty(&ve->context.signal_link)) {
1752 list_del_init(&ve->context.signal_link);
1755 * We cannot acquire the new engine->breadcrumbs.irq_lock
1756 * (as we are holding a breadcrumbs.irq_lock already),
1757 * so attach this request to the signaler on submission.
1758 * The queued irq_work will occur when we finally drop
1759 * the engine->active.lock after dequeue.
1761 set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags);
1763 /* Also transfer the pending irq_work for the old breadcrumb. */
1764 intel_engine_signal_breadcrumbs(rq->engine);
1766 spin_unlock(&old->breadcrumbs.irq_lock);
1769 #define for_each_waiter(p__, rq__) \
1770 list_for_each_entry_lockless(p__, \
1771 &(rq__)->sched.waiters_list, \
1774 #define for_each_signaler(p__, rq__) \
1775 list_for_each_entry_rcu(p__, \
1776 &(rq__)->sched.signalers_list, \
1779 static void defer_request(struct i915_request *rq, struct list_head * const pl)
1784 * We want to move the interrupted request to the back of
1785 * the round-robin list (i.e. its priority level), but
1786 * in doing so, we must then move all requests that were in
1787 * flight and were waiting for the interrupted request to
1788 * be run after it again.
1791 struct i915_dependency *p;
1793 GEM_BUG_ON(i915_request_is_active(rq));
1794 list_move_tail(&rq->sched.link, pl);
1796 for_each_waiter(p, rq) {
1797 struct i915_request *w =
1798 container_of(p->waiter, typeof(*w), sched);
1800 /* Leave semaphores spinning on the other engines */
1801 if (w->engine != rq->engine)
1804 /* No waiter should start before its signaler */
1805 GEM_BUG_ON(i915_request_started(w) &&
1806 !i915_request_completed(rq));
1808 GEM_BUG_ON(i915_request_is_active(w));
1809 if (!i915_request_is_ready(w))
1812 if (rq_prio(w) < rq_prio(rq))
1815 GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
1816 list_move_tail(&w->sched.link, &list);
1819 rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
1823 static void defer_active(struct intel_engine_cs *engine)
1825 struct i915_request *rq;
1827 rq = __unwind_incomplete_requests(engine);
1831 defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
1835 need_timeslice(const struct intel_engine_cs *engine,
1836 const struct i915_request *rq)
1840 if (!intel_engine_has_timeslices(engine))
1843 hint = engine->execlists.queue_priority_hint;
1844 if (!list_is_last(&rq->sched.link, &engine->active.requests))
1845 hint = max(hint, rq_prio(list_next_entry(rq, sched.link)));
1847 return hint >= effective_prio(rq);
1851 timeslice_yield(const struct intel_engine_execlists *el,
1852 const struct i915_request *rq)
1855 * Once bitten, forever smitten!
1857 * If the active context ever busy-waited on a semaphore,
1858 * it will be treated as a hog until the end of its timeslice (i.e.
1859 * until it is scheduled out and replaced by a new submission,
1860 * possibly even its own lite-restore). The HW only sends an interrupt
1861 * on the first miss, and we do know if that semaphore has been
1862 * signaled, or even if it is now stuck on another semaphore. Play
1863 * safe, yield if it might be stuck -- it will be given a fresh
1864 * timeslice in the near future.
1866 return upper_32_bits(rq->context->lrc_desc) == READ_ONCE(el->yield);
1870 timeslice_expired(const struct intel_engine_execlists *el,
1871 const struct i915_request *rq)
1873 return timer_expired(&el->timer) || timeslice_yield(el, rq);
1877 switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq)
1879 if (list_is_last(&rq->sched.link, &engine->active.requests))
1882 return rq_prio(list_next_entry(rq, sched.link));
1885 static inline unsigned long
1886 timeslice(const struct intel_engine_cs *engine)
1888 return READ_ONCE(engine->props.timeslice_duration_ms);
1891 static unsigned long active_timeslice(const struct intel_engine_cs *engine)
1893 const struct intel_engine_execlists *execlists = &engine->execlists;
1894 const struct i915_request *rq = *execlists->active;
1896 if (!rq || i915_request_completed(rq))
1899 if (READ_ONCE(execlists->switch_priority_hint) < effective_prio(rq))
1902 return timeslice(engine);
1905 static void set_timeslice(struct intel_engine_cs *engine)
1907 unsigned long duration;
1909 if (!intel_engine_has_timeslices(engine))
1912 duration = active_timeslice(engine);
1913 ENGINE_TRACE(engine, "bump timeslicing, interval:%lu", duration);
1915 set_timer_ms(&engine->execlists.timer, duration);
1918 static void start_timeslice(struct intel_engine_cs *engine)
1920 struct intel_engine_execlists *execlists = &engine->execlists;
1921 const int prio = queue_prio(execlists);
1922 unsigned long duration;
1924 if (!intel_engine_has_timeslices(engine))
1927 WRITE_ONCE(execlists->switch_priority_hint, prio);
1928 if (prio == INT_MIN)
1931 if (timer_pending(&execlists->timer))
1934 duration = timeslice(engine);
1935 ENGINE_TRACE(engine,
1936 "start timeslicing, prio:%d, interval:%lu",
1939 set_timer_ms(&execlists->timer, duration);
1942 static void record_preemption(struct intel_engine_execlists *execlists)
1944 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
1947 static unsigned long active_preempt_timeout(struct intel_engine_cs *engine,
1948 const struct i915_request *rq)
1953 /* Force a fast reset for terminated contexts (ignoring sysfs!) */
1954 if (unlikely(intel_context_is_banned(rq->context)))
1957 return READ_ONCE(engine->props.preempt_timeout_ms);
1960 static void set_preempt_timeout(struct intel_engine_cs *engine,
1961 const struct i915_request *rq)
1963 if (!intel_engine_has_preempt_reset(engine))
1966 set_timer_ms(&engine->execlists.preempt,
1967 active_preempt_timeout(engine, rq));
1970 static inline void clear_ports(struct i915_request **ports, int count)
1972 memset_p((void **)ports, NULL, count);
1975 static void execlists_dequeue(struct intel_engine_cs *engine)
1977 struct intel_engine_execlists * const execlists = &engine->execlists;
1978 struct i915_request **port = execlists->pending;
1979 struct i915_request ** const last_port = port + execlists->port_mask;
1980 struct i915_request * const *active;
1981 struct i915_request *last;
1983 bool submit = false;
1986 * Hardware submission is through 2 ports. Conceptually each port
1987 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
1988 * static for a context, and unique to each, so we only execute
1989 * requests belonging to a single context from each ring. RING_HEAD
1990 * is maintained by the CS in the context image, it marks the place
1991 * where it got up to last time, and through RING_TAIL we tell the CS
1992 * where we want to execute up to this time.
1994 * In this list the requests are in order of execution. Consecutive
1995 * requests from the same context are adjacent in the ringbuffer. We
1996 * can combine these requests into a single RING_TAIL update:
1998 * RING_HEAD...req1...req2
2000 * since to execute req2 the CS must first execute req1.
2002 * Our goal then is to point each port to the end of a consecutive
2003 * sequence of requests as being the most optimal (fewest wake ups
2004 * and context switches) submission.
2007 for (rb = rb_first_cached(&execlists->virtual); rb; ) {
2008 struct virtual_engine *ve =
2009 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
2010 struct i915_request *rq = READ_ONCE(ve->request);
2012 if (!rq) { /* lazily cleanup after another engine handled rq */
2013 rb_erase_cached(rb, &execlists->virtual);
2015 rb = rb_first_cached(&execlists->virtual);
2019 if (!virtual_matches(ve, rq, engine)) {
2028 * If the queue is higher priority than the last
2029 * request in the currently active context, submit afresh.
2030 * We will resubmit again afterwards in case we need to split
2031 * the active context to interject the preemption request,
2032 * i.e. we will retrigger preemption following the ack in case
2035 active = READ_ONCE(execlists->active);
2038 * In theory we can skip over completed contexts that have not
2039 * yet been processed by events (as those events are in flight):
2041 * while ((last = *active) && i915_request_completed(last))
2044 * However, the GPU cannot handle this as it will ultimately
2045 * find itself trying to jump back into a context it has just
2046 * completed and barf.
2049 if ((last = *active)) {
2050 if (need_preempt(engine, last, rb)) {
2051 if (i915_request_completed(last)) {
2052 tasklet_hi_schedule(&execlists->tasklet);
2056 ENGINE_TRACE(engine,
2057 "preempting last=%llx:%lld, prio=%d, hint=%d\n",
2058 last->fence.context,
2060 last->sched.attr.priority,
2061 execlists->queue_priority_hint);
2062 record_preemption(execlists);
2065 * Don't let the RING_HEAD advance past the breadcrumb
2066 * as we unwind (and until we resubmit) so that we do
2067 * not accidentally tell it to go backwards.
2069 ring_set_paused(engine, 1);
2072 * Note that we have not stopped the GPU at this point,
2073 * so we are unwinding the incomplete requests as they
2074 * remain inflight and so by the time we do complete
2075 * the preemption, some of the unwound requests may
2078 __unwind_incomplete_requests(engine);
2081 } else if (need_timeslice(engine, last) &&
2082 timeslice_expired(execlists, last)) {
2083 if (i915_request_completed(last)) {
2084 tasklet_hi_schedule(&execlists->tasklet);
2088 ENGINE_TRACE(engine,
2089 "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n",
2090 last->fence.context,
2092 last->sched.attr.priority,
2093 execlists->queue_priority_hint,
2094 yesno(timeslice_yield(execlists, last)));
2096 ring_set_paused(engine, 1);
2097 defer_active(engine);
2100 * Unlike for preemption, if we rewind and continue
2101 * executing the same context as previously active,
2102 * the order of execution will remain the same and
2103 * the tail will only advance. We do not need to
2104 * force a full context restore, as a lite-restore
2105 * is sufficient to resample the monotonic TAIL.
2107 * If we switch to any other context, similarly we
2108 * will not rewind TAIL of current context, and
2109 * normal save/restore will preserve state and allow
2110 * us to later continue executing the same request.
2115 * Otherwise if we already have a request pending
2116 * for execution after the current one, we can
2117 * just wait until the next CS event before
2118 * queuing more. In either case we will force a
2119 * lite-restore preemption event, but if we wait
2120 * we hopefully coalesce several updates into a single
2123 if (!list_is_last(&last->sched.link,
2124 &engine->active.requests)) {
2126 * Even if ELSP[1] is occupied and not worthy
2127 * of timeslices, our queue might be.
2129 start_timeslice(engine);
2135 while (rb) { /* XXX virtual is always taking precedence */
2136 struct virtual_engine *ve =
2137 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
2138 struct i915_request *rq;
2140 spin_lock(&ve->base.active.lock);
2143 if (unlikely(!rq)) { /* lost the race to a sibling */
2144 spin_unlock(&ve->base.active.lock);
2145 rb_erase_cached(rb, &execlists->virtual);
2147 rb = rb_first_cached(&execlists->virtual);
2151 GEM_BUG_ON(rq != ve->request);
2152 GEM_BUG_ON(rq->engine != &ve->base);
2153 GEM_BUG_ON(rq->context != &ve->context);
2155 if (rq_prio(rq) >= queue_prio(execlists)) {
2156 if (!virtual_matches(ve, rq, engine)) {
2157 spin_unlock(&ve->base.active.lock);
2162 if (last && !can_merge_rq(last, rq)) {
2163 spin_unlock(&ve->base.active.lock);
2164 start_timeslice(engine);
2165 return; /* leave this for another sibling */
2168 ENGINE_TRACE(engine,
2169 "virtual rq=%llx:%lld%s, new engine? %s\n",
2172 i915_request_completed(rq) ? "!" :
2173 i915_request_started(rq) ? "*" :
2175 yesno(engine != ve->siblings[0]));
2177 WRITE_ONCE(ve->request, NULL);
2178 WRITE_ONCE(ve->base.execlists.queue_priority_hint,
2180 rb_erase_cached(rb, &execlists->virtual);
2183 GEM_BUG_ON(!(rq->execution_mask & engine->mask));
2184 WRITE_ONCE(rq->engine, engine);
2186 if (engine != ve->siblings[0]) {
2187 u32 *regs = ve->context.lrc_reg_state;
2190 GEM_BUG_ON(READ_ONCE(ve->context.inflight));
2192 if (!intel_engine_has_relative_mmio(engine))
2193 virtual_update_register_offsets(regs,
2196 if (!list_empty(&ve->context.signals))
2197 virtual_xfer_breadcrumbs(ve, rq);
2200 * Move the bound engine to the top of the list
2201 * for future execution. We then kick this
2202 * tasklet first before checking others, so that
2203 * we preferentially reuse this set of bound
2206 for (n = 1; n < ve->num_siblings; n++) {
2207 if (ve->siblings[n] == engine) {
2208 swap(ve->siblings[n],
2214 GEM_BUG_ON(ve->siblings[0] != engine);
2217 if (__i915_request_submit(rq)) {
2221 i915_request_put(rq);
2224 * Hmm, we have a bunch of virtual engine requests,
2225 * but the first one was already completed (thanks
2226 * preempt-to-busy!). Keep looking at the veng queue
2227 * until we have no more relevant requests (i.e.
2228 * the normal submit queue has higher priority).
2231 spin_unlock(&ve->base.active.lock);
2232 rb = rb_first_cached(&execlists->virtual);
2237 spin_unlock(&ve->base.active.lock);
2241 while ((rb = rb_first_cached(&execlists->queue))) {
2242 struct i915_priolist *p = to_priolist(rb);
2243 struct i915_request *rq, *rn;
2246 priolist_for_each_request_consume(rq, rn, p, i) {
2250 * Can we combine this request with the current port?
2251 * It has to be the same context/ringbuffer and not
2252 * have any exceptions (e.g. GVT saying never to
2253 * combine contexts).
2255 * If we can combine the requests, we can execute both
2256 * by updating the RING_TAIL to point to the end of the
2257 * second request, and so we never need to tell the
2258 * hardware about the first.
2260 if (last && !can_merge_rq(last, rq)) {
2262 * If we are on the second port and cannot
2263 * combine this request with the last, then we
2266 if (port == last_port)
2270 * We must not populate both ELSP[] with the
2271 * same LRCA, i.e. we must submit 2 different
2272 * contexts if we submit 2 ELSP.
2274 if (last->context == rq->context)
2277 if (i915_request_has_sentinel(last))
2281 * If GVT overrides us we only ever submit
2282 * port[0], leaving port[1] empty. Note that we
2283 * also have to be careful that we don't queue
2284 * the same context (even though a different
2285 * request) to the second port.
2287 if (ctx_single_port_submission(last->context) ||
2288 ctx_single_port_submission(rq->context))
2294 if (__i915_request_submit(rq)) {
2296 *port = execlists_schedule_in(last, port - execlists->pending);
2302 !can_merge_ctx(last->context,
2305 i915_seqno_passed(last->fence.seqno,
2313 rb_erase_cached(&p->node, &execlists->queue);
2314 i915_priolist_free(p);
2319 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
2321 * We choose the priority hint such that if we add a request of greater
2322 * priority than this, we kick the submission tasklet to decide on
2323 * the right order of submitting the requests to hardware. We must
2324 * also be prepared to reorder requests as they are in-flight on the
2325 * HW. We derive the priority hint then as the first "hole" in
2326 * the HW submission ports and if there are no available slots,
2327 * the priority of the lowest executing request, i.e. last.
2329 * When we do receive a higher priority request ready to run from the
2330 * user, see queue_request(), the priority hint is bumped to that
2331 * request triggering preemption on the next dequeue (or subsequent
2332 * interrupt for secondary ports).
2334 execlists->queue_priority_hint = queue_prio(execlists);
2337 *port = execlists_schedule_in(last, port - execlists->pending);
2338 execlists->switch_priority_hint =
2339 switch_prio(engine, *execlists->pending);
2342 * Skip if we ended up with exactly the same set of requests,
2343 * e.g. trying to timeslice a pair of ordered contexts
2345 if (!memcmp(active, execlists->pending,
2346 (port - execlists->pending + 1) * sizeof(*port))) {
2348 execlists_schedule_out(fetch_and_zero(port));
2349 while (port-- != execlists->pending);
2353 clear_ports(port + 1, last_port - port);
2355 WRITE_ONCE(execlists->yield, -1);
2356 execlists_submit_ports(engine);
2357 set_preempt_timeout(engine, *active);
2360 ring_set_paused(engine, 0);
2365 cancel_port_requests(struct intel_engine_execlists * const execlists)
2367 struct i915_request * const *port;
2369 for (port = execlists->pending; *port; port++)
2370 execlists_schedule_out(*port);
2371 clear_ports(execlists->pending, ARRAY_SIZE(execlists->pending));
2373 /* Mark the end of active before we overwrite *active */
2374 for (port = xchg(&execlists->active, execlists->pending); *port; port++)
2375 execlists_schedule_out(*port);
2376 clear_ports(execlists->inflight, ARRAY_SIZE(execlists->inflight));
2378 smp_wmb(); /* complete the seqlock for execlists_active() */
2379 WRITE_ONCE(execlists->active, execlists->inflight);
2383 invalidate_csb_entries(const u32 *first, const u32 *last)
2385 clflush((void *)first);
2386 clflush((void *)last);
2390 * Starting with Gen12, the status has a new format:
2392 * bit 0: switched to new queue
2394 * bit 2: semaphore wait mode (poll or signal), only valid when
2395 * switch detail is set to "wait on semaphore"
2396 * bits 3-5: engine class
2397 * bits 6-11: engine instance
2398 * bits 12-14: reserved
2399 * bits 15-25: sw context id of the lrc the GT switched to
2400 * bits 26-31: sw counter of the lrc the GT switched to
2401 * bits 32-35: context switch detail
2403 * - 1: wait on sync flip
2404 * - 2: wait on vblank
2405 * - 3: wait on scanline
2406 * - 4: wait on semaphore
2407 * - 5: context preempted (not on SEMAPHORE_WAIT or
2410 * bits 37-43: wait detail (for switch detail 1 to 4)
2411 * bits 44-46: reserved
2412 * bits 47-57: sw context id of the lrc the GT switched away from
2413 * bits 58-63: sw counter of the lrc the GT switched away from
2416 gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
2418 u32 lower_dw = csb[0];
2419 u32 upper_dw = csb[1];
2420 bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_dw);
2421 bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_dw);
2422 bool new_queue = lower_dw & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE;
2425 * The context switch detail is not guaranteed to be 5 when a preemption
2426 * occurs, so we can't just check for that. The check below works for
2427 * all the cases we care about, including preemptions of WAIT
2428 * instructions and lite-restore. Preempt-to-idle via the CTRL register
2429 * would require some extra handling, but we don't support that.
2431 if (!ctx_away_valid || new_queue) {
2432 GEM_BUG_ON(!ctx_to_valid);
2437 * switch detail = 5 is covered by the case above and we do not expect a
2438 * context switch on an unsuccessful wait instruction since we always
2441 GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw));
2446 gen8_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
2448 return *csb & (GEN8_CTX_STATUS_IDLE_ACTIVE | GEN8_CTX_STATUS_PREEMPTED);
2451 static void process_csb(struct intel_engine_cs *engine)
2453 struct intel_engine_execlists * const execlists = &engine->execlists;
2454 const u32 * const buf = execlists->csb_status;
2455 const u8 num_entries = execlists->csb_size;
2459 * As we modify our execlists state tracking we require exclusive
2460 * access. Either we are inside the tasklet, or the tasklet is disabled
2461 * and we assume that is only inside the reset paths and so serialised.
2463 GEM_BUG_ON(!tasklet_is_locked(&execlists->tasklet) &&
2464 !reset_in_progress(execlists));
2465 GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine));
2468 * Note that csb_write, csb_status may be either in HWSP or mmio.
2469 * When reading from the csb_write mmio register, we have to be
2470 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
2471 * the low 4bits. As it happens we know the next 4bits are always
2472 * zero and so we can simply masked off the low u8 of the register
2473 * and treat it identically to reading from the HWSP (without having
2474 * to use explicit shifting and masking, and probably bifurcating
2475 * the code to handle the legacy mmio read).
2477 head = execlists->csb_head;
2478 tail = READ_ONCE(*execlists->csb_write);
2479 if (unlikely(head == tail))
2483 * Hopefully paired with a wmb() in HW!
2485 * We must complete the read of the write pointer before any reads
2486 * from the CSB, so that we do not see stale values. Without an rmb
2487 * (lfence) the HW may speculatively perform the CSB[] reads *before*
2488 * we perform the READ_ONCE(*csb_write).
2492 ENGINE_TRACE(engine, "cs-irq head=%d, tail=%d\n", head, tail);
2496 if (++head == num_entries)
2500 * We are flying near dragons again.
2502 * We hold a reference to the request in execlist_port[]
2503 * but no more than that. We are operating in softirq
2504 * context and so cannot hold any mutex or sleep. That
2505 * prevents us stopping the requests we are processing
2506 * in port[] from being retired simultaneously (the
2507 * breadcrumb will be complete before we see the
2508 * context-switch). As we only hold the reference to the
2509 * request, any pointer chasing underneath the request
2510 * is subject to a potential use-after-free. Thus we
2511 * store all of the bookkeeping within port[] as
2512 * required, and avoid using unguarded pointers beneath
2513 * request itself. The same applies to the atomic
2517 ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
2518 head, buf[2 * head + 0], buf[2 * head + 1]);
2520 if (INTEL_GEN(engine->i915) >= 12)
2521 promote = gen12_csb_parse(execlists, buf + 2 * head);
2523 promote = gen8_csb_parse(execlists, buf + 2 * head);
2525 struct i915_request * const *old = execlists->active;
2527 ring_set_paused(engine, 0);
2529 /* Point active to the new ELSP; prevent overwriting */
2530 WRITE_ONCE(execlists->active, execlists->pending);
2531 smp_wmb(); /* notify execlists_active() */
2533 /* cancel old inflight, prepare for switch */
2534 trace_ports(execlists, "preempted", old);
2536 execlists_schedule_out(*old++);
2538 /* switch pending to inflight */
2539 GEM_BUG_ON(!assert_pending_valid(execlists, "promote"));
2540 memcpy(execlists->inflight,
2542 execlists_num_ports(execlists) *
2543 sizeof(*execlists->pending));
2544 smp_wmb(); /* complete the seqlock */
2545 WRITE_ONCE(execlists->active, execlists->inflight);
2547 WRITE_ONCE(execlists->pending[0], NULL);
2549 GEM_BUG_ON(!*execlists->active);
2551 /* port0 completed, advanced to port1 */
2552 trace_ports(execlists, "completed", execlists->active);
2555 * We rely on the hardware being strongly
2556 * ordered, that the breadcrumb write is
2557 * coherent (visible from the CPU) before the
2558 * user interrupt is processed. One might assume
2559 * that the breadcrumb write being before the
2560 * user interrupt and the CS event for the context
2561 * switch would therefore be before the CS event
2564 if (GEM_SHOW_DEBUG() &&
2565 !i915_request_completed(*execlists->active)) {
2566 struct i915_request *rq = *execlists->active;
2567 const u32 *regs __maybe_unused =
2568 rq->context->lrc_reg_state;
2570 ENGINE_TRACE(engine,
2571 "context completed before request!\n");
2572 ENGINE_TRACE(engine,
2573 "ring:{start:0x%08x, head:%04x, tail:%04x, ctl:%08x, mode:%08x}\n",
2574 ENGINE_READ(engine, RING_START),
2575 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR,
2576 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR,
2577 ENGINE_READ(engine, RING_CTL),
2578 ENGINE_READ(engine, RING_MI_MODE));
2579 ENGINE_TRACE(engine,
2580 "rq:{start:%08x, head:%04x, tail:%04x, seqno:%llx:%d, hwsp:%d}, ",
2581 i915_ggtt_offset(rq->ring->vma),
2584 lower_32_bits(rq->fence.seqno),
2586 ENGINE_TRACE(engine,
2587 "ctx:{start:%08x, head:%04x, tail:%04x}, ",
2588 regs[CTX_RING_START],
2589 regs[CTX_RING_HEAD],
2590 regs[CTX_RING_TAIL]);
2593 execlists_schedule_out(*execlists->active++);
2595 GEM_BUG_ON(execlists->active - execlists->inflight >
2596 execlists_num_ports(execlists));
2598 } while (head != tail);
2600 execlists->csb_head = head;
2601 set_timeslice(engine);
2604 * Gen11 has proven to fail wrt global observation point between
2605 * entry and tail update, failing on the ordering and thus
2606 * we see an old entry in the context status buffer.
2608 * Forcibly evict out entries for the next gpu csb update,
2609 * to increase the odds that we get a fresh entries with non
2610 * working hardware. The cost for doing so comes out mostly with
2611 * the wash as hardware, working or not, will need to do the
2612 * invalidation before.
2614 invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
2617 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
2619 lockdep_assert_held(&engine->active.lock);
2620 if (!READ_ONCE(engine->execlists.pending[0])) {
2621 rcu_read_lock(); /* protect peeking at execlists->active */
2622 execlists_dequeue(engine);
2627 static void __execlists_hold(struct i915_request *rq)
2632 struct i915_dependency *p;
2634 if (i915_request_is_active(rq))
2635 __i915_request_unsubmit(rq);
2637 clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
2638 list_move_tail(&rq->sched.link, &rq->engine->active.hold);
2639 i915_request_set_hold(rq);
2640 RQ_TRACE(rq, "on hold\n");
2642 for_each_waiter(p, rq) {
2643 struct i915_request *w =
2644 container_of(p->waiter, typeof(*w), sched);
2646 /* Leave semaphores spinning on the other engines */
2647 if (w->engine != rq->engine)
2650 if (!i915_request_is_ready(w))
2653 if (i915_request_completed(w))
2656 if (i915_request_on_hold(w))
2659 list_move_tail(&w->sched.link, &list);
2662 rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
2666 static bool execlists_hold(struct intel_engine_cs *engine,
2667 struct i915_request *rq)
2669 spin_lock_irq(&engine->active.lock);
2671 if (i915_request_completed(rq)) { /* too late! */
2676 if (rq->engine != engine) { /* preempted virtual engine */
2677 struct virtual_engine *ve = to_virtual_engine(rq->engine);
2680 * intel_context_inflight() is only protected by virtue
2681 * of process_csb() being called only by the tasklet (or
2682 * directly from inside reset while the tasklet is suspended).
2683 * Assert that neither of those are allowed to run while we
2684 * poke at the request queues.
2686 GEM_BUG_ON(!reset_in_progress(&engine->execlists));
2689 * An unsubmitted request along a virtual engine will
2690 * remain on the active (this) engine until we are able
2691 * to process the context switch away (and so mark the
2692 * context as no longer in flight). That cannot have happened
2693 * yet, otherwise we would not be hanging!
2695 spin_lock(&ve->base.active.lock);
2696 GEM_BUG_ON(intel_context_inflight(rq->context) != engine);
2697 GEM_BUG_ON(ve->request != rq);
2699 spin_unlock(&ve->base.active.lock);
2700 i915_request_put(rq);
2702 rq->engine = engine;
2706 * Transfer this request onto the hold queue to prevent it
2707 * being resumbitted to HW (and potentially completed) before we have
2708 * released it. Since we may have already submitted following
2709 * requests, we need to remove those as well.
2711 GEM_BUG_ON(i915_request_on_hold(rq));
2712 GEM_BUG_ON(rq->engine != engine);
2713 __execlists_hold(rq);
2714 GEM_BUG_ON(list_empty(&engine->active.hold));
2717 spin_unlock_irq(&engine->active.lock);
2721 static bool hold_request(const struct i915_request *rq)
2723 struct i915_dependency *p;
2724 bool result = false;
2727 * If one of our ancestors is on hold, we must also be on hold,
2728 * otherwise we will bypass it and execute before it.
2731 for_each_signaler(p, rq) {
2732 const struct i915_request *s =
2733 container_of(p->signaler, typeof(*s), sched);
2735 if (s->engine != rq->engine)
2738 result = i915_request_on_hold(s);
2747 static void __execlists_unhold(struct i915_request *rq)
2752 struct i915_dependency *p;
2754 RQ_TRACE(rq, "hold release\n");
2756 GEM_BUG_ON(!i915_request_on_hold(rq));
2757 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
2759 i915_request_clear_hold(rq);
2760 list_move_tail(&rq->sched.link,
2761 i915_sched_lookup_priolist(rq->engine,
2763 set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
2765 /* Also release any children on this engine that are ready */
2766 for_each_waiter(p, rq) {
2767 struct i915_request *w =
2768 container_of(p->waiter, typeof(*w), sched);
2770 /* Propagate any change in error status */
2771 if (rq->fence.error)
2772 i915_request_set_error_once(w, rq->fence.error);
2774 if (w->engine != rq->engine)
2777 if (!i915_request_on_hold(w))
2780 /* Check that no other parents are also on hold */
2781 if (hold_request(w))
2784 list_move_tail(&w->sched.link, &list);
2787 rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
2791 static void execlists_unhold(struct intel_engine_cs *engine,
2792 struct i915_request *rq)
2794 spin_lock_irq(&engine->active.lock);
2797 * Move this request back to the priority queue, and all of its
2798 * children and grandchildren that were suspended along with it.
2800 __execlists_unhold(rq);
2802 if (rq_prio(rq) > engine->execlists.queue_priority_hint) {
2803 engine->execlists.queue_priority_hint = rq_prio(rq);
2804 tasklet_hi_schedule(&engine->execlists.tasklet);
2807 spin_unlock_irq(&engine->active.lock);
2810 struct execlists_capture {
2811 struct work_struct work;
2812 struct i915_request *rq;
2813 struct i915_gpu_coredump *error;
2816 static void execlists_capture_work(struct work_struct *work)
2818 struct execlists_capture *cap = container_of(work, typeof(*cap), work);
2819 const gfp_t gfp = GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN;
2820 struct intel_engine_cs *engine = cap->rq->engine;
2821 struct intel_gt_coredump *gt = cap->error->gt;
2822 struct intel_engine_capture_vma *vma;
2824 /* Compress all the objects attached to the request, slow! */
2825 vma = intel_engine_coredump_add_request(gt->engine, cap->rq, gfp);
2827 struct i915_vma_compress *compress =
2828 i915_vma_capture_prepare(gt);
2830 intel_engine_coredump_add_vma(gt->engine, vma, compress);
2831 i915_vma_capture_finish(gt, compress);
2834 gt->simulated = gt->engine->simulated;
2835 cap->error->simulated = gt->simulated;
2837 /* Publish the error state, and announce it to the world */
2838 i915_error_state_store(cap->error);
2839 i915_gpu_coredump_put(cap->error);
2841 /* Return this request and all that depend upon it for signaling */
2842 execlists_unhold(engine, cap->rq);
2843 i915_request_put(cap->rq);
2848 static struct execlists_capture *capture_regs(struct intel_engine_cs *engine)
2850 const gfp_t gfp = GFP_ATOMIC | __GFP_NOWARN;
2851 struct execlists_capture *cap;
2853 cap = kmalloc(sizeof(*cap), gfp);
2857 cap->error = i915_gpu_coredump_alloc(engine->i915, gfp);
2861 cap->error->gt = intel_gt_coredump_alloc(engine->gt, gfp);
2862 if (!cap->error->gt)
2865 cap->error->gt->engine = intel_engine_coredump_alloc(engine, gfp);
2866 if (!cap->error->gt->engine)
2872 kfree(cap->error->gt);
2880 static struct i915_request *
2881 active_context(struct intel_engine_cs *engine, u32 ccid)
2883 const struct intel_engine_execlists * const el = &engine->execlists;
2884 struct i915_request * const *port, *rq;
2887 * Use the most recent result from process_csb(), but just in case
2888 * we trigger an error (via interrupt) before the first CS event has
2889 * been written, peek at the next submission.
2892 for (port = el->active; (rq = *port); port++) {
2893 if (upper_32_bits(rq->context->lrc_desc) == ccid) {
2894 ENGINE_TRACE(engine,
2895 "ccid found at active:%zd\n",
2901 for (port = el->pending; (rq = *port); port++) {
2902 if (upper_32_bits(rq->context->lrc_desc) == ccid) {
2903 ENGINE_TRACE(engine,
2904 "ccid found at pending:%zd\n",
2905 port - el->pending);
2910 ENGINE_TRACE(engine, "ccid:%x not found\n", ccid);
2914 static u32 active_ccid(struct intel_engine_cs *engine)
2916 return ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI);
2919 static bool execlists_capture(struct intel_engine_cs *engine)
2921 struct execlists_capture *cap;
2923 if (!IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR))
2927 * We need to _quickly_ capture the engine state before we reset.
2928 * We are inside an atomic section (softirq) here and we are delaying
2929 * the forced preemption event.
2931 cap = capture_regs(engine);
2935 spin_lock_irq(&engine->active.lock);
2936 cap->rq = active_context(engine, active_ccid(engine));
2938 cap->rq = active_request(cap->rq->context->timeline, cap->rq);
2939 cap->rq = i915_request_get_rcu(cap->rq);
2941 spin_unlock_irq(&engine->active.lock);
2946 * Remove the request from the execlists queue, and take ownership
2947 * of the request. We pass it to our worker who will _slowly_ compress
2948 * all the pages the _user_ requested for debugging their batch, after
2949 * which we return it to the queue for signaling.
2951 * By removing them from the execlists queue, we also remove the
2952 * requests from being processed by __unwind_incomplete_requests()
2953 * during the intel_engine_reset(), and so they will *not* be replayed
2956 * Note that because we have not yet reset the engine at this point,
2957 * it is possible for the request that we have identified as being
2958 * guilty, did in fact complete and we will then hit an arbitration
2959 * point allowing the outstanding preemption to succeed. The likelihood
2960 * of that is very low (as capturing of the engine registers should be
2961 * fast enough to run inside an irq-off atomic section!), so we will
2962 * simply hold that request accountable for being non-preemptible
2963 * long enough to force the reset.
2965 if (!execlists_hold(engine, cap->rq))
2968 INIT_WORK(&cap->work, execlists_capture_work);
2969 schedule_work(&cap->work);
2973 i915_request_put(cap->rq);
2975 i915_gpu_coredump_put(cap->error);
2980 static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
2982 const unsigned int bit = I915_RESET_ENGINE + engine->id;
2983 unsigned long *lock = &engine->gt->reset.flags;
2985 if (!intel_has_reset_engine(engine->gt))
2988 if (test_and_set_bit(bit, lock))
2991 ENGINE_TRACE(engine, "reset for %s\n", msg);
2993 /* Mark this tasklet as disabled to avoid waiting for it to complete */
2994 tasklet_disable_nosync(&engine->execlists.tasklet);
2996 ring_set_paused(engine, 1); /* Freeze the current request in place */
2997 if (execlists_capture(engine))
2998 intel_engine_reset(engine, msg);
3000 ring_set_paused(engine, 0);
3002 tasklet_enable(&engine->execlists.tasklet);
3003 clear_and_wake_up_bit(bit, lock);
3006 static bool preempt_timeout(const struct intel_engine_cs *const engine)
3008 const struct timer_list *t = &engine->execlists.preempt;
3010 if (!CONFIG_DRM_I915_PREEMPT_TIMEOUT)
3013 if (!timer_expired(t))
3016 return READ_ONCE(engine->execlists.pending[0]);
3020 * Check the unread Context Status Buffers and manage the submission of new
3021 * contexts to the ELSP accordingly.
3023 static void execlists_submission_tasklet(unsigned long data)
3025 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
3026 bool timeout = preempt_timeout(engine);
3028 process_csb(engine);
3030 if (unlikely(READ_ONCE(engine->execlists.error_interrupt))) {
3031 engine->execlists.error_interrupt = 0;
3032 if (ENGINE_READ(engine, RING_ESR)) /* confirm the error */
3033 execlists_reset(engine, "CS error");
3036 if (!READ_ONCE(engine->execlists.pending[0]) || timeout) {
3037 unsigned long flags;
3039 spin_lock_irqsave(&engine->active.lock, flags);
3040 __execlists_submission_tasklet(engine);
3041 spin_unlock_irqrestore(&engine->active.lock, flags);
3043 /* Recheck after serialising with direct-submission */
3044 if (unlikely(timeout && preempt_timeout(engine)))
3045 execlists_reset(engine, "preemption time out");
3049 static void __execlists_kick(struct intel_engine_execlists *execlists)
3051 /* Kick the tasklet for some interrupt coalescing and reset handling */
3052 tasklet_hi_schedule(&execlists->tasklet);
3055 #define execlists_kick(t, member) \
3056 __execlists_kick(container_of(t, struct intel_engine_execlists, member))
3058 static void execlists_timeslice(struct timer_list *timer)
3060 execlists_kick(timer, timer);
3063 static void execlists_preempt(struct timer_list *timer)
3065 execlists_kick(timer, preempt);
3068 static void queue_request(struct intel_engine_cs *engine,
3069 struct i915_request *rq)
3071 GEM_BUG_ON(!list_empty(&rq->sched.link));
3072 list_add_tail(&rq->sched.link,
3073 i915_sched_lookup_priolist(engine, rq_prio(rq)));
3074 set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
3077 static void __submit_queue_imm(struct intel_engine_cs *engine)
3079 struct intel_engine_execlists * const execlists = &engine->execlists;
3081 if (reset_in_progress(execlists))
3082 return; /* defer until we restart the engine following reset */
3084 /* Hopefully we clear execlists->pending[] to let us through */
3085 if (READ_ONCE(execlists->pending[0]) &&
3086 tasklet_trylock(&execlists->tasklet)) {
3087 process_csb(engine);
3088 tasklet_unlock(&execlists->tasklet);
3091 __execlists_submission_tasklet(engine);
3094 static void submit_queue(struct intel_engine_cs *engine,
3095 const struct i915_request *rq)
3097 struct intel_engine_execlists *execlists = &engine->execlists;
3099 if (rq_prio(rq) <= execlists->queue_priority_hint)
3102 execlists->queue_priority_hint = rq_prio(rq);
3103 __submit_queue_imm(engine);
3106 static bool ancestor_on_hold(const struct intel_engine_cs *engine,
3107 const struct i915_request *rq)
3109 GEM_BUG_ON(i915_request_on_hold(rq));
3110 return !list_empty(&engine->active.hold) && hold_request(rq);
3113 static void execlists_submit_request(struct i915_request *request)
3115 struct intel_engine_cs *engine = request->engine;
3116 unsigned long flags;
3118 /* Will be called from irq-context when using foreign fences. */
3119 spin_lock_irqsave(&engine->active.lock, flags);
3121 if (unlikely(ancestor_on_hold(engine, request))) {
3122 RQ_TRACE(request, "ancestor on hold\n");
3123 list_add_tail(&request->sched.link, &engine->active.hold);
3124 i915_request_set_hold(request);
3126 queue_request(engine, request);
3128 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
3129 GEM_BUG_ON(list_empty(&request->sched.link));
3131 submit_queue(engine, request);
3134 spin_unlock_irqrestore(&engine->active.lock, flags);
3137 static void __execlists_context_fini(struct intel_context *ce)
3139 intel_ring_put(ce->ring);
3140 i915_vma_put(ce->state);
3143 static void execlists_context_destroy(struct kref *kref)
3145 struct intel_context *ce = container_of(kref, typeof(*ce), ref);
3147 GEM_BUG_ON(!i915_active_is_idle(&ce->active));
3148 GEM_BUG_ON(intel_context_is_pinned(ce));
3151 __execlists_context_fini(ce);
3153 intel_context_fini(ce);
3154 intel_context_free(ce);
3158 set_redzone(void *vaddr, const struct intel_engine_cs *engine)
3160 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
3163 vaddr += engine->context_size;
3165 memset(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE);
3169 check_redzone(const void *vaddr, const struct intel_engine_cs *engine)
3171 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
3174 vaddr += engine->context_size;
3176 if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE))
3177 drm_err_once(&engine->i915->drm,
3178 "%s context redzone overwritten!\n",
3182 static void execlists_context_unpin(struct intel_context *ce)
3184 check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
3187 i915_gem_object_unpin_map(ce->state->obj);
3191 __execlists_update_reg_state(const struct intel_context *ce,
3192 const struct intel_engine_cs *engine,
3195 struct intel_ring *ring = ce->ring;
3196 u32 *regs = ce->lrc_reg_state;
3198 GEM_BUG_ON(!intel_ring_offset_valid(ring, head));
3199 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
3201 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
3202 regs[CTX_RING_HEAD] = head;
3203 regs[CTX_RING_TAIL] = ring->tail;
3204 regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
3207 if (engine->class == RENDER_CLASS) {
3208 regs[CTX_R_PWR_CLK_STATE] =
3209 intel_sseu_make_rpcs(engine->i915, &ce->sseu);
3211 i915_oa_init_reg_state(ce, engine);
3216 __execlists_context_pin(struct intel_context *ce,
3217 struct intel_engine_cs *engine)
3221 GEM_BUG_ON(!ce->state);
3222 GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
3224 vaddr = i915_gem_object_pin_map(ce->state->obj,
3225 i915_coherent_map_type(engine->i915) |
3228 return PTR_ERR(vaddr);
3230 ce->lrc_desc = lrc_descriptor(ce, engine) | CTX_DESC_FORCE_RESTORE;
3231 ce->lrc_reg_state = vaddr + LRC_STATE_OFFSET;
3232 __execlists_update_reg_state(ce, engine, ce->ring->tail);
3237 static int execlists_context_pin(struct intel_context *ce)
3239 return __execlists_context_pin(ce, ce->engine);
3242 static int execlists_context_alloc(struct intel_context *ce)
3244 return __execlists_context_alloc(ce, ce->engine);
3247 static void execlists_context_reset(struct intel_context *ce)
3249 CE_TRACE(ce, "reset\n");
3250 GEM_BUG_ON(!intel_context_is_pinned(ce));
3252 intel_ring_reset(ce->ring, ce->ring->emit);
3254 /* Scrub away the garbage */
3255 execlists_init_reg_state(ce->lrc_reg_state,
3256 ce, ce->engine, ce->ring, true);
3257 __execlists_update_reg_state(ce, ce->engine, ce->ring->tail);
3259 ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
3262 static const struct intel_context_ops execlists_context_ops = {
3263 .alloc = execlists_context_alloc,
3265 .pin = execlists_context_pin,
3266 .unpin = execlists_context_unpin,
3268 .enter = intel_context_enter_engine,
3269 .exit = intel_context_exit_engine,
3271 .reset = execlists_context_reset,
3272 .destroy = execlists_context_destroy,
3275 static int gen8_emit_init_breadcrumb(struct i915_request *rq)
3279 if (!i915_request_timeline(rq)->has_initial_breadcrumb)
3282 cs = intel_ring_begin(rq, 6);
3287 * Check if we have been preempted before we even get started.
3289 * After this point i915_request_started() reports true, even if
3290 * we get preempted and so are no longer running.
3292 *cs++ = MI_ARB_CHECK;
3295 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
3296 *cs++ = i915_request_timeline(rq)->hwsp_offset;
3298 *cs++ = rq->fence.seqno - 1;
3300 intel_ring_advance(rq, cs);
3302 /* Record the updated position of the request's payload */
3303 rq->infix = intel_ring_offset(rq, cs);
3308 static int execlists_request_alloc(struct i915_request *request)
3312 GEM_BUG_ON(!intel_context_is_pinned(request->context));
3315 * Flush enough space to reduce the likelihood of waiting after
3316 * we start building the request - in which case we will just
3317 * have to repeat work.
3319 request->reserved_space += EXECLISTS_REQUEST_SIZE;
3322 * Note that after this point, we have committed to using
3323 * this request as it is being used to both track the
3324 * state of engine initialisation and liveness of the
3325 * golden renderstate above. Think twice before you try
3326 * to cancel/unwind this request now.
3329 /* Unconditionally invalidate GPU caches and TLBs. */
3330 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
3334 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
3339 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
3340 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
3341 * but there is a slight complication as this is applied in WA batch where the
3342 * values are only initialized once so we cannot take register value at the
3343 * beginning and reuse it further; hence we save its value to memory, upload a
3344 * constant value with bit21 set and then we restore it back with the saved value.
3345 * To simplify the WA, a constant value is formed by using the default value
3346 * of this register. This shouldn't be a problem because we are only modifying
3347 * it for a short period and this batch in non-premptible. We can ofcourse
3348 * use additional instructions that read the actual value of the register
3349 * at that time and set our bit of interest but it makes the WA complicated.
3351 * This WA is also required for Gen9 so extracting as a function avoids
3355 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
3357 /* NB no one else is allowed to scribble over scratch + 256! */
3358 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
3359 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
3360 *batch++ = intel_gt_scratch_offset(engine->gt,
3361 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
3364 *batch++ = MI_LOAD_REGISTER_IMM(1);
3365 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
3366 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
3368 batch = gen8_emit_pipe_control(batch,
3369 PIPE_CONTROL_CS_STALL |
3370 PIPE_CONTROL_DC_FLUSH_ENABLE,
3373 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
3374 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
3375 *batch++ = intel_gt_scratch_offset(engine->gt,
3376 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
3383 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
3384 * initialized at the beginning and shared across all contexts but this field
3385 * helps us to have multiple batches at different offsets and select them based
3386 * on a criteria. At the moment this batch always start at the beginning of the page
3387 * and at this point we don't have multiple wa_ctx batch buffers.
3389 * The number of WA applied are not known at the beginning; we use this field
3390 * to return the no of DWORDS written.
3392 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
3393 * so it adds NOOPs as padding to make it cacheline aligned.
3394 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
3395 * makes a complete batch buffer.
3397 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
3399 /* WaDisableCtxRestoreArbitration:bdw,chv */
3400 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
3402 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
3403 if (IS_BROADWELL(engine->i915))
3404 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
3406 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
3407 /* Actual scratch location is at 128 bytes offset */
3408 batch = gen8_emit_pipe_control(batch,
3409 PIPE_CONTROL_FLUSH_L3 |
3410 PIPE_CONTROL_STORE_DATA_INDEX |
3411 PIPE_CONTROL_CS_STALL |
3412 PIPE_CONTROL_QW_WRITE,
3413 LRC_PPHWSP_SCRATCH_ADDR);
3415 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
3417 /* Pad to end of cacheline */
3418 while ((unsigned long)batch % CACHELINE_BYTES)
3422 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
3423 * execution depends on the length specified in terms of cache lines
3424 * in the register CTX_RCS_INDIRECT_CTX
3435 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
3437 GEM_BUG_ON(!count || count > 63);
3439 *batch++ = MI_LOAD_REGISTER_IMM(count);
3441 *batch++ = i915_mmio_reg_offset(lri->reg);
3442 *batch++ = lri->value;
3443 } while (lri++, --count);
3449 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
3451 static const struct lri lri[] = {
3452 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
3454 COMMON_SLICE_CHICKEN2,
3455 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
3462 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
3463 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
3469 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
3470 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
3474 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
3476 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
3477 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
3479 /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */
3480 batch = gen8_emit_pipe_control(batch,
3481 PIPE_CONTROL_FLUSH_L3 |
3482 PIPE_CONTROL_STORE_DATA_INDEX |
3483 PIPE_CONTROL_CS_STALL |
3484 PIPE_CONTROL_QW_WRITE,
3485 LRC_PPHWSP_SCRATCH_ADDR);
3487 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
3489 /* WaMediaPoolStateCmdInWABB:bxt,glk */
3490 if (HAS_POOLED_EU(engine->i915)) {
3492 * EU pool configuration is setup along with golden context
3493 * during context initialization. This value depends on
3494 * device type (2x6 or 3x6) and needs to be updated based
3495 * on which subslice is disabled especially for 2x6
3496 * devices, however it is safe to load default
3497 * configuration of 3x6 device instead of masking off
3498 * corresponding bits because HW ignores bits of a disabled
3499 * subslice and drops down to appropriate config. Please
3500 * see render_state_setup() in i915_gem_render_state.c for
3501 * possible configurations, to avoid duplication they are
3502 * not shown here again.
3504 *batch++ = GEN9_MEDIA_POOL_STATE;
3505 *batch++ = GEN9_MEDIA_POOL_ENABLE;
3506 *batch++ = 0x00777000;
3512 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
3514 /* Pad to end of cacheline */
3515 while ((unsigned long)batch % CACHELINE_BYTES)
3522 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
3527 * WaPipeControlBefore3DStateSamplePattern: cnl
3529 * Ensure the engine is idle prior to programming a
3530 * 3DSTATE_SAMPLE_PATTERN during a context restore.
3532 batch = gen8_emit_pipe_control(batch,
3533 PIPE_CONTROL_CS_STALL,
3536 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
3537 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
3538 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
3539 * confusing. Since gen8_emit_pipe_control() already advances the
3540 * batch by 6 dwords, we advance the other 10 here, completing a
3541 * cacheline. It's not clear if the workaround requires this padding
3542 * before other commands, or if it's just the regular padding we would
3543 * already have for the workaround bb, so leave it here for now.
3545 for (i = 0; i < 10; i++)
3548 /* Pad to end of cacheline */
3549 while ((unsigned long)batch % CACHELINE_BYTES)
3555 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
3557 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
3559 struct drm_i915_gem_object *obj;
3560 struct i915_vma *vma;
3563 obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_OBJ_SIZE);
3565 return PTR_ERR(obj);
3567 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
3573 err = i915_ggtt_pin(vma, 0, PIN_HIGH);
3577 engine->wa_ctx.vma = vma;
3581 i915_gem_object_put(obj);
3585 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
3587 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
3590 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
3592 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
3594 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
3595 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
3597 wa_bb_func_t wa_bb_fn[2];
3599 void *batch, *batch_ptr;
3603 if (engine->class != RENDER_CLASS)
3606 switch (INTEL_GEN(engine->i915)) {
3611 wa_bb_fn[0] = gen10_init_indirectctx_bb;
3615 wa_bb_fn[0] = gen9_init_indirectctx_bb;
3619 wa_bb_fn[0] = gen8_init_indirectctx_bb;
3623 MISSING_CASE(INTEL_GEN(engine->i915));
3627 ret = lrc_setup_wa_ctx(engine);
3629 drm_dbg(&engine->i915->drm,
3630 "Failed to setup context WA page: %d\n", ret);
3634 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
3635 batch = batch_ptr = kmap_atomic(page);
3638 * Emit the two workaround batch buffers, recording the offset from the
3639 * start of the workaround batch buffer object for each and their
3642 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
3643 wa_bb[i]->offset = batch_ptr - batch;
3644 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
3645 CACHELINE_BYTES))) {
3650 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
3651 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
3654 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
3656 kunmap_atomic(batch);
3658 lrc_destroy_wa_ctx(engine);
3663 static void reset_csb_pointers(struct intel_engine_cs *engine)
3665 struct intel_engine_execlists * const execlists = &engine->execlists;
3666 const unsigned int reset_value = execlists->csb_size - 1;
3668 ring_set_paused(engine, 0);
3671 * After a reset, the HW starts writing into CSB entry [0]. We
3672 * therefore have to set our HEAD pointer back one entry so that
3673 * the *first* entry we check is entry 0. To complicate this further,
3674 * as we don't wait for the first interrupt after reset, we have to
3675 * fake the HW write to point back to the last entry so that our
3676 * inline comparison of our cached head position against the last HW
3677 * write works even before the first interrupt.
3679 execlists->csb_head = reset_value;
3680 WRITE_ONCE(*execlists->csb_write, reset_value);
3681 wmb(); /* Make sure this is visible to HW (paranoia?) */
3684 * Sometimes Icelake forgets to reset its pointers on a GPU reset.
3685 * Bludgeon them with a mmio update to be sure.
3687 ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
3688 reset_value << 8 | reset_value);
3689 ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);
3691 invalidate_csb_entries(&execlists->csb_status[0],
3692 &execlists->csb_status[reset_value]);
3695 static void execlists_sanitize(struct intel_engine_cs *engine)
3698 * Poison residual state on resume, in case the suspend didn't!
3700 * We have to assume that across suspend/resume (or other loss
3701 * of control) that the contents of our pinned buffers has been
3702 * lost, replaced by garbage. Since this doesn't always happen,
3703 * let's poison such state so that we more quickly spot when
3704 * we falsely assume it has been preserved.
3706 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
3707 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);
3709 reset_csb_pointers(engine);
3712 * The kernel_context HWSP is stored in the status_page. As above,
3713 * that may be lost on resume/initialisation, and so we need to
3714 * reset the value in the HWSP.
3716 intel_timeline_reset_seqno(engine->kernel_context->timeline);
3719 static void enable_error_interrupt(struct intel_engine_cs *engine)
3723 engine->execlists.error_interrupt = 0;
3724 ENGINE_WRITE(engine, RING_EMR, ~0u);
3725 ENGINE_WRITE(engine, RING_EIR, ~0u); /* clear all existing errors */
3727 status = ENGINE_READ(engine, RING_ESR);
3728 if (unlikely(status)) {
3729 drm_err(&engine->i915->drm,
3730 "engine '%s' resumed still in error: %08x\n",
3731 engine->name, status);
3732 __intel_gt_reset(engine->gt, engine->mask);
3736 * On current gen8+, we have 2 signals to play with
3738 * - I915_ERROR_INSTUCTION (bit 0)
3740 * Generate an error if the command parser encounters an invalid
3743 * This is a fatal error.
3747 * Generate an error on privilege violation (where the CP replaces
3748 * the instruction with a no-op). This also fires for writes into
3749 * read-only scratch pages.
3751 * This is a non-fatal error, parsing continues.
3753 * * there are a few others defined for odd HW that we do not use
3755 * Since CP_PRIV fires for cases where we have chosen to ignore the
3756 * error (as the HW is validating and suppressing the mistakes), we
3757 * only unmask the instruction error bit.
3759 ENGINE_WRITE(engine, RING_EMR, ~I915_ERROR_INSTRUCTION);
3762 static void enable_execlists(struct intel_engine_cs *engine)
3766 assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
3768 intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
3770 if (INTEL_GEN(engine->i915) >= 11)
3771 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
3773 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
3774 ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode);
3776 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
3778 ENGINE_WRITE_FW(engine,
3780 i915_ggtt_offset(engine->status_page.vma));
3781 ENGINE_POSTING_READ(engine, RING_HWS_PGA);
3783 enable_error_interrupt(engine);
3785 engine->context_tag = 0;
3788 static bool unexpected_starting_state(struct intel_engine_cs *engine)
3790 bool unexpected = false;
3792 if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
3793 drm_dbg(&engine->i915->drm,
3794 "STOP_RING still set in RING_MI_MODE\n");
3801 static int execlists_resume(struct intel_engine_cs *engine)
3803 intel_mocs_init_engine(engine);
3805 intel_engine_reset_breadcrumbs(engine);
3807 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
3808 struct drm_printer p = drm_debug_printer(__func__);
3810 intel_engine_dump(engine, &p, NULL);
3813 enable_execlists(engine);
3818 static void execlists_reset_prepare(struct intel_engine_cs *engine)
3820 struct intel_engine_execlists * const execlists = &engine->execlists;
3821 unsigned long flags;
3823 ENGINE_TRACE(engine, "depth<-%d\n",
3824 atomic_read(&execlists->tasklet.count));
3827 * Prevent request submission to the hardware until we have
3828 * completed the reset in i915_gem_reset_finish(). If a request
3829 * is completed by one engine, it may then queue a request
3830 * to a second via its execlists->tasklet *just* as we are
3831 * calling engine->resume() and also writing the ELSP.
3832 * Turning off the execlists->tasklet until the reset is over
3833 * prevents the race.
3835 __tasklet_disable_sync_once(&execlists->tasklet);
3836 GEM_BUG_ON(!reset_in_progress(execlists));
3838 /* And flush any current direct submission. */
3839 spin_lock_irqsave(&engine->active.lock, flags);
3840 spin_unlock_irqrestore(&engine->active.lock, flags);
3843 * We stop engines, otherwise we might get failed reset and a
3844 * dead gpu (on elk). Also as modern gpu as kbl can suffer
3845 * from system hang if batchbuffer is progressing when
3846 * the reset is issued, regardless of READY_TO_RESET ack.
3847 * Thus assume it is best to stop engines on all gens
3848 * where we have a gpu reset.
3850 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
3852 * FIXME: Wa for more modern gens needs to be validated
3854 ring_set_paused(engine, 1);
3855 intel_engine_stop_cs(engine);
3858 static void __reset_stop_ring(u32 *regs, const struct intel_engine_cs *engine)
3862 x = lrc_ring_mi_mode(engine);
3864 regs[x + 1] &= ~STOP_RING;
3865 regs[x + 1] |= STOP_RING << 16;
3869 static void __execlists_reset_reg_state(const struct intel_context *ce,
3870 const struct intel_engine_cs *engine)
3872 u32 *regs = ce->lrc_reg_state;
3874 __reset_stop_ring(regs, engine);
3877 static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
3879 struct intel_engine_execlists * const execlists = &engine->execlists;
3880 struct intel_context *ce;
3881 struct i915_request *rq;
3884 mb(); /* paranoia: read the CSB pointers from after the reset */
3885 clflush(execlists->csb_write);
3888 process_csb(engine); /* drain preemption events */
3890 /* Following the reset, we need to reload the CSB read/write pointers */
3891 reset_csb_pointers(engine);
3894 * Save the currently executing context, even if we completed
3895 * its request, it was still running at the time of the
3896 * reset and will have been clobbered.
3898 rq = execlists_active(execlists);
3903 GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
3905 if (i915_request_completed(rq)) {
3906 /* Idle context; tidy up the ring so we can restart afresh */
3907 head = intel_ring_wrap(ce->ring, rq->tail);
3911 /* We still have requests in-flight; the engine should be active */
3912 GEM_BUG_ON(!intel_engine_pm_is_awake(engine));
3914 /* Context has requests still in-flight; it should not be idle! */
3915 GEM_BUG_ON(i915_active_is_idle(&ce->active));
3917 rq = active_request(ce->timeline, rq);
3918 head = intel_ring_wrap(ce->ring, rq->head);
3919 GEM_BUG_ON(head == ce->ring->tail);
3922 * If this request hasn't started yet, e.g. it is waiting on a
3923 * semaphore, we need to avoid skipping the request or else we
3924 * break the signaling chain. However, if the context is corrupt
3925 * the request will not restart and we will be stuck with a wedged
3926 * device. It is quite often the case that if we issue a reset
3927 * while the GPU is loading the context image, that the context
3928 * image becomes corrupt.
3930 * Otherwise, if we have not started yet, the request should replay
3931 * perfectly and we do not need to flag the result as being erroneous.
3933 if (!i915_request_started(rq))
3937 * If the request was innocent, we leave the request in the ELSP
3938 * and will try to replay it on restarting. The context image may
3939 * have been corrupted by the reset, in which case we may have
3940 * to service a new GPU hang, but more likely we can continue on
3943 * If the request was guilty, we presume the context is corrupt
3944 * and have to at least restore the RING register in the context
3945 * image back to the expected values to skip over the guilty request.
3947 __i915_request_reset(rq, stalled);
3952 * We want a simple context + ring to execute the breadcrumb update.
3953 * We cannot rely on the context being intact across the GPU hang,
3954 * so clear it and rebuild just what we need for the breadcrumb.
3955 * All pending requests for this context will be zapped, and any
3956 * future request will be after userspace has had the opportunity
3957 * to recreate its own state.
3959 GEM_BUG_ON(!intel_context_is_pinned(ce));
3960 restore_default_state(ce, engine);
3963 ENGINE_TRACE(engine, "replay {head:%04x, tail:%04x}\n",
3964 head, ce->ring->tail);
3965 __execlists_reset_reg_state(ce, engine);
3966 __execlists_update_reg_state(ce, engine, head);
3967 ce->lrc_desc |= CTX_DESC_FORCE_RESTORE; /* paranoid: GPU was reset! */
3970 /* Push back any incomplete requests for replay after the reset. */
3971 cancel_port_requests(execlists);
3972 __unwind_incomplete_requests(engine);
3975 static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
3977 unsigned long flags;
3979 ENGINE_TRACE(engine, "\n");
3981 spin_lock_irqsave(&engine->active.lock, flags);
3983 __execlists_reset(engine, stalled);
3985 spin_unlock_irqrestore(&engine->active.lock, flags);
3988 static void nop_submission_tasklet(unsigned long data)
3990 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
3992 /* The driver is wedged; don't process any more events. */
3993 WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN);
3996 static void execlists_reset_cancel(struct intel_engine_cs *engine)
3998 struct intel_engine_execlists * const execlists = &engine->execlists;
3999 struct i915_request *rq, *rn;
4001 unsigned long flags;
4003 ENGINE_TRACE(engine, "\n");
4006 * Before we call engine->cancel_requests(), we should have exclusive
4007 * access to the submission state. This is arranged for us by the
4008 * caller disabling the interrupt generation, the tasklet and other
4009 * threads that may then access the same state, giving us a free hand
4010 * to reset state. However, we still need to let lockdep be aware that
4011 * we know this state may be accessed in hardirq context, so we
4012 * disable the irq around this manipulation and we want to keep
4013 * the spinlock focused on its duties and not accidentally conflate
4014 * coverage to the submission's irq state. (Similarly, although we
4015 * shouldn't need to disable irq around the manipulation of the
4016 * submission's irq state, we also wish to remind ourselves that
4019 spin_lock_irqsave(&engine->active.lock, flags);
4021 __execlists_reset(engine, true);
4023 /* Mark all executing requests as skipped. */
4024 list_for_each_entry(rq, &engine->active.requests, sched.link)
4027 /* Flush the queued requests to the timeline list (for retiring). */
4028 while ((rb = rb_first_cached(&execlists->queue))) {
4029 struct i915_priolist *p = to_priolist(rb);
4032 priolist_for_each_request_consume(rq, rn, p, i) {
4034 __i915_request_submit(rq);
4037 rb_erase_cached(&p->node, &execlists->queue);
4038 i915_priolist_free(p);
4041 /* On-hold requests will be flushed to timeline upon their release */
4042 list_for_each_entry(rq, &engine->active.hold, sched.link)
4045 /* Cancel all attached virtual engines */
4046 while ((rb = rb_first_cached(&execlists->virtual))) {
4047 struct virtual_engine *ve =
4048 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
4050 rb_erase_cached(rb, &execlists->virtual);
4053 spin_lock(&ve->base.active.lock);
4054 rq = fetch_and_zero(&ve->request);
4058 rq->engine = engine;
4059 __i915_request_submit(rq);
4060 i915_request_put(rq);
4062 ve->base.execlists.queue_priority_hint = INT_MIN;
4064 spin_unlock(&ve->base.active.lock);
4067 /* Remaining _unready_ requests will be nop'ed when submitted */
4069 execlists->queue_priority_hint = INT_MIN;
4070 execlists->queue = RB_ROOT_CACHED;
4072 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
4073 execlists->tasklet.func = nop_submission_tasklet;
4075 spin_unlock_irqrestore(&engine->active.lock, flags);
4078 static void execlists_reset_finish(struct intel_engine_cs *engine)
4080 struct intel_engine_execlists * const execlists = &engine->execlists;
4083 * After a GPU reset, we may have requests to replay. Do so now while
4084 * we still have the forcewake to be sure that the GPU is not allowed
4085 * to sleep before we restart and reload a context.
4087 GEM_BUG_ON(!reset_in_progress(execlists));
4088 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
4089 execlists->tasklet.func(execlists->tasklet.data);
4091 if (__tasklet_enable(&execlists->tasklet))
4092 /* And kick in case we missed a new request submission. */
4093 tasklet_hi_schedule(&execlists->tasklet);
4094 ENGINE_TRACE(engine, "depth->%d\n",
4095 atomic_read(&execlists->tasklet.count));
4098 static int gen8_emit_bb_start_noarb(struct i915_request *rq,
4099 u64 offset, u32 len,
4100 const unsigned int flags)
4104 cs = intel_ring_begin(rq, 4);
4109 * WaDisableCtxRestoreArbitration:bdw,chv
4111 * We don't need to perform MI_ARB_ENABLE as often as we do (in
4112 * particular all the gen that do not need the w/a at all!), if we
4113 * took care to make sure that on every switch into this context
4114 * (both ordinary and for preemption) that arbitrartion was enabled
4115 * we would be fine. However, for gen8 there is another w/a that
4116 * requires us to not preempt inside GPGPU execution, so we keep
4117 * arbitration disabled for gen8 batches. Arbitration will be
4118 * re-enabled before we close the request
4119 * (engine->emit_fini_breadcrumb).
4121 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
4123 /* FIXME(BDW+): Address space and security selectors. */
4124 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
4125 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
4126 *cs++ = lower_32_bits(offset);
4127 *cs++ = upper_32_bits(offset);
4129 intel_ring_advance(rq, cs);
4134 static int gen8_emit_bb_start(struct i915_request *rq,
4135 u64 offset, u32 len,
4136 const unsigned int flags)
4140 cs = intel_ring_begin(rq, 6);
4144 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
4146 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
4147 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
4148 *cs++ = lower_32_bits(offset);
4149 *cs++ = upper_32_bits(offset);
4151 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
4154 intel_ring_advance(rq, cs);
4159 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
4161 ENGINE_WRITE(engine, RING_IMR,
4162 ~(engine->irq_enable_mask | engine->irq_keep_mask));
4163 ENGINE_POSTING_READ(engine, RING_IMR);
4166 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
4168 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
4171 static int gen8_emit_flush(struct i915_request *request, u32 mode)
4175 cs = intel_ring_begin(request, 4);
4179 cmd = MI_FLUSH_DW + 1;
4181 /* We always require a command barrier so that subsequent
4182 * commands, such as breadcrumb interrupts, are strictly ordered
4183 * wrt the contents of the write cache being flushed to memory
4184 * (and thus being coherent from the CPU).
4186 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
4188 if (mode & EMIT_INVALIDATE) {
4189 cmd |= MI_INVALIDATE_TLB;
4190 if (request->engine->class == VIDEO_DECODE_CLASS)
4191 cmd |= MI_INVALIDATE_BSD;
4195 *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
4196 *cs++ = 0; /* upper addr */
4197 *cs++ = 0; /* value */
4198 intel_ring_advance(request, cs);
4203 static int gen8_emit_flush_render(struct i915_request *request,
4206 bool vf_flush_wa = false, dc_flush_wa = false;
4210 flags |= PIPE_CONTROL_CS_STALL;
4212 if (mode & EMIT_FLUSH) {
4213 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
4214 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4215 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
4216 flags |= PIPE_CONTROL_FLUSH_ENABLE;
4219 if (mode & EMIT_INVALIDATE) {
4220 flags |= PIPE_CONTROL_TLB_INVALIDATE;
4221 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
4222 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
4223 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
4224 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
4225 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
4226 flags |= PIPE_CONTROL_QW_WRITE;
4227 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
4230 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
4233 if (IS_GEN(request->i915, 9))
4236 /* WaForGAMHang:kbl */
4237 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
4249 cs = intel_ring_begin(request, len);
4254 cs = gen8_emit_pipe_control(cs, 0, 0);
4257 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
4260 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
4263 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
4265 intel_ring_advance(request, cs);
4270 static int gen11_emit_flush_render(struct i915_request *request,
4273 if (mode & EMIT_FLUSH) {
4277 flags |= PIPE_CONTROL_CS_STALL;
4279 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
4280 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
4281 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4282 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
4283 flags |= PIPE_CONTROL_FLUSH_ENABLE;
4284 flags |= PIPE_CONTROL_QW_WRITE;
4285 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
4287 cs = intel_ring_begin(request, 6);
4291 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
4292 intel_ring_advance(request, cs);
4295 if (mode & EMIT_INVALIDATE) {
4299 flags |= PIPE_CONTROL_CS_STALL;
4301 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
4302 flags |= PIPE_CONTROL_TLB_INVALIDATE;
4303 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
4304 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
4305 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
4306 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
4307 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
4308 flags |= PIPE_CONTROL_QW_WRITE;
4309 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
4311 cs = intel_ring_begin(request, 6);
4315 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
4316 intel_ring_advance(request, cs);
4322 static u32 preparser_disable(bool state)
4324 return MI_ARB_CHECK | 1 << 8 | state;
4327 static int gen12_emit_flush_render(struct i915_request *request,
4330 if (mode & EMIT_FLUSH) {
4334 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
4335 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
4336 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4337 /* Wa_1409600907:tgl */
4338 flags |= PIPE_CONTROL_DEPTH_STALL;
4339 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
4340 flags |= PIPE_CONTROL_FLUSH_ENABLE;
4341 flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
4343 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
4344 flags |= PIPE_CONTROL_QW_WRITE;
4346 flags |= PIPE_CONTROL_CS_STALL;
4348 cs = intel_ring_begin(request, 6);
4352 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
4353 intel_ring_advance(request, cs);
4356 if (mode & EMIT_INVALIDATE) {
4360 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
4361 flags |= PIPE_CONTROL_TLB_INVALIDATE;
4362 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
4363 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
4364 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
4365 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
4366 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
4367 flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE;
4369 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
4370 flags |= PIPE_CONTROL_QW_WRITE;
4372 flags |= PIPE_CONTROL_CS_STALL;
4374 cs = intel_ring_begin(request, 8);
4379 * Prevent the pre-parser from skipping past the TLB
4380 * invalidate and loading a stale page for the batch
4381 * buffer / request payload.
4383 *cs++ = preparser_disable(true);
4385 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
4387 *cs++ = preparser_disable(false);
4388 intel_ring_advance(request, cs);
4395 * Reserve space for 2 NOOPs at the end of each request to be
4396 * used as a workaround for not being allowed to do lite
4397 * restore with HEAD==TAIL (WaIdleLiteRestore).
4399 static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
4401 /* Ensure there's always at least one preemption point per-request. */
4402 *cs++ = MI_ARB_CHECK;
4404 request->wa_tail = intel_ring_offset(request, cs);
4409 static u32 *emit_preempt_busywait(struct i915_request *request, u32 *cs)
4411 *cs++ = MI_SEMAPHORE_WAIT |
4412 MI_SEMAPHORE_GLOBAL_GTT |
4414 MI_SEMAPHORE_SAD_EQ_SDD;
4416 *cs++ = intel_hws_preempt_address(request->engine);
4422 static __always_inline u32*
4423 gen8_emit_fini_breadcrumb_footer(struct i915_request *request,
4426 *cs++ = MI_USER_INTERRUPT;
4428 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
4429 if (intel_engine_has_semaphores(request->engine))
4430 cs = emit_preempt_busywait(request, cs);
4432 request->tail = intel_ring_offset(request, cs);
4433 assert_ring_tail_valid(request->ring, request->tail);
4435 return gen8_emit_wa_tail(request, cs);
4438 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
4440 cs = gen8_emit_ggtt_write(cs,
4441 request->fence.seqno,
4442 i915_request_active_timeline(request)->hwsp_offset,
4445 return gen8_emit_fini_breadcrumb_footer(request, cs);
4448 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
4450 cs = gen8_emit_pipe_control(cs,
4451 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
4452 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
4453 PIPE_CONTROL_DC_FLUSH_ENABLE,
4456 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
4457 cs = gen8_emit_ggtt_write_rcs(cs,
4458 request->fence.seqno,
4459 i915_request_active_timeline(request)->hwsp_offset,
4460 PIPE_CONTROL_FLUSH_ENABLE |
4461 PIPE_CONTROL_CS_STALL);
4463 return gen8_emit_fini_breadcrumb_footer(request, cs);
4467 gen11_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
4469 cs = gen8_emit_ggtt_write_rcs(cs,
4470 request->fence.seqno,
4471 i915_request_active_timeline(request)->hwsp_offset,
4472 PIPE_CONTROL_CS_STALL |
4473 PIPE_CONTROL_TILE_CACHE_FLUSH |
4474 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
4475 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
4476 PIPE_CONTROL_DC_FLUSH_ENABLE |
4477 PIPE_CONTROL_FLUSH_ENABLE);
4479 return gen8_emit_fini_breadcrumb_footer(request, cs);
4483 * Note that the CS instruction pre-parser will not stall on the breadcrumb
4484 * flush and will continue pre-fetching the instructions after it before the
4485 * memory sync is completed. On pre-gen12 HW, the pre-parser will stop at
4486 * BB_START/END instructions, so, even though we might pre-fetch the pre-amble
4487 * of the next request before the memory has been flushed, we're guaranteed that
4488 * we won't access the batch itself too early.
4489 * However, on gen12+ the parser can pre-fetch across the BB_START/END commands,
4490 * so, if the current request is modifying an instruction in the next request on
4491 * the same intel_context, we might pre-fetch and then execute the pre-update
4492 * instruction. To avoid this, the users of self-modifying code should either
4493 * disable the parser around the code emitting the memory writes, via a new flag
4494 * added to MI_ARB_CHECK, or emit the writes from a different intel_context. For
4495 * the in-kernel use-cases we've opted to use a separate context, see
4496 * reloc_gpu() as an example.
4497 * All the above applies only to the instructions themselves. Non-inline data
4498 * used by the instructions is not pre-fetched.
4501 static u32 *gen12_emit_preempt_busywait(struct i915_request *request, u32 *cs)
4503 *cs++ = MI_SEMAPHORE_WAIT_TOKEN |
4504 MI_SEMAPHORE_GLOBAL_GTT |
4506 MI_SEMAPHORE_SAD_EQ_SDD;
4508 *cs++ = intel_hws_preempt_address(request->engine);
4516 static __always_inline u32*
4517 gen12_emit_fini_breadcrumb_footer(struct i915_request *request, u32 *cs)
4519 *cs++ = MI_USER_INTERRUPT;
4521 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
4522 if (intel_engine_has_semaphores(request->engine))
4523 cs = gen12_emit_preempt_busywait(request, cs);
4525 request->tail = intel_ring_offset(request, cs);
4526 assert_ring_tail_valid(request->ring, request->tail);
4528 return gen8_emit_wa_tail(request, cs);
4531 static u32 *gen12_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
4533 cs = gen8_emit_ggtt_write(cs,
4534 request->fence.seqno,
4535 i915_request_active_timeline(request)->hwsp_offset,
4538 return gen12_emit_fini_breadcrumb_footer(request, cs);
4542 gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
4544 cs = gen8_emit_ggtt_write_rcs(cs,
4545 request->fence.seqno,
4546 i915_request_active_timeline(request)->hwsp_offset,
4547 PIPE_CONTROL_CS_STALL |
4548 PIPE_CONTROL_TILE_CACHE_FLUSH |
4549 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
4550 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
4551 /* Wa_1409600907:tgl */
4552 PIPE_CONTROL_DEPTH_STALL |
4553 PIPE_CONTROL_DC_FLUSH_ENABLE |
4554 PIPE_CONTROL_FLUSH_ENABLE |
4555 PIPE_CONTROL_HDC_PIPELINE_FLUSH);
4557 return gen12_emit_fini_breadcrumb_footer(request, cs);
4560 static void execlists_park(struct intel_engine_cs *engine)
4562 cancel_timer(&engine->execlists.timer);
4563 cancel_timer(&engine->execlists.preempt);
4566 void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
4568 engine->submit_request = execlists_submit_request;
4569 engine->schedule = i915_schedule;
4570 engine->execlists.tasklet.func = execlists_submission_tasklet;
4572 engine->reset.prepare = execlists_reset_prepare;
4573 engine->reset.rewind = execlists_reset_rewind;
4574 engine->reset.cancel = execlists_reset_cancel;
4575 engine->reset.finish = execlists_reset_finish;
4577 engine->park = execlists_park;
4578 engine->unpark = NULL;
4580 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
4581 if (!intel_vgpu_active(engine->i915)) {
4582 engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
4583 if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
4584 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
4587 if (INTEL_GEN(engine->i915) >= 12)
4588 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
4590 if (intel_engine_has_preemption(engine))
4591 engine->emit_bb_start = gen8_emit_bb_start;
4593 engine->emit_bb_start = gen8_emit_bb_start_noarb;
4596 static void execlists_shutdown(struct intel_engine_cs *engine)
4598 /* Synchronise with residual timers and any softirq they raise */
4599 del_timer_sync(&engine->execlists.timer);
4600 del_timer_sync(&engine->execlists.preempt);
4601 tasklet_kill(&engine->execlists.tasklet);
4604 static void execlists_release(struct intel_engine_cs *engine)
4606 engine->sanitize = NULL; /* no longer in control, nothing to sanitize */
4608 execlists_shutdown(engine);
4610 intel_engine_cleanup_common(engine);
4611 lrc_destroy_wa_ctx(engine);
4615 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
4617 /* Default vfuncs which can be overriden by each engine. */
4619 engine->resume = execlists_resume;
4621 engine->cops = &execlists_context_ops;
4622 engine->request_alloc = execlists_request_alloc;
4624 engine->emit_flush = gen8_emit_flush;
4625 engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
4626 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb;
4627 if (INTEL_GEN(engine->i915) >= 12)
4628 engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb;
4630 engine->set_default_submission = intel_execlists_set_default_submission;
4632 if (INTEL_GEN(engine->i915) < 11) {
4633 engine->irq_enable = gen8_logical_ring_enable_irq;
4634 engine->irq_disable = gen8_logical_ring_disable_irq;
4637 * TODO: On Gen11 interrupt masks need to be clear
4638 * to allow C6 entry. Keep interrupts enabled at
4639 * and take the hit of generating extra interrupts
4640 * until a more refined solution exists.
4646 logical_ring_default_irqs(struct intel_engine_cs *engine)
4648 unsigned int shift = 0;
4650 if (INTEL_GEN(engine->i915) < 11) {
4651 const u8 irq_shifts[] = {
4652 [RCS0] = GEN8_RCS_IRQ_SHIFT,
4653 [BCS0] = GEN8_BCS_IRQ_SHIFT,
4654 [VCS0] = GEN8_VCS0_IRQ_SHIFT,
4655 [VCS1] = GEN8_VCS1_IRQ_SHIFT,
4656 [VECS0] = GEN8_VECS_IRQ_SHIFT,
4659 shift = irq_shifts[engine->id];
4662 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
4663 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
4664 engine->irq_keep_mask |= GT_CS_MASTER_ERROR_INTERRUPT << shift;
4665 engine->irq_keep_mask |= GT_WAIT_SEMAPHORE_INTERRUPT << shift;
4668 static void rcs_submission_override(struct intel_engine_cs *engine)
4670 switch (INTEL_GEN(engine->i915)) {
4672 engine->emit_flush = gen12_emit_flush_render;
4673 engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
4676 engine->emit_flush = gen11_emit_flush_render;
4677 engine->emit_fini_breadcrumb = gen11_emit_fini_breadcrumb_rcs;
4680 engine->emit_flush = gen8_emit_flush_render;
4681 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
4686 int intel_execlists_submission_setup(struct intel_engine_cs *engine)
4688 struct intel_engine_execlists * const execlists = &engine->execlists;
4689 struct drm_i915_private *i915 = engine->i915;
4690 struct intel_uncore *uncore = engine->uncore;
4691 u32 base = engine->mmio_base;
4693 tasklet_init(&engine->execlists.tasklet,
4694 execlists_submission_tasklet, (unsigned long)engine);
4695 timer_setup(&engine->execlists.timer, execlists_timeslice, 0);
4696 timer_setup(&engine->execlists.preempt, execlists_preempt, 0);
4698 logical_ring_default_vfuncs(engine);
4699 logical_ring_default_irqs(engine);
4701 if (engine->class == RENDER_CLASS)
4702 rcs_submission_override(engine);
4704 if (intel_init_workaround_bb(engine))
4706 * We continue even if we fail to initialize WA batch
4707 * because we only expect rare glitches but nothing
4708 * critical to prevent us from using GPU
4710 drm_err(&i915->drm, "WA batch buffer initialization failed\n");
4712 if (HAS_LOGICAL_RING_ELSQ(i915)) {
4713 execlists->submit_reg = uncore->regs +
4714 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
4715 execlists->ctrl_reg = uncore->regs +
4716 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
4718 execlists->submit_reg = uncore->regs +
4719 i915_mmio_reg_offset(RING_ELSP(base));
4722 execlists->csb_status =
4723 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
4725 execlists->csb_write =
4726 &engine->status_page.addr[intel_hws_csb_write_index(i915)];
4728 if (INTEL_GEN(i915) < 11)
4729 execlists->csb_size = GEN8_CSB_ENTRIES;
4731 execlists->csb_size = GEN11_CSB_ENTRIES;
4733 /* Finally, take ownership and responsibility for cleanup! */
4734 engine->sanitize = execlists_sanitize;
4735 engine->release = execlists_release;
4741 static void init_common_reg_state(u32 * const regs,
4742 const struct intel_engine_cs *engine,
4743 const struct intel_ring *ring,
4748 ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
4749 ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
4751 ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
4752 if (INTEL_GEN(engine->i915) < 11)
4753 ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
4754 CTX_CTRL_RS_CTX_ENABLE);
4755 regs[CTX_CONTEXT_CONTROL] = ctl;
4757 regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
4758 regs[CTX_TIMESTAMP] = 0;
4761 static void init_wa_bb_reg_state(u32 * const regs,
4762 const struct intel_engine_cs *engine)
4764 const struct i915_ctx_workarounds * const wa_ctx = &engine->wa_ctx;
4766 if (wa_ctx->per_ctx.size) {
4767 const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
4769 GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);
4770 regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =
4771 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
4774 if (wa_ctx->indirect_ctx.size) {
4775 const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
4777 GEM_BUG_ON(lrc_ring_indirect_ptr(engine) == -1);
4778 regs[lrc_ring_indirect_ptr(engine) + 1] =
4779 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
4780 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
4782 GEM_BUG_ON(lrc_ring_indirect_offset(engine) == -1);
4783 regs[lrc_ring_indirect_offset(engine) + 1] =
4784 lrc_ring_indirect_offset_default(engine) << 6;
4788 static void init_ppgtt_reg_state(u32 *regs, const struct i915_ppgtt *ppgtt)
4790 if (i915_vm_is_4lvl(&ppgtt->vm)) {
4791 /* 64b PPGTT (48bit canonical)
4792 * PDP0_DESCRIPTOR contains the base address to PML4 and
4793 * other PDP Descriptors are ignored.
4795 ASSIGN_CTX_PML4(ppgtt, regs);
4797 ASSIGN_CTX_PDP(ppgtt, regs, 3);
4798 ASSIGN_CTX_PDP(ppgtt, regs, 2);
4799 ASSIGN_CTX_PDP(ppgtt, regs, 1);
4800 ASSIGN_CTX_PDP(ppgtt, regs, 0);
4804 static struct i915_ppgtt *vm_alias(struct i915_address_space *vm)
4806 if (i915_is_ggtt(vm))
4807 return i915_vm_to_ggtt(vm)->alias;
4809 return i915_vm_to_ppgtt(vm);
4812 static void execlists_init_reg_state(u32 *regs,
4813 const struct intel_context *ce,
4814 const struct intel_engine_cs *engine,
4815 const struct intel_ring *ring,
4819 * A context is actually a big batch buffer with several
4820 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
4821 * values we are setting here are only for the first context restore:
4822 * on a subsequent save, the GPU will recreate this batchbuffer with new
4823 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
4824 * we are not initializing here).
4826 * Must keep consistent with virtual_update_register_offsets().
4828 set_offsets(regs, reg_offsets(engine), engine, inhibit);
4830 init_common_reg_state(regs, engine, ring, inhibit);
4831 init_ppgtt_reg_state(regs, vm_alias(ce->vm));
4833 init_wa_bb_reg_state(regs, engine);
4835 __reset_stop_ring(regs, engine);
4839 populate_lr_context(struct intel_context *ce,
4840 struct drm_i915_gem_object *ctx_obj,
4841 struct intel_engine_cs *engine,
4842 struct intel_ring *ring)
4844 bool inhibit = true;
4848 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
4849 if (IS_ERR(vaddr)) {
4850 ret = PTR_ERR(vaddr);
4851 drm_dbg(&engine->i915->drm,
4852 "Could not map object pages! (%d)\n", ret);
4856 set_redzone(vaddr, engine);
4858 if (engine->default_state) {
4861 defaults = i915_gem_object_pin_map(engine->default_state,
4863 if (IS_ERR(defaults)) {
4864 ret = PTR_ERR(defaults);
4868 memcpy(vaddr, defaults, engine->context_size);
4869 i915_gem_object_unpin_map(engine->default_state);
4870 __set_bit(CONTEXT_VALID_BIT, &ce->flags);
4874 /* Clear the ppHWSP (inc. per-context counters) */
4875 memset(vaddr, 0, PAGE_SIZE);
4878 * The second page of the context object contains some registers which
4879 * must be set up prior to the first execution.
4881 execlists_init_reg_state(vaddr + LRC_STATE_OFFSET,
4882 ce, engine, ring, inhibit);
4886 __i915_gem_object_flush_map(ctx_obj, 0, engine->context_size);
4887 i915_gem_object_unpin_map(ctx_obj);
4891 static int __execlists_context_alloc(struct intel_context *ce,
4892 struct intel_engine_cs *engine)
4894 struct drm_i915_gem_object *ctx_obj;
4895 struct intel_ring *ring;
4896 struct i915_vma *vma;
4900 GEM_BUG_ON(ce->state);
4901 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
4903 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
4904 context_size += I915_GTT_PAGE_SIZE; /* for redzone */
4906 ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
4907 if (IS_ERR(ctx_obj))
4908 return PTR_ERR(ctx_obj);
4910 vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
4913 goto error_deref_obj;
4916 if (!ce->timeline) {
4917 struct intel_timeline *tl;
4918 struct i915_vma *hwsp;
4921 * Use the static global HWSP for the kernel context, and
4922 * a dynamically allocated cacheline for everyone else.
4925 if (unlikely(intel_context_is_barrier(ce)))
4926 hwsp = engine->status_page.vma;
4928 tl = intel_timeline_create(engine->gt, hwsp);
4931 goto error_deref_obj;
4937 ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
4939 ret = PTR_ERR(ring);
4940 goto error_deref_obj;
4943 ret = populate_lr_context(ce, ctx_obj, engine, ring);
4945 drm_dbg(&engine->i915->drm,
4946 "Failed to populate LRC: %d\n", ret);
4947 goto error_ring_free;
4956 intel_ring_put(ring);
4958 i915_gem_object_put(ctx_obj);
4962 static struct list_head *virtual_queue(struct virtual_engine *ve)
4964 return &ve->base.execlists.default_priolist.requests[0];
4967 static void virtual_context_destroy(struct kref *kref)
4969 struct virtual_engine *ve =
4970 container_of(kref, typeof(*ve), context.ref);
4973 GEM_BUG_ON(!list_empty(virtual_queue(ve)));
4974 GEM_BUG_ON(ve->request);
4975 GEM_BUG_ON(ve->context.inflight);
4977 for (n = 0; n < ve->num_siblings; n++) {
4978 struct intel_engine_cs *sibling = ve->siblings[n];
4979 struct rb_node *node = &ve->nodes[sibling->id].rb;
4980 unsigned long flags;
4982 if (RB_EMPTY_NODE(node))
4985 spin_lock_irqsave(&sibling->active.lock, flags);
4987 /* Detachment is lazily performed in the execlists tasklet */
4988 if (!RB_EMPTY_NODE(node))
4989 rb_erase_cached(node, &sibling->execlists.virtual);
4991 spin_unlock_irqrestore(&sibling->active.lock, flags);
4993 GEM_BUG_ON(__tasklet_is_scheduled(&ve->base.execlists.tasklet));
4995 if (ve->context.state)
4996 __execlists_context_fini(&ve->context);
4997 intel_context_fini(&ve->context);
4999 intel_engine_free_request_pool(&ve->base);
5005 static void virtual_engine_initial_hint(struct virtual_engine *ve)
5010 * Pick a random sibling on starting to help spread the load around.
5012 * New contexts are typically created with exactly the same order
5013 * of siblings, and often started in batches. Due to the way we iterate
5014 * the array of sibling when submitting requests, sibling[0] is
5015 * prioritised for dequeuing. If we make sure that sibling[0] is fairly
5016 * randomised across the system, we also help spread the load by the
5017 * first engine we inspect being different each time.
5019 * NB This does not force us to execute on this engine, it will just
5020 * typically be the first we inspect for submission.
5022 swp = prandom_u32_max(ve->num_siblings);
5026 swap(ve->siblings[swp], ve->siblings[0]);
5027 if (!intel_engine_has_relative_mmio(ve->siblings[0]))
5028 virtual_update_register_offsets(ve->context.lrc_reg_state,
5032 static int virtual_context_alloc(struct intel_context *ce)
5034 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
5036 return __execlists_context_alloc(ce, ve->siblings[0]);
5039 static int virtual_context_pin(struct intel_context *ce)
5041 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
5044 /* Note: we must use a real engine class for setting up reg state */
5045 err = __execlists_context_pin(ce, ve->siblings[0]);
5049 virtual_engine_initial_hint(ve);
5053 static void virtual_context_enter(struct intel_context *ce)
5055 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
5058 for (n = 0; n < ve->num_siblings; n++)
5059 intel_engine_pm_get(ve->siblings[n]);
5061 intel_timeline_enter(ce->timeline);
5064 static void virtual_context_exit(struct intel_context *ce)
5066 struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
5069 intel_timeline_exit(ce->timeline);
5071 for (n = 0; n < ve->num_siblings; n++)
5072 intel_engine_pm_put(ve->siblings[n]);
5075 static const struct intel_context_ops virtual_context_ops = {
5076 .alloc = virtual_context_alloc,
5078 .pin = virtual_context_pin,
5079 .unpin = execlists_context_unpin,
5081 .enter = virtual_context_enter,
5082 .exit = virtual_context_exit,
5084 .destroy = virtual_context_destroy,
5087 static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve)
5089 struct i915_request *rq;
5090 intel_engine_mask_t mask;
5092 rq = READ_ONCE(ve->request);
5096 /* The rq is ready for submission; rq->execution_mask is now stable. */
5097 mask = rq->execution_mask;
5098 if (unlikely(!mask)) {
5099 /* Invalid selection, submit to a random engine in error */
5100 i915_request_set_error_once(rq, -ENODEV);
5101 mask = ve->siblings[0]->mask;
5104 ENGINE_TRACE(&ve->base, "rq=%llx:%lld, mask=%x, prio=%d\n",
5105 rq->fence.context, rq->fence.seqno,
5106 mask, ve->base.execlists.queue_priority_hint);
5111 static void virtual_submission_tasklet(unsigned long data)
5113 struct virtual_engine * const ve = (struct virtual_engine *)data;
5114 const int prio = READ_ONCE(ve->base.execlists.queue_priority_hint);
5115 intel_engine_mask_t mask;
5119 mask = virtual_submission_mask(ve);
5121 if (unlikely(!mask))
5124 local_irq_disable();
5125 for (n = 0; n < ve->num_siblings; n++) {
5126 struct intel_engine_cs *sibling = READ_ONCE(ve->siblings[n]);
5127 struct ve_node * const node = &ve->nodes[sibling->id];
5128 struct rb_node **parent, *rb;
5131 if (!READ_ONCE(ve->request))
5132 break; /* already handled by a sibling's tasklet */
5134 if (unlikely(!(mask & sibling->mask))) {
5135 if (!RB_EMPTY_NODE(&node->rb)) {
5136 spin_lock(&sibling->active.lock);
5137 rb_erase_cached(&node->rb,
5138 &sibling->execlists.virtual);
5139 RB_CLEAR_NODE(&node->rb);
5140 spin_unlock(&sibling->active.lock);
5145 spin_lock(&sibling->active.lock);
5147 if (!RB_EMPTY_NODE(&node->rb)) {
5149 * Cheat and avoid rebalancing the tree if we can
5150 * reuse this node in situ.
5152 first = rb_first_cached(&sibling->execlists.virtual) ==
5154 if (prio == node->prio || (prio > node->prio && first))
5157 rb_erase_cached(&node->rb, &sibling->execlists.virtual);
5162 parent = &sibling->execlists.virtual.rb_root.rb_node;
5164 struct ve_node *other;
5167 other = rb_entry(rb, typeof(*other), rb);
5168 if (prio > other->prio) {
5169 parent = &rb->rb_left;
5171 parent = &rb->rb_right;
5176 rb_link_node(&node->rb, rb, parent);
5177 rb_insert_color_cached(&node->rb,
5178 &sibling->execlists.virtual,
5182 GEM_BUG_ON(RB_EMPTY_NODE(&node->rb));
5184 if (first && prio > sibling->execlists.queue_priority_hint)
5185 tasklet_hi_schedule(&sibling->execlists.tasklet);
5187 spin_unlock(&sibling->active.lock);
5192 static void virtual_submit_request(struct i915_request *rq)
5194 struct virtual_engine *ve = to_virtual_engine(rq->engine);
5195 struct i915_request *old;
5196 unsigned long flags;
5198 ENGINE_TRACE(&ve->base, "rq=%llx:%lld\n",
5202 GEM_BUG_ON(ve->base.submit_request != virtual_submit_request);
5204 spin_lock_irqsave(&ve->base.active.lock, flags);
5207 if (old) { /* background completion event from preempt-to-busy */
5208 GEM_BUG_ON(!i915_request_completed(old));
5209 __i915_request_submit(old);
5210 i915_request_put(old);
5213 if (i915_request_completed(rq)) {
5214 __i915_request_submit(rq);
5216 ve->base.execlists.queue_priority_hint = INT_MIN;
5219 ve->base.execlists.queue_priority_hint = rq_prio(rq);
5220 ve->request = i915_request_get(rq);
5222 GEM_BUG_ON(!list_empty(virtual_queue(ve)));
5223 list_move_tail(&rq->sched.link, virtual_queue(ve));
5225 tasklet_schedule(&ve->base.execlists.tasklet);
5228 spin_unlock_irqrestore(&ve->base.active.lock, flags);
5231 static struct ve_bond *
5232 virtual_find_bond(struct virtual_engine *ve,
5233 const struct intel_engine_cs *master)
5237 for (i = 0; i < ve->num_bonds; i++) {
5238 if (ve->bonds[i].master == master)
5239 return &ve->bonds[i];
5246 virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal)
5248 struct virtual_engine *ve = to_virtual_engine(rq->engine);
5249 intel_engine_mask_t allowed, exec;
5250 struct ve_bond *bond;
5252 allowed = ~to_request(signal)->engine->mask;
5254 bond = virtual_find_bond(ve, to_request(signal)->engine);
5256 allowed &= bond->sibling_mask;
5258 /* Restrict the bonded request to run on only the available engines */
5259 exec = READ_ONCE(rq->execution_mask);
5260 while (!try_cmpxchg(&rq->execution_mask, &exec, exec & allowed))
5263 /* Prevent the master from being re-run on the bonded engines */
5264 to_request(signal)->execution_mask &= ~allowed;
5267 struct intel_context *
5268 intel_execlists_create_virtual(struct intel_engine_cs **siblings,
5271 struct virtual_engine *ve;
5276 return ERR_PTR(-EINVAL);
5279 return intel_context_create(siblings[0]);
5281 ve = kzalloc(struct_size(ve, siblings, count), GFP_KERNEL);
5283 return ERR_PTR(-ENOMEM);
5285 ve->base.i915 = siblings[0]->i915;
5286 ve->base.gt = siblings[0]->gt;
5287 ve->base.uncore = siblings[0]->uncore;
5290 ve->base.class = OTHER_CLASS;
5291 ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;
5292 ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
5293 ve->base.uabi_instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
5296 * The decision on whether to submit a request using semaphores
5297 * depends on the saturated state of the engine. We only compute
5298 * this during HW submission of the request, and we need for this
5299 * state to be globally applied to all requests being submitted
5300 * to this engine. Virtual engines encompass more than one physical
5301 * engine and so we cannot accurately tell in advance if one of those
5302 * engines is already saturated and so cannot afford to use a semaphore
5303 * and be pessimized in priority for doing so -- if we are the only
5304 * context using semaphores after all other clients have stopped, we
5305 * will be starved on the saturated system. Such a global switch for
5306 * semaphores is less than ideal, but alas is the current compromise.
5308 ve->base.saturated = ALL_ENGINES;
5310 snprintf(ve->base.name, sizeof(ve->base.name), "virtual");
5312 intel_engine_init_active(&ve->base, ENGINE_VIRTUAL);
5313 intel_engine_init_breadcrumbs(&ve->base);
5314 intel_engine_init_execlists(&ve->base);
5316 ve->base.cops = &virtual_context_ops;
5317 ve->base.request_alloc = execlists_request_alloc;
5319 ve->base.schedule = i915_schedule;
5320 ve->base.submit_request = virtual_submit_request;
5321 ve->base.bond_execute = virtual_bond_execute;
5323 INIT_LIST_HEAD(virtual_queue(ve));
5324 ve->base.execlists.queue_priority_hint = INT_MIN;
5325 tasklet_init(&ve->base.execlists.tasklet,
5326 virtual_submission_tasklet,
5329 intel_context_init(&ve->context, &ve->base);
5331 for (n = 0; n < count; n++) {
5332 struct intel_engine_cs *sibling = siblings[n];
5334 GEM_BUG_ON(!is_power_of_2(sibling->mask));
5335 if (sibling->mask & ve->base.mask) {
5336 DRM_DEBUG("duplicate %s entry in load balancer\n",
5343 * The virtual engine implementation is tightly coupled to
5344 * the execlists backend -- we push out request directly
5345 * into a tree inside each physical engine. We could support
5346 * layering if we handle cloning of the requests and
5347 * submitting a copy into each backend.
5349 if (sibling->execlists.tasklet.func !=
5350 execlists_submission_tasklet) {
5355 GEM_BUG_ON(RB_EMPTY_NODE(&ve->nodes[sibling->id].rb));
5356 RB_CLEAR_NODE(&ve->nodes[sibling->id].rb);
5358 ve->siblings[ve->num_siblings++] = sibling;
5359 ve->base.mask |= sibling->mask;
5362 * All physical engines must be compatible for their emission
5363 * functions (as we build the instructions during request
5364 * construction and do not alter them before submission
5365 * on the physical engine). We use the engine class as a guide
5366 * here, although that could be refined.
5368 if (ve->base.class != OTHER_CLASS) {
5369 if (ve->base.class != sibling->class) {
5370 DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
5371 sibling->class, ve->base.class);
5378 ve->base.class = sibling->class;
5379 ve->base.uabi_class = sibling->uabi_class;
5380 snprintf(ve->base.name, sizeof(ve->base.name),
5381 "v%dx%d", ve->base.class, count);
5382 ve->base.context_size = sibling->context_size;
5384 ve->base.emit_bb_start = sibling->emit_bb_start;
5385 ve->base.emit_flush = sibling->emit_flush;
5386 ve->base.emit_init_breadcrumb = sibling->emit_init_breadcrumb;
5387 ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb;
5388 ve->base.emit_fini_breadcrumb_dw =
5389 sibling->emit_fini_breadcrumb_dw;
5391 ve->base.flags = sibling->flags;
5394 ve->base.flags |= I915_ENGINE_IS_VIRTUAL;
5396 return &ve->context;
5399 intel_context_put(&ve->context);
5400 return ERR_PTR(err);
5403 struct intel_context *
5404 intel_execlists_clone_virtual(struct intel_engine_cs *src)
5406 struct virtual_engine *se = to_virtual_engine(src);
5407 struct intel_context *dst;
5409 dst = intel_execlists_create_virtual(se->siblings,
5414 if (se->num_bonds) {
5415 struct virtual_engine *de = to_virtual_engine(dst->engine);
5417 de->bonds = kmemdup(se->bonds,
5418 sizeof(*se->bonds) * se->num_bonds,
5421 intel_context_put(dst);
5422 return ERR_PTR(-ENOMEM);
5425 de->num_bonds = se->num_bonds;
5431 int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
5432 const struct intel_engine_cs *master,
5433 const struct intel_engine_cs *sibling)
5435 struct virtual_engine *ve = to_virtual_engine(engine);
5436 struct ve_bond *bond;
5439 /* Sanity check the sibling is part of the virtual engine */
5440 for (n = 0; n < ve->num_siblings; n++)
5441 if (sibling == ve->siblings[n])
5443 if (n == ve->num_siblings)
5446 bond = virtual_find_bond(ve, master);
5448 bond->sibling_mask |= sibling->mask;
5452 bond = krealloc(ve->bonds,
5453 sizeof(*bond) * (ve->num_bonds + 1),
5458 bond[ve->num_bonds].master = master;
5459 bond[ve->num_bonds].sibling_mask = sibling->mask;
5467 struct intel_engine_cs *
5468 intel_virtual_engine_get_sibling(struct intel_engine_cs *engine,
5469 unsigned int sibling)
5471 struct virtual_engine *ve = to_virtual_engine(engine);
5473 if (sibling >= ve->num_siblings)
5476 return ve->siblings[sibling];
5479 void intel_execlists_show_requests(struct intel_engine_cs *engine,
5480 struct drm_printer *m,
5481 void (*show_request)(struct drm_printer *m,
5482 struct i915_request *rq,
5483 const char *prefix),
5486 const struct intel_engine_execlists *execlists = &engine->execlists;
5487 struct i915_request *rq, *last;
5488 unsigned long flags;
5492 spin_lock_irqsave(&engine->active.lock, flags);
5496 list_for_each_entry(rq, &engine->active.requests, sched.link) {
5497 if (count++ < max - 1)
5498 show_request(m, rq, "\t\tE ");
5505 "\t\t...skipping %d executing requests...\n",
5508 show_request(m, last, "\t\tE ");
5511 if (execlists->switch_priority_hint != INT_MIN)
5512 drm_printf(m, "\t\tSwitch priority hint: %d\n",
5513 READ_ONCE(execlists->switch_priority_hint));
5514 if (execlists->queue_priority_hint != INT_MIN)
5515 drm_printf(m, "\t\tQueue priority hint: %d\n",
5516 READ_ONCE(execlists->queue_priority_hint));
5520 for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
5521 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
5524 priolist_for_each_request(rq, p, i) {
5525 if (count++ < max - 1)
5526 show_request(m, rq, "\t\tQ ");
5534 "\t\t...skipping %d queued requests...\n",
5537 show_request(m, last, "\t\tQ ");
5542 for (rb = rb_first_cached(&execlists->virtual); rb; rb = rb_next(rb)) {
5543 struct virtual_engine *ve =
5544 rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
5545 struct i915_request *rq = READ_ONCE(ve->request);
5548 if (count++ < max - 1)
5549 show_request(m, rq, "\t\tV ");
5557 "\t\t...skipping %d virtual requests...\n",
5560 show_request(m, last, "\t\tV ");
5563 spin_unlock_irqrestore(&engine->active.lock, flags);
5566 void intel_lr_context_reset(struct intel_engine_cs *engine,
5567 struct intel_context *ce,
5571 GEM_BUG_ON(!intel_context_is_pinned(ce));
5574 * We want a simple context + ring to execute the breadcrumb update.
5575 * We cannot rely on the context being intact across the GPU hang,
5576 * so clear it and rebuild just what we need for the breadcrumb.
5577 * All pending requests for this context will be zapped, and any
5578 * future request will be after userspace has had the opportunity
5579 * to recreate its own state.
5582 restore_default_state(ce, engine);
5584 /* Rerun the request; its payload has been neutered (if guilty). */
5585 __execlists_update_reg_state(ce, engine, head);
5589 intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine)
5591 return engine->set_default_submission ==
5592 intel_execlists_set_default_submission;
5595 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5596 #include "selftest_lrc.c"